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set device xc6slx75csg484-3
set projName fifo_short_2clk
set design fifo_short_2clk
set projDir [file dirname [info script]]
create_project $projName $projDir/results/$projName -part $device -force
set_property design_mode RTL [current_fileset -srcset]
set top_module fifo_short_2clk_exdes
add_files -norecurse {../../example_design/fifo_short_2clk_exdes.vhd}
add_files -norecurse {./fifo_short_2clk.ngc}
import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/fifo_short_2clk_exdes.xdc}
set_property top fifo_short_2clk_exdes [get_property srcset [current_run]]
synth_design
opt_design 
place_design 
route_design 
write_sdf -rename_top_module fifo_short_2clk_exdes -file routed.sdf 
write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module fifo_short_2clk_exdes routed.v
report_timing -nworst 30 -path_type full -file routed.twr
report_drc -file report.drc
write_bitstream -bitgen_options {-g UnconstrainedPins:Allow}
