/* This file auto-generated from insns.dat by insns.pl - don't edit it */

#include "nasm.h"
#include "insns.h"

static const struct itemplate instrux_RESB[1] = {
    /*   0 : RESB imm [          resb                              ] PSEUDO */
        /* 340 : PSEUDO */
        {I_RESB, 1, {IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72827, 0},
};

static const struct itemplate instrux_RESW[1] = {
    /*   0 : RESW imm [          resb                              ] PSEUDO */
        /* 340 : PSEUDO */
        {I_RESW, 1, {IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72827, 0},
};

static const struct itemplate instrux_RESD[1] = {
    /*   0 : RESD imm [          resb                              ] PSEUDO */
        /* 340 : PSEUDO */
        {I_RESD, 1, {IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72827, 0},
};

static const struct itemplate instrux_RESQ[1] = {
    /*   0 : RESQ imm [          resb                              ] PSEUDO */
        /* 340 : PSEUDO */
        {I_RESQ, 1, {IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72827, 0},
};

static const struct itemplate instrux_REST[1] = {
    /*   0 : REST imm [          resb                              ] PSEUDO */
        /* 340 : PSEUDO */
        {I_REST, 1, {IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72827, 0},
};

static const struct itemplate instrux_RESO[1] = {
    /*   0 : RESO imm [          resb                              ] PSEUDO */
        /* 340 : PSEUDO */
        {I_RESO, 1, {IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72827, 0},
};

static const struct itemplate instrux_RESY[1] = {
    /*   0 : RESY imm [          resb                              ] PSEUDO */
        /* 340 : PSEUDO */
        {I_RESY, 1, {IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72827, 0},
};

static const struct itemplate instrux_RESZ[1] = {
    /*   0 : RESZ imm [          resb                              ] PSEUDO */
        /* 340 : PSEUDO */
        {I_RESZ, 1, {IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72827, 0},
};

static const struct itemplate instrux_EQU[3] = {
    /*   0 : EQU imm ignore PSEUDO */
        /* no bytecode : PSEUDO */
        {I_EQU, 1, {IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73331, 0},
    /*   1 : EQU imm:imm ignore PSEUDO */
        /* no bytecode : PSEUDO */
        {I_EQU, 2, {IMM_NORMAL|COLON,IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+73331, 0},
    /*   2 : EQU spec4 ignore PSEUDO,DFV */
        /* no bytecode : PSEUDO,DFV */
        {I_EQU, 1, {IMMEDIATE|FOURBITS,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73331, 1},
};

static const struct itemplate instrux_NOP[7] = {
    /*   0 : NOP void [          osz norexb nof3 90                ] BESTDIS,8086 */
        /* 330 314 326 001(90) : BESTDIS,8086 */
        {I_NOP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66224, 2},
    /*   1 : NOP rm16 [m:        o16 0f 1f /0                      ] BESTDIS,P6 */
        /* 320 355 001(1f) 200 : BESTDIS,P6 */
        {I_NOP, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66236, 4},
    /*   2 : NOP rm32 [m:        o32 0f 1f /0                      ] BESTDIS,P6 */
        /* 321 355 001(1f) 200 : BESTDIS,P6 */
        {I_NOP, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66242, 4},
    /*   3 : NOP rm64 [m:        o64 0f 1f /0                      ] LONG,BESTDIS,PROT,X86_64 */
        /* 324 355 001(1f) 200 : LONG,BESTDIS,PROT,X86_64 */
        {I_NOP, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66248, 5},
    /*   4 : NOP imm,reg16,rm16 [irm:      o16 0f ibn /r                     ] SM1-2,UNDOC,P6 */
        /* 320 355 300 121 : SM1,SM2,UNDOC,P6 */
        {I_NOP, 3, {IMM_NORMAL,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+72418, 649},
    /*   5 : NOP imm,reg32,rm32 [irm:      o32 0f ibn /r                     ] SM1-2,UNDOC,P6 */
        /* 321 355 300 121 : SM1,SM2,UNDOC,P6 */
        {I_NOP, 3, {IMM_NORMAL,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+72423, 649},
    /*   6 : NOP imm,reg64,rm64 [irm:      o64 0f ibn /r                     ] SM1-2,LONG,PROT,UNDOC,X86_64 */
        /* 324 355 300 121 : SM1,SM2,LONG,PROT,UNDOC,X86_64 */
        {I_NOP, 3, {IMM_NORMAL,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+72428, 650},
};

static const struct itemplate instrux_NOP2[1] = {
    /*   0 : NOP2 void [          norexb nof3 66 90                 ] ND,386 */
        /* 314 326 361 001(90) : 386 */
        {I_NOP2, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66230, 3},
};

static const struct itemplate instrux_MOV[84] = {
    /*   0 : MOV reg_al,mem_offs [-i:       o8 a0 iwdq                        ] SM0-1,NOAPX,8086 */
        /* 001(a0) 045 : SM0,SM1,NOAPX,8086 */
        {I_MOV, 2, {REG_AL|RN_L16,MEM_OFFS,0,0,0}, NO_DECORATOR, nasm_bytecodes+72433, 6},
    /*   1 : MOV reg_ax,mem_offs [-i:       o16 a1 iwdq                       ] SM0-1,NOAPX,8086 */
        /* 320 001(a1) 045 : SM0,SM1,NOAPX,8086 */
        {I_MOV, 2, {REG_AX|RN_L16,MEM_OFFS,0,0,0}, NO_DECORATOR, nasm_bytecodes+71168, 6},
    /*   2 : MOV reg_eax,mem_offs [-i:       o32 a1 iwdq                       ] SM0-1,NOAPX,ZU,386 */
        /* 321 001(a1) 045 : SM0,SM1,NOAPX,ZU,386 */
        {I_MOV, 2, {REG_EAX|RN_L16,MEM_OFFS,0,0,0}, NO_DECORATOR, nasm_bytecodes+71173, 7},
    /*   3 : MOV reg_rax,mem_offs [-i:       o64 a1 iwdq                       ] SM0-1,NOAPX,ZU,LONG,PROT,X86_64 */
        /* 324 001(a1) 045 : SM0,SM1,NOAPX,ZU,LONG,PROT,X86_64 */
        {I_MOV, 2, {REG_RAX|RN_L16,MEM_OFFS,0,0,0}, NO_DECORATOR, nasm_bytecodes+71178, 8},
    /*   4 : MOV mem_offs,reg_al [i-:       o8 a2 iwdq                        ] SM0-1,NOAPX,NOHLE,8086 */
        /* 001(a2) 044 : SM0,SM1,NOAPX,NOHLE,8086 */
        {I_MOV, 2, {MEM_OFFS,REG_AL|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+72437, 9},
    /*   5 : MOV mem_offs,reg_ax [i-:       o16 a3 iwdq                       ] SM0-1,NOAPX,NOHLE,8086 */
        /* 320 001(a3) 044 : SM0,SM1,NOAPX,NOHLE,8086 */
        {I_MOV, 2, {MEM_OFFS,REG_AX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+71183, 9},
    /*   6 : MOV mem_offs,reg_eax [i-:       o32 a3 iwdq                       ] SM0-1,NOAPX,NOHLE,386 */
        /* 321 001(a3) 044 : SM0,SM1,NOAPX,NOHLE,386 */
        {I_MOV, 2, {MEM_OFFS,REG_EAX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+71188, 10},
    /*   7 : MOV mem_offs,reg_rax [i-:       o64 a3 iwdq                       ] SM0-1,NOAPX,LONG,NOHLE,PROT,X86_64 */
        /* 324 001(a3) 044 : SM0,SM1,NOAPX,LONG,NOHLE,PROT,X86_64 */
        {I_MOV, 2, {MEM_OFFS,REG_RAX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+71193, 11},
    /*   8 : MOV rm8,reg8 [mr:       hlexr o8 88 /r                    ] SM0-1,8086 */
        /* 271 001(88) 101 : SM0,SM1,8086 */
        {I_MOV, 2, {RM_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+71198, 12},
    /*   9 : MOV rm16,reg16 [mr:       hlexr o16 89 /r                   ] SM0-1,8086 */
        /* 271 320 001(89) 101 : SM0,SM1,8086 */
        {I_MOV, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66254, 12},
    /*  10 : MOV rm32,reg32 [mr:       hlexr o32 89 /r                   ] SM0-1,386 */
        /* 271 321 001(89) 101 : SM0,SM1,386 */
        {I_MOV, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+66260, 13},
    /*  11 : MOV rm64,reg64 [mr:       hlexr o64 89 /r                   ] SM0-1,LONG,PROT,X86_64 */
        /* 271 324 001(89) 101 : SM0,SM1,LONG,PROT,X86_64 */
        {I_MOV, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+66266, 14},
    /*  12 : MOV reg8,rm8 [rm:       o8 8a /r                          ] SM0-1,8086 */
        /* 001(8a) 110 : SM0,SM1,8086 */
        {I_MOV, 2, {REG_GPR|BITS8,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+66280, 12},
    /*  13 : MOV reg16,rm16 [rm:       o16 8b /r                         ] SM0-1,8086 */
        /* 320 001(8b) 110 : SM0,SM1,8086 */
        {I_MOV, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66825, 12},
    /*  14 : MOV reg32,rm32 [rm:       o32 8b /r                         ] SM0-1,386 */
        /* 321 001(8b) 110 : SM0,SM1,386 */
        {I_MOV, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+66831, 13},
    /*  15 : MOV reg64,rm64 [rm:       o64 8b /r                         ] SM0-1,LONG,PROT,X86_64 */
        /* 324 001(8b) 110 : SM0,SM1,LONG,PROT,X86_64 */
        {I_MOV, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+66837, 14},
    /*  16 : MOV reg64,udword64 [ri:       o32 b8+r id,u                     ] ND,SM0-1,OPT,LONG,PROT,X86_64 */
        /* 321 010 270(265  : SM0,SM1,OPT,LONG,PROT,X86_64 */
        {I_MOV, 2, {REG_GPR|BITS64,UDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+71203, 15},
    /*  17 : MOV reg64,sdword64 [mi:       o64 c7 /0 id,s                    ] ND,SM0-1,SDWORD,OPT,LONG,PROT,X86_64 */
        /* 324 001(c7) 200 255 : SM0,SM1,SDWORD,OPT,LONG,PROT,X86_64 */
        {I_MOV, 2, {REG_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+54724, 16},
    /*  18 : MOV reg8,imm8 [ri:       o8 b0+r ib                        ] SM0-1,8086 */
        /* 010 260(021  : SM0,SM1,8086 */
        {I_MOV, 2, {REG_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+72441, 12},
    /*  19 : MOV reg16,imm16 [ri:       o16 b8+r iw                       ] SM0-1,8086 */
        /* 320 010 270(031  : SM0,SM1,8086 */
        {I_MOV, 2, {REG_GPR|BITS16,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+71208, 12},
    /*  20 : MOV reg32,imm32 [ri:       o32 b8+r id                       ] SM0-1,386 */
        /* 321 010 270(041  : SM0,SM1,386 */
        {I_MOV, 2, {REG_GPR|BITS32,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+71213, 13},
    /*  21 : MOV reg64,imm64 [ri:       o64 b8+r iq                       ] SM0-1,LONG,PROT,X86_64 */
        /* 324 010 270(055  : SM0,SM1,LONG,PROT,X86_64 */
        {I_MOV, 2, {REG_GPR|BITS64,IMM_NORMAL|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+71218, 14},
    /*  22 : MOV reg8,imm8|abs [ri:       o8 b0+r ib                        ] ND,SM0-1,8086 */
        /* 010 260(021  : SM0,SM1,8086 */
        {I_MOV, 2, {REG_GPR|BITS8,IMM_NORMAL|BITS8|ABS,0,0,0}, NO_DECORATOR, nasm_bytecodes+72441, 12},
    /*  23 : MOV reg16,imm16|abs [ri:       o16 b8+r iw                       ] ND,SM0-1,8086 */
        /* 320 010 270(031  : SM0,SM1,8086 */
        {I_MOV, 2, {REG_GPR|BITS16,IMM_NORMAL|BITS16|ABS,0,0,0}, NO_DECORATOR, nasm_bytecodes+71208, 12},
    /*  24 : MOV reg32,imm32|abs [ri:       o32 b8+r id                       ] ND,SM0-1,386 */
        /* 321 010 270(041  : SM0,SM1,386 */
        {I_MOV, 2, {REG_GPR|BITS32,IMM_NORMAL|BITS32|ABS,0,0,0}, NO_DECORATOR, nasm_bytecodes+71213, 13},
    /*  25 : MOV reg64,imm64|abs [ri:       o64 b8+r iq                       ] ND,SM0-1,LONG,PROT,X86_64 */
        /* 324 010 270(055  : SM0,SM1,LONG,PROT,X86_64 */
        {I_MOV, 2, {REG_GPR|BITS64,IMM_NORMAL|BITS64|ABS,0,0,0}, NO_DECORATOR, nasm_bytecodes+71218, 14},
    /*  26 : MOV rm8,imm8 [mi:       hlexr o8 c6 /0 ib                 ] SM0-1,8086 */
        /* 271 001(c6) 200 021 : SM0,SM1,8086 */
        {I_MOV, 2, {RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+66272, 12},
    /*  27 : MOV rm16,imm16 [mi:       hlexr o16 c7 /0 iw                ] SM0-1,8086 */
        /* 271 320 001(c7) 200 031 : SM0,SM1,8086 */
        {I_MOV, 2, {RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+54709, 12},
    /*  28 : MOV rm32,imm32 [mi:       hlexr o32 c7 /0 id                ] SM0-1,386 */
        /* 271 321 001(c7) 200 041 : SM0,SM1,386 */
        {I_MOV, 2, {RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+54716, 13},
    /*  29 : MOV rm64,sdword64 [mi:       hlexr o64 c7 /0 id,s              ] SM0-1,LONG,PROT,X86_64 */
        /* 271 324 001(c7) 200 255 : SM0,SM1,LONG,PROT,X86_64 */
        {I_MOV, 2, {RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+54723, 14},
    /*  30 : MOV reg32,reg_creg [mr:       rex.l 0f 20 /r                    ] NOREX,NOAPX,NOLONG,PRIV,386 */
        /* 334 355 001(20) 101 : NOREX,NOAPX,NOLONG,PRIV,386 */
        {I_MOV, 2, {REG_GPR|BITS32|RN_L16,REG_CREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67226, 276},
    /*  31 : MOV reg_creg,reg32 [rm:       rex.l 0f 22 /r                    ] NOREX,NOAPX,NOLONG,PRIV,386 */
        /* 334 355 001(22) 110 : NOREX,NOAPX,NOLONG,PRIV,386 */
        {I_MOV, 2, {REG_CREG|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67232, 276},
    /*  32 : MOV reg64,reg_creg [mr:       o64nw 0f 20 /r                    ] LONG,PRIV,PROT,X86_64 */
        /* 323 355 001(20) 101 : NWSIZE,LONG,PRIV,PROT,X86_64 */
        {I_MOV, 2, {REG_GPR|BITS64,REG_CREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+67238, 277},
    /*  33 : MOV reg_creg,reg64 [rm:       o64nw 0f 22 /r                    ] LONG,PRIV,PROT,X86_64 */
        /* 323 355 001(22) 110 : NWSIZE,LONG,PRIV,PROT,X86_64 */
        {I_MOV, 2, {REG_CREG,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+67244, 277},
    /*  34 : MOV reg32,reg_dreg [mr:       0f 21 /r                          ] NOREX,NOAPX,NOLONG,PRIV,386 */
        /* 355 001(21) 101 : NOREX,NOAPX,NOLONG,PRIV,386 */
        {I_MOV, 2, {REG_GPR|BITS32|RN_L16,REG_DREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67251, 276},
    /*  35 : MOV reg_dreg,reg32 [rm:       0f 23 /r                          ] NOREX,NOAPX,NOLONG,PRIV,386 */
        /* 355 001(23) 110 : NOREX,NOAPX,NOLONG,PRIV,386 */
        {I_MOV, 2, {REG_DREG|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67257, 276},
    /*  36 : MOV reg64,reg_dreg [mr:       o64nw 0f 21 /r                    ] LONG,PRIV,PROT,X86_64 */
        /* 323 355 001(21) 101 : NWSIZE,LONG,PRIV,PROT,X86_64 */
        {I_MOV, 2, {REG_GPR|BITS64,REG_DREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+67250, 277},
    /*  37 : MOV reg_dreg,reg64 [rm:       o64nw 0f 23 /r                    ] LONG,PRIV,PROT,X86_64 */
        /* 323 355 001(23) 110 : NWSIZE,LONG,PRIV,PROT,X86_64 */
        {I_MOV, 2, {REG_DREG,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+67256, 277},
    /*  38 : MOV reg32,reg_treg [mr:       0f 24 /r                          ] ND,NOREX,NOAPX,NOLONG,OBSOLETE,386 */
        /* 355 001(24) 101 : NOREX,NOAPX,NOLONG,OBSOLETE,386 */
        {I_MOV, 2, {REG_GPR|BITS32|RN_L16,REG_TREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+71683, 278},
    /*  39 : MOV reg_treg,reg32 [rm:       0f 26 /r                          ] ND,NOREX,NOAPX,NOLONG,OBSOLETE,386 */
        /* 355 001(26) 110 : NOREX,NOAPX,NOLONG,OBSOLETE,386 */
        {I_MOV, 2, {REG_TREG|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+71688, 278},
    /*  40 : MOV mem16,reg_sreg [mr:       8c /r                             ] 8086 */
        /* 001(8c) 101 : 8086 */
        {I_MOV, 2, {MEMORY|BITS16,REG_SREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+71749, 23},
    /*  41 : MOV reg16,reg_sreg [mr:       o16 8c /r                         ] 8086 */
        /* 320 001(8c) 101 : 8086 */
        {I_MOV, 2, {REG_GPR|BITS16,REG_SREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+71748, 23},
    /*  42 : MOV reg32,reg_sreg [mr:       optd o32 8c /r                    ] 386 */
        /* 337 321 001(8c) 101 : 386 */
        {I_MOV, 2, {REG_GPR|BITS32,REG_SREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+67358, 3},
    /*  43 : MOV reg64,reg_sreg [mr:       optd o64 8c /r                    ] LONG,386,X86_64 */
        /* 337 324 001(8c) 101 : LONG,PROT,X86_64 */
        {I_MOV, 2, {REG_GPR|BITS64,REG_SREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+67364, 24},
    /*  44 : MOV reg_sreg,mem16 [rm:       8e /r                             ] 8086 */
        /* 001(8e) 110 : 8086 */
        {I_MOV, 2, {REG_SREG,MEMORY|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67384, 23},
    /*  45 : MOV reg_sreg,reg16 [rm:       optw o16 8e /r                    ] 8086 */
        /* 336 320 001(8e) 110 : 8086 */
        {I_MOV, 2, {REG_SREG,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67370, 23},
    /*  46 : MOV reg_sreg,reg32 [rm:       optw o32 8e /r                    ] 386 */
        /* 336 321 001(8e) 110 : 386 */
        {I_MOV, 2, {REG_SREG,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+67376, 3},
    /*  47 : MOV reg_sreg,reg64 [rm:       optw o64 8e /r                    ] LONG,386,X86_64 */
        /* 336 324 001(8e) 110 : LONG,PROT,X86_64 */
        {I_MOV, 2, {REG_SREG,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+67382, 24},
    /*  48 : MOV kreg8,krm8 [rm:       vex.l0.0f.ko8 90 /r              ] ND,ZU,AVX512DQ,FUTURE */
        /* 270(001 001) 001(90) 110 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_MOV, 2, {OPMASKREG|BITS8|RN_L16,RM_OPMASK|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65118, 500},
    /*  49 : MOV kreg8,krm8 [rm:       evex.l0.0f.ko8 90 /r              ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 250(f1 7d 08) 300 001(90) 110 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_MOV, 2, {OPMASKREG|BITS8,RM_OPMASK|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+29664, 501},
    /*  50 : MOV kreg16,krm16 [rm:       vex.l0.0f.ko16 90 /r             ] ND,ZU,AVX512F,FUTURE */
        /* 270(001 000) 001(90) 110 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_MOV, 2, {OPMASKREG|BITS16|RN_L16,RM_OPMASK|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65125, 502},
    /*  51 : MOV kreg16,krm16 [rm:       evex.l0.0f.ko16 90 /r             ] ND,ZU,AVX512F,FUTURE,APX */
        /* 250(f1 7c 08) 300 001(90) 110 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_MOV, 2, {OPMASKREG|BITS16,RM_OPMASK|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29673, 503},
    /*  52 : MOV kreg32,krm32 [rm:       vex.l0.0f.ko32 90 /r             ] ND,ZU,AVX512BW,FUTURE */
        /* 270(001 201) 001(90) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_MOV, 2, {OPMASKREG|BITS32|RN_L16,RM_OPMASK|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65132, 504},
    /*  53 : MOV kreg32,krm32 [rm:       evex.l0.0f.ko32 90 /r             ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 250(f1 fd 08) 300 001(90) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_MOV, 2, {OPMASKREG|BITS32,RM_OPMASK|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+29682, 505},
    /*  54 : MOV kreg64,krm64 [rm:       vex.l0.0f.ko64 90 /r             ] ND,ZU,AVX512BW,FUTURE */
        /* 270(001 200) 001(90) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_MOV, 2, {OPMASKREG|BITS64|RN_L16,RM_OPMASK|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65139, 504},
    /*  55 : MOV kreg64,krm64 [rm:       evex.l0.0f.ko64 90 /r             ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 250(f1 fc 08) 300 001(90) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_MOV, 2, {OPMASKREG|BITS64,RM_OPMASK|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+29691, 505},
    /*  56 : MOV mem8,kreg8 [mr:       vex.l0.0f.ko8 91 /r              ] ND,ZU,AVX512DQ,FUTURE */
        /* 270(001 001) 001(91) 101 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_MOV, 2, {MEMORY|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65146, 500},
    /*  57 : MOV mem8,kreg8 [mr:       evex.l0.0f.ko8 91 /r              ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 250(f1 7d 08) 300 001(91) 101 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_MOV, 2, {MEMORY|BITS8,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+29700, 501},
    /*  58 : MOV mem16,kreg16 [mr:       vex.l0.0f.ko16 91 /r             ] ND,ZU,AVX512DQ,FUTURE */
        /* 270(001 000) 001(91) 101 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_MOV, 2, {MEMORY|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65153, 500},
    /*  59 : MOV mem16,kreg16 [mr:       evex.l0.0f.ko16 91 /r             ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 250(f1 7c 08) 300 001(91) 101 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_MOV, 2, {MEMORY|BITS16,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29709, 501},
    /*  60 : MOV mem32,kreg32 [mr:       vex.l0.0f.ko32 91 /r             ] ND,ZU,AVX512BW,FUTURE */
        /* 270(001 201) 001(91) 101 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_MOV, 2, {MEMORY|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65160, 504},
    /*  61 : MOV mem32,kreg32 [mr:       evex.l0.0f.ko32 91 /r             ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 250(f1 fd 08) 300 001(91) 101 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_MOV, 2, {MEMORY|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+29718, 505},
    /*  62 : MOV mem64,kreg64 [mr:       vex.l0.0f.ko64 91 /r             ] ND,ZU,AVX512BW,FUTURE */
        /* 270(001 200) 001(91) 101 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_MOV, 2, {MEMORY|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65167, 504},
    /*  63 : MOV mem64,kreg64 [mr:       evex.l0.0f.ko64 91 /r             ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 250(f1 fc 08) 300 001(91) 101 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_MOV, 2, {MEMORY|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+29727, 505},
    /*  64 : MOV kreg32,reg32 [rm:       vex.l0.0f.f2.w0 92 /r            ] ND,ZU,AVX512BW,FUTURE */
        /* 270(001 003) 001(92) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_MOV, 2, {OPMASKREG|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65174, 504},
    /*  65 : MOV kreg32,reg32 [rm:       evex.l0.0f.f2.w0 92 /r            ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 250(f1 7f 08) 300 001(92) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_MOV, 2, {OPMASKREG|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+29736, 505},
    /*  66 : MOV kreg64,reg64 [rm:       vex.l0.0f.f2.w1 92 /r            ] ND,ZU,LONG,PROT,AVX512BW,X86_64 */
        /* 270(001 203) 001(92) 110 : NOAPX,ZU,LONG,VEX,PROT,AVX512BW,X86_64 */
        {I_MOV, 2, {OPMASKREG|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65181, 506},
    /*  67 : MOV kreg64,reg64 [rm:       evex.l0.0f.f2.w1 92 /r            ] ND,ZU,LONG,PROT,AVX512BW,X86_64,APX */
        /* 250(f1 ff 08) 300 001(92) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,X86_64 */
        {I_MOV, 2, {OPMASKREG|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+29745, 507},
    /*  68 : MOV reg32,kreg32 [rm:       vex.l0.0f.f2.w0 93 /r            ] ND,ZU,AVX512BW,FUTURE */
        /* 270(001 003) 001(93) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_MOV, 2, {REG_GPR|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65188, 504},
    /*  69 : MOV reg32,kreg32 [rm:       evex.l0.0f.f2.w0 93 /r            ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 250(f1 7f 08) 300 001(93) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_MOV, 2, {REG_GPR|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+29754, 505},
    /*  70 : MOV reg64,kreg64 [rm:       vex.l0.0f.f2.w1 93 /r            ] ND,ZU,LONG,PROT,AVX512BW,X86_64 */
        /* 270(001 203) 001(93) 110 : NOAPX,ZU,LONG,VEX,PROT,AVX512BW,X86_64 */
        {I_MOV, 2, {REG_GPR|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65195, 506},
    /*  71 : MOV reg64,kreg64 [rm:       evex.l0.0f.f2.w1 93 /r            ] ND,ZU,LONG,PROT,AVX512BW,X86_64,APX */
        /* 250(f1 ff 08) 300 001(93) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,X86_64 */
        {I_MOV, 2, {REG_GPR|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+29763, 507},
    /*  72 : MOV kreg8,reg32 [rm:       vex.l0.0f.66.w0 92 /r            ] ND,ZU,AVX512DQ,FUTURE */
        /* 270(001 001) 001(92) 110 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_MOV, 2, {OPMASKREG|BITS8|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65202, 500},
    /*  73 : MOV kreg8,reg32 [rm:       evex.l0.0f.66.w0 92 /r            ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 250(f1 7d 08) 300 001(92) 110 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_MOV, 2, {OPMASKREG|BITS8,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+29772, 501},
    /*  74 : MOV kreg8,reg8 [rm:       vex.l0.0f.66.w0 92 /r            ] ND,ZU,AVX512DQ,FUTURE */
        /* 270(001 001) 001(92) 110 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_MOV, 2, {OPMASKREG|BITS8|RN_L16,REG_GPR|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65202, 500},
    /*  75 : MOV kreg8,reg8 [rm:       evex.l0.0f.66.w0 92 /r            ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 250(f1 7d 08) 300 001(92) 110 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_MOV, 2, {OPMASKREG|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+29772, 501},
    /*  76 : MOV kreg16,reg32 [rm:       vex.l0.0f.np.w0 92 /r            ] ND,ZU,AVX512F,FUTURE */
        /* 270(001 000) 001(92) 110 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_MOV, 2, {OPMASKREG|BITS16|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65209, 502},
    /*  77 : MOV kreg16,reg32 [rm:       evex.l0.0f.np.w0 92 /r            ] ND,ZU,AVX512F,FUTURE,APX */
        /* 250(f1 7c 08) 300 001(92) 110 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_MOV, 2, {OPMASKREG|BITS16,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+29781, 503},
    /*  78 : MOV kreg16,reg16 [rm:       vex.l0.0f.np.w0 92 /r            ] ND,ZU,AVX512F,FUTURE */
        /* 270(001 000) 001(92) 110 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_MOV, 2, {OPMASKREG|BITS16|RN_L16,REG_GPR|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65209, 502},
    /*  79 : MOV kreg16,reg16 [rm:       evex.l0.0f.np.w0 92 /r            ] ND,ZU,AVX512F,FUTURE,APX */
        /* 250(f1 7c 08) 300 001(92) 110 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_MOV, 2, {OPMASKREG|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29781, 503},
    /*  80 : MOV reg32,kreg8 [rm:       vex.l0.0f.66.w0 93 /r            ] ND,ZU,AVX512DQ,FUTURE */
        /* 270(001 001) 001(93) 110 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_MOV, 2, {REG_GPR|BITS32|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65216, 500},
    /*  81 : MOV reg32,kreg8 [rm:       evex.l0.0f.66.w0 93 /r            ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 250(f1 7d 08) 300 001(93) 110 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_MOV, 2, {REG_GPR|BITS32,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+29790, 501},
    /*  82 : MOV reg32,kreg16 [rm:       vex.l0.0f.np.w0 93 /r            ] ND,ZU,AVX512F,FUTURE */
        /* 270(001 000) 001(93) 110 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_MOV, 2, {REG_GPR|BITS32|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65223, 502},
    /*  83 : MOV reg32,kreg16 [rm:       evex.l0.0f.np.w0 93 /r            ] ND,ZU,AVX512F,FUTURE,APX */
        /* 250(f1 7c 08) 300 001(93) 110 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_MOV, 2, {REG_GPR|BITS32,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29799, 503},
};

static const struct itemplate instrux_MOVABS[12] = {
    /*   0 : MOVABS reg_al,mem_offs [-i:       o8 a0 iwdq                        ] ND,SM0-1,NOAPX,8086 */
        /* 001(a0) 045 : SM0,SM1,NOAPX,8086 */
        {I_MOVABS, 2, {REG_AL|RN_L16,MEM_OFFS,0,0,0}, NO_DECORATOR, nasm_bytecodes+72433, 6},
    /*   1 : MOVABS reg_ax,mem_offs [-i:       o16 a1 iwdq                       ] ND,SM0-1,NOAPX,8086 */
        /* 320 001(a1) 045 : SM0,SM1,NOAPX,8086 */
        {I_MOVABS, 2, {REG_AX|RN_L16,MEM_OFFS,0,0,0}, NO_DECORATOR, nasm_bytecodes+71168, 6},
    /*   2 : MOVABS reg_eax,mem_offs [-i:       o32 a1 iwdq                       ] ND,SM0-1,NOAPX,ZU,386 */
        /* 321 001(a1) 045 : SM0,SM1,NOAPX,ZU,386 */
        {I_MOVABS, 2, {REG_EAX|RN_L16,MEM_OFFS,0,0,0}, NO_DECORATOR, nasm_bytecodes+71173, 7},
    /*   3 : MOVABS reg_rax,mem_offs [-i:       o64 a1 iwdq                       ] ND,SM0-1,NOAPX,ZU,LONG,PROT,X86_64 */
        /* 324 001(a1) 045 : SM0,SM1,NOAPX,ZU,LONG,PROT,X86_64 */
        {I_MOVABS, 2, {REG_RAX|RN_L16,MEM_OFFS,0,0,0}, NO_DECORATOR, nasm_bytecodes+71178, 8},
    /*   4 : MOVABS mem_offs,reg_al [i-:       o8 a2 iwdq                        ] ND,SM0-1,NOAPX,NOHLE,8086 */
        /* 001(a2) 044 : SM0,SM1,NOAPX,NOHLE,8086 */
        {I_MOVABS, 2, {MEM_OFFS,REG_AL|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+72437, 9},
    /*   5 : MOVABS mem_offs,reg_ax [i-:       o16 a3 iwdq                       ] ND,SM0-1,NOAPX,NOHLE,8086 */
        /* 320 001(a3) 044 : SM0,SM1,NOAPX,NOHLE,8086 */
        {I_MOVABS, 2, {MEM_OFFS,REG_AX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+71183, 9},
    /*   6 : MOVABS mem_offs,reg_eax [i-:       o32 a3 iwdq                       ] ND,SM0-1,NOAPX,NOHLE,386 */
        /* 321 001(a3) 044 : SM0,SM1,NOAPX,NOHLE,386 */
        {I_MOVABS, 2, {MEM_OFFS,REG_EAX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+71188, 10},
    /*   7 : MOVABS mem_offs,reg_rax [i-:       o64 a3 iwdq                       ] ND,SM0-1,NOAPX,LONG,NOHLE,PROT,X86_64 */
        /* 324 001(a3) 044 : SM0,SM1,NOAPX,LONG,NOHLE,PROT,X86_64 */
        {I_MOVABS, 2, {MEM_OFFS,REG_RAX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+71193, 11},
    /*   8 : MOVABS reg8,imm8 [ri:       o8 b0+r ib                        ] ND,SM0-1,8086 */
        /* 010 260(021  : SM0,SM1,8086 */
        {I_MOVABS, 2, {REG_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+72441, 12},
    /*   9 : MOVABS reg16,imm16 [ri:       o16 b8+r iw                       ] ND,SM0-1,8086 */
        /* 320 010 270(031  : SM0,SM1,8086 */
        {I_MOVABS, 2, {REG_GPR|BITS16,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+71208, 12},
    /*  10 : MOVABS reg32,imm32 [ri:       o32 b8+r id                       ] ND,SM0-1,386 */
        /* 321 010 270(041  : SM0,SM1,386 */
        {I_MOVABS, 2, {REG_GPR|BITS32,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+71213, 13},
    /*  11 : MOVABS reg64,imm64 [ri:       o64 b8+r iq                       ] ND,SM0-1,LONG,PROT,X86_64 */
        /* 324 010 270(055  : SM0,SM1,LONG,PROT,X86_64 */
        {I_MOVABS, 2, {REG_GPR|BITS64,IMM_NORMAL|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+71218, 14},
};

static const struct itemplate instrux_MOVRS[8] = {
    /*   0 : MOVRS reg8,mem8 [rm:       o8 norep 0f38 8a /r               ] SM0-1,FUTURE */
        /* 331 356 001(8a) 110 : SM0,SM1,NOAPX,FUTURE */
        {I_MOVRS, 2, {REG_GPR|BITS8|RN_L16,MEMORY|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66278, 17},
    /*   1 : MOVRS reg16,mem16 [rm:       o16 norep 0f38 8b /r              ] SM0-1,FUTURE */
        /* 320 331 356 001(8b) 110 : SM0,SM1,NOAPX,FUTURE */
        {I_MOVRS, 2, {REG_GPR|BITS16|RN_L16,MEMORY|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+54730, 17},
    /*   2 : MOVRS reg32,mem32 [rm:       o32 norep 0f38 8b /r              ] SM0-1,FUTURE */
        /* 321 331 356 001(8b) 110 : SM0,SM1,NOAPX,FUTURE */
        {I_MOVRS, 2, {REG_GPR|BITS32|RN_L16,MEMORY|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+54737, 17},
    /*   3 : MOVRS reg64,mem64 [rm:       o64 norep 0f38 8b /r              ] SM0-1,LONG,PROT,X86_64,FUTURE */
        /* 324 331 356 001(8b) 110 : SM0,SM1,NOAPX,LONG,PROT,FUTURE */
        {I_MOVRS, 2, {REG_GPR|BITS64|RN_L16,MEMORY|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+54744, 18},
    /*   4 : MOVRS reg8,mem8 [rm:       evex.nf0.nd0.l0.m4.o8 8a /r       ] SM0-1,FUTURE */
        /* 250(f4 7c 08) 300 001(8a) 110 : SM0,SM1,WIG,EVEX,PROT,FUTURE */
        {I_MOVRS, 2, {REG_GPR|BITS8,MEMORY|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+23373, 19},
    /*   5 : MOVRS reg16,mem16 [rm:       evex.nf0.nd0.l0.m4.o16 8b /r      ] SM0-1,FUTURE */
        /* 250(f4 7d 08) 300 320 001(8b) 110 : SM0,SM1,EVEX,PROT,FUTURE */
        {I_MOVRS, 2, {REG_GPR|BITS16,MEMORY|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+9143, 20},
    /*   6 : MOVRS reg32,mem32 [rm:       evex.nf0.nd0.l0.m4.o32 8b /r      ] SM0-1,FUTURE */
        /* 250(f4 7c 08) 300 321 001(8b) 110 : SM0,SM1,WW,EVEX,PROT,FUTURE */
        {I_MOVRS, 2, {REG_GPR|BITS32,MEMORY|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+9153, 21},
    /*   7 : MOVRS reg64,mem64 [rm:       evex.nf0.nd0.l0.m4.o64 8b /r      ] SM0-1,LONG,PROT,X86_64,FUTURE */
        /* 250(f4 fc 08) 300 324 001(8b) 110 : SM0,SM1,WW,LONG,EVEX,PROT,FUTURE */
        {I_MOVRS, 2, {REG_GPR|BITS64,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+9163, 22},
};

static const struct itemplate instrux_LEA[6] = {
    /*   0 : LEA reg16,mem [rm:       o16 8d /r                         ] 8086 */
        /* 320 001(8d) 110 : 8086 */
        {I_LEA, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+71223, 23},
    /*   1 : LEA reg32,mem [rm:       o32 8d /r                         ] 386 */
        /* 321 001(8d) 110 : 386 */
        {I_LEA, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+71228, 3},
    /*   2 : LEA reg64,mem [rm:       o64 8d /r                         ] LONG,PROT,X86_64 */
        /* 324 001(8d) 110 : LONG,PROT,X86_64 */
        {I_LEA, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+71233, 24},
    /*   3 : LEA reg16,imm16 [rn:       o16 8d /r                         ] ND,8086 */
        /* 320 001(8d) 110 : 8086 */
        {I_LEA, 2, {REG_GPR|BITS16,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+71223, 23},
    /*   4 : LEA reg32,imm32 [rn:       o32 8d /r                         ] ND,386 */
        /* 321 001(8d) 110 : 386 */
        {I_LEA, 2, {REG_GPR|BITS32,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+71228, 3},
    /*   5 : LEA reg64,sdword64 [rn:       o64 8d /r                         ] ND,LONG,PROT,X86_64 */
        /* 324 001(8d) 110 : LONG,PROT,X86_64 */
        {I_LEA, 2, {REG_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+71233, 24},
};

static const struct itemplate instrux_ADD[80] = {
    /*   0 : ADD rm8,reg8 [mr:       hle o8 00 /r                      ] SM0-1,LOCK,FL,8086 */
        /* 273 001(00) 101 : SM0,SM1,LOCK,FL,8086 */
        {I_ADD, 2, {RM_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+71238, 25},
    /*   1 : ADD rm16,reg16 [mr:       hle o16 01 /r                     ] SM0-1,LOCK,FL,8086 */
        /* 273 320 001(01) 101 : SM0,SM1,LOCK,FL,8086 */
        {I_ADD, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66284, 25},
    /*   2 : ADD rm32,reg32 [mr:       hle o32 01 /r                     ] SM0-1,LOCK,FL,386 */
        /* 273 321 001(01) 101 : SM0,SM1,LOCK,FL,386 */
        {I_ADD, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+66290, 26},
    /*   3 : ADD rm64,reg64 [mr:       hle o64 01 /r                     ] SM0-1,LOCK,LONG,FL,PROT,X86_64 */
        /* 273 324 001(01) 101 : SM0,SM1,LOCK,LONG,FL,PROT,X86_64 */
        {I_ADD, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+66296, 27},
    /*   4 : ADD reg8,rm8 [rm:       o8 02 /r                          ] SM0-1,FL,8086 */
        /* 001(02) 110 : SM0,SM1,FL,8086 */
        {I_ADD, 2, {REG_GPR|BITS8,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+69388, 28},
    /*   5 : ADD reg16,rm16 [rm:       o16 03 /r                         ] SM0-1,FL,8086 */
        /* 320 001(03) 110 : SM0,SM1,FL,8086 */
        {I_ADD, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+9198, 28},
    /*   6 : ADD reg32,rm32 [rm:       o32 03 /r                         ] SM0-1,FL,386 */
        /* 321 001(03) 110 : SM0,SM1,FL,386 */
        {I_ADD, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+9228, 29},
    /*   7 : ADD reg64,rm64 [rm:       o64 03 /r                         ] SM0-1,LONG,FL,PROT,X86_64 */
        /* 324 001(03) 110 : SM0,SM1,LONG,FL,PROT,X86_64 */
        {I_ADD, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+9258, 30},
    /*   8 : ADD rm16,sbyteword16 [mi:       hle o16 83 /0 ib,s                ] SM0-1,LOCK,FL,8086 */
        /* 273 320 001(83) 200 275 : SM0,SM1,LOCK,FL,8086 */
        {I_ADD, 2, {RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+54751, 25},
    /*   9 : ADD rm32,sbytedword32 [mi:       hle o32 83 /0 ib,s                ] SM0-1,LOCK,FL,386 */
        /* 273 321 001(83) 200 275 : SM0,SM1,LOCK,FL,386 */
        {I_ADD, 2, {RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+54758, 26},
    /*  10 : ADD rm64,sbytedword64 [mi:       hle o64 83 /0 ib,s                ] SM0-1,LOCK,LONG,FL,PROT,X86_64 */
        /* 273 324 001(83) 200 275 : SM0,SM1,LOCK,LONG,FL,PROT,X86_64 */
        {I_ADD, 2, {RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+54765, 27},
    /*  11 : ADD reg_al,imm8 [-i:       o8 04 ib                          ] SM0-1,FL,8086 */
        /* 001(04) 021 : SM0,SM1,FL,8086 */
        {I_ADD, 2, {REG_AL,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+72445, 28},
    /*  12 : ADD reg_ax,imm16 [-i:       o16 05 iw                         ] SM0-1,FL,8086 */
        /* 320 001(05) 031 : SM0,SM1,FL,8086 */
        {I_ADD, 2, {REG_AX,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+71243, 28},
    /*  13 : ADD reg_eax,imm32 [-i:       o32 05 id                         ] SM0-1,ZU,FL,386 */
        /* 321 001(05) 041 : SM0,SM1,ZU,FL,386 */
        {I_ADD, 2, {REG_EAX,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+71248, 31},
    /*  14 : ADD reg_rax,sdword64 [-i:       o64 05 id,s                       ] SM0-1,ZU,LONG,FL,PROT,X86_64 */
        /* 324 001(05) 255 : SM0,SM1,ZU,LONG,FL,PROT,X86_64 */
        {I_ADD, 2, {REG_RAX,SDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+71253, 32},
    /*  15 : ADD rm8,imm8 [mi:       hle o8 80 /0 ib                   ] SM0-1,LOCK,FL,8086 */
        /* 273 001(80) 200 021 : SM0,SM1,LOCK,FL,8086 */
        {I_ADD, 2, {RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+66302, 25},
    /*  16 : ADD rm16,imm16 [mi:       hle o16 81 /0 iw                  ] SM0-1,LOCK,FL,8086 */
        /* 273 320 001(81) 200 031 : SM0,SM1,LOCK,FL,8086 */
        {I_ADD, 2, {RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+54772, 25},
    /*  17 : ADD rm32,imm32 [mi:       hle o32 81 /0 id                  ] SM0-1,LOCK,FL,386 */
        /* 273 321 001(81) 200 041 : SM0,SM1,LOCK,FL,386 */
        {I_ADD, 2, {RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+54779, 26},
    /*  18 : ADD rm64,sdword64 [mi:       hle o64 81 /0 id,s                ] SM0-1,LOCK,LONG,FL,PROT,X86_64 */
        /* 273 324 001(81) 200 255 : SM0,SM1,LOCK,LONG,FL,PROT,X86_64 */
        {I_ADD, 2, {RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+54786, 27},
    /*  19 : ADD reg8?,reg8,rm8 [vrm:      evex.nd1.nf.l0.m4.o8 02 /r        ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(02) 121 : SM0,SM1,SM2,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 3, {REG_GPR|BITS8,REG_GPR|BITS8,RM_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+23382, 33},
    /*  20 : ADD reg8,rm8 [rm:      evex.nd0.nf.l0.m4.o8 02 /r        ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(02) 110 : SM0,SM1,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 2, {REG_GPR|BITS8,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+23391, 34},
    /*  21 : ADD reg8?,rm8 [v+rm:      evex.nd1.nf.l0.m4.o8 02 /r        ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(02) 110 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 2, {REG_GPR|BITS8,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+23400, 35},
    /*  22 : ADD reg16?,reg16,rm16 [vrm:      evex.nd1.nf.l0.m4.o16 03 /r       ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(03) 121 : SM0,SM1,SM2,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+9173, 36},
    /*  23 : ADD reg16,rm16 [rm:      evex.nd0.nf.l0.m4.o16 03 /r       ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(03) 110 : SM0,SM1,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+9183, 37},
    /*  24 : ADD reg16?,rm16 [v+rm:      evex.nd1.nf.l0.m4.o16 03 /r       ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(03) 110 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+9193, 38},
    /*  25 : ADD reg32?,reg32,rm32 [vrm:      evex.nd1.nf.l0.m4.o32 03 /r       ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(03) 121 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+9203, 39},
    /*  26 : ADD reg32,rm32 [rm:      evex.nd0.nf.l0.m4.o32 03 /r       ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(03) 110 : SM0,SM1,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+9213, 40},
    /*  27 : ADD reg32?,rm32 [v+rm:      evex.nd1.nf.l0.m4.o32 03 /r       ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(03) 110 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+9223, 41},
    /*  28 : ADD reg64?,reg64,rm64 [vrm:      evex.nd1.nf.l0.m4.o64 03 /r       ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(03) 121 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+9233, 39},
    /*  29 : ADD reg64,rm64 [rm:      evex.nd0.nf.l0.m4.o64 03 /r       ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(03) 110 : SM0,SM1,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+9243, 40},
    /*  30 : ADD reg64?,rm64 [v+rm:      evex.nd1.nf.l0.m4.o64 03 /r       ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(03) 110 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+9253, 41},
    /*  31 : ADD reg8?,rm8,reg8 [vmr:      evex.nd1.nf.l0.m4.o8 00 /r        ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(00) 112 : SM0,SM1,SM2,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 3, {REG_GPR|BITS8,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+23409, 33},
    /*  32 : ADD rm8,reg8 [mr:      evex.nd0.nf.l0.m4.o8 00 /r        ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(00) 101 : SM0,SM1,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 2, {RM_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+23418, 34},
    /*  33 : ADD reg8?,reg8 [v+mr:      evex.nd1.nf.l0.m4.o8 00 /r        ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(00) 101 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+23427, 35},
    /*  34 : ADD reg16?,rm16,reg16 [vmr:      evex.nd1.nf.l0.m4.o16 01 /r       ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(01) 112 : SM0,SM1,SM2,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 3, {REG_GPR|BITS16,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+9263, 36},
    /*  35 : ADD rm16,reg16 [mr:      evex.nd0.nf.l0.m4.o16 01 /r       ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(01) 101 : SM0,SM1,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+9273, 37},
    /*  36 : ADD reg16?,reg16 [v+mr:      evex.nd1.nf.l0.m4.o16 01 /r       ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(01) 101 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+9283, 38},
    /*  37 : ADD reg32?,rm32,reg32 [vmr:      evex.nd1.nf.l0.m4.o32 01 /r       ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(01) 112 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+9293, 39},
    /*  38 : ADD rm32,reg32 [mr:      evex.nd0.nf.l0.m4.o32 01 /r       ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(01) 101 : SM0,SM1,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+9303, 40},
    /*  39 : ADD reg32?,reg32 [v+mr:      evex.nd1.nf.l0.m4.o32 01 /r       ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(01) 101 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+9313, 41},
    /*  40 : ADD reg64?,rm64,reg64 [vmr:      evex.nd1.nf.l0.m4.o64 01 /r       ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(01) 112 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+9323, 39},
    /*  41 : ADD rm64,reg64 [mr:      evex.nd0.nf.l0.m4.o64 01 /r       ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(01) 101 : SM0,SM1,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+9333, 40},
    /*  42 : ADD reg64?,reg64 [v+mr:      evex.nd1.nf.l0.m4.o64 01 /r       ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(01) 101 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+9343, 41},
    /*  43 : ADD reg16?,rm16,sbyteword16 [vmi:      evex.nd1.nf.l0.m4.o16 83 /0 ib,s  ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(83) 210 276 : SM0,SM1,SM2,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 3, {REG_GPR|BITS16,RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+24, 36},
    /*  44 : ADD rm16,sbyteword16 [mi:      evex.nd0.nf.l0.m4.o16 83 /0 ib,s  ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(83) 200 275 : SM0,SM1,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 2, {RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+35, 37},
    /*  45 : ADD reg16?,sbyteword16 [v+mi:      evex.nd1.nf.l0.m4.o16 83 /0 ib,s  ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(83) 200 275 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 2, {REG_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+46, 38},
    /*  46 : ADD reg32?,rm32,sbytedword32 [vmi:      evex.nd1.nf.l0.m4.o32 83 /0 ib,s  ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(83) 210 276 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 3, {REG_GPR|BITS32,RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+57, 39},
    /*  47 : ADD rm32,sbytedword32 [mi:      evex.nd0.nf.l0.m4.o32 83 /0 ib,s  ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(83) 200 275 : SM0,SM1,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 2, {RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+68, 40},
    /*  48 : ADD reg32?,sbytedword32 [v+mi:      evex.nd1.nf.l0.m4.o32 83 /0 ib,s  ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(83) 200 275 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 2, {REG_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+79, 41},
    /*  49 : ADD reg64?,rm64,sbytedword64 [vmi:      evex.nd1.nf.l0.m4.o64 83 /0 ib,s  ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(83) 210 276 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 3, {REG_GPR|BITS64,RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+90, 39},
    /*  50 : ADD rm64,sbytedword64 [mi:      evex.nd0.nf.l0.m4.o64 83 /0 ib,s  ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(83) 200 275 : SM0,SM1,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 2, {RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+101, 40},
    /*  51 : ADD reg64?,sbytedword64 [v+mi:      evex.nd1.nf.l0.m4.o64 83 /0 ib,s  ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(83) 200 275 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 2, {REG_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+112, 41},
    /*  52 : ADD reg8?,rm8,imm8 [vmi:      evex.nd1.nf.l0.m4.o8 80 /0 ib     ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(80) 210 022 : SM0,SM1,SM2,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 3, {REG_GPR|BITS8,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9353, 33},
    /*  53 : ADD rm8,imm8 [mi:      evex.nd0.nf.l0.m4.o8 80 /0 ib     ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(80) 200 021 : SM0,SM1,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 2, {RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+9363, 34},
    /*  54 : ADD reg8?,imm8 [v+mi:      evex.nd1.nf.l0.m4.o8 80 /0 ib     ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(80) 200 021 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 2, {REG_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+9373, 35},
    /*  55 : ADD reg16?,rm16,imm16 [vmi:      evex.nd1.nf.l0.m4.o16 81 /0 iw    ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(81) 210 032 : SM0,SM1,SM2,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 3, {REG_GPR|BITS16,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+123, 36},
    /*  56 : ADD rm16,imm16 [mi:      evex.nd0.nf.l0.m4.o16 81 /0 iw    ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(81) 200 031 : SM0,SM1,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 2, {RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+134, 37},
    /*  57 : ADD reg16?,imm16 [v+mi:      evex.nd1.nf.l0.m4.o16 81 /0 iw    ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(81) 200 031 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 2, {REG_GPR|BITS16,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+145, 38},
    /*  58 : ADD reg32?,rm32,imm32 [vmi:      evex.nd1.nf.l0.m4.o32 81 /0 id    ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(81) 210 042 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 3, {REG_GPR|BITS32,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+156, 39},
    /*  59 : ADD rm32,imm32 [mi:      evex.nd0.nf.l0.m4.o32 81 /0 id    ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(81) 200 041 : SM0,SM1,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 2, {RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+167, 40},
    /*  60 : ADD reg32?,imm32 [v+mi:      evex.nd1.nf.l0.m4.o32 81 /0 id    ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(81) 200 041 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 2, {REG_GPR|BITS32,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+178, 41},
    /*  61 : ADD reg64?,rm64,sdword64 [vmi:      evex.nd1.nf.l0.m4.o64 81 /0 id,s  ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(81) 210 256 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 3, {REG_GPR|BITS64,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+189, 39},
    /*  62 : ADD rm64,sdword64 [mi:      evex.nd0.nf.l0.m4.o64 81 /0 id,s  ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(81) 200 255 : SM0,SM1,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 2, {RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+200, 40},
    /*  63 : ADD reg64?,sdword64 [v+mi:      evex.nd1.nf.l0.m4.o64 81 /0 id,s  ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(81) 200 255 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADD, 2, {REG_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+211, 41},
    /*  64 : ADD kreg8,kreg8*,kreg8 [rvm:      vex.l1.0f.ko8 4a /r              ] ND,SM0,SM1,SM2,ZU,FL,AVX512DQ,FUTURE */
        /* 261(001 005) 001(4a) 120 : SM0,SM1,SM2,NOAPX,ZU,FL,VEX,AVX512DQ,FUTURE */
        {I_ADD, 3, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65230, 516},
    /*  65 : ADD kreg8,kreg8*,kreg8 [rvm:      evex.l1.0f.ko8 4a /r              ] ND,SM0,SM1,SM2,ZU,FL,AVX512DQ,FUTURE,APX */
        /* 241(f1 7d 28) 300 001(4a) 120 : SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_ADD, 3, {OPMASKREG|BITS8,OPMASKREG|BITS8,OPMASKREG|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+29808, 517},
    /*  66 : ADD kreg8,kreg8 [r+vm:      vex.l1.0f.ko8 4a /r              ] ND,SM0,SM1,ZU,FL,AVX512DQ,FUTURE */
        /* 260(001 005) 001(4a) 110 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512DQ,FUTURE */
        {I_ADD, 2, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65237, 518},
    /*  67 : ADD kreg8,kreg8 [r+vm:      evex.l1.0f.ko8 4a /r              ] ND,SM0,SM1,ZU,FL,AVX512DQ,FUTURE,APX */
        /* 240(f1 7d 28) 300 001(4a) 110 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_ADD, 2, {OPMASKREG|BITS8,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+29817, 519},
    /*  68 : ADD kreg16,kreg16*,kreg16 [rvm:      vex.l1.0f.ko16 4a /r             ] ND,SM0,SM1,SM2,ZU,FL,AVX512DQ,FUTURE */
        /* 261(001 004) 001(4a) 120 : SM0,SM1,SM2,NOAPX,ZU,FL,VEX,AVX512DQ,FUTURE */
        {I_ADD, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65244, 516},
    /*  69 : ADD kreg16,kreg16*,kreg16 [rvm:      evex.l1.0f.ko16 4a /r             ] ND,SM0,SM1,SM2,ZU,FL,AVX512DQ,FUTURE,APX */
        /* 241(f1 7c 28) 300 001(4a) 120 : SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_ADD, 3, {OPMASKREG|BITS16,OPMASKREG|BITS16,OPMASKREG|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+29826, 517},
    /*  70 : ADD kreg16,kreg16 [r+vm:      vex.l1.0f.ko16 4a /r             ] ND,SM0,SM1,ZU,FL,AVX512DQ,FUTURE */
        /* 260(001 004) 001(4a) 110 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512DQ,FUTURE */
        {I_ADD, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65251, 518},
    /*  71 : ADD kreg16,kreg16 [r+vm:      evex.l1.0f.ko16 4a /r             ] ND,SM0,SM1,ZU,FL,AVX512DQ,FUTURE,APX */
        /* 240(f1 7c 28) 300 001(4a) 110 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_ADD, 2, {OPMASKREG|BITS16,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29835, 519},
    /*  72 : ADD kreg32,kreg32*,kreg32 [rvm:      vex.l1.0f.ko32 4a /r             ] ND,SM0,SM1,SM2,ZU,FL,AVX512BW,FUTURE */
        /* 261(001 205) 001(4a) 120 : SM0,SM1,SM2,NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_ADD, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65258, 520},
    /*  73 : ADD kreg32,kreg32*,kreg32 [rvm:      evex.l1.0f.ko32 4a /r             ] ND,SM0,SM1,SM2,ZU,FL,AVX512BW,FUTURE,APX */
        /* 241(f1 fd 28) 300 001(4a) 120 : SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_ADD, 3, {OPMASKREG|BITS32,OPMASKREG|BITS32,OPMASKREG|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+29844, 521},
    /*  74 : ADD kreg32,kreg32 [r+vm:      vex.l1.0f.ko32 4a /r             ] ND,SM0,SM1,ZU,FL,AVX512BW,FUTURE */
        /* 260(001 205) 001(4a) 110 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_ADD, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65265, 522},
    /*  75 : ADD kreg32,kreg32 [r+vm:      evex.l1.0f.ko32 4a /r             ] ND,SM0,SM1,ZU,FL,AVX512BW,FUTURE,APX */
        /* 240(f1 fd 28) 300 001(4a) 110 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_ADD, 2, {OPMASKREG|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+29853, 523},
    /*  76 : ADD kreg64,kreg64*,kreg64 [rvm:      vex.l1.0f.ko64 4a /r             ] ND,SM0,SM1,SM2,ZU,FL,AVX512BW,FUTURE */
        /* 261(001 204) 001(4a) 120 : SM0,SM1,SM2,NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_ADD, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65272, 520},
    /*  77 : ADD kreg64,kreg64*,kreg64 [rvm:      evex.l1.0f.ko64 4a /r             ] ND,SM0,SM1,SM2,ZU,FL,AVX512BW,FUTURE,APX */
        /* 241(f1 fc 28) 300 001(4a) 120 : SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_ADD, 3, {OPMASKREG|BITS64,OPMASKREG|BITS64,OPMASKREG|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+29862, 521},
    /*  78 : ADD kreg64,kreg64 [r+vm:      vex.l1.0f.ko64 4a /r             ] ND,SM0,SM1,ZU,FL,AVX512BW,FUTURE */
        /* 260(001 204) 001(4a) 110 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_ADD, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65279, 522},
    /*  79 : ADD kreg64,kreg64 [r+vm:      evex.l1.0f.ko64 4a /r             ] ND,SM0,SM1,ZU,FL,AVX512BW,FUTURE,APX */
        /* 240(f1 fc 28) 300 001(4a) 110 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_ADD, 2, {OPMASKREG|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+29871, 523},
};

static const struct itemplate instrux_OR[80] = {
    /*   0 : OR rm8,reg8 [mr:       hle o8 08 /r                      ] SM0-1,LOCK,FL,8086 */
        /* 273 001(08) 101 : SM0,SM1,LOCK,FL,8086 */
        {I_OR, 2, {RM_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+71258, 25},
    /*   1 : OR rm16,reg16 [mr:       hle o16 09 /r                     ] SM0-1,LOCK,FL,8086 */
        /* 273 320 001(09) 101 : SM0,SM1,LOCK,FL,8086 */
        {I_OR, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66308, 25},
    /*   2 : OR rm32,reg32 [mr:       hle o32 09 /r                     ] SM0-1,LOCK,FL,386 */
        /* 273 321 001(09) 101 : SM0,SM1,LOCK,FL,386 */
        {I_OR, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+66314, 26},
    /*   3 : OR rm64,reg64 [mr:       hle o64 09 /r                     ] SM0-1,LOCK,LONG,FL,PROT,X86_64 */
        /* 273 324 001(09) 101 : SM0,SM1,LOCK,LONG,FL,PROT,X86_64 */
        {I_OR, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+66320, 27},
    /*   4 : OR reg8,rm8 [rm:       o8 0a /r                          ] SM0-1,FL,8086 */
        /* 001(0a) 110 : SM0,SM1,FL,8086 */
        {I_OR, 2, {REG_GPR|BITS8,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+69508, 28},
    /*   5 : OR reg16,rm16 [rm:       o16 0b /r                         ] SM0-1,FL,8086 */
        /* 320 001(0b) 110 : SM0,SM1,FL,8086 */
        {I_OR, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+9408, 28},
    /*   6 : OR reg32,rm32 [rm:       o32 0b /r                         ] SM0-1,FL,386 */
        /* 321 001(0b) 110 : SM0,SM1,FL,386 */
        {I_OR, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+9438, 29},
    /*   7 : OR reg64,rm64 [rm:       o64 0b /r                         ] SM0-1,LONG,FL,PROT,X86_64 */
        /* 324 001(0b) 110 : SM0,SM1,LONG,FL,PROT,X86_64 */
        {I_OR, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+9468, 30},
    /*   8 : OR rm16,sbyteword16 [mi:       hle o16 83 /1 ib,s                ] SM0-1,LOCK,FL,8086 */
        /* 273 320 001(83) 201 275 : SM0,SM1,LOCK,FL,8086 */
        {I_OR, 2, {RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+54793, 25},
    /*   9 : OR rm32,sbytedword32 [mi:       hle o32 83 /1 ib,s                ] SM0-1,LOCK,FL,386 */
        /* 273 321 001(83) 201 275 : SM0,SM1,LOCK,FL,386 */
        {I_OR, 2, {RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+54800, 26},
    /*  10 : OR rm64,sbytedword64 [mi:       hle o64 83 /1 ib,s                ] SM0-1,LOCK,LONG,FL,PROT,X86_64 */
        /* 273 324 001(83) 201 275 : SM0,SM1,LOCK,LONG,FL,PROT,X86_64 */
        {I_OR, 2, {RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+54807, 27},
    /*  11 : OR reg_al,imm8 [-i:       o8 0c ib                          ] SM0-1,FL,8086 */
        /* 001(0c) 021 : SM0,SM1,FL,8086 */
        {I_OR, 2, {REG_AL,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+72449, 28},
    /*  12 : OR reg_ax,imm16 [-i:       o16 0d iw                         ] SM0-1,FL,8086 */
        /* 320 001(0d) 031 : SM0,SM1,FL,8086 */
        {I_OR, 2, {REG_AX,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+71263, 28},
    /*  13 : OR reg_eax,imm32 [-i:       o32 0d id                         ] SM0-1,ZU,FL,386 */
        /* 321 001(0d) 041 : SM0,SM1,ZU,FL,386 */
        {I_OR, 2, {REG_EAX,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+71268, 31},
    /*  14 : OR reg_rax,sdword64 [-i:       o64 0d id,s                       ] SM0-1,ZU,LONG,FL,PROT,X86_64 */
        /* 324 001(0d) 255 : SM0,SM1,ZU,LONG,FL,PROT,X86_64 */
        {I_OR, 2, {REG_RAX,SDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+71273, 32},
    /*  15 : OR rm8,imm8 [mi:       hle o8 80 /1 ib                   ] SM0-1,LOCK,FL,8086 */
        /* 273 001(80) 201 021 : SM0,SM1,LOCK,FL,8086 */
        {I_OR, 2, {RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+66326, 25},
    /*  16 : OR rm16,imm16 [mi:       hle o16 81 /1 iw                  ] SM0-1,LOCK,FL,8086 */
        /* 273 320 001(81) 201 031 : SM0,SM1,LOCK,FL,8086 */
        {I_OR, 2, {RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+54814, 25},
    /*  17 : OR rm32,imm32 [mi:       hle o32 81 /1 id                  ] SM0-1,LOCK,FL,386 */
        /* 273 321 001(81) 201 041 : SM0,SM1,LOCK,FL,386 */
        {I_OR, 2, {RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+54821, 26},
    /*  18 : OR rm64,sdword64 [mi:       hle o64 81 /1 id,s                ] SM0-1,LOCK,LONG,FL,PROT,X86_64 */
        /* 273 324 001(81) 201 255 : SM0,SM1,LOCK,LONG,FL,PROT,X86_64 */
        {I_OR, 2, {RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+54828, 27},
    /*  19 : OR reg8?,reg8,rm8 [vrm:      evex.nd1.nf.l0.m4.o8 0a /r        ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(0a) 121 : SM0,SM1,SM2,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 3, {REG_GPR|BITS8,REG_GPR|BITS8,RM_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+23436, 33},
    /*  20 : OR reg8,rm8 [rm:      evex.nd0.nf.l0.m4.o8 0a /r        ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(0a) 110 : SM0,SM1,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 2, {REG_GPR|BITS8,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+23445, 34},
    /*  21 : OR reg8?,rm8 [v+rm:      evex.nd1.nf.l0.m4.o8 0a /r        ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(0a) 110 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 2, {REG_GPR|BITS8,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+23454, 35},
    /*  22 : OR reg16?,reg16,rm16 [vrm:      evex.nd1.nf.l0.m4.o16 0b /r       ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(0b) 121 : SM0,SM1,SM2,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+9383, 36},
    /*  23 : OR reg16,rm16 [rm:      evex.nd0.nf.l0.m4.o16 0b /r       ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(0b) 110 : SM0,SM1,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+9393, 37},
    /*  24 : OR reg16?,rm16 [v+rm:      evex.nd1.nf.l0.m4.o16 0b /r       ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(0b) 110 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+9403, 38},
    /*  25 : OR reg32?,reg32,rm32 [vrm:      evex.nd1.nf.l0.m4.o32 0b /r       ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(0b) 121 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+9413, 39},
    /*  26 : OR reg32,rm32 [rm:      evex.nd0.nf.l0.m4.o32 0b /r       ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(0b) 110 : SM0,SM1,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+9423, 40},
    /*  27 : OR reg32?,rm32 [v+rm:      evex.nd1.nf.l0.m4.o32 0b /r       ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(0b) 110 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+9433, 41},
    /*  28 : OR reg64?,reg64,rm64 [vrm:      evex.nd1.nf.l0.m4.o64 0b /r       ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(0b) 121 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+9443, 39},
    /*  29 : OR reg64,rm64 [rm:      evex.nd0.nf.l0.m4.o64 0b /r       ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(0b) 110 : SM0,SM1,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+9453, 40},
    /*  30 : OR reg64?,rm64 [v+rm:      evex.nd1.nf.l0.m4.o64 0b /r       ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(0b) 110 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+9463, 41},
    /*  31 : OR reg8?,rm8,reg8 [vmr:      evex.nd1.nf.l0.m4.o8 08 /r        ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(08) 112 : SM0,SM1,SM2,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 3, {REG_GPR|BITS8,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+23463, 33},
    /*  32 : OR rm8,reg8 [mr:      evex.nd0.nf.l0.m4.o8 08 /r        ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(08) 101 : SM0,SM1,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 2, {RM_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+23472, 34},
    /*  33 : OR reg8?,reg8 [v+mr:      evex.nd1.nf.l0.m4.o8 08 /r        ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(08) 101 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+23481, 35},
    /*  34 : OR reg16?,rm16,reg16 [vmr:      evex.nd1.nf.l0.m4.o16 09 /r       ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(09) 112 : SM0,SM1,SM2,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 3, {REG_GPR|BITS16,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+9473, 36},
    /*  35 : OR rm16,reg16 [mr:      evex.nd0.nf.l0.m4.o16 09 /r       ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(09) 101 : SM0,SM1,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+9483, 37},
    /*  36 : OR reg16?,reg16 [v+mr:      evex.nd1.nf.l0.m4.o16 09 /r       ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(09) 101 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+9493, 38},
    /*  37 : OR reg32?,rm32,reg32 [vmr:      evex.nd1.nf.l0.m4.o32 09 /r       ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(09) 112 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+9503, 39},
    /*  38 : OR rm32,reg32 [mr:      evex.nd0.nf.l0.m4.o32 09 /r       ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(09) 101 : SM0,SM1,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+9513, 40},
    /*  39 : OR reg32?,reg32 [v+mr:      evex.nd1.nf.l0.m4.o32 09 /r       ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(09) 101 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+9523, 41},
    /*  40 : OR reg64?,rm64,reg64 [vmr:      evex.nd1.nf.l0.m4.o64 09 /r       ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(09) 112 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+9533, 39},
    /*  41 : OR rm64,reg64 [mr:      evex.nd0.nf.l0.m4.o64 09 /r       ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(09) 101 : SM0,SM1,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+9543, 40},
    /*  42 : OR reg64?,reg64 [v+mr:      evex.nd1.nf.l0.m4.o64 09 /r       ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(09) 101 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+9553, 41},
    /*  43 : OR reg16?,rm16,sbyteword16 [vmi:      evex.nd1.nf.l0.m4.o16 83 /1 ib,s  ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(83) 211 276 : SM0,SM1,SM2,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 3, {REG_GPR|BITS16,RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+222, 36},
    /*  44 : OR rm16,sbyteword16 [mi:      evex.nd0.nf.l0.m4.o16 83 /1 ib,s  ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(83) 201 275 : SM0,SM1,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 2, {RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+233, 37},
    /*  45 : OR reg16?,sbyteword16 [v+mi:      evex.nd1.nf.l0.m4.o16 83 /1 ib,s  ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(83) 201 275 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 2, {REG_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+244, 38},
    /*  46 : OR reg32?,rm32,sbytedword32 [vmi:      evex.nd1.nf.l0.m4.o32 83 /1 ib,s  ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(83) 211 276 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+255, 39},
    /*  47 : OR rm32,sbytedword32 [mi:      evex.nd0.nf.l0.m4.o32 83 /1 ib,s  ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(83) 201 275 : SM0,SM1,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 2, {RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+266, 40},
    /*  48 : OR reg32?,sbytedword32 [v+mi:      evex.nd1.nf.l0.m4.o32 83 /1 ib,s  ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(83) 201 275 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 2, {REG_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+277, 41},
    /*  49 : OR reg64?,rm64,sbytedword64 [vmi:      evex.nd1.nf.l0.m4.o64 83 /1 ib,s  ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(83) 211 276 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+288, 39},
    /*  50 : OR rm64,sbytedword64 [mi:      evex.nd0.nf.l0.m4.o64 83 /1 ib,s  ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(83) 201 275 : SM0,SM1,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 2, {RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+299, 40},
    /*  51 : OR reg64?,sbytedword64 [v+mi:      evex.nd1.nf.l0.m4.o64 83 /1 ib,s  ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(83) 201 275 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 2, {REG_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+310, 41},
    /*  52 : OR reg8?,rm8,imm8 [vmi:      evex.nd1.nf.l0.m4.o8 80 /1 ib     ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(80) 211 022 : SM0,SM1,SM2,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 3, {REG_GPR|BITS8,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9563, 33},
    /*  53 : OR rm8,imm8 [mi:      evex.nd0.nf.l0.m4.o8 80 /1 ib     ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(80) 201 021 : SM0,SM1,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 2, {RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+9573, 34},
    /*  54 : OR reg8?,imm8 [v+mi:      evex.nd1.nf.l0.m4.o8 80 /1 ib     ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(80) 201 021 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 2, {REG_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+9583, 35},
    /*  55 : OR reg16?,rm16,imm16 [vmi:      evex.nd1.nf.l0.m4.o16 81 /1 iw    ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(81) 211 032 : SM0,SM1,SM2,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 3, {REG_GPR|BITS16,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+321, 36},
    /*  56 : OR rm16,imm16 [mi:      evex.nd0.nf.l0.m4.o16 81 /1 iw    ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(81) 201 031 : SM0,SM1,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 2, {RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+332, 37},
    /*  57 : OR reg16?,imm16 [v+mi:      evex.nd1.nf.l0.m4.o16 81 /1 iw    ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(81) 201 031 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 2, {REG_GPR|BITS16,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+343, 38},
    /*  58 : OR reg32?,rm32,imm32 [vmi:      evex.nd1.nf.l0.m4.o32 81 /1 id    ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(81) 211 042 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+354, 39},
    /*  59 : OR rm32,imm32 [mi:      evex.nd0.nf.l0.m4.o32 81 /1 id    ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(81) 201 041 : SM0,SM1,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 2, {RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+365, 40},
    /*  60 : OR reg32?,imm32 [v+mi:      evex.nd1.nf.l0.m4.o32 81 /1 id    ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(81) 201 041 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 2, {REG_GPR|BITS32,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+376, 41},
    /*  61 : OR reg64?,rm64,sdword64 [vmi:      evex.nd1.nf.l0.m4.o64 81 /1 id,s  ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(81) 211 256 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+387, 39},
    /*  62 : OR rm64,sdword64 [mi:      evex.nd0.nf.l0.m4.o64 81 /1 id,s  ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(81) 201 255 : SM0,SM1,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 2, {RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+398, 40},
    /*  63 : OR reg64?,sdword64 [v+mi:      evex.nd1.nf.l0.m4.o64 81 /1 id,s  ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(81) 201 255 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_OR, 2, {REG_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+409, 41},
    /*  64 : OR kreg8,kreg8*,kreg8 [rvm:      vex.nds.l1.0f.ko8 45 /r          ] ND,SM0,SM1,SM2,ZU,FL,AVX512DQ,FUTURE */
        /* 261(001 005) 001(45) 120 : SM0,SM1,SM2,NOAPX,ZU,FL,VEX,AVX512DQ,FUTURE */
        {I_OR, 3, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65454, 516},
    /*  65 : OR kreg8,kreg8*,kreg8 [rvm:      evex.nds.l1.0f.ko8 45 /r          ] ND,SM0,SM1,SM2,ZU,FL,AVX512DQ,FUTURE,APX */
        /* 241(f1 7d 28) 300 001(45) 120 : SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_OR, 3, {OPMASKREG|BITS8,OPMASKREG|BITS8,OPMASKREG|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+30096, 517},
    /*  66 : OR kreg8,kreg8 [r+vm:      vex.nds.l1.0f.ko8 45 /r          ] ND,SM0,SM1,ZU,FL,AVX512DQ,FUTURE */
        /* 260(001 005) 001(45) 110 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512DQ,FUTURE */
        {I_OR, 2, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65461, 518},
    /*  67 : OR kreg8,kreg8 [r+vm:      evex.nds.l1.0f.ko8 45 /r          ] ND,SM0,SM1,ZU,FL,AVX512DQ,FUTURE,APX */
        /* 240(f1 7d 28) 300 001(45) 110 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_OR, 2, {OPMASKREG|BITS8,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+30105, 519},
    /*  68 : OR kreg16,kreg16*,kreg16 [rvm:      vex.nds.l1.0f.ko16 45 /r         ] ND,SM0,SM1,SM2,ZU,FL,AVX512F,FUTURE */
        /* 261(001 004) 001(45) 120 : SM0,SM1,SM2,NOAPX,ZU,FL,VEX,AVX512F,FUTURE */
        {I_OR, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65468, 528},
    /*  69 : OR kreg16,kreg16*,kreg16 [rvm:      evex.nds.l1.0f.ko16 45 /r         ] ND,SM0,SM1,SM2,ZU,FL,AVX512F,FUTURE,APX */
        /* 241(f1 7c 28) 300 001(45) 120 : SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_OR, 3, {OPMASKREG|BITS16,OPMASKREG|BITS16,OPMASKREG|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+30114, 529},
    /*  70 : OR kreg16,kreg16 [r+vm:      vex.nds.l1.0f.ko16 45 /r         ] ND,SM0,SM1,ZU,FL,AVX512F,FUTURE */
        /* 260(001 004) 001(45) 110 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512F,FUTURE */
        {I_OR, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65475, 530},
    /*  71 : OR kreg16,kreg16 [r+vm:      evex.nds.l1.0f.ko16 45 /r         ] ND,SM0,SM1,ZU,FL,AVX512F,FUTURE,APX */
        /* 240(f1 7c 28) 300 001(45) 110 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_OR, 2, {OPMASKREG|BITS16,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+30123, 531},
    /*  72 : OR kreg32,kreg32*,kreg32 [rvm:      vex.nds.l1.0f.ko32 45 /r         ] ND,SM0,SM1,SM2,ZU,FL,AVX512BW,FUTURE */
        /* 261(001 205) 001(45) 120 : SM0,SM1,SM2,NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_OR, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65482, 520},
    /*  73 : OR kreg32,kreg32*,kreg32 [rvm:      evex.nds.l1.0f.ko32 45 /r         ] ND,SM0,SM1,SM2,ZU,FL,AVX512BW,FUTURE,APX */
        /* 241(f1 fd 28) 300 001(45) 120 : SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_OR, 3, {OPMASKREG|BITS32,OPMASKREG|BITS32,OPMASKREG|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+30132, 521},
    /*  74 : OR kreg32,kreg32 [r+vm:      vex.nds.l1.0f.ko32 45 /r         ] ND,SM0,SM1,ZU,FL,AVX512BW,FUTURE */
        /* 260(001 205) 001(45) 110 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_OR, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65489, 522},
    /*  75 : OR kreg32,kreg32 [r+vm:      evex.nds.l1.0f.ko32 45 /r         ] ND,SM0,SM1,ZU,FL,AVX512BW,FUTURE,APX */
        /* 240(f1 fd 28) 300 001(45) 110 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_OR, 2, {OPMASKREG|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+30141, 523},
    /*  76 : OR kreg64,kreg64*,kreg64 [rvm:      vex.nds.l1.0f.ko64 45 /r         ] ND,SM0,SM1,SM2,ZU,FL,AVX512BW,FUTURE */
        /* 261(001 204) 001(45) 120 : SM0,SM1,SM2,NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_OR, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65496, 520},
    /*  77 : OR kreg64,kreg64*,kreg64 [rvm:      evex.nds.l1.0f.ko64 45 /r         ] ND,SM0,SM1,SM2,ZU,FL,AVX512BW,FUTURE,APX */
        /* 241(f1 fc 28) 300 001(45) 120 : SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_OR, 3, {OPMASKREG|BITS64,OPMASKREG|BITS64,OPMASKREG|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+30150, 521},
    /*  78 : OR kreg64,kreg64 [r+vm:      vex.nds.l1.0f.ko64 45 /r         ] ND,SM0,SM1,ZU,FL,AVX512BW,FUTURE */
        /* 260(001 204) 001(45) 110 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_OR, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65503, 522},
    /*  79 : OR kreg64,kreg64 [r+vm:      evex.nds.l1.0f.ko64 45 /r         ] ND,SM0,SM1,ZU,FL,AVX512BW,FUTURE,APX */
        /* 240(f1 fc 28) 300 001(45) 110 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_OR, 2, {OPMASKREG|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+30159, 523},
};

static const struct itemplate instrux_ADC[64] = {
    /*   0 : ADC rm8,reg8 [mr:       hle o8 10 /r                      ] SM0-1,LOCK,FL,8086 */
        /* 273 001(10) 101 : SM0,SM1,LOCK,FL,8086 */
        {I_ADC, 2, {RM_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+71278, 25},
    /*   1 : ADC rm16,reg16 [mr:       hle o16 11 /r                     ] SM0-1,LOCK,FL,8086 */
        /* 273 320 001(11) 101 : SM0,SM1,LOCK,FL,8086 */
        {I_ADC, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66332, 25},
    /*   2 : ADC rm32,reg32 [mr:       hle o32 11 /r                     ] SM0-1,LOCK,FL,386 */
        /* 273 321 001(11) 101 : SM0,SM1,LOCK,FL,386 */
        {I_ADC, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+66338, 26},
    /*   3 : ADC rm64,reg64 [mr:       hle o64 11 /r                     ] SM0-1,LOCK,LONG,FL,PROT,X86_64 */
        /* 273 324 001(11) 101 : SM0,SM1,LOCK,LONG,FL,PROT,X86_64 */
        {I_ADC, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+66344, 27},
    /*   4 : ADC reg8,rm8 [rm:       o8 12 /r                          ] SM0-1,FL,8086 */
        /* 001(12) 110 : SM0,SM1,FL,8086 */
        {I_ADC, 2, {REG_GPR|BITS8,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+69286, 28},
    /*   5 : ADC reg16,rm16 [rm:       o16 13 /r                         ] SM0-1,FL,8086 */
        /* 320 001(13) 110 : SM0,SM1,FL,8086 */
        {I_ADC, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+9618, 28},
    /*   6 : ADC reg32,rm32 [rm:       o32 13 /r                         ] SM0-1,FL,386 */
        /* 321 001(13) 110 : SM0,SM1,FL,386 */
        {I_ADC, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+9648, 29},
    /*   7 : ADC reg64,rm64 [rm:       o64 13 /r                         ] SM0-1,LONG,FL,PROT,X86_64 */
        /* 324 001(13) 110 : SM0,SM1,LONG,FL,PROT,X86_64 */
        {I_ADC, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+9678, 30},
    /*   8 : ADC rm16,sbyteword16 [mi:       hle o16 83 /2 ib,s                ] SM0-1,LOCK,FL,8086 */
        /* 273 320 001(83) 202 275 : SM0,SM1,LOCK,FL,8086 */
        {I_ADC, 2, {RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+54835, 25},
    /*   9 : ADC rm32,sbytedword32 [mi:       hle o32 83 /2 ib,s                ] SM0-1,LOCK,FL,386 */
        /* 273 321 001(83) 202 275 : SM0,SM1,LOCK,FL,386 */
        {I_ADC, 2, {RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+54842, 26},
    /*  10 : ADC rm64,sbytedword64 [mi:       hle o64 83 /2 ib,s                ] SM0-1,LOCK,LONG,FL,PROT,X86_64 */
        /* 273 324 001(83) 202 275 : SM0,SM1,LOCK,LONG,FL,PROT,X86_64 */
        {I_ADC, 2, {RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+54849, 27},
    /*  11 : ADC reg_al,imm8 [-i:       o8 14 ib                          ] SM0-1,FL,8086 */
        /* 001(14) 021 : SM0,SM1,FL,8086 */
        {I_ADC, 2, {REG_AL,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+72453, 28},
    /*  12 : ADC reg_ax,imm16 [-i:       o16 15 iw                         ] SM0-1,FL,8086 */
        /* 320 001(15) 031 : SM0,SM1,FL,8086 */
        {I_ADC, 2, {REG_AX,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+71283, 28},
    /*  13 : ADC reg_eax,imm32 [-i:       o32 15 id                         ] SM0-1,ZU,FL,386 */
        /* 321 001(15) 041 : SM0,SM1,ZU,FL,386 */
        {I_ADC, 2, {REG_EAX,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+71288, 31},
    /*  14 : ADC reg_rax,sdword64 [-i:       o64 15 id,s                       ] SM0-1,ZU,LONG,FL,PROT,X86_64 */
        /* 324 001(15) 255 : SM0,SM1,ZU,LONG,FL,PROT,X86_64 */
        {I_ADC, 2, {REG_RAX,SDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+71293, 32},
    /*  15 : ADC rm8,imm8 [mi:       hle o8 80 /2 ib                   ] SM0-1,LOCK,FL,8086 */
        /* 273 001(80) 202 021 : SM0,SM1,LOCK,FL,8086 */
        {I_ADC, 2, {RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+66350, 25},
    /*  16 : ADC rm16,imm16 [mi:       hle o16 81 /2 iw                  ] SM0-1,LOCK,FL,8086 */
        /* 273 320 001(81) 202 031 : SM0,SM1,LOCK,FL,8086 */
        {I_ADC, 2, {RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+54856, 25},
    /*  17 : ADC rm32,imm32 [mi:       hle o32 81 /2 id                  ] SM0-1,LOCK,FL,386 */
        /* 273 321 001(81) 202 041 : SM0,SM1,LOCK,FL,386 */
        {I_ADC, 2, {RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+54863, 26},
    /*  18 : ADC rm64,sdword64 [mi:       hle o64 81 /2 id,s                ] SM0-1,LOCK,LONG,FL,PROT,X86_64 */
        /* 273 324 001(81) 202 255 : SM0,SM1,LOCK,LONG,FL,PROT,X86_64 */
        {I_ADC, 2, {RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+54870, 27},
    /*  19 : ADC reg8?,reg8,rm8 [vrm:      evex.nd1..l0.m4.o8 12 /r          ] SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(12) 121 : SM0,SM1,SM2,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 3, {REG_GPR|BITS8,REG_GPR|BITS8,RM_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+23490, 42},
    /*  20 : ADC reg8,rm8 [rm:      evex.nd0..l0.m4.o8 12 /r          ] SM0,SM1,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(12) 110 : SM0,SM1,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 2, {REG_GPR|BITS8,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+23499, 43},
    /*  21 : ADC reg8?,rm8 [v+rm:      evex.nd1..l0.m4.o8 12 /r          ] ND,SM0,SM1,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(12) 110 : SM0,SM1,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 2, {REG_GPR|BITS8,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+23508, 44},
    /*  22 : ADC reg16?,reg16,rm16 [vrm:      evex.nd1..l0.m4.o16 13 /r         ] SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(13) 121 : SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+9593, 45},
    /*  23 : ADC reg16,rm16 [rm:      evex.nd0..l0.m4.o16 13 /r         ] SM0,SM1,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(13) 110 : SM0,SM1,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+9603, 46},
    /*  24 : ADC reg16?,rm16 [v+rm:      evex.nd1..l0.m4.o16 13 /r         ] ND,SM0,SM1,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(13) 110 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+9613, 47},
    /*  25 : ADC reg32?,reg32,rm32 [vrm:      evex.nd1..l0.m4.o32 13 /r         ] SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(13) 121 : SM0,SM1,SM2,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+9623, 48},
    /*  26 : ADC reg32,rm32 [rm:      evex.nd0..l0.m4.o32 13 /r         ] SM0,SM1,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(13) 110 : SM0,SM1,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+9633, 49},
    /*  27 : ADC reg32?,rm32 [v+rm:      evex.nd1..l0.m4.o32 13 /r         ] ND,SM0,SM1,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(13) 110 : SM0,SM1,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+9643, 50},
    /*  28 : ADC reg64?,reg64,rm64 [vrm:      evex.nd1..l0.m4.o64 13 /r         ] SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(13) 121 : SM0,SM1,SM2,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+9653, 48},
    /*  29 : ADC reg64,rm64 [rm:      evex.nd0..l0.m4.o64 13 /r         ] SM0,SM1,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(13) 110 : SM0,SM1,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+9663, 49},
    /*  30 : ADC reg64?,rm64 [v+rm:      evex.nd1..l0.m4.o64 13 /r         ] ND,SM0,SM1,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(13) 110 : SM0,SM1,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+9673, 50},
    /*  31 : ADC reg8?,rm8,reg8 [vmr:      evex.nd1..l0.m4.o8 10 /r          ] SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(10) 112 : SM0,SM1,SM2,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 3, {REG_GPR|BITS8,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+23517, 42},
    /*  32 : ADC rm8,reg8 [mr:      evex.nd0..l0.m4.o8 10 /r          ] SM0,SM1,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(10) 101 : SM0,SM1,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 2, {RM_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+23526, 43},
    /*  33 : ADC reg8?,reg8 [v+mr:      evex.nd1..l0.m4.o8 10 /r          ] ND,SM0,SM1,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(10) 101 : SM0,SM1,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+23535, 44},
    /*  34 : ADC reg16?,rm16,reg16 [vmr:      evex.nd1..l0.m4.o16 11 /r         ] SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(11) 112 : SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 3, {REG_GPR|BITS16,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+9683, 45},
    /*  35 : ADC rm16,reg16 [mr:      evex.nd0..l0.m4.o16 11 /r         ] SM0,SM1,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(11) 101 : SM0,SM1,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+9693, 46},
    /*  36 : ADC reg16?,reg16 [v+mr:      evex.nd1..l0.m4.o16 11 /r         ] ND,SM0,SM1,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(11) 101 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+9703, 47},
    /*  37 : ADC reg32?,rm32,reg32 [vmr:      evex.nd1..l0.m4.o32 11 /r         ] SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(11) 112 : SM0,SM1,SM2,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+9713, 48},
    /*  38 : ADC rm32,reg32 [mr:      evex.nd0..l0.m4.o32 11 /r         ] SM0,SM1,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(11) 101 : SM0,SM1,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+9723, 49},
    /*  39 : ADC reg32?,reg32 [v+mr:      evex.nd1..l0.m4.o32 11 /r         ] ND,SM0,SM1,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(11) 101 : SM0,SM1,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+9733, 50},
    /*  40 : ADC reg64?,rm64,reg64 [vmr:      evex.nd1..l0.m4.o64 11 /r         ] SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(11) 112 : SM0,SM1,SM2,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+9743, 48},
    /*  41 : ADC rm64,reg64 [mr:      evex.nd0..l0.m4.o64 11 /r         ] SM0,SM1,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(11) 101 : SM0,SM1,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+9753, 49},
    /*  42 : ADC reg64?,reg64 [v+mr:      evex.nd1..l0.m4.o64 11 /r         ] ND,SM0,SM1,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(11) 101 : SM0,SM1,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+9763, 50},
    /*  43 : ADC reg16?,rm16,sbyteword16 [vmi:      evex.nd1..l0.m4.o16 83 /2 ib,s    ] SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(83) 212 276 : SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 3, {REG_GPR|BITS16,RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+420, 45},
    /*  44 : ADC rm16,sbyteword16 [mi:      evex.nd0..l0.m4.o16 83 /2 ib,s    ] SM0,SM1,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(83) 202 275 : SM0,SM1,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 2, {RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+431, 46},
    /*  45 : ADC reg16?,sbyteword16 [v+mi:      evex.nd1..l0.m4.o16 83 /2 ib,s    ] ND,SM0,SM1,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(83) 202 275 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 2, {REG_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+442, 47},
    /*  46 : ADC reg32?,rm32,sbytedword32 [vmi:      evex.nd1..l0.m4.o32 83 /2 ib,s    ] SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(83) 212 276 : SM0,SM1,SM2,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 3, {REG_GPR|BITS32,RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+453, 48},
    /*  47 : ADC rm32,sbytedword32 [mi:      evex.nd0..l0.m4.o32 83 /2 ib,s    ] SM0,SM1,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(83) 202 275 : SM0,SM1,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 2, {RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+464, 49},
    /*  48 : ADC reg32?,sbytedword32 [v+mi:      evex.nd1..l0.m4.o32 83 /2 ib,s    ] ND,SM0,SM1,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(83) 202 275 : SM0,SM1,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 2, {REG_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+475, 50},
    /*  49 : ADC reg64?,rm64,sbytedword64 [vmi:      evex.nd1..l0.m4.o64 83 /2 ib,s    ] SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(83) 212 276 : SM0,SM1,SM2,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 3, {REG_GPR|BITS64,RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+486, 48},
    /*  50 : ADC rm64,sbytedword64 [mi:      evex.nd0..l0.m4.o64 83 /2 ib,s    ] SM0,SM1,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(83) 202 275 : SM0,SM1,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 2, {RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+497, 49},
    /*  51 : ADC reg64?,sbytedword64 [v+mi:      evex.nd1..l0.m4.o64 83 /2 ib,s    ] ND,SM0,SM1,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(83) 202 275 : SM0,SM1,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 2, {REG_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+508, 50},
    /*  52 : ADC reg8?,rm8,imm8 [vmi:      evex.nd1..l0.m4.o8 80 /2 ib       ] SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(80) 212 022 : SM0,SM1,SM2,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 3, {REG_GPR|BITS8,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9773, 42},
    /*  53 : ADC rm8,imm8 [mi:      evex.nd0..l0.m4.o8 80 /2 ib       ] SM0,SM1,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(80) 202 021 : SM0,SM1,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 2, {RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+9783, 43},
    /*  54 : ADC reg8?,imm8 [v+mi:      evex.nd1..l0.m4.o8 80 /2 ib       ] ND,SM0,SM1,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(80) 202 021 : SM0,SM1,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 2, {REG_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+9793, 44},
    /*  55 : ADC reg16?,rm16,imm16 [vmi:      evex.nd1..l0.m4.o16 81 /2 iw      ] SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(81) 212 032 : SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 3, {REG_GPR|BITS16,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+519, 45},
    /*  56 : ADC rm16,imm16 [mi:      evex.nd0..l0.m4.o16 81 /2 iw      ] SM0,SM1,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(81) 202 031 : SM0,SM1,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 2, {RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+530, 46},
    /*  57 : ADC reg16?,imm16 [v+mi:      evex.nd1..l0.m4.o16 81 /2 iw      ] ND,SM0,SM1,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(81) 202 031 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 2, {REG_GPR|BITS16,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+541, 47},
    /*  58 : ADC reg32?,rm32,imm32 [vmi:      evex.nd1..l0.m4.o32 81 /2 id      ] SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(81) 212 042 : SM0,SM1,SM2,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 3, {REG_GPR|BITS32,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+552, 48},
    /*  59 : ADC rm32,imm32 [mi:      evex.nd0..l0.m4.o32 81 /2 id      ] SM0,SM1,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(81) 202 041 : SM0,SM1,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 2, {RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+563, 49},
    /*  60 : ADC reg32?,imm32 [v+mi:      evex.nd1..l0.m4.o32 81 /2 id      ] ND,SM0,SM1,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(81) 202 041 : SM0,SM1,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 2, {REG_GPR|BITS32,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+574, 50},
    /*  61 : ADC reg64?,rm64,sdword64 [vmi:      evex.nd1..l0.m4.o64 81 /2 id,s    ] SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(81) 212 256 : SM0,SM1,SM2,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 3, {REG_GPR|BITS64,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+585, 48},
    /*  62 : ADC rm64,sdword64 [mi:      evex.nd0..l0.m4.o64 81 /2 id,s    ] SM0,SM1,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(81) 202 255 : SM0,SM1,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 2, {RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+596, 49},
    /*  63 : ADC reg64?,sdword64 [v+mi:      evex.nd1..l0.m4.o64 81 /2 id,s    ] ND,SM0,SM1,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(81) 202 255 : SM0,SM1,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ADC, 2, {REG_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+607, 50},
};

static const struct itemplate instrux_SBB[64] = {
    /*   0 : SBB rm8,reg8 [mr:       hle o8 18 /r                      ] SM0-1,LOCK,FL,8086 */
        /* 273 001(18) 101 : SM0,SM1,LOCK,FL,8086 */
        {I_SBB, 2, {RM_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+71298, 25},
    /*   1 : SBB rm16,reg16 [mr:       hle o16 19 /r                     ] SM0-1,LOCK,FL,8086 */
        /* 273 320 001(19) 101 : SM0,SM1,LOCK,FL,8086 */
        {I_SBB, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66356, 25},
    /*   2 : SBB rm32,reg32 [mr:       hle o32 19 /r                     ] SM0-1,LOCK,FL,386 */
        /* 273 321 001(19) 101 : SM0,SM1,LOCK,FL,386 */
        {I_SBB, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+66362, 26},
    /*   3 : SBB rm64,reg64 [mr:       hle o64 19 /r                     ] SM0-1,LOCK,LONG,FL,PROT,X86_64 */
        /* 273 324 001(19) 101 : SM0,SM1,LOCK,LONG,FL,PROT,X86_64 */
        {I_SBB, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+66368, 27},
    /*   4 : SBB reg8,rm8 [rm:       o8 1a /r                          ] SM0-1,FL,8086 */
        /* 001(1a) 110 : SM0,SM1,FL,8086 */
        {I_SBB, 2, {REG_GPR|BITS8,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+69880, 28},
    /*   5 : SBB reg16,rm16 [rm:       o16 1b /r                         ] SM0-1,FL,8086 */
        /* 320 001(1b) 110 : SM0,SM1,FL,8086 */
        {I_SBB, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+9828, 28},
    /*   6 : SBB reg32,rm32 [rm:       o32 1b /r                         ] SM0-1,FL,386 */
        /* 321 001(1b) 110 : SM0,SM1,FL,386 */
        {I_SBB, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+9858, 29},
    /*   7 : SBB reg64,rm64 [rm:       o64 1b /r                         ] SM0-1,LONG,FL,PROT,X86_64 */
        /* 324 001(1b) 110 : SM0,SM1,LONG,FL,PROT,X86_64 */
        {I_SBB, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+9888, 30},
    /*   8 : SBB rm16,sbyteword16 [mi:       hle o16 83 /3 ib,s                ] SM0-1,LOCK,FL,8086 */
        /* 273 320 001(83) 203 275 : SM0,SM1,LOCK,FL,8086 */
        {I_SBB, 2, {RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+54877, 25},
    /*   9 : SBB rm32,sbytedword32 [mi:       hle o32 83 /3 ib,s                ] SM0-1,LOCK,FL,386 */
        /* 273 321 001(83) 203 275 : SM0,SM1,LOCK,FL,386 */
        {I_SBB, 2, {RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+54884, 26},
    /*  10 : SBB rm64,sbytedword64 [mi:       hle o64 83 /3 ib,s                ] SM0-1,LOCK,LONG,FL,PROT,X86_64 */
        /* 273 324 001(83) 203 275 : SM0,SM1,LOCK,LONG,FL,PROT,X86_64 */
        {I_SBB, 2, {RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+54891, 27},
    /*  11 : SBB reg_al,imm8 [-i:       o8 1c ib                          ] SM0-1,FL,8086 */
        /* 001(1c) 021 : SM0,SM1,FL,8086 */
        {I_SBB, 2, {REG_AL,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+72457, 28},
    /*  12 : SBB reg_ax,imm16 [-i:       o16 1d iw                         ] SM0-1,FL,8086 */
        /* 320 001(1d) 031 : SM0,SM1,FL,8086 */
        {I_SBB, 2, {REG_AX,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+71303, 28},
    /*  13 : SBB reg_eax,imm32 [-i:       o32 1d id                         ] SM0-1,ZU,FL,386 */
        /* 321 001(1d) 041 : SM0,SM1,ZU,FL,386 */
        {I_SBB, 2, {REG_EAX,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+71308, 31},
    /*  14 : SBB reg_rax,sdword64 [-i:       o64 1d id,s                       ] SM0-1,ZU,LONG,FL,PROT,X86_64 */
        /* 324 001(1d) 255 : SM0,SM1,ZU,LONG,FL,PROT,X86_64 */
        {I_SBB, 2, {REG_RAX,SDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+71313, 32},
    /*  15 : SBB rm8,imm8 [mi:       hle o8 80 /3 ib                   ] SM0-1,LOCK,FL,8086 */
        /* 273 001(80) 203 021 : SM0,SM1,LOCK,FL,8086 */
        {I_SBB, 2, {RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+66374, 25},
    /*  16 : SBB rm16,imm16 [mi:       hle o16 81 /3 iw                  ] SM0-1,LOCK,FL,8086 */
        /* 273 320 001(81) 203 031 : SM0,SM1,LOCK,FL,8086 */
        {I_SBB, 2, {RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+54898, 25},
    /*  17 : SBB rm32,imm32 [mi:       hle o32 81 /3 id                  ] SM0-1,LOCK,FL,386 */
        /* 273 321 001(81) 203 041 : SM0,SM1,LOCK,FL,386 */
        {I_SBB, 2, {RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+54905, 26},
    /*  18 : SBB rm64,sdword64 [mi:       hle o64 81 /3 id,s                ] SM0-1,LOCK,LONG,FL,PROT,X86_64 */
        /* 273 324 001(81) 203 255 : SM0,SM1,LOCK,LONG,FL,PROT,X86_64 */
        {I_SBB, 2, {RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+54912, 27},
    /*  19 : SBB reg8?,reg8,rm8 [vrm:      evex.nd1..l0.m4.o8 1a /r          ] SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(1a) 121 : SM0,SM1,SM2,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 3, {REG_GPR|BITS8,REG_GPR|BITS8,RM_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+23544, 42},
    /*  20 : SBB reg8,rm8 [rm:      evex.nd0..l0.m4.o8 1a /r          ] SM0,SM1,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(1a) 110 : SM0,SM1,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 2, {REG_GPR|BITS8,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+23553, 43},
    /*  21 : SBB reg8?,rm8 [v+rm:      evex.nd1..l0.m4.o8 1a /r          ] ND,SM0,SM1,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(1a) 110 : SM0,SM1,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 2, {REG_GPR|BITS8,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+23562, 44},
    /*  22 : SBB reg16?,reg16,rm16 [vrm:      evex.nd1..l0.m4.o16 1b /r         ] SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(1b) 121 : SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+9803, 45},
    /*  23 : SBB reg16,rm16 [rm:      evex.nd0..l0.m4.o16 1b /r         ] SM0,SM1,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(1b) 110 : SM0,SM1,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+9813, 46},
    /*  24 : SBB reg16?,rm16 [v+rm:      evex.nd1..l0.m4.o16 1b /r         ] ND,SM0,SM1,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(1b) 110 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+9823, 47},
    /*  25 : SBB reg32?,reg32,rm32 [vrm:      evex.nd1..l0.m4.o32 1b /r         ] SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(1b) 121 : SM0,SM1,SM2,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+9833, 48},
    /*  26 : SBB reg32,rm32 [rm:      evex.nd0..l0.m4.o32 1b /r         ] SM0,SM1,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(1b) 110 : SM0,SM1,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+9843, 49},
    /*  27 : SBB reg32?,rm32 [v+rm:      evex.nd1..l0.m4.o32 1b /r         ] ND,SM0,SM1,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(1b) 110 : SM0,SM1,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+9853, 50},
    /*  28 : SBB reg64?,reg64,rm64 [vrm:      evex.nd1..l0.m4.o64 1b /r         ] SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(1b) 121 : SM0,SM1,SM2,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+9863, 48},
    /*  29 : SBB reg64,rm64 [rm:      evex.nd0..l0.m4.o64 1b /r         ] SM0,SM1,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(1b) 110 : SM0,SM1,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+9873, 49},
    /*  30 : SBB reg64?,rm64 [v+rm:      evex.nd1..l0.m4.o64 1b /r         ] ND,SM0,SM1,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(1b) 110 : SM0,SM1,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+9883, 50},
    /*  31 : SBB reg8?,rm8,reg8 [vmr:      evex.nd1..l0.m4.o8 18 /r          ] SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(18) 112 : SM0,SM1,SM2,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 3, {REG_GPR|BITS8,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+23571, 42},
    /*  32 : SBB rm8,reg8 [mr:      evex.nd0..l0.m4.o8 18 /r          ] SM0,SM1,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(18) 101 : SM0,SM1,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 2, {RM_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+23580, 43},
    /*  33 : SBB reg8?,reg8 [v+mr:      evex.nd1..l0.m4.o8 18 /r          ] ND,SM0,SM1,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(18) 101 : SM0,SM1,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+23589, 44},
    /*  34 : SBB reg16?,rm16,reg16 [vmr:      evex.nd1..l0.m4.o16 19 /r         ] SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(19) 112 : SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 3, {REG_GPR|BITS16,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+9893, 45},
    /*  35 : SBB rm16,reg16 [mr:      evex.nd0..l0.m4.o16 19 /r         ] SM0,SM1,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(19) 101 : SM0,SM1,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+9903, 46},
    /*  36 : SBB reg16?,reg16 [v+mr:      evex.nd1..l0.m4.o16 19 /r         ] ND,SM0,SM1,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(19) 101 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+9913, 47},
    /*  37 : SBB reg32?,rm32,reg32 [vmr:      evex.nd1..l0.m4.o32 19 /r         ] SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(19) 112 : SM0,SM1,SM2,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+9923, 48},
    /*  38 : SBB rm32,reg32 [mr:      evex.nd0..l0.m4.o32 19 /r         ] SM0,SM1,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(19) 101 : SM0,SM1,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+9933, 49},
    /*  39 : SBB reg32?,reg32 [v+mr:      evex.nd1..l0.m4.o32 19 /r         ] ND,SM0,SM1,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(19) 101 : SM0,SM1,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+9943, 50},
    /*  40 : SBB reg64?,rm64,reg64 [vmr:      evex.nd1..l0.m4.o64 19 /r         ] SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(19) 112 : SM0,SM1,SM2,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+9953, 48},
    /*  41 : SBB rm64,reg64 [mr:      evex.nd0..l0.m4.o64 19 /r         ] SM0,SM1,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(19) 101 : SM0,SM1,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+9963, 49},
    /*  42 : SBB reg64?,reg64 [v+mr:      evex.nd1..l0.m4.o64 19 /r         ] ND,SM0,SM1,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(19) 101 : SM0,SM1,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+9973, 50},
    /*  43 : SBB reg16?,rm16,sbyteword16 [vmi:      evex.nd1..l0.m4.o16 83 /3 ib,s    ] SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(83) 213 276 : SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 3, {REG_GPR|BITS16,RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+618, 45},
    /*  44 : SBB rm16,sbyteword16 [mi:      evex.nd0..l0.m4.o16 83 /3 ib,s    ] SM0,SM1,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(83) 203 275 : SM0,SM1,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 2, {RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+629, 46},
    /*  45 : SBB reg16?,sbyteword16 [v+mi:      evex.nd1..l0.m4.o16 83 /3 ib,s    ] ND,SM0,SM1,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(83) 203 275 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 2, {REG_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+640, 47},
    /*  46 : SBB reg32?,rm32,sbytedword32 [vmi:      evex.nd1..l0.m4.o32 83 /3 ib,s    ] SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(83) 213 276 : SM0,SM1,SM2,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 3, {REG_GPR|BITS32,RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+651, 48},
    /*  47 : SBB rm32,sbytedword32 [mi:      evex.nd0..l0.m4.o32 83 /3 ib,s    ] SM0,SM1,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(83) 203 275 : SM0,SM1,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 2, {RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+662, 49},
    /*  48 : SBB reg32?,sbytedword32 [v+mi:      evex.nd1..l0.m4.o32 83 /3 ib,s    ] ND,SM0,SM1,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(83) 203 275 : SM0,SM1,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 2, {REG_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+673, 50},
    /*  49 : SBB reg64?,rm64,sbytedword64 [vmi:      evex.nd1..l0.m4.o64 83 /3 ib,s    ] SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(83) 213 276 : SM0,SM1,SM2,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 3, {REG_GPR|BITS64,RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+684, 48},
    /*  50 : SBB rm64,sbytedword64 [mi:      evex.nd0..l0.m4.o64 83 /3 ib,s    ] SM0,SM1,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(83) 203 275 : SM0,SM1,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 2, {RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+695, 49},
    /*  51 : SBB reg64?,sbytedword64 [v+mi:      evex.nd1..l0.m4.o64 83 /3 ib,s    ] ND,SM0,SM1,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(83) 203 275 : SM0,SM1,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 2, {REG_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+706, 50},
    /*  52 : SBB reg8?,rm8,imm8 [vmi:      evex.nd1..l0.m4.o8 80 /3 ib       ] SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(80) 213 022 : SM0,SM1,SM2,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 3, {REG_GPR|BITS8,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9983, 42},
    /*  53 : SBB rm8,imm8 [mi:      evex.nd0..l0.m4.o8 80 /3 ib       ] SM0,SM1,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(80) 203 021 : SM0,SM1,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 2, {RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+9993, 43},
    /*  54 : SBB reg8?,imm8 [v+mi:      evex.nd1..l0.m4.o8 80 /3 ib       ] ND,SM0,SM1,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(80) 203 021 : SM0,SM1,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 2, {REG_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+10003, 44},
    /*  55 : SBB reg16?,rm16,imm16 [vmi:      evex.nd1..l0.m4.o16 81 /3 iw      ] SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(81) 213 032 : SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 3, {REG_GPR|BITS16,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+717, 45},
    /*  56 : SBB rm16,imm16 [mi:      evex.nd0..l0.m4.o16 81 /3 iw      ] SM0,SM1,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(81) 203 031 : SM0,SM1,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 2, {RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+728, 46},
    /*  57 : SBB reg16?,imm16 [v+mi:      evex.nd1..l0.m4.o16 81 /3 iw      ] ND,SM0,SM1,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(81) 203 031 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 2, {REG_GPR|BITS16,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+739, 47},
    /*  58 : SBB reg32?,rm32,imm32 [vmi:      evex.nd1..l0.m4.o32 81 /3 id      ] SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(81) 213 042 : SM0,SM1,SM2,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 3, {REG_GPR|BITS32,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+750, 48},
    /*  59 : SBB rm32,imm32 [mi:      evex.nd0..l0.m4.o32 81 /3 id      ] SM0,SM1,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(81) 203 041 : SM0,SM1,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 2, {RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+761, 49},
    /*  60 : SBB reg32?,imm32 [v+mi:      evex.nd1..l0.m4.o32 81 /3 id      ] ND,SM0,SM1,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(81) 203 041 : SM0,SM1,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 2, {REG_GPR|BITS32,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+772, 50},
    /*  61 : SBB reg64?,rm64,sdword64 [vmi:      evex.nd1..l0.m4.o64 81 /3 id,s    ] SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(81) 213 256 : SM0,SM1,SM2,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 3, {REG_GPR|BITS64,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+783, 48},
    /*  62 : SBB rm64,sdword64 [mi:      evex.nd0..l0.m4.o64 81 /3 id,s    ] SM0,SM1,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(81) 203 255 : SM0,SM1,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 2, {RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+794, 49},
    /*  63 : SBB reg64?,sdword64 [v+mi:      evex.nd1..l0.m4.o64 81 /3 id,s    ] ND,SM0,SM1,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(81) 203 255 : SM0,SM1,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SBB, 2, {REG_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+805, 50},
};

static const struct itemplate instrux_AND[80] = {
    /*   0 : AND rm8,reg8 [mr:       hle o8 20 /r                      ] SM0-1,LOCK,FL,8086 */
        /* 273 001(20) 101 : SM0,SM1,LOCK,FL,8086 */
        {I_AND, 2, {RM_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+71318, 25},
    /*   1 : AND rm16,reg16 [mr:       hle o16 21 /r                     ] SM0-1,LOCK,FL,8086 */
        /* 273 320 001(21) 101 : SM0,SM1,LOCK,FL,8086 */
        {I_AND, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66380, 25},
    /*   2 : AND rm32,reg32 [mr:       hle o32 21 /r                     ] SM0-1,LOCK,FL,386 */
        /* 273 321 001(21) 101 : SM0,SM1,LOCK,FL,386 */
        {I_AND, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+66386, 26},
    /*   3 : AND rm64,reg64 [mr:       hle o64 21 /r                     ] SM0-1,LOCK,LONG,FL,PROT,X86_64 */
        /* 273 324 001(21) 101 : SM0,SM1,LOCK,LONG,FL,PROT,X86_64 */
        {I_AND, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+66392, 27},
    /*   4 : AND reg8,rm8 [rm:       o8 22 /r                          ] SM0-1,FL,8086 */
        /* 001(22) 110 : SM0,SM1,FL,8086 */
        {I_AND, 2, {REG_GPR|BITS8,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+69640, 28},
    /*   5 : AND reg16,rm16 [rm:       o16 23 /r                         ] SM0-1,FL,8086 */
        /* 320 001(23) 110 : SM0,SM1,FL,8086 */
        {I_AND, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+10038, 28},
    /*   6 : AND reg32,rm32 [rm:       o32 23 /r                         ] SM0-1,FL,386 */
        /* 321 001(23) 110 : SM0,SM1,FL,386 */
        {I_AND, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+10068, 29},
    /*   7 : AND reg64,rm64 [rm:       o64 23 /r                         ] SM0-1,LONG,FL,PROT,X86_64 */
        /* 324 001(23) 110 : SM0,SM1,LONG,FL,PROT,X86_64 */
        {I_AND, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+10098, 30},
    /*   8 : AND rm16,sbyteword16 [mi:       hle o16 83 /4 ib,s                ] SM0-1,LOCK,FL,8086 */
        /* 273 320 001(83) 204 275 : SM0,SM1,LOCK,FL,8086 */
        {I_AND, 2, {RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+54919, 25},
    /*   9 : AND rm32,sbytedword32 [mi:       hle o32 83 /4 ib,s                ] SM0-1,LOCK,FL,386 */
        /* 273 321 001(83) 204 275 : SM0,SM1,LOCK,FL,386 */
        {I_AND, 2, {RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+54926, 26},
    /*  10 : AND rm64,sbytedword64 [mi:       hle o64 83 /4 ib,s                ] SM0-1,LOCK,LONG,FL,PROT,X86_64 */
        /* 273 324 001(83) 204 275 : SM0,SM1,LOCK,LONG,FL,PROT,X86_64 */
        {I_AND, 2, {RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+54933, 27},
    /*  11 : AND reg_al,imm8 [-i:       o8 24 ib                          ] SM0-1,FL,8086 */
        /* 001(24) 021 : SM0,SM1,FL,8086 */
        {I_AND, 2, {REG_AL,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+72461, 28},
    /*  12 : AND reg_ax,imm16 [-i:       o16 25 iw                         ] SM0-1,FL,8086 */
        /* 320 001(25) 031 : SM0,SM1,FL,8086 */
        {I_AND, 2, {REG_AX,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+71323, 28},
    /*  13 : AND reg_eax,imm32 [-i:       o32 25 id                         ] SM0-1,ZU,FL,386 */
        /* 321 001(25) 041 : SM0,SM1,ZU,FL,386 */
        {I_AND, 2, {REG_EAX,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+71328, 31},
    /*  14 : AND reg_rax,sdword64 [-i:       o64 25 id,s                       ] SM0-1,ZU,LONG,FL,PROT,X86_64 */
        /* 324 001(25) 255 : SM0,SM1,ZU,LONG,FL,PROT,X86_64 */
        {I_AND, 2, {REG_RAX,SDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+71333, 32},
    /*  15 : AND rm8,imm8 [mi:       hle o8 80 /4 ib                   ] SM0-1,LOCK,FL,8086 */
        /* 273 001(80) 204 021 : SM0,SM1,LOCK,FL,8086 */
        {I_AND, 2, {RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+66398, 25},
    /*  16 : AND rm16,imm16 [mi:       hle o16 81 /4 iw                  ] SM0-1,LOCK,FL,8086 */
        /* 273 320 001(81) 204 031 : SM0,SM1,LOCK,FL,8086 */
        {I_AND, 2, {RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+54940, 25},
    /*  17 : AND rm32,imm32 [mi:       hle o32 81 /4 id                  ] SM0-1,LOCK,FL,386 */
        /* 273 321 001(81) 204 041 : SM0,SM1,LOCK,FL,386 */
        {I_AND, 2, {RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+54947, 26},
    /*  18 : AND rm64,sdword64 [mi:       hle o64 81 /4 id,s                ] SM0-1,LOCK,LONG,FL,PROT,X86_64 */
        /* 273 324 001(81) 204 255 : SM0,SM1,LOCK,LONG,FL,PROT,X86_64 */
        {I_AND, 2, {RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+54954, 27},
    /*  19 : AND reg8?,reg8,rm8 [vrm:      evex.nd1.nf.l0.m4.o8 22 /r        ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(22) 121 : SM0,SM1,SM2,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 3, {REG_GPR|BITS8,REG_GPR|BITS8,RM_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+23598, 33},
    /*  20 : AND reg8,rm8 [rm:      evex.nd0.nf.l0.m4.o8 22 /r        ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(22) 110 : SM0,SM1,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 2, {REG_GPR|BITS8,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+23607, 34},
    /*  21 : AND reg8?,rm8 [v+rm:      evex.nd1.nf.l0.m4.o8 22 /r        ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(22) 110 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 2, {REG_GPR|BITS8,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+23616, 35},
    /*  22 : AND reg16?,reg16,rm16 [vrm:      evex.nd1.nf.l0.m4.o16 23 /r       ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(23) 121 : SM0,SM1,SM2,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+10013, 36},
    /*  23 : AND reg16,rm16 [rm:      evex.nd0.nf.l0.m4.o16 23 /r       ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(23) 110 : SM0,SM1,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+10023, 37},
    /*  24 : AND reg16?,rm16 [v+rm:      evex.nd1.nf.l0.m4.o16 23 /r       ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(23) 110 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+10033, 38},
    /*  25 : AND reg32?,reg32,rm32 [vrm:      evex.nd1.nf.l0.m4.o32 23 /r       ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(23) 121 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+10043, 39},
    /*  26 : AND reg32,rm32 [rm:      evex.nd0.nf.l0.m4.o32 23 /r       ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(23) 110 : SM0,SM1,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+10053, 40},
    /*  27 : AND reg32?,rm32 [v+rm:      evex.nd1.nf.l0.m4.o32 23 /r       ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(23) 110 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+10063, 41},
    /*  28 : AND reg64?,reg64,rm64 [vrm:      evex.nd1.nf.l0.m4.o64 23 /r       ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(23) 121 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+10073, 39},
    /*  29 : AND reg64,rm64 [rm:      evex.nd0.nf.l0.m4.o64 23 /r       ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(23) 110 : SM0,SM1,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+10083, 40},
    /*  30 : AND reg64?,rm64 [v+rm:      evex.nd1.nf.l0.m4.o64 23 /r       ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(23) 110 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+10093, 41},
    /*  31 : AND reg8?,rm8,reg8 [vmr:      evex.nd1.nf.l0.m4.o8 20 /r        ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(20) 112 : SM0,SM1,SM2,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 3, {REG_GPR|BITS8,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+23625, 33},
    /*  32 : AND rm8,reg8 [mr:      evex.nd0.nf.l0.m4.o8 20 /r        ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(20) 101 : SM0,SM1,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 2, {RM_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+23634, 34},
    /*  33 : AND reg8?,reg8 [v+mr:      evex.nd1.nf.l0.m4.o8 20 /r        ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(20) 101 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+23643, 35},
    /*  34 : AND reg16?,rm16,reg16 [vmr:      evex.nd1.nf.l0.m4.o16 21 /r       ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(21) 112 : SM0,SM1,SM2,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 3, {REG_GPR|BITS16,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+10103, 36},
    /*  35 : AND rm16,reg16 [mr:      evex.nd0.nf.l0.m4.o16 21 /r       ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(21) 101 : SM0,SM1,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+10113, 37},
    /*  36 : AND reg16?,reg16 [v+mr:      evex.nd1.nf.l0.m4.o16 21 /r       ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(21) 101 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+10123, 38},
    /*  37 : AND reg32?,rm32,reg32 [vmr:      evex.nd1.nf.l0.m4.o32 21 /r       ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(21) 112 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+10133, 39},
    /*  38 : AND rm32,reg32 [mr:      evex.nd0.nf.l0.m4.o32 21 /r       ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(21) 101 : SM0,SM1,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+10143, 40},
    /*  39 : AND reg32?,reg32 [v+mr:      evex.nd1.nf.l0.m4.o32 21 /r       ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(21) 101 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+10153, 41},
    /*  40 : AND reg64?,rm64,reg64 [vmr:      evex.nd1.nf.l0.m4.o64 21 /r       ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(21) 112 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+10163, 39},
    /*  41 : AND rm64,reg64 [mr:      evex.nd0.nf.l0.m4.o64 21 /r       ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(21) 101 : SM0,SM1,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+10173, 40},
    /*  42 : AND reg64?,reg64 [v+mr:      evex.nd1.nf.l0.m4.o64 21 /r       ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(21) 101 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+10183, 41},
    /*  43 : AND reg16?,rm16,sbyteword16 [vmi:      evex.nd1.nf.l0.m4.o16 83 /4 ib,s  ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(83) 214 276 : SM0,SM1,SM2,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 3, {REG_GPR|BITS16,RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+816, 36},
    /*  44 : AND rm16,sbyteword16 [mi:      evex.nd0.nf.l0.m4.o16 83 /4 ib,s  ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(83) 204 275 : SM0,SM1,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 2, {RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+827, 37},
    /*  45 : AND reg16?,sbyteword16 [v+mi:      evex.nd1.nf.l0.m4.o16 83 /4 ib,s  ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(83) 204 275 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 2, {REG_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+838, 38},
    /*  46 : AND reg32?,rm32,sbytedword32 [vmi:      evex.nd1.nf.l0.m4.o32 83 /4 ib,s  ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(83) 214 276 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 3, {REG_GPR|BITS32,RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+849, 39},
    /*  47 : AND rm32,sbytedword32 [mi:      evex.nd0.nf.l0.m4.o32 83 /4 ib,s  ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(83) 204 275 : SM0,SM1,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 2, {RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+860, 40},
    /*  48 : AND reg32?,sbytedword32 [v+mi:      evex.nd1.nf.l0.m4.o32 83 /4 ib,s  ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(83) 204 275 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 2, {REG_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+871, 41},
    /*  49 : AND reg64?,rm64,sbytedword64 [vmi:      evex.nd1.nf.l0.m4.o64 83 /4 ib,s  ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(83) 214 276 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 3, {REG_GPR|BITS64,RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+882, 39},
    /*  50 : AND rm64,sbytedword64 [mi:      evex.nd0.nf.l0.m4.o64 83 /4 ib,s  ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(83) 204 275 : SM0,SM1,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 2, {RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+893, 40},
    /*  51 : AND reg64?,sbytedword64 [v+mi:      evex.nd1.nf.l0.m4.o64 83 /4 ib,s  ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(83) 204 275 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 2, {REG_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+904, 41},
    /*  52 : AND reg8?,rm8,imm8 [vmi:      evex.nd1.nf.l0.m4.o8 80 /4 ib     ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(80) 214 022 : SM0,SM1,SM2,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 3, {REG_GPR|BITS8,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+10193, 33},
    /*  53 : AND rm8,imm8 [mi:      evex.nd0.nf.l0.m4.o8 80 /4 ib     ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(80) 204 021 : SM0,SM1,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 2, {RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+10203, 34},
    /*  54 : AND reg8?,imm8 [v+mi:      evex.nd1.nf.l0.m4.o8 80 /4 ib     ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(80) 204 021 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 2, {REG_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+10213, 35},
    /*  55 : AND reg16?,rm16,imm16 [vmi:      evex.nd1.nf.l0.m4.o16 81 /4 iw    ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(81) 214 032 : SM0,SM1,SM2,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 3, {REG_GPR|BITS16,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+915, 36},
    /*  56 : AND rm16,imm16 [mi:      evex.nd0.nf.l0.m4.o16 81 /4 iw    ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(81) 204 031 : SM0,SM1,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 2, {RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+926, 37},
    /*  57 : AND reg16?,imm16 [v+mi:      evex.nd1.nf.l0.m4.o16 81 /4 iw    ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(81) 204 031 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 2, {REG_GPR|BITS16,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+937, 38},
    /*  58 : AND reg32?,rm32,imm32 [vmi:      evex.nd1.nf.l0.m4.o32 81 /4 id    ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(81) 214 042 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 3, {REG_GPR|BITS32,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+948, 39},
    /*  59 : AND rm32,imm32 [mi:      evex.nd0.nf.l0.m4.o32 81 /4 id    ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(81) 204 041 : SM0,SM1,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 2, {RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+959, 40},
    /*  60 : AND reg32?,imm32 [v+mi:      evex.nd1.nf.l0.m4.o32 81 /4 id    ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(81) 204 041 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 2, {REG_GPR|BITS32,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+970, 41},
    /*  61 : AND reg64?,rm64,sdword64 [vmi:      evex.nd1.nf.l0.m4.o64 81 /4 id,s  ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(81) 214 256 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 3, {REG_GPR|BITS64,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+981, 39},
    /*  62 : AND rm64,sdword64 [mi:      evex.nd0.nf.l0.m4.o64 81 /4 id,s  ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(81) 204 255 : SM0,SM1,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 2, {RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+992, 40},
    /*  63 : AND reg64?,sdword64 [v+mi:      evex.nd1.nf.l0.m4.o64 81 /4 id,s  ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(81) 204 255 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_AND, 2, {REG_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+1003, 41},
    /*  64 : AND kreg8,kreg8*,kreg8 [rvm:      vex.l1.0f.ko8 41 /r              ] ND,SM0,SM1,SM2,ZU,FL,AVX512DQ,FUTURE */
        /* 261(001 005) 001(41) 120 : SM0,SM1,SM2,NOAPX,ZU,FL,VEX,AVX512DQ,FUTURE */
        {I_AND, 3, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65286, 516},
    /*  65 : AND kreg8,kreg8*,kreg8 [rvm:      evex.l1.0f.ko8 41 /r              ] ND,SM0,SM1,SM2,ZU,FL,AVX512DQ,FUTURE,APX */
        /* 241(f1 7d 28) 300 001(41) 120 : SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_AND, 3, {OPMASKREG|BITS8,OPMASKREG|BITS8,OPMASKREG|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+29880, 517},
    /*  66 : AND kreg8,kreg8 [r+vm:      vex.l1.0f.ko8 41 /r              ] ND,SM0,SM1,ZU,FL,AVX512DQ,FUTURE */
        /* 260(001 005) 001(41) 110 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512DQ,FUTURE */
        {I_AND, 2, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65293, 518},
    /*  67 : AND kreg8,kreg8 [r+vm:      evex.l1.0f.ko8 41 /r              ] ND,SM0,SM1,ZU,FL,AVX512DQ,FUTURE,APX */
        /* 240(f1 7d 28) 300 001(41) 110 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_AND, 2, {OPMASKREG|BITS8,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+29889, 519},
    /*  68 : AND kreg16,kreg16*,kreg16 [rvm:      vex.l1.0f.ko16 41 /r             ] ND,SM0,SM1,SM2,ZU,FL,AVX512F,FUTURE */
        /* 261(001 004) 001(41) 120 : SM0,SM1,SM2,NOAPX,ZU,FL,VEX,AVX512F,FUTURE */
        {I_AND, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65300, 528},
    /*  69 : AND kreg16,kreg16*,kreg16 [rvm:      evex.l1.0f.ko16 41 /r             ] ND,SM0,SM1,SM2,ZU,FL,AVX512F,FUTURE,APX */
        /* 241(f1 7c 28) 300 001(41) 120 : SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_AND, 3, {OPMASKREG|BITS16,OPMASKREG|BITS16,OPMASKREG|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+29898, 529},
    /*  70 : AND kreg16,kreg16 [r+vm:      vex.l1.0f.ko16 41 /r             ] ND,SM0,SM1,ZU,FL,AVX512F,FUTURE */
        /* 260(001 004) 001(41) 110 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512F,FUTURE */
        {I_AND, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65307, 530},
    /*  71 : AND kreg16,kreg16 [r+vm:      evex.l1.0f.ko16 41 /r             ] ND,SM0,SM1,ZU,FL,AVX512F,FUTURE,APX */
        /* 240(f1 7c 28) 300 001(41) 110 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_AND, 2, {OPMASKREG|BITS16,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29907, 531},
    /*  72 : AND kreg32,kreg32*,kreg32 [rvm:      vex.l1.0f.ko32 41 /r             ] ND,SM0,SM1,SM2,ZU,FL,AVX512BW,FUTURE */
        /* 261(001 205) 001(41) 120 : SM0,SM1,SM2,NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_AND, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65314, 520},
    /*  73 : AND kreg32,kreg32*,kreg32 [rvm:      evex.l1.0f.ko32 41 /r             ] ND,SM0,SM1,SM2,ZU,FL,AVX512BW,FUTURE,APX */
        /* 241(f1 fd 28) 300 001(41) 120 : SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_AND, 3, {OPMASKREG|BITS32,OPMASKREG|BITS32,OPMASKREG|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+29916, 521},
    /*  74 : AND kreg32,kreg32 [r+vm:      vex.l1.0f.ko32 41 /r             ] ND,SM0,SM1,ZU,FL,AVX512BW,FUTURE */
        /* 260(001 205) 001(41) 110 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_AND, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65321, 522},
    /*  75 : AND kreg32,kreg32 [r+vm:      evex.l1.0f.ko32 41 /r             ] ND,SM0,SM1,ZU,FL,AVX512BW,FUTURE,APX */
        /* 240(f1 fd 28) 300 001(41) 110 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_AND, 2, {OPMASKREG|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+29925, 523},
    /*  76 : AND kreg64,kreg64*,kreg64 [rvm:      vex.l1.0f.ko64 41 /r             ] ND,SM0,SM1,SM2,ZU,FL,AVX512BW,FUTURE */
        /* 261(001 204) 001(41) 120 : SM0,SM1,SM2,NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_AND, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65328, 520},
    /*  77 : AND kreg64,kreg64*,kreg64 [rvm:      evex.l1.0f.ko64 41 /r             ] ND,SM0,SM1,SM2,ZU,FL,AVX512BW,FUTURE,APX */
        /* 241(f1 fc 28) 300 001(41) 120 : SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_AND, 3, {OPMASKREG|BITS64,OPMASKREG|BITS64,OPMASKREG|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+29934, 521},
    /*  78 : AND kreg64,kreg64 [r+vm:      vex.l1.0f.ko64 41 /r             ] ND,SM0,SM1,ZU,FL,AVX512BW,FUTURE */
        /* 260(001 204) 001(41) 110 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_AND, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65335, 522},
    /*  79 : AND kreg64,kreg64 [r+vm:      evex.l1.0f.ko64 41 /r             ] ND,SM0,SM1,ZU,FL,AVX512BW,FUTURE,APX */
        /* 240(f1 fc 28) 300 001(41) 110 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_AND, 2, {OPMASKREG|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+29943, 523},
};

static const struct itemplate instrux_SUB[64] = {
    /*   0 : SUB rm8,reg8 [mr:       hle o8 28 /r                      ] SM0-1,LOCK,FL,8086 */
        /* 273 001(28) 101 : SM0,SM1,LOCK,FL,8086 */
        {I_SUB, 2, {RM_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+71338, 25},
    /*   1 : SUB rm16,reg16 [mr:       hle o16 29 /r                     ] SM0-1,LOCK,FL,8086 */
        /* 273 320 001(29) 101 : SM0,SM1,LOCK,FL,8086 */
        {I_SUB, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66404, 25},
    /*   2 : SUB rm32,reg32 [mr:       hle o32 29 /r                     ] SM0-1,LOCK,FL,386 */
        /* 273 321 001(29) 101 : SM0,SM1,LOCK,FL,386 */
        {I_SUB, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+66410, 26},
    /*   3 : SUB rm64,reg64 [mr:       hle o64 29 /r                     ] SM0-1,LOCK,LONG,FL,PROT,X86_64 */
        /* 273 324 001(29) 101 : SM0,SM1,LOCK,LONG,FL,PROT,X86_64 */
        {I_SUB, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+66416, 27},
    /*   4 : SUB reg8,rm8 [rm:       o8 2a /r                          ] SM0-1,FL,8086 */
        /* 001(2a) 110 : SM0,SM1,FL,8086 */
        {I_SUB, 2, {REG_GPR|BITS8,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+69550, 28},
    /*   5 : SUB reg16,rm16 [rm:       o16 2b /r                         ] SM0-1,FL,8086 */
        /* 320 001(2b) 110 : SM0,SM1,FL,8086 */
        {I_SUB, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+10248, 28},
    /*   6 : SUB reg32,rm32 [rm:       o32 2b /r                         ] SM0-1,FL,386 */
        /* 321 001(2b) 110 : SM0,SM1,FL,386 */
        {I_SUB, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+10278, 29},
    /*   7 : SUB reg64,rm64 [rm:       o64 2b /r                         ] SM0-1,LONG,FL,PROT,X86_64 */
        /* 324 001(2b) 110 : SM0,SM1,LONG,FL,PROT,X86_64 */
        {I_SUB, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+10308, 30},
    /*   8 : SUB rm16,sbyteword16 [mi:       hle o16 83 /5 ib,s                ] SM0-1,LOCK,FL,8086 */
        /* 273 320 001(83) 205 275 : SM0,SM1,LOCK,FL,8086 */
        {I_SUB, 2, {RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+54961, 25},
    /*   9 : SUB rm32,sbytedword32 [mi:       hle o32 83 /5 ib,s                ] SM0-1,LOCK,FL,386 */
        /* 273 321 001(83) 205 275 : SM0,SM1,LOCK,FL,386 */
        {I_SUB, 2, {RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+54968, 26},
    /*  10 : SUB rm64,sbytedword64 [mi:       hle o64 83 /5 ib,s                ] SM0-1,LOCK,LONG,FL,PROT,X86_64 */
        /* 273 324 001(83) 205 275 : SM0,SM1,LOCK,LONG,FL,PROT,X86_64 */
        {I_SUB, 2, {RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+54975, 27},
    /*  11 : SUB reg_al,imm8 [-i:       o8 2c ib                          ] SM0-1,FL,8086 */
        /* 001(2c) 021 : SM0,SM1,FL,8086 */
        {I_SUB, 2, {REG_AL,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+72465, 28},
    /*  12 : SUB reg_ax,imm16 [-i:       o16 2d iw                         ] SM0-1,FL,8086 */
        /* 320 001(2d) 031 : SM0,SM1,FL,8086 */
        {I_SUB, 2, {REG_AX,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+71343, 28},
    /*  13 : SUB reg_eax,imm32 [-i:       o32 2d id                         ] SM0-1,ZU,FL,386 */
        /* 321 001(2d) 041 : SM0,SM1,ZU,FL,386 */
        {I_SUB, 2, {REG_EAX,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+71348, 31},
    /*  14 : SUB reg_rax,sdword64 [-i:       o64 2d id,s                       ] SM0-1,ZU,LONG,FL,PROT,X86_64 */
        /* 324 001(2d) 255 : SM0,SM1,ZU,LONG,FL,PROT,X86_64 */
        {I_SUB, 2, {REG_RAX,SDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+71353, 32},
    /*  15 : SUB rm8,imm8 [mi:       hle o8 80 /5 ib                   ] SM0-1,LOCK,FL,8086 */
        /* 273 001(80) 205 021 : SM0,SM1,LOCK,FL,8086 */
        {I_SUB, 2, {RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+66422, 25},
    /*  16 : SUB rm16,imm16 [mi:       hle o16 81 /5 iw                  ] SM0-1,LOCK,FL,8086 */
        /* 273 320 001(81) 205 031 : SM0,SM1,LOCK,FL,8086 */
        {I_SUB, 2, {RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+54982, 25},
    /*  17 : SUB rm32,imm32 [mi:       hle o32 81 /5 id                  ] SM0-1,LOCK,FL,386 */
        /* 273 321 001(81) 205 041 : SM0,SM1,LOCK,FL,386 */
        {I_SUB, 2, {RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+54989, 26},
    /*  18 : SUB rm64,sdword64 [mi:       hle o64 81 /5 id,s                ] SM0-1,LOCK,LONG,FL,PROT,X86_64 */
        /* 273 324 001(81) 205 255 : SM0,SM1,LOCK,LONG,FL,PROT,X86_64 */
        {I_SUB, 2, {RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+54996, 27},
    /*  19 : SUB reg8?,reg8,rm8 [vrm:      evex.nd1.nf.l0.m4.o8 2a /r        ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(2a) 121 : SM0,SM1,SM2,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 3, {REG_GPR|BITS8,REG_GPR|BITS8,RM_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+23652, 33},
    /*  20 : SUB reg8,rm8 [rm:      evex.nd0.nf.l0.m4.o8 2a /r        ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(2a) 110 : SM0,SM1,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 2, {REG_GPR|BITS8,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+23661, 34},
    /*  21 : SUB reg8?,rm8 [v+rm:      evex.nd1.nf.l0.m4.o8 2a /r        ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(2a) 110 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 2, {REG_GPR|BITS8,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+23670, 35},
    /*  22 : SUB reg16?,reg16,rm16 [vrm:      evex.nd1.nf.l0.m4.o16 2b /r       ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(2b) 121 : SM0,SM1,SM2,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+10223, 36},
    /*  23 : SUB reg16,rm16 [rm:      evex.nd0.nf.l0.m4.o16 2b /r       ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(2b) 110 : SM0,SM1,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+10233, 37},
    /*  24 : SUB reg16?,rm16 [v+rm:      evex.nd1.nf.l0.m4.o16 2b /r       ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(2b) 110 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+10243, 38},
    /*  25 : SUB reg32?,reg32,rm32 [vrm:      evex.nd1.nf.l0.m4.o32 2b /r       ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(2b) 121 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+10253, 39},
    /*  26 : SUB reg32,rm32 [rm:      evex.nd0.nf.l0.m4.o32 2b /r       ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(2b) 110 : SM0,SM1,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+10263, 40},
    /*  27 : SUB reg32?,rm32 [v+rm:      evex.nd1.nf.l0.m4.o32 2b /r       ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(2b) 110 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+10273, 41},
    /*  28 : SUB reg64?,reg64,rm64 [vrm:      evex.nd1.nf.l0.m4.o64 2b /r       ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(2b) 121 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+10283, 39},
    /*  29 : SUB reg64,rm64 [rm:      evex.nd0.nf.l0.m4.o64 2b /r       ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(2b) 110 : SM0,SM1,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+10293, 40},
    /*  30 : SUB reg64?,rm64 [v+rm:      evex.nd1.nf.l0.m4.o64 2b /r       ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(2b) 110 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+10303, 41},
    /*  31 : SUB reg8?,rm8,reg8 [vmr:      evex.nd1.nf.l0.m4.o8 28 /r        ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(28) 112 : SM0,SM1,SM2,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 3, {REG_GPR|BITS8,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+23679, 33},
    /*  32 : SUB rm8,reg8 [mr:      evex.nd0.nf.l0.m4.o8 28 /r        ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(28) 101 : SM0,SM1,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 2, {RM_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+23688, 34},
    /*  33 : SUB reg8?,reg8 [v+mr:      evex.nd1.nf.l0.m4.o8 28 /r        ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(28) 101 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+23697, 35},
    /*  34 : SUB reg16?,rm16,reg16 [vmr:      evex.nd1.nf.l0.m4.o16 29 /r       ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(29) 112 : SM0,SM1,SM2,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 3, {REG_GPR|BITS16,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+10313, 36},
    /*  35 : SUB rm16,reg16 [mr:      evex.nd0.nf.l0.m4.o16 29 /r       ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(29) 101 : SM0,SM1,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+10323, 37},
    /*  36 : SUB reg16?,reg16 [v+mr:      evex.nd1.nf.l0.m4.o16 29 /r       ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(29) 101 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+10333, 38},
    /*  37 : SUB reg32?,rm32,reg32 [vmr:      evex.nd1.nf.l0.m4.o32 29 /r       ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(29) 112 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+10343, 39},
    /*  38 : SUB rm32,reg32 [mr:      evex.nd0.nf.l0.m4.o32 29 /r       ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(29) 101 : SM0,SM1,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+10353, 40},
    /*  39 : SUB reg32?,reg32 [v+mr:      evex.nd1.nf.l0.m4.o32 29 /r       ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(29) 101 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+10363, 41},
    /*  40 : SUB reg64?,rm64,reg64 [vmr:      evex.nd1.nf.l0.m4.o64 29 /r       ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(29) 112 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+10373, 39},
    /*  41 : SUB rm64,reg64 [mr:      evex.nd0.nf.l0.m4.o64 29 /r       ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(29) 101 : SM0,SM1,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+10383, 40},
    /*  42 : SUB reg64?,reg64 [v+mr:      evex.nd1.nf.l0.m4.o64 29 /r       ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(29) 101 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+10393, 41},
    /*  43 : SUB reg16?,rm16,sbyteword16 [vmi:      evex.nd1.nf.l0.m4.o16 83 /5 ib,s  ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(83) 215 276 : SM0,SM1,SM2,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 3, {REG_GPR|BITS16,RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+1014, 36},
    /*  44 : SUB rm16,sbyteword16 [mi:      evex.nd0.nf.l0.m4.o16 83 /5 ib,s  ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(83) 205 275 : SM0,SM1,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 2, {RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+1025, 37},
    /*  45 : SUB reg16?,sbyteword16 [v+mi:      evex.nd1.nf.l0.m4.o16 83 /5 ib,s  ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(83) 205 275 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 2, {REG_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+1036, 38},
    /*  46 : SUB reg32?,rm32,sbytedword32 [vmi:      evex.nd1.nf.l0.m4.o32 83 /5 ib,s  ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(83) 215 276 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 3, {REG_GPR|BITS32,RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+1047, 39},
    /*  47 : SUB rm32,sbytedword32 [mi:      evex.nd0.nf.l0.m4.o32 83 /5 ib,s  ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(83) 205 275 : SM0,SM1,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 2, {RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+1058, 40},
    /*  48 : SUB reg32?,sbytedword32 [v+mi:      evex.nd1.nf.l0.m4.o32 83 /5 ib,s  ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(83) 205 275 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 2, {REG_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+1069, 41},
    /*  49 : SUB reg64?,rm64,sbytedword64 [vmi:      evex.nd1.nf.l0.m4.o64 83 /5 ib,s  ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(83) 215 276 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 3, {REG_GPR|BITS64,RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+1080, 39},
    /*  50 : SUB rm64,sbytedword64 [mi:      evex.nd0.nf.l0.m4.o64 83 /5 ib,s  ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(83) 205 275 : SM0,SM1,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 2, {RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+1091, 40},
    /*  51 : SUB reg64?,sbytedword64 [v+mi:      evex.nd1.nf.l0.m4.o64 83 /5 ib,s  ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(83) 205 275 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 2, {REG_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+1102, 41},
    /*  52 : SUB reg8?,rm8,imm8 [vmi:      evex.nd1.nf.l0.m4.o8 80 /5 ib     ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(80) 215 022 : SM0,SM1,SM2,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 3, {REG_GPR|BITS8,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+10403, 33},
    /*  53 : SUB rm8,imm8 [mi:      evex.nd0.nf.l0.m4.o8 80 /5 ib     ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(80) 205 021 : SM0,SM1,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 2, {RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+10413, 34},
    /*  54 : SUB reg8?,imm8 [v+mi:      evex.nd1.nf.l0.m4.o8 80 /5 ib     ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(80) 205 021 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 2, {REG_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+10423, 35},
    /*  55 : SUB reg16?,rm16,imm16 [vmi:      evex.nd1.nf.l0.m4.o16 81 /5 iw    ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(81) 215 032 : SM0,SM1,SM2,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 3, {REG_GPR|BITS16,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+1113, 36},
    /*  56 : SUB rm16,imm16 [mi:      evex.nd0.nf.l0.m4.o16 81 /5 iw    ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(81) 205 031 : SM0,SM1,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 2, {RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+1124, 37},
    /*  57 : SUB reg16?,imm16 [v+mi:      evex.nd1.nf.l0.m4.o16 81 /5 iw    ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(81) 205 031 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 2, {REG_GPR|BITS16,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+1135, 38},
    /*  58 : SUB reg32?,rm32,imm32 [vmi:      evex.nd1.nf.l0.m4.o32 81 /5 id    ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(81) 215 042 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 3, {REG_GPR|BITS32,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+1146, 39},
    /*  59 : SUB rm32,imm32 [mi:      evex.nd0.nf.l0.m4.o32 81 /5 id    ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(81) 205 041 : SM0,SM1,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 2, {RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+1157, 40},
    /*  60 : SUB reg32?,imm32 [v+mi:      evex.nd1.nf.l0.m4.o32 81 /5 id    ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(81) 205 041 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 2, {REG_GPR|BITS32,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+1168, 41},
    /*  61 : SUB reg64?,rm64,sdword64 [vmi:      evex.nd1.nf.l0.m4.o64 81 /5 id,s  ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(81) 215 256 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 3, {REG_GPR|BITS64,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+1179, 39},
    /*  62 : SUB rm64,sdword64 [mi:      evex.nd0.nf.l0.m4.o64 81 /5 id,s  ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(81) 205 255 : SM0,SM1,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 2, {RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+1190, 40},
    /*  63 : SUB reg64?,sdword64 [v+mi:      evex.nd1.nf.l0.m4.o64 81 /5 id,s  ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(81) 205 255 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SUB, 2, {REG_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+1201, 41},
};

static const struct itemplate instrux_XOR[80] = {
    /*   0 : XOR rm8,reg8 [mr:       hle o8 30 /r                      ] SM0-1,LOCK,FL,8086 */
        /* 273 001(30) 101 : SM0,SM1,LOCK,FL,8086 */
        {I_XOR, 2, {RM_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+71358, 25},
    /*   1 : XOR rm16,reg16 [mr:       hle o16 31 /r                     ] SM0-1,LOCK,FL,8086 */
        /* 273 320 001(31) 101 : SM0,SM1,LOCK,FL,8086 */
        {I_XOR, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66428, 25},
    /*   2 : XOR rm32,reg32 [mr:       hle o32 31 /r                     ] SM0-1,LOCK,FL,386 */
        /* 273 321 001(31) 101 : SM0,SM1,LOCK,FL,386 */
        {I_XOR, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+66434, 26},
    /*   3 : XOR rm64,reg64 [mr:       hle o64 31 /r                     ] SM0-1,LOCK,LONG,FL,PROT,X86_64 */
        /* 273 324 001(31) 101 : SM0,SM1,LOCK,LONG,FL,PROT,X86_64 */
        {I_XOR, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+66440, 27},
    /*   4 : XOR reg8,rm8 [rm:       o8 32 /r                          ] SM0-1,FL,8086 */
        /* 001(32) 110 : SM0,SM1,FL,8086 */
        {I_XOR, 2, {REG_GPR|BITS8,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+69676, 28},
    /*   5 : XOR reg16,rm16 [rm:       o16 33 /r                         ] SM0-1,FL,8086 */
        /* 320 001(33) 110 : SM0,SM1,FL,8086 */
        {I_XOR, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+10458, 28},
    /*   6 : XOR reg32,rm32 [rm:       o32 33 /r                         ] SM0-1,FL,386 */
        /* 321 001(33) 110 : SM0,SM1,FL,386 */
        {I_XOR, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+10488, 29},
    /*   7 : XOR reg64,rm64 [rm:       o64 33 /r                         ] SM0-1,LONG,FL,PROT,X86_64 */
        /* 324 001(33) 110 : SM0,SM1,LONG,FL,PROT,X86_64 */
        {I_XOR, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+10518, 30},
    /*   8 : XOR rm16,sbyteword16 [mi:       hle o16 83 /6 ib,s                ] SM0-1,LOCK,FL,8086 */
        /* 273 320 001(83) 206 275 : SM0,SM1,LOCK,FL,8086 */
        {I_XOR, 2, {RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+55003, 25},
    /*   9 : XOR rm32,sbytedword32 [mi:       hle o32 83 /6 ib,s                ] SM0-1,LOCK,FL,386 */
        /* 273 321 001(83) 206 275 : SM0,SM1,LOCK,FL,386 */
        {I_XOR, 2, {RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+55010, 26},
    /*  10 : XOR rm64,sbytedword64 [mi:       hle o64 83 /6 ib,s                ] SM0-1,LOCK,LONG,FL,PROT,X86_64 */
        /* 273 324 001(83) 206 275 : SM0,SM1,LOCK,LONG,FL,PROT,X86_64 */
        {I_XOR, 2, {RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+55017, 27},
    /*  11 : XOR reg_al,imm8 [-i:       o8 34 ib                          ] SM0-1,FL,8086 */
        /* 001(34) 021 : SM0,SM1,FL,8086 */
        {I_XOR, 2, {REG_AL,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+72469, 28},
    /*  12 : XOR reg_ax,imm16 [-i:       o16 35 iw                         ] SM0-1,FL,8086 */
        /* 320 001(35) 031 : SM0,SM1,FL,8086 */
        {I_XOR, 2, {REG_AX,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+71363, 28},
    /*  13 : XOR reg_eax,imm32 [-i:       o32 35 id                         ] SM0-1,ZU,FL,386 */
        /* 321 001(35) 041 : SM0,SM1,ZU,FL,386 */
        {I_XOR, 2, {REG_EAX,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+71368, 31},
    /*  14 : XOR reg_rax,sdword64 [-i:       o64 35 id,s                       ] SM0-1,ZU,LONG,FL,PROT,X86_64 */
        /* 324 001(35) 255 : SM0,SM1,ZU,LONG,FL,PROT,X86_64 */
        {I_XOR, 2, {REG_RAX,SDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+71373, 32},
    /*  15 : XOR rm8,imm8 [mi:       hle o8 80 /6 ib                   ] SM0-1,LOCK,FL,8086 */
        /* 273 001(80) 206 021 : SM0,SM1,LOCK,FL,8086 */
        {I_XOR, 2, {RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+66446, 25},
    /*  16 : XOR rm16,imm16 [mi:       hle o16 81 /6 iw                  ] SM0-1,LOCK,FL,8086 */
        /* 273 320 001(81) 206 031 : SM0,SM1,LOCK,FL,8086 */
        {I_XOR, 2, {RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55024, 25},
    /*  17 : XOR rm32,imm32 [mi:       hle o32 81 /6 id                  ] SM0-1,LOCK,FL,386 */
        /* 273 321 001(81) 206 041 : SM0,SM1,LOCK,FL,386 */
        {I_XOR, 2, {RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+55031, 26},
    /*  18 : XOR rm64,sdword64 [mi:       hle o64 81 /6 id,s                ] SM0-1,LOCK,LONG,FL,PROT,X86_64 */
        /* 273 324 001(81) 206 255 : SM0,SM1,LOCK,LONG,FL,PROT,X86_64 */
        {I_XOR, 2, {RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+55038, 27},
    /*  19 : XOR reg8?,reg8,rm8 [vrm:      evex.nd1.nf.l0.m4.o8 32 /r        ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(32) 121 : SM0,SM1,SM2,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 3, {REG_GPR|BITS8,REG_GPR|BITS8,RM_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+23706, 33},
    /*  20 : XOR reg8,rm8 [rm:      evex.nd0.nf.l0.m4.o8 32 /r        ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(32) 110 : SM0,SM1,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 2, {REG_GPR|BITS8,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+23715, 34},
    /*  21 : XOR reg8?,rm8 [v+rm:      evex.nd1.nf.l0.m4.o8 32 /r        ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(32) 110 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 2, {REG_GPR|BITS8,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+23724, 35},
    /*  22 : XOR reg16?,reg16,rm16 [vrm:      evex.nd1.nf.l0.m4.o16 33 /r       ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(33) 121 : SM0,SM1,SM2,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+10433, 36},
    /*  23 : XOR reg16,rm16 [rm:      evex.nd0.nf.l0.m4.o16 33 /r       ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(33) 110 : SM0,SM1,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+10443, 37},
    /*  24 : XOR reg16?,rm16 [v+rm:      evex.nd1.nf.l0.m4.o16 33 /r       ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(33) 110 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+10453, 38},
    /*  25 : XOR reg32?,reg32,rm32 [vrm:      evex.nd1.nf.l0.m4.o32 33 /r       ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(33) 121 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+10463, 39},
    /*  26 : XOR reg32,rm32 [rm:      evex.nd0.nf.l0.m4.o32 33 /r       ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(33) 110 : SM0,SM1,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+10473, 40},
    /*  27 : XOR reg32?,rm32 [v+rm:      evex.nd1.nf.l0.m4.o32 33 /r       ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(33) 110 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+10483, 41},
    /*  28 : XOR reg64?,reg64,rm64 [vrm:      evex.nd1.nf.l0.m4.o64 33 /r       ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(33) 121 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+10493, 39},
    /*  29 : XOR reg64,rm64 [rm:      evex.nd0.nf.l0.m4.o64 33 /r       ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(33) 110 : SM0,SM1,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+10503, 40},
    /*  30 : XOR reg64?,rm64 [v+rm:      evex.nd1.nf.l0.m4.o64 33 /r       ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(33) 110 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+10513, 41},
    /*  31 : XOR reg8?,rm8,reg8 [vmr:      evex.nd1.nf.l0.m4.o8 30 /r        ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(30) 112 : SM0,SM1,SM2,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 3, {REG_GPR|BITS8,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+23733, 33},
    /*  32 : XOR rm8,reg8 [mr:      evex.nd0.nf.l0.m4.o8 30 /r        ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(30) 101 : SM0,SM1,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 2, {RM_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+23742, 34},
    /*  33 : XOR reg8?,reg8 [v+mr:      evex.nd1.nf.l0.m4.o8 30 /r        ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(30) 101 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+23751, 35},
    /*  34 : XOR reg16?,rm16,reg16 [vmr:      evex.nd1.nf.l0.m4.o16 31 /r       ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(31) 112 : SM0,SM1,SM2,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 3, {REG_GPR|BITS16,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+10523, 36},
    /*  35 : XOR rm16,reg16 [mr:      evex.nd0.nf.l0.m4.o16 31 /r       ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(31) 101 : SM0,SM1,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+10533, 37},
    /*  36 : XOR reg16?,reg16 [v+mr:      evex.nd1.nf.l0.m4.o16 31 /r       ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(31) 101 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+10543, 38},
    /*  37 : XOR reg32?,rm32,reg32 [vmr:      evex.nd1.nf.l0.m4.o32 31 /r       ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(31) 112 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+10553, 39},
    /*  38 : XOR rm32,reg32 [mr:      evex.nd0.nf.l0.m4.o32 31 /r       ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(31) 101 : SM0,SM1,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+10563, 40},
    /*  39 : XOR reg32?,reg32 [v+mr:      evex.nd1.nf.l0.m4.o32 31 /r       ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(31) 101 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+10573, 41},
    /*  40 : XOR reg64?,rm64,reg64 [vmr:      evex.nd1.nf.l0.m4.o64 31 /r       ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(31) 112 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+10583, 39},
    /*  41 : XOR rm64,reg64 [mr:      evex.nd0.nf.l0.m4.o64 31 /r       ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(31) 101 : SM0,SM1,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+10593, 40},
    /*  42 : XOR reg64?,reg64 [v+mr:      evex.nd1.nf.l0.m4.o64 31 /r       ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(31) 101 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+10603, 41},
    /*  43 : XOR reg16?,rm16,sbyteword16 [vmi:      evex.nd1.nf.l0.m4.o16 83 /6 ib,s  ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(83) 216 276 : SM0,SM1,SM2,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 3, {REG_GPR|BITS16,RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+1212, 36},
    /*  44 : XOR rm16,sbyteword16 [mi:      evex.nd0.nf.l0.m4.o16 83 /6 ib,s  ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(83) 206 275 : SM0,SM1,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 2, {RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+1223, 37},
    /*  45 : XOR reg16?,sbyteword16 [v+mi:      evex.nd1.nf.l0.m4.o16 83 /6 ib,s  ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(83) 206 275 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 2, {REG_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+1234, 38},
    /*  46 : XOR reg32?,rm32,sbytedword32 [vmi:      evex.nd1.nf.l0.m4.o32 83 /6 ib,s  ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(83) 216 276 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+1245, 39},
    /*  47 : XOR rm32,sbytedword32 [mi:      evex.nd0.nf.l0.m4.o32 83 /6 ib,s  ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(83) 206 275 : SM0,SM1,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 2, {RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+1256, 40},
    /*  48 : XOR reg32?,sbytedword32 [v+mi:      evex.nd1.nf.l0.m4.o32 83 /6 ib,s  ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(83) 206 275 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 2, {REG_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+1267, 41},
    /*  49 : XOR reg64?,rm64,sbytedword64 [vmi:      evex.nd1.nf.l0.m4.o64 83 /6 ib,s  ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(83) 216 276 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+1278, 39},
    /*  50 : XOR rm64,sbytedword64 [mi:      evex.nd0.nf.l0.m4.o64 83 /6 ib,s  ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(83) 206 275 : SM0,SM1,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 2, {RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+1289, 40},
    /*  51 : XOR reg64?,sbytedword64 [v+mi:      evex.nd1.nf.l0.m4.o64 83 /6 ib,s  ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(83) 206 275 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 2, {REG_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+1300, 41},
    /*  52 : XOR reg8?,rm8,imm8 [vmi:      evex.nd1.nf.l0.m4.o8 80 /6 ib     ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(80) 216 022 : SM0,SM1,SM2,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 3, {REG_GPR|BITS8,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+10613, 33},
    /*  53 : XOR rm8,imm8 [mi:      evex.nd0.nf.l0.m4.o8 80 /6 ib     ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(80) 206 021 : SM0,SM1,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 2, {RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+10623, 34},
    /*  54 : XOR reg8?,imm8 [v+mi:      evex.nd1.nf.l0.m4.o8 80 /6 ib     ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(80) 206 021 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 2, {REG_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+10633, 35},
    /*  55 : XOR reg16?,rm16,imm16 [vmi:      evex.nd1.nf.l0.m4.o16 81 /6 iw    ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(81) 216 032 : SM0,SM1,SM2,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 3, {REG_GPR|BITS16,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+1311, 36},
    /*  56 : XOR rm16,imm16 [mi:      evex.nd0.nf.l0.m4.o16 81 /6 iw    ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(81) 206 031 : SM0,SM1,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 2, {RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+1322, 37},
    /*  57 : XOR reg16?,imm16 [v+mi:      evex.nd1.nf.l0.m4.o16 81 /6 iw    ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(81) 206 031 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 2, {REG_GPR|BITS16,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+1333, 38},
    /*  58 : XOR reg32?,rm32,imm32 [vmi:      evex.nd1.nf.l0.m4.o32 81 /6 id    ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(81) 216 042 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+1344, 39},
    /*  59 : XOR rm32,imm32 [mi:      evex.nd0.nf.l0.m4.o32 81 /6 id    ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(81) 206 041 : SM0,SM1,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 2, {RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+1355, 40},
    /*  60 : XOR reg32?,imm32 [v+mi:      evex.nd1.nf.l0.m4.o32 81 /6 id    ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(81) 206 041 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 2, {REG_GPR|BITS32,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+1366, 41},
    /*  61 : XOR reg64?,rm64,sdword64 [vmi:      evex.nd1.nf.l0.m4.o64 81 /6 id,s  ] SM0,SM1,SM2,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(81) 216 256 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+1377, 39},
    /*  62 : XOR rm64,sdword64 [mi:      evex.nd0.nf.l0.m4.o64 81 /6 id,s  ] SM0,SM1,NF,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(81) 206 255 : SM0,SM1,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 2, {RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+1388, 40},
    /*  63 : XOR reg64?,sdword64 [v+mi:      evex.nd1.nf.l0.m4.o64 81 /6 id,s  ] ND,SM0,SM1,NF,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(81) 206 255 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_XOR, 2, {REG_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+1399, 41},
    /*  64 : XOR kreg8,kreg8*,kreg8 [rvm:      vex.nds.l1.0f.ko8 47 /r          ] ND,SM0,SM1,SM2,ZU,FL,AVX512DQ,FUTURE */
        /* 261(001 005) 001(47) 120 : SM0,SM1,SM2,NOAPX,ZU,FL,VEX,AVX512DQ,FUTURE */
        {I_XOR, 3, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65664, 516},
    /*  65 : XOR kreg8,kreg8*,kreg8 [rvm:      evex.nds.l1.0f.ko8 47 /r          ] ND,SM0,SM1,SM2,ZU,FL,AVX512DQ,FUTURE,APX */
        /* 241(f1 7d 28) 300 001(47) 120 : SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_XOR, 3, {OPMASKREG|BITS8,OPMASKREG|BITS8,OPMASKREG|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+30366, 517},
    /*  66 : XOR kreg8,kreg8 [r+vm:      vex.nds.l1.0f.ko8 47 /r          ] ND,SM0,SM1,ZU,FL,AVX512DQ,FUTURE */
        /* 260(001 005) 001(47) 110 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512DQ,FUTURE */
        {I_XOR, 2, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65671, 518},
    /*  67 : XOR kreg8,kreg8 [r+vm:      evex.nds.l1.0f.ko8 47 /r          ] ND,SM0,SM1,ZU,FL,AVX512DQ,FUTURE,APX */
        /* 240(f1 7d 28) 300 001(47) 110 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_XOR, 2, {OPMASKREG|BITS8,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+30375, 519},
    /*  68 : XOR kreg16,kreg16*,kreg16 [rvm:      vex.nds.l1.0f.ko16 47 /r         ] ND,SM0,SM1,SM2,ZU,FL,AVX512F,FUTURE */
        /* 261(001 004) 001(47) 120 : SM0,SM1,SM2,NOAPX,ZU,FL,VEX,AVX512F,FUTURE */
        {I_XOR, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65678, 528},
    /*  69 : XOR kreg16,kreg16*,kreg16 [rvm:      evex.nds.l1.0f.ko16 47 /r         ] ND,SM0,SM1,SM2,ZU,FL,AVX512F,FUTURE,APX */
        /* 241(f1 7c 28) 300 001(47) 120 : SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_XOR, 3, {OPMASKREG|BITS16,OPMASKREG|BITS16,OPMASKREG|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+30384, 529},
    /*  70 : XOR kreg16,kreg16 [r+vm:      vex.nds.l1.0f.ko16 47 /r         ] ND,SM0,SM1,ZU,FL,AVX512F,FUTURE */
        /* 260(001 004) 001(47) 110 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512F,FUTURE */
        {I_XOR, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65685, 530},
    /*  71 : XOR kreg16,kreg16 [r+vm:      evex.nds.l1.0f.ko16 47 /r         ] ND,SM0,SM1,ZU,FL,AVX512F,FUTURE,APX */
        /* 240(f1 7c 28) 300 001(47) 110 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_XOR, 2, {OPMASKREG|BITS16,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+30393, 531},
    /*  72 : XOR kreg32,kreg32*,kreg32 [rvm:      vex.nds.l1.0f.ko32 47 /r         ] ND,SM0,SM1,SM2,ZU,FL,AVX512BW,FUTURE */
        /* 261(001 205) 001(47) 120 : SM0,SM1,SM2,NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_XOR, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65692, 520},
    /*  73 : XOR kreg32,kreg32*,kreg32 [rvm:      evex.nds.l1.0f.ko32 47 /r         ] ND,SM0,SM1,SM2,ZU,FL,AVX512BW,FUTURE,APX */
        /* 241(f1 fd 28) 300 001(47) 120 : SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_XOR, 3, {OPMASKREG|BITS32,OPMASKREG|BITS32,OPMASKREG|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+30402, 521},
    /*  74 : XOR kreg32,kreg32 [r+vm:      vex.nds.l1.0f.ko32 47 /r         ] ND,SM0,SM1,ZU,FL,AVX512BW,FUTURE */
        /* 260(001 205) 001(47) 110 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_XOR, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65699, 522},
    /*  75 : XOR kreg32,kreg32 [r+vm:      evex.nds.l1.0f.ko32 47 /r         ] ND,SM0,SM1,ZU,FL,AVX512BW,FUTURE,APX */
        /* 240(f1 fd 28) 300 001(47) 110 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_XOR, 2, {OPMASKREG|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+30411, 523},
    /*  76 : XOR kreg64,kreg64*,kreg64 [rvm:      vex.nds.l1.0f.ko64 47 /r         ] ND,SM0,SM1,SM2,ZU,FL,AVX512BW,FUTURE */
        /* 261(001 204) 001(47) 120 : SM0,SM1,SM2,NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_XOR, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65706, 520},
    /*  77 : XOR kreg64,kreg64*,kreg64 [rvm:      evex.nds.l1.0f.ko64 47 /r         ] ND,SM0,SM1,SM2,ZU,FL,AVX512BW,FUTURE,APX */
        /* 241(f1 fc 28) 300 001(47) 120 : SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_XOR, 3, {OPMASKREG|BITS64,OPMASKREG|BITS64,OPMASKREG|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+30420, 521},
    /*  78 : XOR kreg64,kreg64 [r+vm:      vex.nds.l1.0f.ko64 47 /r         ] ND,SM0,SM1,ZU,FL,AVX512BW,FUTURE */
        /* 260(001 204) 001(47) 110 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_XOR, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65713, 522},
    /*  79 : XOR kreg64,kreg64 [r+vm:      evex.nds.l1.0f.ko64 47 /r         ] ND,SM0,SM1,ZU,FL,AVX512BW,FUTURE,APX */
        /* 240(f1 fc 28) 300 001(47) 110 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_XOR, 2, {OPMASKREG|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+30429, 523},
};

static const struct itemplate instrux_CMP[19] = {
    /*   0 : CMP rm8,reg8 [mr:       hle o8 38 /r                      ] SM0-1,LOCK,FL,8086 */
        /* 273 001(38) 101 : SM0,SM1,LOCK,FL,8086 */
        {I_CMP, 2, {RM_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+71378, 25},
    /*   1 : CMP rm16,reg16 [mr:       hle o16 39 /r                     ] SM0-1,LOCK,FL,8086 */
        /* 273 320 001(39) 101 : SM0,SM1,LOCK,FL,8086 */
        {I_CMP, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66452, 25},
    /*   2 : CMP rm32,reg32 [mr:       hle o32 39 /r                     ] SM0-1,LOCK,FL,386 */
        /* 273 321 001(39) 101 : SM0,SM1,LOCK,FL,386 */
        {I_CMP, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+66458, 26},
    /*   3 : CMP rm64,reg64 [mr:       hle o64 39 /r                     ] SM0-1,LOCK,LONG,FL,PROT,X86_64 */
        /* 273 324 001(39) 101 : SM0,SM1,LOCK,LONG,FL,PROT,X86_64 */
        {I_CMP, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+66464, 27},
    /*   4 : CMP reg8,rm8 [rm:       o8 3a /r                          ] SM0-1,FL,8086 */
        /* 001(3a) 110 : SM0,SM1,FL,8086 */
        {I_CMP, 2, {REG_GPR|BITS8,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+69622, 28},
    /*   5 : CMP reg16,rm16 [rm:       o16 3b /r                         ] SM0-1,FL,8086 */
        /* 320 001(3b) 110 : SM0,SM1,FL,8086 */
        {I_CMP, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+71383, 28},
    /*   6 : CMP reg32,rm32 [rm:       o32 3b /r                         ] SM0-1,FL,386 */
        /* 321 001(3b) 110 : SM0,SM1,FL,386 */
        {I_CMP, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+71388, 29},
    /*   7 : CMP reg64,rm64 [rm:       o64 3b /r                         ] SM0-1,LONG,FL,PROT,X86_64 */
        /* 324 001(3b) 110 : SM0,SM1,LONG,FL,PROT,X86_64 */
        {I_CMP, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+71393, 30},
    /*   8 : CMP rm16,sbyteword16 [mi:       hle o16 83 /7 ib,s                ] SM0-1,LOCK,FL,8086 */
        /* 273 320 001(83) 207 275 : SM0,SM1,LOCK,FL,8086 */
        {I_CMP, 2, {RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+55045, 25},
    /*   9 : CMP rm32,sbytedword32 [mi:       hle o32 83 /7 ib,s                ] SM0-1,LOCK,FL,386 */
        /* 273 321 001(83) 207 275 : SM0,SM1,LOCK,FL,386 */
        {I_CMP, 2, {RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+55052, 26},
    /*  10 : CMP rm64,sbytedword64 [mi:       hle o64 83 /7 ib,s                ] SM0-1,LOCK,LONG,FL,PROT,X86_64 */
        /* 273 324 001(83) 207 275 : SM0,SM1,LOCK,LONG,FL,PROT,X86_64 */
        {I_CMP, 2, {RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+55059, 27},
    /*  11 : CMP reg_al,imm8 [-i:       o8 3c ib                          ] SM0-1,FL,8086 */
        /* 001(3c) 021 : SM0,SM1,FL,8086 */
        {I_CMP, 2, {REG_AL,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+72473, 28},
    /*  12 : CMP reg_ax,imm16 [-i:       o16 3d iw                         ] SM0-1,FL,8086 */
        /* 320 001(3d) 031 : SM0,SM1,FL,8086 */
        {I_CMP, 2, {REG_AX,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+71398, 28},
    /*  13 : CMP reg_eax,imm32 [-i:       o32 3d id                         ] SM0-1,FL,386 */
        /* 321 001(3d) 041 : SM0,SM1,FL,386 */
        {I_CMP, 2, {REG_EAX,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+71403, 29},
    /*  14 : CMP reg_rax,sdword64 [-i:       o64 3d id,s                       ] SM0-1,LONG,FL,PROT,X86_64 */
        /* 324 001(3d) 255 : SM0,SM1,LONG,FL,PROT,X86_64 */
        {I_CMP, 2, {REG_RAX,SDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+71408, 30},
    /*  15 : CMP rm8,imm8 [mi:       hle o8 80 /7 ib                   ] SM0-1,LOCK,FL,8086 */
        /* 273 001(80) 207 021 : SM0,SM1,LOCK,FL,8086 */
        {I_CMP, 2, {RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+66470, 25},
    /*  16 : CMP rm16,imm16 [mi:       hle o16 81 /7 iw                  ] SM0-1,LOCK,FL,8086 */
        /* 273 320 001(81) 207 031 : SM0,SM1,LOCK,FL,8086 */
        {I_CMP, 2, {RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55066, 25},
    /*  17 : CMP rm32,imm32 [mi:       hle o32 81 /7 id                  ] SM0-1,LOCK,FL,386 */
        /* 273 321 001(81) 207 041 : SM0,SM1,LOCK,FL,386 */
        {I_CMP, 2, {RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+55073, 26},
    /*  18 : CMP rm64,sdword64 [mi:       hle o64 81 /7 id,s                ] SM0-1,LOCK,LONG,FL,PROT,X86_64 */
        /* 273 324 001(81) 207 255 : SM0,SM1,LOCK,LONG,FL,PROT,X86_64 */
        {I_CMP, 2, {RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+55080, 27},
};

static const struct itemplate instrux_TEST[24] = {
    /*   0 : TEST rm8,reg8 [mr:       o8 84 /r                          ] SM0-1,FL,8086 */
        /* 001(84) 101 : SM0,SM1,FL,8086 */
        {I_TEST, 2, {RM_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+72477, 28},
    /*   1 : TEST rm16,reg16 [mr:       o16 85 /r                         ] SM0-1,FL,8086 */
        /* 320 001(85) 101 : SM0,SM1,FL,8086 */
        {I_TEST, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+71413, 28},
    /*   2 : TEST rm32,reg32 [mr:       o32 85 /r                         ] SM0-1,FL,386 */
        /* 321 001(85) 101 : SM0,SM1,FL,386 */
        {I_TEST, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+71418, 29},
    /*   3 : TEST rm64,reg64 [mr:       o64 85 /r                         ] SM0-1,LONG,FL,PROT,X86_64 */
        /* 324 001(85) 101 : SM0,SM1,LONG,FL,PROT,X86_64 */
        {I_TEST, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+71423, 30},
    /*   4 : TEST reg8,mem8 [rm:       o8 84 /r                          ] ND,SM0-1,FL,8086 */
        /* 001(84) 110 : SM0,SM1,FL,8086 */
        {I_TEST, 2, {REG_GPR|BITS8,MEMORY|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+72481, 28},
    /*   5 : TEST reg16,mem16 [rm:       o16 85 /r                         ] ND,SM0-1,FL,8086 */
        /* 320 001(85) 110 : SM0,SM1,FL,8086 */
        {I_TEST, 2, {REG_GPR|BITS16,MEMORY|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+71428, 28},
    /*   6 : TEST reg32,mem32 [rm:       o32 85 /r                         ] ND,SM0-1,FL,386 */
        /* 321 001(85) 110 : SM0,SM1,FL,386 */
        {I_TEST, 2, {REG_GPR|BITS32,MEMORY|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+71433, 29},
    /*   7 : TEST reg64,mem64 [rm:       o64 85 /r                         ] ND,SM0-1,LONG,FL,PROT,X86_64 */
        /* 324 001(85) 110 : SM0,SM1,LONG,FL,PROT,X86_64 */
        {I_TEST, 2, {REG_GPR|BITS64,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+71438, 30},
    /*   8 : TEST reg_al,imm8 [-i:       o8 a8 ib                          ] SM0-1,NOAPX,FL,8086 */
        /* 001(a8) 021 : SM0,SM1,NOAPX,FL,8086 */
        {I_TEST, 2, {REG_AL|RN_L16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+72485, 51},
    /*   9 : TEST reg_ax,imm16 [-i:       o16 a9 iw                         ] SM0-1,NOAPX,FL,8086 */
        /* 320 001(a9) 031 : SM0,SM1,NOAPX,FL,8086 */
        {I_TEST, 2, {REG_AX|RN_L16,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+71443, 51},
    /*  10 : TEST reg_eax,imm32 [-i:       o32 a9 id                         ] SM0-1,NOAPX,FL,386 */
        /* 321 001(a9) 041 : SM0,SM1,NOAPX,FL,386 */
        {I_TEST, 2, {REG_EAX|RN_L16,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+71448, 52},
    /*  11 : TEST reg_rax,sdword64 [-i:       o64 a9 id,s                       ] SM0-1,NOAPX,LONG,FL,PROT,X86_64 */
        /* 324 001(a9) 255 : SM0,SM1,NOAPX,LONG,FL,PROT,X86_64 */
        {I_TEST, 2, {REG_RAX|RN_L16,SDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+71453, 53},
    /*  12 : TEST rm8,imm8 [mi:       o8 f6 /0 ib                       ] SM0-1,FL,8086 */
        /* 001(f6) 200 021 : SM0,SM1,FL,8086 */
        {I_TEST, 2, {RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+71458, 28},
    /*  13 : TEST rm16,imm16 [mi:       o16 f7 /0 iw                      ] SM0-1,FL,8086 */
        /* 320 001(f7) 200 031 : SM0,SM1,FL,8086 */
        {I_TEST, 2, {RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66476, 28},
    /*  14 : TEST rm32,imm32 [mi:       o32 f7 /0 id                      ] SM0-1,FL,386 */
        /* 321 001(f7) 200 041 : SM0,SM1,FL,386 */
        {I_TEST, 2, {RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+66482, 29},
    /*  15 : TEST rm64,sdword64 [mi:       o64 f7 /0 id,s                    ] SM0-1,LONG,FL,PROT,X86_64 */
        /* 324 001(f7) 200 255 : SM0,SM1,LONG,FL,PROT,X86_64 */
        {I_TEST, 2, {RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+66488, 30},
    /*  16 : TEST kreg8,kreg8 [rm:       vex.l0.0f.ko8 99 /r              ] ND,SM0-1,ZU,FL,AVX512DQ,FUTURE */
        /* 270(001 001) 001(99) 110 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512DQ,FUTURE */
        {I_TEST, 2, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65538, 518},
    /*  17 : TEST kreg8,kreg8 [rm:       evex.l0.0f.ko8 99 /r              ] ND,SM0-1,ZU,FL,AVX512DQ,FUTURE,APX */
        /* 250(f1 7d 08) 300 001(99) 110 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_TEST, 2, {OPMASKREG|BITS8,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+30204, 519},
    /*  18 : TEST kreg16,kreg16 [rm:       vex.l0.0f.ko16 99 /r             ] ND,SM0-1,ZU,FL,AVX512DQ,FUTURE */
        /* 270(001 000) 001(99) 110 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512DQ,FUTURE */
        {I_TEST, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65545, 518},
    /*  19 : TEST kreg16,kreg16 [rm:       evex.l0.0f.ko16 99 /r             ] ND,SM0-1,ZU,FL,AVX512DQ,FUTURE,APX */
        /* 250(f1 7c 08) 300 001(99) 110 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_TEST, 2, {OPMASKREG|BITS16,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+30213, 519},
    /*  20 : TEST kreg32,kreg32 [rm:       vex.l0.0f.ko32 99 /r             ] ND,SM0-1,ZU,FL,AVX512BW,FUTURE */
        /* 270(001 201) 001(99) 110 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_TEST, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65552, 522},
    /*  21 : TEST kreg32,kreg32 [rm:       evex.l0.0f.ko32 99 /r             ] ND,SM0-1,ZU,FL,AVX512BW,FUTURE,APX */
        /* 250(f1 fd 08) 300 001(99) 110 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_TEST, 2, {OPMASKREG|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+30222, 523},
    /*  22 : TEST kreg64,kreg64 [rm:       vex.l0.0f.ko64 99 /r             ] ND,SM0-1,ZU,FL,AVX512BW,FUTURE */
        /* 270(001 200) 001(99) 110 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_TEST, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65559, 522},
    /*  23 : TEST kreg64,kreg64 [rm:       evex.l0.0f.ko64 99 /r             ] ND,SM0-1,ZU,FL,AVX512BW,FUTURE,APX */
        /* 250(f1 fc 08) 300 001(99) 110 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_TEST, 2, {OPMASKREG|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+30231, 523},
};

static const struct itemplate instrux_ROL[100] = {
    /*   0 : ROL rm8,unity [m-:       o8 d0 /0                          ] FL,8086 */
        /* 001(d0) 200 : FL,8086 */
        {I_ROL, 2, {RM_GPR|BITS8,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+23783, 54},
    /*   1 : ROL rm16,unity [m-:       o16 d1 /0                         ] FL,8086 */
        /* 320 001(d1) 200 : FL,8086 */
        {I_ROL, 2, {RM_GPR|BITS16,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+10688, 54},
    /*   2 : ROL rm32,unity [m-:       o32 d1 /0                         ] FL,386 */
        /* 321 001(d1) 200 : FL,386 */
        {I_ROL, 2, {RM_GPR|BITS32,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+10718, 55},
    /*   3 : ROL rm64,unity [m-:       o64 d1 /0                         ] LONG,FL,PROT,X86_64 */
        /* 324 001(d1) 200 : LONG,FL,PROT,X86_64 */
        {I_ROL, 2, {RM_GPR|BITS64,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+10748, 56},
    /*   4 : ROL rm8,reg_cl [m-:       o8 d2 /0                          ] FL,8086 */
        /* 001(d2) 200 : FL,8086 */
        {I_ROL, 2, {RM_GPR|BITS8,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+23810, 54},
    /*   5 : ROL rm16,reg_cl [m-:       o16 d3 /0                         ] FL,8086 */
        /* 320 001(d3) 200 : FL,8086 */
        {I_ROL, 2, {RM_GPR|BITS16,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+10778, 54},
    /*   6 : ROL rm32,reg_cl [m-:       o32 d3 /0                         ] FL,386 */
        /* 321 001(d3) 200 : FL,386 */
        {I_ROL, 2, {RM_GPR|BITS32,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+10808, 55},
    /*   7 : ROL rm64,reg_cl [m-:       o64 d3 /0                         ] LONG,FL,PROT,X86_64 */
        /* 324 001(d3) 200 : LONG,FL,PROT,X86_64 */
        {I_ROL, 2, {RM_GPR|BITS64,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+10838, 56},
    /*   8 : ROL rm8,reg_cx [m-:       o8 d2 /0                          ] ND,FL,8086 */
        /* 001(d2) 200 : FL,8086 */
        {I_ROL, 2, {RM_GPR|BITS8,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+23810, 54},
    /*   9 : ROL rm16,reg_cx [m-:       o16 d3 /0                         ] ND,FL,8086 */
        /* 320 001(d3) 200 : FL,8086 */
        {I_ROL, 2, {RM_GPR|BITS16,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+10778, 54},
    /*  10 : ROL rm32,reg_cx [m-:       o32 d3 /0                         ] ND,FL,386 */
        /* 321 001(d3) 200 : FL,386 */
        {I_ROL, 2, {RM_GPR|BITS32,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+10808, 55},
    /*  11 : ROL rm64,reg_cx [m-:       o64 d3 /0                         ] ND,LONG,FL,PROT,X86_64 */
        /* 324 001(d3) 200 : LONG,FL,PROT,X86_64 */
        {I_ROL, 2, {RM_GPR|BITS64,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+10838, 56},
    /*  12 : ROL rm8,reg_ecx [m-:       o8 d2 /0                          ] ND,FL,8086 */
        /* 001(d2) 200 : FL,8086 */
        {I_ROL, 2, {RM_GPR|BITS8,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+23810, 54},
    /*  13 : ROL rm16,reg_ecx [m-:       o16 d3 /0                         ] ND,FL,8086 */
        /* 320 001(d3) 200 : FL,8086 */
        {I_ROL, 2, {RM_GPR|BITS16,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+10778, 54},
    /*  14 : ROL rm32,reg_ecx [m-:       o32 d3 /0                         ] ND,FL,386 */
        /* 321 001(d3) 200 : FL,386 */
        {I_ROL, 2, {RM_GPR|BITS32,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+10808, 55},
    /*  15 : ROL rm64,reg_ecx [m-:       o64 d3 /0                         ] ND,LONG,FL,PROT,X86_64 */
        /* 324 001(d3) 200 : LONG,FL,PROT,X86_64 */
        {I_ROL, 2, {RM_GPR|BITS64,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+10838, 56},
    /*  16 : ROL rm8,reg_rcx [m-:       o8 d2 /0                          ] ND,FL,8086 */
        /* 001(d2) 200 : FL,8086 */
        {I_ROL, 2, {RM_GPR|BITS8,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+23810, 54},
    /*  17 : ROL rm16,reg_rcx [m-:       o16 d3 /0                         ] ND,FL,8086 */
        /* 320 001(d3) 200 : FL,8086 */
        {I_ROL, 2, {RM_GPR|BITS16,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+10778, 54},
    /*  18 : ROL rm32,reg_rcx [m-:       o32 d3 /0                         ] ND,FL,386 */
        /* 321 001(d3) 200 : FL,386 */
        {I_ROL, 2, {RM_GPR|BITS32,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+10808, 55},
    /*  19 : ROL rm64,reg_rcx [m-:       o64 d3 /0                         ] ND,LONG,FL,PROT,X86_64 */
        /* 324 001(d3) 200 : LONG,FL,PROT,X86_64 */
        {I_ROL, 2, {RM_GPR|BITS64,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+10838, 56},
    /*  20 : ROL rm8,imm8 [mi:       o8 c0 /0 ib,u                     ] FL,186 */
        /* 001(c0) 200 025 : FL,186 */
        {I_ROL, 2, {RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+10868, 57},
    /*  21 : ROL rm16,imm8 [mi:       o16 c1 /0 ib,u                    ] FL,186 */
        /* 320 001(c1) 200 025 : FL,186 */
        {I_ROL, 2, {RM_GPR|BITS16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1437, 57},
    /*  22 : ROL rm32,imm8 [mi:       o32 c1 /0 ib,u                    ] FL,386 */
        /* 321 001(c1) 200 025 : FL,386 */
        {I_ROL, 2, {RM_GPR|BITS32,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1470, 55},
    /*  23 : ROL rm64,imm8 [mi:       o64 c1 /0 ib,u                    ] LONG,FL,PROT,X86_64 */
        /* 324 001(c1) 200 025 : LONG,FL,PROT,X86_64 */
        {I_ROL, 2, {RM_GPR|BITS64,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1503, 56},
    /*  24 : ROL reg32,rm32,imm_known8 [rmi:      vex.lz.f2.0f3a.w0 f0 /r ib^1f     ] ND,SM0-1,OPT,NF,NF_R,BMI2,FUTURE */
        /* 270(003 003) 001(f0) 110 306 000 037 : SM0,SM1,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_ROL, 3, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,IMM_KNOWN|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+10643, 60},
    /*  25 : ROL reg64,rm64,imm_known8 [rmi:      vex.lz.f2.0f3a.w1 f0 /r ib^3f     ] ND,SM0-1,OPT,NF,NF_R,BMI2,FUTURE */
        /* 270(003 203) 001(f0) 110 306 000 077 : SM0,SM1,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_ROL, 3, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,IMM_KNOWN|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+10653, 60},
    /*  26 : ROL reg8?,rm8,unity [vm-:      evex.nd1.nf.l0.m4.o8 d0 /0        ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d0) 210 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 3, {REG_GPR|BITS8,RM_GPR|BITS8,UNITY|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+23760, 35},
    /*  27 : ROL rm8,unity [m-:      evex.nd0.nf.l0.m4.o8 d0 /0        ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(d0) 200 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {RM_GPR|BITS8,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+23769, 62},
    /*  28 : ROL reg8?,unity [v+m-:      evex.nd1.nf.l0.m4.o8 d0 /0        ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d0) 200 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {REG_GPR|BITS8,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+23778, 63},
    /*  29 : ROL reg16?,rm16,unity [vm-:      evex.nd1.nf.l0.m4.o16 d1 /0       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d1) 210 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 3, {REG_GPR|BITS16,RM_GPR|BITS16,UNITY|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+10663, 38},
    /*  30 : ROL rm16,unity [m-:      evex.nd0.nf.l0.m4.o16 d1 /0       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(d1) 200 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {RM_GPR|BITS16,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+10673, 64},
    /*  31 : ROL reg16?,unity [v+m-:      evex.nd1.nf.l0.m4.o16 d1 /0       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d1) 200 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {REG_GPR|BITS16,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+10683, 65},
    /*  32 : ROL reg32?,rm32,unity [vm-:      evex.nd1.nf.l0.m4.o32 d1 /0       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d1) 210 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,UNITY|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+10693, 41},
    /*  33 : ROL rm32,unity [m-:      evex.nd0.nf.l0.m4.o32 d1 /0       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(d1) 200 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {RM_GPR|BITS32,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+10703, 66},
    /*  34 : ROL reg32?,unity [v+m-:      evex.nd1.nf.l0.m4.o32 d1 /0       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d1) 200 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {REG_GPR|BITS32,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+10713, 67},
    /*  35 : ROL reg64?,rm64,unity [vm-:      evex.nd1.nf.l0.m4.o64 d1 /0       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d1) 210 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 3, {REG_GPR|BITS64,RM_GPR|BITS64,UNITY|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+10723, 41},
    /*  36 : ROL rm64,unity [m-:      evex.nd0.nf.l0.m4.o64 d1 /0       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(d1) 200 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {RM_GPR|BITS64,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+10733, 66},
    /*  37 : ROL reg64?,unity [v+m-:      evex.nd1.nf.l0.m4.o64 d1 /0       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d1) 200 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {REG_GPR|BITS64,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+10743, 67},
    /*  38 : ROL reg8?,rm8,reg_cl [vm-:      evex.nd1.nf.l0.m4.o8 d2 /0        ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 210 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 3, {REG_GPR|BITS8,RM_GPR|BITS8,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+23787, 35},
    /*  39 : ROL rm8,reg_cl [m-:      evex.nd0.nf.l0.m4.o8 d2 /0        ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(d2) 200 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {RM_GPR|BITS8,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+23796, 62},
    /*  40 : ROL reg8?,reg_cl [v+m-:      evex.nd1.nf.l0.m4.o8 d2 /0        ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 200 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {REG_GPR|BITS8,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+23805, 63},
    /*  41 : ROL reg16?,rm16,reg_cl [vm-:      evex.nd1.nf.l0.m4.o16 d3 /0       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 210 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 3, {REG_GPR|BITS16,RM_GPR|BITS16,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+10753, 38},
    /*  42 : ROL rm16,reg_cl [m-:      evex.nd0.nf.l0.m4.o16 d3 /0       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(d3) 200 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {RM_GPR|BITS16,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+10763, 64},
    /*  43 : ROL reg16?,reg_cl [v+m-:      evex.nd1.nf.l0.m4.o16 d3 /0       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 200 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {REG_GPR|BITS16,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+10773, 65},
    /*  44 : ROL reg32?,rm32,reg_cl [vm-:      evex.nd1.nf.l0.m4.o32 d3 /0       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 210 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+10783, 41},
    /*  45 : ROL rm32,reg_cl [m-:      evex.nd0.nf.l0.m4.o32 d3 /0       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(d3) 200 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {RM_GPR|BITS32,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+10793, 66},
    /*  46 : ROL reg32?,reg_cl [v+m-:      evex.nd1.nf.l0.m4.o32 d3 /0       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 200 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {REG_GPR|BITS32,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+10803, 67},
    /*  47 : ROL reg64?,rm64,reg_cl [vm-:      evex.nd1.nf.l0.m4.o64 d3 /0       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 210 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+10813, 41},
    /*  48 : ROL rm64,reg_cl [m-:      evex.nd0.nf.l0.m4.o64 d3 /0       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(d3) 200 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {RM_GPR|BITS64,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+10823, 66},
    /*  49 : ROL reg64?,reg_cl [v+m-:      evex.nd1.nf.l0.m4.o64 d3 /0       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 200 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {REG_GPR|BITS64,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+10833, 67},
    /*  50 : ROL reg8?,rm8,reg_cx [vm-:      evex.nd1.nf.l0.m4.o8 d2 /0        ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 210 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 3, {REG_GPR|BITS8,RM_GPR|BITS8,REG_CX,0,0}, NO_DECORATOR, nasm_bytecodes+23787, 35},
    /*  51 : ROL rm8,reg_cx [m-:      evex.nd0.nf.l0.m4.o8 d2 /0        ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(d2) 200 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {RM_GPR|BITS8,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+23796, 62},
    /*  52 : ROL reg8?,reg_cx [v+m-:      evex.nd1.nf.l0.m4.o8 d2 /0        ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 200 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {REG_GPR|BITS8,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+23805, 63},
    /*  53 : ROL reg16?,rm16,reg_cx [vm-:      evex.nd1.nf.l0.m4.o16 d3 /0       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 210 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 3, {REG_GPR|BITS16,RM_GPR|BITS16,REG_CX,0,0}, NO_DECORATOR, nasm_bytecodes+10753, 38},
    /*  54 : ROL rm16,reg_cx [m-:      evex.nd0.nf.l0.m4.o16 d3 /0       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(d3) 200 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {RM_GPR|BITS16,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+10763, 64},
    /*  55 : ROL reg16?,reg_cx [v+m-:      evex.nd1.nf.l0.m4.o16 d3 /0       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 200 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {REG_GPR|BITS16,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+10773, 65},
    /*  56 : ROL reg32?,rm32,reg_cx [vm-:      evex.nd1.nf.l0.m4.o32 d3 /0       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 210 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_CX,0,0}, NO_DECORATOR, nasm_bytecodes+10783, 41},
    /*  57 : ROL rm32,reg_cx [m-:      evex.nd0.nf.l0.m4.o32 d3 /0       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(d3) 200 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {RM_GPR|BITS32,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+10793, 66},
    /*  58 : ROL reg32?,reg_cx [v+m-:      evex.nd1.nf.l0.m4.o32 d3 /0       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 200 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {REG_GPR|BITS32,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+10803, 67},
    /*  59 : ROL reg64?,rm64,reg_cx [vm-:      evex.nd1.nf.l0.m4.o64 d3 /0       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 210 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_CX,0,0}, NO_DECORATOR, nasm_bytecodes+10813, 41},
    /*  60 : ROL rm64,reg_cx [m-:      evex.nd0.nf.l0.m4.o64 d3 /0       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(d3) 200 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {RM_GPR|BITS64,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+10823, 66},
    /*  61 : ROL reg64?,reg_cx [v+m-:      evex.nd1.nf.l0.m4.o64 d3 /0       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 200 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {REG_GPR|BITS64,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+10833, 67},
    /*  62 : ROL reg8?,rm8,reg_ecx [vm-:      evex.nd1.nf.l0.m4.o8 d2 /0        ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 210 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 3, {REG_GPR|BITS8,RM_GPR|BITS8,REG_ECX,0,0}, NO_DECORATOR, nasm_bytecodes+23787, 35},
    /*  63 : ROL rm8,reg_ecx [m-:      evex.nd0.nf.l0.m4.o8 d2 /0        ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(d2) 200 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {RM_GPR|BITS8,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+23796, 62},
    /*  64 : ROL reg8?,reg_ecx [v+m-:      evex.nd1.nf.l0.m4.o8 d2 /0        ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 200 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {REG_GPR|BITS8,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+23805, 63},
    /*  65 : ROL reg16?,rm16,reg_ecx [vm-:      evex.nd1.nf.l0.m4.o16 d3 /0       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 210 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 3, {REG_GPR|BITS16,RM_GPR|BITS16,REG_ECX,0,0}, NO_DECORATOR, nasm_bytecodes+10753, 38},
    /*  66 : ROL rm16,reg_ecx [m-:      evex.nd0.nf.l0.m4.o16 d3 /0       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(d3) 200 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {RM_GPR|BITS16,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+10763, 64},
    /*  67 : ROL reg16?,reg_ecx [v+m-:      evex.nd1.nf.l0.m4.o16 d3 /0       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 200 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {REG_GPR|BITS16,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+10773, 65},
    /*  68 : ROL reg32?,rm32,reg_ecx [vm-:      evex.nd1.nf.l0.m4.o32 d3 /0       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 210 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_ECX,0,0}, NO_DECORATOR, nasm_bytecodes+10783, 41},
    /*  69 : ROL rm32,reg_ecx [m-:      evex.nd0.nf.l0.m4.o32 d3 /0       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(d3) 200 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {RM_GPR|BITS32,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+10793, 66},
    /*  70 : ROL reg32?,reg_ecx [v+m-:      evex.nd1.nf.l0.m4.o32 d3 /0       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 200 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {REG_GPR|BITS32,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+10803, 67},
    /*  71 : ROL reg64?,rm64,reg_ecx [vm-:      evex.nd1.nf.l0.m4.o64 d3 /0       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 210 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_ECX,0,0}, NO_DECORATOR, nasm_bytecodes+10813, 41},
    /*  72 : ROL rm64,reg_ecx [m-:      evex.nd0.nf.l0.m4.o64 d3 /0       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(d3) 200 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {RM_GPR|BITS64,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+10823, 66},
    /*  73 : ROL reg64?,reg_ecx [v+m-:      evex.nd1.nf.l0.m4.o64 d3 /0       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 200 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {REG_GPR|BITS64,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+10833, 67},
    /*  74 : ROL reg8?,rm8,reg_rcx [vm-:      evex.nd1.nf.l0.m4.o8 d2 /0        ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 210 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 3, {REG_GPR|BITS8,RM_GPR|BITS8,REG_RCX,0,0}, NO_DECORATOR, nasm_bytecodes+23787, 35},
    /*  75 : ROL rm8,reg_rcx [m-:      evex.nd0.nf.l0.m4.o8 d2 /0        ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(d2) 200 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {RM_GPR|BITS8,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+23796, 62},
    /*  76 : ROL reg8?,reg_rcx [v+m-:      evex.nd1.nf.l0.m4.o8 d2 /0        ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 200 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {REG_GPR|BITS8,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+23805, 63},
    /*  77 : ROL reg16?,rm16,reg_rcx [vm-:      evex.nd1.nf.l0.m4.o16 d3 /0       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 210 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 3, {REG_GPR|BITS16,RM_GPR|BITS16,REG_RCX,0,0}, NO_DECORATOR, nasm_bytecodes+10753, 38},
    /*  78 : ROL rm16,reg_rcx [m-:      evex.nd0.nf.l0.m4.o16 d3 /0       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(d3) 200 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {RM_GPR|BITS16,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+10763, 64},
    /*  79 : ROL reg16?,reg_rcx [v+m-:      evex.nd1.nf.l0.m4.o16 d3 /0       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 200 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {REG_GPR|BITS16,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+10773, 65},
    /*  80 : ROL reg32?,rm32,reg_rcx [vm-:      evex.nd1.nf.l0.m4.o32 d3 /0       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 210 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_RCX,0,0}, NO_DECORATOR, nasm_bytecodes+10783, 41},
    /*  81 : ROL rm32,reg_rcx [m-:      evex.nd0.nf.l0.m4.o32 d3 /0       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(d3) 200 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {RM_GPR|BITS32,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+10793, 66},
    /*  82 : ROL reg32?,reg_rcx [v+m-:      evex.nd1.nf.l0.m4.o32 d3 /0       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 200 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {REG_GPR|BITS32,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+10803, 67},
    /*  83 : ROL reg64?,rm64,reg_rcx [vm-:      evex.nd1.nf.l0.m4.o64 d3 /0       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 210 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_RCX,0,0}, NO_DECORATOR, nasm_bytecodes+10813, 41},
    /*  84 : ROL rm64,reg_rcx [m-:      evex.nd0.nf.l0.m4.o64 d3 /0       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(d3) 200 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {RM_GPR|BITS64,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+10823, 66},
    /*  85 : ROL reg64?,reg_rcx [v+m-:      evex.nd1.nf.l0.m4.o64 d3 /0       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 200 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {REG_GPR|BITS64,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+10833, 67},
    /*  86 : ROL reg8?,rm8,imm8 [vmi:      evex.nd1.nf.l0.m4.o8 c0 /0 ib,u   ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(c0) 210 026 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 3, {REG_GPR|BITS8,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+10843, 35},
    /*  87 : ROL rm8,imm8 [mi:      evex.nd0.nf.l0.m4.o8 c0 /0 ib,u   ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(c0) 200 025 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+10853, 62},
    /*  88 : ROL reg8?,imm8 [v+mi:      evex.nd1.nf.l0.m4.o8 c0 /0 ib,u   ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(c0) 200 025 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {REG_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+10863, 63},
    /*  89 : ROL reg16?,rm16,imm8 [vmi:      evex.nd1.nf.l0.m4.o16 c1 /0 ib,u  ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(c1) 210 026 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 3, {REG_GPR|BITS16,RM_GPR|BITS16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+1410, 38},
    /*  90 : ROL rm16,imm8 [mi:      evex.nd0.nf.l0.m4.o16 c1 /0 ib,u  ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(c1) 200 025 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {RM_GPR|BITS16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1421, 64},
    /*  91 : ROL reg16?,imm8 [v+mi:      evex.nd1.nf.l0.m4.o16 c1 /0 ib,u  ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(c1) 200 025 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {REG_GPR|BITS16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1432, 65},
    /*  92 : ROL reg32?,rm32,imm8 [vmi:      evex.nd1.nf.l0.m4.o32 c1 /0 ib,u  ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(c1) 210 026 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+1443, 41},
    /*  93 : ROL rm32,imm8 [mi:      evex.nd0.nf.l0.m4.o32 c1 /0 ib,u  ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(c1) 200 025 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {RM_GPR|BITS32,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1454, 66},
    /*  94 : ROL reg32?,imm8 [v+mi:      evex.nd1.nf.l0.m4.o32 c1 /0 ib,u  ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(c1) 200 025 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {REG_GPR|BITS32,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1465, 67},
    /*  95 : ROL reg64?,rm64,imm8 [vmi:      evex.nd1.nf.l0.m4.o64 c1 /0 ib,u  ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(c1) 210 026 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 3, {REG_GPR|BITS64,RM_GPR|BITS64,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+1476, 41},
    /*  96 : ROL rm64,imm8 [mi:      evex.nd0.nf.l0.m4.o64 c1 /0 ib,u  ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(c1) 200 025 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {RM_GPR|BITS64,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1487, 66},
    /*  97 : ROL reg64?,imm8 [v+mi:      evex.nd1.nf.l0.m4.o64 c1 /0 ib,u  ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(c1) 200 025 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROL, 2, {REG_GPR|BITS64,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1498, 67},
    /*  98 : ROL reg32,rm32,imm_known8 [rmi:      evex.lz.f2.0f3a.w0 f0 /r ib^1f    ] ND,SM0-1,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 250(f3 7f 08) 300 001(f0) 110 306 000 037 : SM0,SM1,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_ROL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,IMM_KNOWN|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+0, 70},
    /*  99 : ROL reg64,rm64,imm_known8 [rmi:      evex.lz.f2.0f3a.w1 f0 /r ib^3f    ] ND,SM0-1,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 250(f3 ff 08) 300 001(f0) 110 306 000 077 : SM0,SM1,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_ROL, 3, {REG_GPR|BITS64,RM_GPR|BITS64,IMM_KNOWN|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+12, 70},
};

static const struct itemplate instrux_ROR[100] = {
    /*   0 : ROR rm8,unity [m-:       o8 d0 /1                          ] FL,8086 */
        /* 001(d0) 201 : FL,8086 */
        {I_ROR, 2, {RM_GPR|BITS8,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+23837, 54},
    /*   1 : ROR rm16,unity [m-:       o16 d1 /1                         ] FL,8086 */
        /* 320 001(d1) 201 : FL,8086 */
        {I_ROR, 2, {RM_GPR|BITS16,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+10898, 54},
    /*   2 : ROR rm32,unity [m-:       o32 d1 /1                         ] FL,386 */
        /* 321 001(d1) 201 : FL,386 */
        {I_ROR, 2, {RM_GPR|BITS32,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+10928, 55},
    /*   3 : ROR rm64,unity [m-:       o64 d1 /1                         ] LONG,FL,PROT,X86_64 */
        /* 324 001(d1) 201 : LONG,FL,PROT,X86_64 */
        {I_ROR, 2, {RM_GPR|BITS64,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+10958, 56},
    /*   4 : ROR rm8,reg_cl [m-:       o8 d2 /1                          ] FL,8086 */
        /* 001(d2) 201 : FL,8086 */
        {I_ROR, 2, {RM_GPR|BITS8,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+23864, 54},
    /*   5 : ROR rm16,reg_cl [m-:       o16 d3 /1                         ] FL,8086 */
        /* 320 001(d3) 201 : FL,8086 */
        {I_ROR, 2, {RM_GPR|BITS16,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+10988, 54},
    /*   6 : ROR rm32,reg_cl [m-:       o32 d3 /1                         ] FL,386 */
        /* 321 001(d3) 201 : FL,386 */
        {I_ROR, 2, {RM_GPR|BITS32,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11018, 55},
    /*   7 : ROR rm64,reg_cl [m-:       o64 d3 /1                         ] LONG,FL,PROT,X86_64 */
        /* 324 001(d3) 201 : LONG,FL,PROT,X86_64 */
        {I_ROR, 2, {RM_GPR|BITS64,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11048, 56},
    /*   8 : ROR rm8,reg_cx [m-:       o8 d2 /1                          ] ND,FL,8086 */
        /* 001(d2) 201 : FL,8086 */
        {I_ROR, 2, {RM_GPR|BITS8,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+23864, 54},
    /*   9 : ROR rm16,reg_cx [m-:       o16 d3 /1                         ] ND,FL,8086 */
        /* 320 001(d3) 201 : FL,8086 */
        {I_ROR, 2, {RM_GPR|BITS16,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+10988, 54},
    /*  10 : ROR rm32,reg_cx [m-:       o32 d3 /1                         ] ND,FL,386 */
        /* 321 001(d3) 201 : FL,386 */
        {I_ROR, 2, {RM_GPR|BITS32,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11018, 55},
    /*  11 : ROR rm64,reg_cx [m-:       o64 d3 /1                         ] ND,LONG,FL,PROT,X86_64 */
        /* 324 001(d3) 201 : LONG,FL,PROT,X86_64 */
        {I_ROR, 2, {RM_GPR|BITS64,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11048, 56},
    /*  12 : ROR rm8,reg_ecx [m-:       o8 d2 /1                          ] ND,FL,8086 */
        /* 001(d2) 201 : FL,8086 */
        {I_ROR, 2, {RM_GPR|BITS8,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+23864, 54},
    /*  13 : ROR rm16,reg_ecx [m-:       o16 d3 /1                         ] ND,FL,8086 */
        /* 320 001(d3) 201 : FL,8086 */
        {I_ROR, 2, {RM_GPR|BITS16,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+10988, 54},
    /*  14 : ROR rm32,reg_ecx [m-:       o32 d3 /1                         ] ND,FL,386 */
        /* 321 001(d3) 201 : FL,386 */
        {I_ROR, 2, {RM_GPR|BITS32,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11018, 55},
    /*  15 : ROR rm64,reg_ecx [m-:       o64 d3 /1                         ] ND,LONG,FL,PROT,X86_64 */
        /* 324 001(d3) 201 : LONG,FL,PROT,X86_64 */
        {I_ROR, 2, {RM_GPR|BITS64,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11048, 56},
    /*  16 : ROR rm8,reg_rcx [m-:       o8 d2 /1                          ] ND,FL,8086 */
        /* 001(d2) 201 : FL,8086 */
        {I_ROR, 2, {RM_GPR|BITS8,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+23864, 54},
    /*  17 : ROR rm16,reg_rcx [m-:       o16 d3 /1                         ] ND,FL,8086 */
        /* 320 001(d3) 201 : FL,8086 */
        {I_ROR, 2, {RM_GPR|BITS16,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+10988, 54},
    /*  18 : ROR rm32,reg_rcx [m-:       o32 d3 /1                         ] ND,FL,386 */
        /* 321 001(d3) 201 : FL,386 */
        {I_ROR, 2, {RM_GPR|BITS32,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11018, 55},
    /*  19 : ROR rm64,reg_rcx [m-:       o64 d3 /1                         ] ND,LONG,FL,PROT,X86_64 */
        /* 324 001(d3) 201 : LONG,FL,PROT,X86_64 */
        {I_ROR, 2, {RM_GPR|BITS64,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11048, 56},
    /*  20 : ROR rm8,imm8 [mi:       o8 c0 /1 ib,u                     ] FL,186 */
        /* 001(c0) 201 025 : FL,186 */
        {I_ROR, 2, {RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+11078, 57},
    /*  21 : ROR rm16,imm8 [mi:       o16 c1 /1 ib,u                    ] FL,186 */
        /* 320 001(c1) 201 025 : FL,186 */
        {I_ROR, 2, {RM_GPR|BITS16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1536, 57},
    /*  22 : ROR rm32,imm8 [mi:       o32 c1 /1 ib,u                    ] FL,386 */
        /* 321 001(c1) 201 025 : FL,386 */
        {I_ROR, 2, {RM_GPR|BITS32,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1569, 55},
    /*  23 : ROR rm64,imm8 [mi:       o64 c1 /1 ib,u                    ] LONG,FL,PROT,X86_64 */
        /* 324 001(c1) 201 025 : LONG,FL,PROT,X86_64 */
        {I_ROR, 2, {RM_GPR|BITS64,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1602, 56},
    /*  24 : ROR reg32,rm32,imm8 [rmi:      vex.lz.f2.0f3a.w0 f0 /r ib        ] ND,SM0-1,OPT,NF,NF_R,BMI2,FUTURE */
        /* 270(003 003) 001(f0) 110 022 : SM0,SM1,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_ROR, 3, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51093, 60},
    /*  25 : ROR reg64,rm64,imm8 [rmi:      vex.lz.f2.0f3a.w1 f0 /r ib        ] ND,SM0-1,OPT,NF,NF_R,BMI2,FUTURE */
        /* 270(003 203) 001(f0) 110 022 : SM0,SM1,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_ROR, 3, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51101, 60},
    /*  26 : ROR reg8?,rm8,unity [vm-:      evex.nd1.nf.l0.m4.o8 d0 /1        ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d0) 211 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 3, {REG_GPR|BITS8,RM_GPR|BITS8,UNITY|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+23814, 35},
    /*  27 : ROR rm8,unity [m-:      evex.nd0.nf.l0.m4.o8 d0 /1        ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(d0) 201 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {RM_GPR|BITS8,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+23823, 62},
    /*  28 : ROR reg8?,unity [v+m-:      evex.nd1.nf.l0.m4.o8 d0 /1        ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d0) 201 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {REG_GPR|BITS8,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+23832, 63},
    /*  29 : ROR reg16?,rm16,unity [vm-:      evex.nd1.nf.l0.m4.o16 d1 /1       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d1) 211 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 3, {REG_GPR|BITS16,RM_GPR|BITS16,UNITY|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+10873, 38},
    /*  30 : ROR rm16,unity [m-:      evex.nd0.nf.l0.m4.o16 d1 /1       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(d1) 201 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {RM_GPR|BITS16,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+10883, 64},
    /*  31 : ROR reg16?,unity [v+m-:      evex.nd1.nf.l0.m4.o16 d1 /1       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d1) 201 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {REG_GPR|BITS16,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+10893, 65},
    /*  32 : ROR reg32?,rm32,unity [vm-:      evex.nd1.nf.l0.m4.o32 d1 /1       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d1) 211 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,UNITY|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+10903, 41},
    /*  33 : ROR rm32,unity [m-:      evex.nd0.nf.l0.m4.o32 d1 /1       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(d1) 201 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {RM_GPR|BITS32,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+10913, 66},
    /*  34 : ROR reg32?,unity [v+m-:      evex.nd1.nf.l0.m4.o32 d1 /1       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d1) 201 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {REG_GPR|BITS32,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+10923, 67},
    /*  35 : ROR reg64?,rm64,unity [vm-:      evex.nd1.nf.l0.m4.o64 d1 /1       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d1) 211 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,UNITY|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+10933, 41},
    /*  36 : ROR rm64,unity [m-:      evex.nd0.nf.l0.m4.o64 d1 /1       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(d1) 201 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {RM_GPR|BITS64,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+10943, 66},
    /*  37 : ROR reg64?,unity [v+m-:      evex.nd1.nf.l0.m4.o64 d1 /1       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d1) 201 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {REG_GPR|BITS64,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+10953, 67},
    /*  38 : ROR reg8?,rm8,reg_cl [vm-:      evex.nd1.nf.l0.m4.o8 d2 /1        ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 211 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 3, {REG_GPR|BITS8,RM_GPR|BITS8,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+23841, 35},
    /*  39 : ROR rm8,reg_cl [m-:      evex.nd0.nf.l0.m4.o8 d2 /1        ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(d2) 201 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {RM_GPR|BITS8,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+23850, 62},
    /*  40 : ROR reg8?,reg_cl [v+m-:      evex.nd1.nf.l0.m4.o8 d2 /1        ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 201 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {REG_GPR|BITS8,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+23859, 63},
    /*  41 : ROR reg16?,rm16,reg_cl [vm-:      evex.nd1.nf.l0.m4.o16 d3 /1       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 211 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 3, {REG_GPR|BITS16,RM_GPR|BITS16,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+10963, 38},
    /*  42 : ROR rm16,reg_cl [m-:      evex.nd0.nf.l0.m4.o16 d3 /1       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(d3) 201 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {RM_GPR|BITS16,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+10973, 64},
    /*  43 : ROR reg16?,reg_cl [v+m-:      evex.nd1.nf.l0.m4.o16 d3 /1       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 201 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {REG_GPR|BITS16,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+10983, 65},
    /*  44 : ROR reg32?,rm32,reg_cl [vm-:      evex.nd1.nf.l0.m4.o32 d3 /1       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 211 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+10993, 41},
    /*  45 : ROR rm32,reg_cl [m-:      evex.nd0.nf.l0.m4.o32 d3 /1       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(d3) 201 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {RM_GPR|BITS32,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11003, 66},
    /*  46 : ROR reg32?,reg_cl [v+m-:      evex.nd1.nf.l0.m4.o32 d3 /1       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 201 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {REG_GPR|BITS32,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11013, 67},
    /*  47 : ROR reg64?,rm64,reg_cl [vm-:      evex.nd1.nf.l0.m4.o64 d3 /1       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 211 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+11023, 41},
    /*  48 : ROR rm64,reg_cl [m-:      evex.nd0.nf.l0.m4.o64 d3 /1       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(d3) 201 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {RM_GPR|BITS64,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11033, 66},
    /*  49 : ROR reg64?,reg_cl [v+m-:      evex.nd1.nf.l0.m4.o64 d3 /1       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 201 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {REG_GPR|BITS64,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11043, 67},
    /*  50 : ROR reg8?,rm8,reg_cx [vm-:      evex.nd1.nf.l0.m4.o8 d2 /1        ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 211 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 3, {REG_GPR|BITS8,RM_GPR|BITS8,REG_CX,0,0}, NO_DECORATOR, nasm_bytecodes+23841, 35},
    /*  51 : ROR rm8,reg_cx [m-:      evex.nd0.nf.l0.m4.o8 d2 /1        ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(d2) 201 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {RM_GPR|BITS8,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+23850, 62},
    /*  52 : ROR reg8?,reg_cx [v+m-:      evex.nd1.nf.l0.m4.o8 d2 /1        ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 201 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {REG_GPR|BITS8,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+23859, 63},
    /*  53 : ROR reg16?,rm16,reg_cx [vm-:      evex.nd1.nf.l0.m4.o16 d3 /1       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 211 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 3, {REG_GPR|BITS16,RM_GPR|BITS16,REG_CX,0,0}, NO_DECORATOR, nasm_bytecodes+10963, 38},
    /*  54 : ROR rm16,reg_cx [m-:      evex.nd0.nf.l0.m4.o16 d3 /1       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(d3) 201 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {RM_GPR|BITS16,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+10973, 64},
    /*  55 : ROR reg16?,reg_cx [v+m-:      evex.nd1.nf.l0.m4.o16 d3 /1       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 201 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {REG_GPR|BITS16,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+10983, 65},
    /*  56 : ROR reg32?,rm32,reg_cx [vm-:      evex.nd1.nf.l0.m4.o32 d3 /1       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 211 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_CX,0,0}, NO_DECORATOR, nasm_bytecodes+10993, 41},
    /*  57 : ROR rm32,reg_cx [m-:      evex.nd0.nf.l0.m4.o32 d3 /1       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(d3) 201 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {RM_GPR|BITS32,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11003, 66},
    /*  58 : ROR reg32?,reg_cx [v+m-:      evex.nd1.nf.l0.m4.o32 d3 /1       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 201 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {REG_GPR|BITS32,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11013, 67},
    /*  59 : ROR reg64?,rm64,reg_cx [vm-:      evex.nd1.nf.l0.m4.o64 d3 /1       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 211 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_CX,0,0}, NO_DECORATOR, nasm_bytecodes+11023, 41},
    /*  60 : ROR rm64,reg_cx [m-:      evex.nd0.nf.l0.m4.o64 d3 /1       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(d3) 201 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {RM_GPR|BITS64,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11033, 66},
    /*  61 : ROR reg64?,reg_cx [v+m-:      evex.nd1.nf.l0.m4.o64 d3 /1       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 201 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {REG_GPR|BITS64,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11043, 67},
    /*  62 : ROR reg8?,rm8,reg_ecx [vm-:      evex.nd1.nf.l0.m4.o8 d2 /1        ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 211 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 3, {REG_GPR|BITS8,RM_GPR|BITS8,REG_ECX,0,0}, NO_DECORATOR, nasm_bytecodes+23841, 35},
    /*  63 : ROR rm8,reg_ecx [m-:      evex.nd0.nf.l0.m4.o8 d2 /1        ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(d2) 201 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {RM_GPR|BITS8,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+23850, 62},
    /*  64 : ROR reg8?,reg_ecx [v+m-:      evex.nd1.nf.l0.m4.o8 d2 /1        ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 201 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {REG_GPR|BITS8,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+23859, 63},
    /*  65 : ROR reg16?,rm16,reg_ecx [vm-:      evex.nd1.nf.l0.m4.o16 d3 /1       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 211 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 3, {REG_GPR|BITS16,RM_GPR|BITS16,REG_ECX,0,0}, NO_DECORATOR, nasm_bytecodes+10963, 38},
    /*  66 : ROR rm16,reg_ecx [m-:      evex.nd0.nf.l0.m4.o16 d3 /1       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(d3) 201 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {RM_GPR|BITS16,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+10973, 64},
    /*  67 : ROR reg16?,reg_ecx [v+m-:      evex.nd1.nf.l0.m4.o16 d3 /1       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 201 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {REG_GPR|BITS16,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+10983, 65},
    /*  68 : ROR reg32?,rm32,reg_ecx [vm-:      evex.nd1.nf.l0.m4.o32 d3 /1       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 211 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_ECX,0,0}, NO_DECORATOR, nasm_bytecodes+10993, 41},
    /*  69 : ROR rm32,reg_ecx [m-:      evex.nd0.nf.l0.m4.o32 d3 /1       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(d3) 201 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {RM_GPR|BITS32,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11003, 66},
    /*  70 : ROR reg32?,reg_ecx [v+m-:      evex.nd1.nf.l0.m4.o32 d3 /1       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 201 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {REG_GPR|BITS32,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11013, 67},
    /*  71 : ROR reg64?,rm64,reg_ecx [vm-:      evex.nd1.nf.l0.m4.o64 d3 /1       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 211 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_ECX,0,0}, NO_DECORATOR, nasm_bytecodes+11023, 41},
    /*  72 : ROR rm64,reg_ecx [m-:      evex.nd0.nf.l0.m4.o64 d3 /1       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(d3) 201 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {RM_GPR|BITS64,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11033, 66},
    /*  73 : ROR reg64?,reg_ecx [v+m-:      evex.nd1.nf.l0.m4.o64 d3 /1       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 201 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {REG_GPR|BITS64,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11043, 67},
    /*  74 : ROR reg8?,rm8,reg_rcx [vm-:      evex.nd1.nf.l0.m4.o8 d2 /1        ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 211 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 3, {REG_GPR|BITS8,RM_GPR|BITS8,REG_RCX,0,0}, NO_DECORATOR, nasm_bytecodes+23841, 35},
    /*  75 : ROR rm8,reg_rcx [m-:      evex.nd0.nf.l0.m4.o8 d2 /1        ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(d2) 201 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {RM_GPR|BITS8,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+23850, 62},
    /*  76 : ROR reg8?,reg_rcx [v+m-:      evex.nd1.nf.l0.m4.o8 d2 /1        ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 201 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {REG_GPR|BITS8,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+23859, 63},
    /*  77 : ROR reg16?,rm16,reg_rcx [vm-:      evex.nd1.nf.l0.m4.o16 d3 /1       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 211 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 3, {REG_GPR|BITS16,RM_GPR|BITS16,REG_RCX,0,0}, NO_DECORATOR, nasm_bytecodes+10963, 38},
    /*  78 : ROR rm16,reg_rcx [m-:      evex.nd0.nf.l0.m4.o16 d3 /1       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(d3) 201 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {RM_GPR|BITS16,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+10973, 64},
    /*  79 : ROR reg16?,reg_rcx [v+m-:      evex.nd1.nf.l0.m4.o16 d3 /1       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 201 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {REG_GPR|BITS16,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+10983, 65},
    /*  80 : ROR reg32?,rm32,reg_rcx [vm-:      evex.nd1.nf.l0.m4.o32 d3 /1       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 211 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_RCX,0,0}, NO_DECORATOR, nasm_bytecodes+10993, 41},
    /*  81 : ROR rm32,reg_rcx [m-:      evex.nd0.nf.l0.m4.o32 d3 /1       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(d3) 201 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {RM_GPR|BITS32,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11003, 66},
    /*  82 : ROR reg32?,reg_rcx [v+m-:      evex.nd1.nf.l0.m4.o32 d3 /1       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 201 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {REG_GPR|BITS32,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11013, 67},
    /*  83 : ROR reg64?,rm64,reg_rcx [vm-:      evex.nd1.nf.l0.m4.o64 d3 /1       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 211 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_RCX,0,0}, NO_DECORATOR, nasm_bytecodes+11023, 41},
    /*  84 : ROR rm64,reg_rcx [m-:      evex.nd0.nf.l0.m4.o64 d3 /1       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(d3) 201 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {RM_GPR|BITS64,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11033, 66},
    /*  85 : ROR reg64?,reg_rcx [v+m-:      evex.nd1.nf.l0.m4.o64 d3 /1       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 201 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {REG_GPR|BITS64,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11043, 67},
    /*  86 : ROR reg8?,rm8,imm8 [vmi:      evex.nd1.nf.l0.m4.o8 c0 /1 ib,u   ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(c0) 211 026 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 3, {REG_GPR|BITS8,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+11053, 35},
    /*  87 : ROR rm8,imm8 [mi:      evex.nd0.nf.l0.m4.o8 c0 /1 ib,u   ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(c0) 201 025 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+11063, 62},
    /*  88 : ROR reg8?,imm8 [v+mi:      evex.nd1.nf.l0.m4.o8 c0 /1 ib,u   ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(c0) 201 025 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {REG_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+11073, 63},
    /*  89 : ROR reg16?,rm16,imm8 [vmi:      evex.nd1.nf.l0.m4.o16 c1 /1 ib,u  ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(c1) 211 026 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 3, {REG_GPR|BITS16,RM_GPR|BITS16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+1509, 38},
    /*  90 : ROR rm16,imm8 [mi:      evex.nd0.nf.l0.m4.o16 c1 /1 ib,u  ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(c1) 201 025 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {RM_GPR|BITS16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1520, 64},
    /*  91 : ROR reg16?,imm8 [v+mi:      evex.nd1.nf.l0.m4.o16 c1 /1 ib,u  ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(c1) 201 025 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {REG_GPR|BITS16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1531, 65},
    /*  92 : ROR reg32?,rm32,imm8 [vmi:      evex.nd1.nf.l0.m4.o32 c1 /1 ib,u  ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(c1) 211 026 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+1542, 41},
    /*  93 : ROR rm32,imm8 [mi:      evex.nd0.nf.l0.m4.o32 c1 /1 ib,u  ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(c1) 201 025 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {RM_GPR|BITS32,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1553, 66},
    /*  94 : ROR reg32?,imm8 [v+mi:      evex.nd1.nf.l0.m4.o32 c1 /1 ib,u  ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(c1) 201 025 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {REG_GPR|BITS32,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1564, 67},
    /*  95 : ROR reg64?,rm64,imm8 [vmi:      evex.nd1.nf.l0.m4.o64 c1 /1 ib,u  ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(c1) 211 026 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+1575, 41},
    /*  96 : ROR rm64,imm8 [mi:      evex.nd0.nf.l0.m4.o64 c1 /1 ib,u  ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(c1) 201 025 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {RM_GPR|BITS64,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1586, 66},
    /*  97 : ROR reg64?,imm8 [v+mi:      evex.nd1.nf.l0.m4.o64 c1 /1 ib,u  ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(c1) 201 025 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_ROR, 2, {REG_GPR|BITS64,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1597, 67},
    /*  98 : ROR reg32,rm32,imm8 [rmi:      evex.lz.f2.0f3a.w0 f0 /r ib       ] ND,SM0-1,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 250(f3 7f 08) 300 001(f0) 110 022 : SM0,SM1,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_ROR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+12133, 70},
    /*  99 : ROR reg64,rm64,imm8 [rmi:      evex.lz.f2.0f3a.w1 f0 /r ib       ] ND,SM0-1,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 250(f3 ff 08) 300 001(f0) 110 022 : SM0,SM1,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_ROR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+12143, 70},
};

static const struct itemplate instrux_RCL[96] = {
    /*   0 : RCL rm8,unity [m-:       o8 d0 /2                          ] FL,8086 */
        /* 001(d0) 202 : FL,8086 */
        {I_RCL, 2, {RM_GPR|BITS8,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+23891, 54},
    /*   1 : RCL rm16,unity [m-:       o16 d1 /2                         ] FL,8086 */
        /* 320 001(d1) 202 : FL,8086 */
        {I_RCL, 2, {RM_GPR|BITS16,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11108, 54},
    /*   2 : RCL rm32,unity [m-:       o32 d1 /2                         ] FL,386 */
        /* 321 001(d1) 202 : FL,386 */
        {I_RCL, 2, {RM_GPR|BITS32,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11138, 55},
    /*   3 : RCL rm64,unity [m-:       o64 d1 /2                         ] LONG,FL,PROT,X86_64 */
        /* 324 001(d1) 202 : LONG,FL,PROT,X86_64 */
        {I_RCL, 2, {RM_GPR|BITS64,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11168, 56},
    /*   4 : RCL rm8,reg_cl [m-:       o8 d2 /2                          ] FL,8086 */
        /* 001(d2) 202 : FL,8086 */
        {I_RCL, 2, {RM_GPR|BITS8,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+23918, 54},
    /*   5 : RCL rm16,reg_cl [m-:       o16 d3 /2                         ] FL,8086 */
        /* 320 001(d3) 202 : FL,8086 */
        {I_RCL, 2, {RM_GPR|BITS16,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11198, 54},
    /*   6 : RCL rm32,reg_cl [m-:       o32 d3 /2                         ] FL,386 */
        /* 321 001(d3) 202 : FL,386 */
        {I_RCL, 2, {RM_GPR|BITS32,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11228, 55},
    /*   7 : RCL rm64,reg_cl [m-:       o64 d3 /2                         ] LONG,FL,PROT,X86_64 */
        /* 324 001(d3) 202 : LONG,FL,PROT,X86_64 */
        {I_RCL, 2, {RM_GPR|BITS64,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11258, 56},
    /*   8 : RCL rm8,reg_cx [m-:       o8 d2 /2                          ] ND,FL,8086 */
        /* 001(d2) 202 : FL,8086 */
        {I_RCL, 2, {RM_GPR|BITS8,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+23918, 54},
    /*   9 : RCL rm16,reg_cx [m-:       o16 d3 /2                         ] ND,FL,8086 */
        /* 320 001(d3) 202 : FL,8086 */
        {I_RCL, 2, {RM_GPR|BITS16,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11198, 54},
    /*  10 : RCL rm32,reg_cx [m-:       o32 d3 /2                         ] ND,FL,386 */
        /* 321 001(d3) 202 : FL,386 */
        {I_RCL, 2, {RM_GPR|BITS32,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11228, 55},
    /*  11 : RCL rm64,reg_cx [m-:       o64 d3 /2                         ] ND,LONG,FL,PROT,X86_64 */
        /* 324 001(d3) 202 : LONG,FL,PROT,X86_64 */
        {I_RCL, 2, {RM_GPR|BITS64,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11258, 56},
    /*  12 : RCL rm8,reg_ecx [m-:       o8 d2 /2                          ] ND,FL,8086 */
        /* 001(d2) 202 : FL,8086 */
        {I_RCL, 2, {RM_GPR|BITS8,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+23918, 54},
    /*  13 : RCL rm16,reg_ecx [m-:       o16 d3 /2                         ] ND,FL,8086 */
        /* 320 001(d3) 202 : FL,8086 */
        {I_RCL, 2, {RM_GPR|BITS16,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11198, 54},
    /*  14 : RCL rm32,reg_ecx [m-:       o32 d3 /2                         ] ND,FL,386 */
        /* 321 001(d3) 202 : FL,386 */
        {I_RCL, 2, {RM_GPR|BITS32,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11228, 55},
    /*  15 : RCL rm64,reg_ecx [m-:       o64 d3 /2                         ] ND,LONG,FL,PROT,X86_64 */
        /* 324 001(d3) 202 : LONG,FL,PROT,X86_64 */
        {I_RCL, 2, {RM_GPR|BITS64,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11258, 56},
    /*  16 : RCL rm8,reg_rcx [m-:       o8 d2 /2                          ] ND,FL,8086 */
        /* 001(d2) 202 : FL,8086 */
        {I_RCL, 2, {RM_GPR|BITS8,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+23918, 54},
    /*  17 : RCL rm16,reg_rcx [m-:       o16 d3 /2                         ] ND,FL,8086 */
        /* 320 001(d3) 202 : FL,8086 */
        {I_RCL, 2, {RM_GPR|BITS16,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11198, 54},
    /*  18 : RCL rm32,reg_rcx [m-:       o32 d3 /2                         ] ND,FL,386 */
        /* 321 001(d3) 202 : FL,386 */
        {I_RCL, 2, {RM_GPR|BITS32,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11228, 55},
    /*  19 : RCL rm64,reg_rcx [m-:       o64 d3 /2                         ] ND,LONG,FL,PROT,X86_64 */
        /* 324 001(d3) 202 : LONG,FL,PROT,X86_64 */
        {I_RCL, 2, {RM_GPR|BITS64,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11258, 56},
    /*  20 : RCL rm8,imm8 [mi:       o8 c0 /2 ib,u                     ] FL,186 */
        /* 001(c0) 202 025 : FL,186 */
        {I_RCL, 2, {RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+11288, 57},
    /*  21 : RCL rm16,imm8 [mi:       o16 c1 /2 ib,u                    ] FL,186 */
        /* 320 001(c1) 202 025 : FL,186 */
        {I_RCL, 2, {RM_GPR|BITS16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1635, 57},
    /*  22 : RCL rm32,imm8 [mi:       o32 c1 /2 ib,u                    ] FL,386 */
        /* 321 001(c1) 202 025 : FL,386 */
        {I_RCL, 2, {RM_GPR|BITS32,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1668, 55},
    /*  23 : RCL rm64,imm8 [mi:       o64 c1 /2 ib,u                    ] LONG,FL,PROT,X86_64 */
        /* 324 001(c1) 202 025 : LONG,FL,PROT,X86_64 */
        {I_RCL, 2, {RM_GPR|BITS64,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1701, 56},
    /*  24 : RCL reg8?,rm8,unity [vm-:      evex.nd1.nf.l0.m4.o8 d0 /2        ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d0) 212 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 3, {REG_GPR|BITS8,RM_GPR|BITS8,UNITY|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+23868, 35},
    /*  25 : RCL rm8,unity [m-:      evex.nd0.nf.l0.m4.o8 d0 /2        ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(d0) 202 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {RM_GPR|BITS8,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+23877, 62},
    /*  26 : RCL reg8?,unity [v+m-:      evex.nd1.nf.l0.m4.o8 d0 /2        ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d0) 202 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {REG_GPR|BITS8,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+23886, 63},
    /*  27 : RCL reg16?,rm16,unity [vm-:      evex.nd1.nf.l0.m4.o16 d1 /2       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d1) 212 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 3, {REG_GPR|BITS16,RM_GPR|BITS16,UNITY|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+11083, 38},
    /*  28 : RCL rm16,unity [m-:      evex.nd0.nf.l0.m4.o16 d1 /2       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(d1) 202 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {RM_GPR|BITS16,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11093, 64},
    /*  29 : RCL reg16?,unity [v+m-:      evex.nd1.nf.l0.m4.o16 d1 /2       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d1) 202 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {REG_GPR|BITS16,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11103, 65},
    /*  30 : RCL reg32?,rm32,unity [vm-:      evex.nd1.nf.l0.m4.o32 d1 /2       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d1) 212 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,UNITY|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+11113, 41},
    /*  31 : RCL rm32,unity [m-:      evex.nd0.nf.l0.m4.o32 d1 /2       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(d1) 202 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {RM_GPR|BITS32,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11123, 66},
    /*  32 : RCL reg32?,unity [v+m-:      evex.nd1.nf.l0.m4.o32 d1 /2       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d1) 202 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {REG_GPR|BITS32,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11133, 67},
    /*  33 : RCL reg64?,rm64,unity [vm-:      evex.nd1.nf.l0.m4.o64 d1 /2       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d1) 212 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 3, {REG_GPR|BITS64,RM_GPR|BITS64,UNITY|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+11143, 41},
    /*  34 : RCL rm64,unity [m-:      evex.nd0.nf.l0.m4.o64 d1 /2       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(d1) 202 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {RM_GPR|BITS64,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11153, 66},
    /*  35 : RCL reg64?,unity [v+m-:      evex.nd1.nf.l0.m4.o64 d1 /2       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d1) 202 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {REG_GPR|BITS64,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11163, 67},
    /*  36 : RCL reg8?,rm8,reg_cl [vm-:      evex.nd1.nf.l0.m4.o8 d2 /2        ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 212 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 3, {REG_GPR|BITS8,RM_GPR|BITS8,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+23895, 35},
    /*  37 : RCL rm8,reg_cl [m-:      evex.nd0.nf.l0.m4.o8 d2 /2        ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(d2) 202 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {RM_GPR|BITS8,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+23904, 62},
    /*  38 : RCL reg8?,reg_cl [v+m-:      evex.nd1.nf.l0.m4.o8 d2 /2        ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 202 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {REG_GPR|BITS8,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+23913, 63},
    /*  39 : RCL reg16?,rm16,reg_cl [vm-:      evex.nd1.nf.l0.m4.o16 d3 /2       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 212 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 3, {REG_GPR|BITS16,RM_GPR|BITS16,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+11173, 38},
    /*  40 : RCL rm16,reg_cl [m-:      evex.nd0.nf.l0.m4.o16 d3 /2       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(d3) 202 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {RM_GPR|BITS16,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11183, 64},
    /*  41 : RCL reg16?,reg_cl [v+m-:      evex.nd1.nf.l0.m4.o16 d3 /2       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 202 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {REG_GPR|BITS16,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11193, 65},
    /*  42 : RCL reg32?,rm32,reg_cl [vm-:      evex.nd1.nf.l0.m4.o32 d3 /2       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 212 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+11203, 41},
    /*  43 : RCL rm32,reg_cl [m-:      evex.nd0.nf.l0.m4.o32 d3 /2       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(d3) 202 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {RM_GPR|BITS32,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11213, 66},
    /*  44 : RCL reg32?,reg_cl [v+m-:      evex.nd1.nf.l0.m4.o32 d3 /2       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 202 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {REG_GPR|BITS32,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11223, 67},
    /*  45 : RCL reg64?,rm64,reg_cl [vm-:      evex.nd1.nf.l0.m4.o64 d3 /2       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 212 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+11233, 41},
    /*  46 : RCL rm64,reg_cl [m-:      evex.nd0.nf.l0.m4.o64 d3 /2       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(d3) 202 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {RM_GPR|BITS64,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11243, 66},
    /*  47 : RCL reg64?,reg_cl [v+m-:      evex.nd1.nf.l0.m4.o64 d3 /2       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 202 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {REG_GPR|BITS64,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11253, 67},
    /*  48 : RCL reg8?,rm8,reg_cx [vm-:      evex.nd1.nf.l0.m4.o8 d2 /2        ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 212 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 3, {REG_GPR|BITS8,RM_GPR|BITS8,REG_CX,0,0}, NO_DECORATOR, nasm_bytecodes+23895, 35},
    /*  49 : RCL rm8,reg_cx [m-:      evex.nd0.nf.l0.m4.o8 d2 /2        ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(d2) 202 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {RM_GPR|BITS8,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+23904, 62},
    /*  50 : RCL reg8?,reg_cx [v+m-:      evex.nd1.nf.l0.m4.o8 d2 /2        ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 202 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {REG_GPR|BITS8,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+23913, 63},
    /*  51 : RCL reg16?,rm16,reg_cx [vm-:      evex.nd1.nf.l0.m4.o16 d3 /2       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 212 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 3, {REG_GPR|BITS16,RM_GPR|BITS16,REG_CX,0,0}, NO_DECORATOR, nasm_bytecodes+11173, 38},
    /*  52 : RCL rm16,reg_cx [m-:      evex.nd0.nf.l0.m4.o16 d3 /2       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(d3) 202 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {RM_GPR|BITS16,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11183, 64},
    /*  53 : RCL reg16?,reg_cx [v+m-:      evex.nd1.nf.l0.m4.o16 d3 /2       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 202 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {REG_GPR|BITS16,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11193, 65},
    /*  54 : RCL reg32?,rm32,reg_cx [vm-:      evex.nd1.nf.l0.m4.o32 d3 /2       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 212 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_CX,0,0}, NO_DECORATOR, nasm_bytecodes+11203, 41},
    /*  55 : RCL rm32,reg_cx [m-:      evex.nd0.nf.l0.m4.o32 d3 /2       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(d3) 202 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {RM_GPR|BITS32,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11213, 66},
    /*  56 : RCL reg32?,reg_cx [v+m-:      evex.nd1.nf.l0.m4.o32 d3 /2       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 202 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {REG_GPR|BITS32,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11223, 67},
    /*  57 : RCL reg64?,rm64,reg_cx [vm-:      evex.nd1.nf.l0.m4.o64 d3 /2       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 212 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_CX,0,0}, NO_DECORATOR, nasm_bytecodes+11233, 41},
    /*  58 : RCL rm64,reg_cx [m-:      evex.nd0.nf.l0.m4.o64 d3 /2       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(d3) 202 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {RM_GPR|BITS64,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11243, 66},
    /*  59 : RCL reg64?,reg_cx [v+m-:      evex.nd1.nf.l0.m4.o64 d3 /2       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 202 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {REG_GPR|BITS64,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11253, 67},
    /*  60 : RCL reg8?,rm8,reg_ecx [vm-:      evex.nd1.nf.l0.m4.o8 d2 /2        ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 212 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 3, {REG_GPR|BITS8,RM_GPR|BITS8,REG_ECX,0,0}, NO_DECORATOR, nasm_bytecodes+23895, 35},
    /*  61 : RCL rm8,reg_ecx [m-:      evex.nd0.nf.l0.m4.o8 d2 /2        ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(d2) 202 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {RM_GPR|BITS8,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+23904, 62},
    /*  62 : RCL reg8?,reg_ecx [v+m-:      evex.nd1.nf.l0.m4.o8 d2 /2        ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 202 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {REG_GPR|BITS8,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+23913, 63},
    /*  63 : RCL reg16?,rm16,reg_ecx [vm-:      evex.nd1.nf.l0.m4.o16 d3 /2       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 212 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 3, {REG_GPR|BITS16,RM_GPR|BITS16,REG_ECX,0,0}, NO_DECORATOR, nasm_bytecodes+11173, 38},
    /*  64 : RCL rm16,reg_ecx [m-:      evex.nd0.nf.l0.m4.o16 d3 /2       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(d3) 202 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {RM_GPR|BITS16,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11183, 64},
    /*  65 : RCL reg16?,reg_ecx [v+m-:      evex.nd1.nf.l0.m4.o16 d3 /2       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 202 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {REG_GPR|BITS16,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11193, 65},
    /*  66 : RCL reg32?,rm32,reg_ecx [vm-:      evex.nd1.nf.l0.m4.o32 d3 /2       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 212 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_ECX,0,0}, NO_DECORATOR, nasm_bytecodes+11203, 41},
    /*  67 : RCL rm32,reg_ecx [m-:      evex.nd0.nf.l0.m4.o32 d3 /2       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(d3) 202 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {RM_GPR|BITS32,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11213, 66},
    /*  68 : RCL reg32?,reg_ecx [v+m-:      evex.nd1.nf.l0.m4.o32 d3 /2       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 202 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {REG_GPR|BITS32,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11223, 67},
    /*  69 : RCL reg64?,rm64,reg_ecx [vm-:      evex.nd1.nf.l0.m4.o64 d3 /2       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 212 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_ECX,0,0}, NO_DECORATOR, nasm_bytecodes+11233, 41},
    /*  70 : RCL rm64,reg_ecx [m-:      evex.nd0.nf.l0.m4.o64 d3 /2       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(d3) 202 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {RM_GPR|BITS64,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11243, 66},
    /*  71 : RCL reg64?,reg_ecx [v+m-:      evex.nd1.nf.l0.m4.o64 d3 /2       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 202 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {REG_GPR|BITS64,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11253, 67},
    /*  72 : RCL reg8?,rm8,reg_rcx [vm-:      evex.nd1.nf.l0.m4.o8 d2 /2        ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 212 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 3, {REG_GPR|BITS8,RM_GPR|BITS8,REG_RCX,0,0}, NO_DECORATOR, nasm_bytecodes+23895, 35},
    /*  73 : RCL rm8,reg_rcx [m-:      evex.nd0.nf.l0.m4.o8 d2 /2        ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(d2) 202 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {RM_GPR|BITS8,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+23904, 62},
    /*  74 : RCL reg8?,reg_rcx [v+m-:      evex.nd1.nf.l0.m4.o8 d2 /2        ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 202 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {REG_GPR|BITS8,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+23913, 63},
    /*  75 : RCL reg16?,rm16,reg_rcx [vm-:      evex.nd1.nf.l0.m4.o16 d3 /2       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 212 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 3, {REG_GPR|BITS16,RM_GPR|BITS16,REG_RCX,0,0}, NO_DECORATOR, nasm_bytecodes+11173, 38},
    /*  76 : RCL rm16,reg_rcx [m-:      evex.nd0.nf.l0.m4.o16 d3 /2       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(d3) 202 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {RM_GPR|BITS16,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11183, 64},
    /*  77 : RCL reg16?,reg_rcx [v+m-:      evex.nd1.nf.l0.m4.o16 d3 /2       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 202 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {REG_GPR|BITS16,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11193, 65},
    /*  78 : RCL reg32?,rm32,reg_rcx [vm-:      evex.nd1.nf.l0.m4.o32 d3 /2       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 212 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_RCX,0,0}, NO_DECORATOR, nasm_bytecodes+11203, 41},
    /*  79 : RCL rm32,reg_rcx [m-:      evex.nd0.nf.l0.m4.o32 d3 /2       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(d3) 202 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {RM_GPR|BITS32,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11213, 66},
    /*  80 : RCL reg32?,reg_rcx [v+m-:      evex.nd1.nf.l0.m4.o32 d3 /2       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 202 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {REG_GPR|BITS32,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11223, 67},
    /*  81 : RCL reg64?,rm64,reg_rcx [vm-:      evex.nd1.nf.l0.m4.o64 d3 /2       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 212 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_RCX,0,0}, NO_DECORATOR, nasm_bytecodes+11233, 41},
    /*  82 : RCL rm64,reg_rcx [m-:      evex.nd0.nf.l0.m4.o64 d3 /2       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(d3) 202 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {RM_GPR|BITS64,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11243, 66},
    /*  83 : RCL reg64?,reg_rcx [v+m-:      evex.nd1.nf.l0.m4.o64 d3 /2       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 202 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {REG_GPR|BITS64,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11253, 67},
    /*  84 : RCL reg8?,rm8,imm8 [vmi:      evex.nd1.nf.l0.m4.o8 c0 /2 ib,u   ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(c0) 212 026 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 3, {REG_GPR|BITS8,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+11263, 35},
    /*  85 : RCL rm8,imm8 [mi:      evex.nd0.nf.l0.m4.o8 c0 /2 ib,u   ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(c0) 202 025 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+11273, 62},
    /*  86 : RCL reg8?,imm8 [v+mi:      evex.nd1.nf.l0.m4.o8 c0 /2 ib,u   ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(c0) 202 025 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {REG_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+11283, 63},
    /*  87 : RCL reg16?,rm16,imm8 [vmi:      evex.nd1.nf.l0.m4.o16 c1 /2 ib,u  ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(c1) 212 026 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 3, {REG_GPR|BITS16,RM_GPR|BITS16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+1608, 38},
    /*  88 : RCL rm16,imm8 [mi:      evex.nd0.nf.l0.m4.o16 c1 /2 ib,u  ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(c1) 202 025 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {RM_GPR|BITS16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1619, 64},
    /*  89 : RCL reg16?,imm8 [v+mi:      evex.nd1.nf.l0.m4.o16 c1 /2 ib,u  ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(c1) 202 025 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {REG_GPR|BITS16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1630, 65},
    /*  90 : RCL reg32?,rm32,imm8 [vmi:      evex.nd1.nf.l0.m4.o32 c1 /2 ib,u  ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(c1) 212 026 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+1641, 41},
    /*  91 : RCL rm32,imm8 [mi:      evex.nd0.nf.l0.m4.o32 c1 /2 ib,u  ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(c1) 202 025 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {RM_GPR|BITS32,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1652, 66},
    /*  92 : RCL reg32?,imm8 [v+mi:      evex.nd1.nf.l0.m4.o32 c1 /2 ib,u  ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(c1) 202 025 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {REG_GPR|BITS32,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1663, 67},
    /*  93 : RCL reg64?,rm64,imm8 [vmi:      evex.nd1.nf.l0.m4.o64 c1 /2 ib,u  ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(c1) 212 026 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 3, {REG_GPR|BITS64,RM_GPR|BITS64,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+1674, 41},
    /*  94 : RCL rm64,imm8 [mi:      evex.nd0.nf.l0.m4.o64 c1 /2 ib,u  ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(c1) 202 025 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {RM_GPR|BITS64,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1685, 66},
    /*  95 : RCL reg64?,imm8 [v+mi:      evex.nd1.nf.l0.m4.o64 c1 /2 ib,u  ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(c1) 202 025 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCL, 2, {REG_GPR|BITS64,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1696, 67},
};

static const struct itemplate instrux_RCR[96] = {
    /*   0 : RCR rm8,unity [m-:       o8 d0 /3                          ] FL,8086 */
        /* 001(d0) 203 : FL,8086 */
        {I_RCR, 2, {RM_GPR|BITS8,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+23945, 54},
    /*   1 : RCR rm16,unity [m-:       o16 d1 /3                         ] FL,8086 */
        /* 320 001(d1) 203 : FL,8086 */
        {I_RCR, 2, {RM_GPR|BITS16,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11318, 54},
    /*   2 : RCR rm32,unity [m-:       o32 d1 /3                         ] FL,386 */
        /* 321 001(d1) 203 : FL,386 */
        {I_RCR, 2, {RM_GPR|BITS32,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11348, 55},
    /*   3 : RCR rm64,unity [m-:       o64 d1 /3                         ] LONG,FL,PROT,X86_64 */
        /* 324 001(d1) 203 : LONG,FL,PROT,X86_64 */
        {I_RCR, 2, {RM_GPR|BITS64,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11378, 56},
    /*   4 : RCR rm8,reg_cl [m-:       o8 d2 /3                          ] FL,8086 */
        /* 001(d2) 203 : FL,8086 */
        {I_RCR, 2, {RM_GPR|BITS8,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+23972, 54},
    /*   5 : RCR rm16,reg_cl [m-:       o16 d3 /3                         ] FL,8086 */
        /* 320 001(d3) 203 : FL,8086 */
        {I_RCR, 2, {RM_GPR|BITS16,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11408, 54},
    /*   6 : RCR rm32,reg_cl [m-:       o32 d3 /3                         ] FL,386 */
        /* 321 001(d3) 203 : FL,386 */
        {I_RCR, 2, {RM_GPR|BITS32,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11438, 55},
    /*   7 : RCR rm64,reg_cl [m-:       o64 d3 /3                         ] LONG,FL,PROT,X86_64 */
        /* 324 001(d3) 203 : LONG,FL,PROT,X86_64 */
        {I_RCR, 2, {RM_GPR|BITS64,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11468, 56},
    /*   8 : RCR rm8,reg_cx [m-:       o8 d2 /3                          ] ND,FL,8086 */
        /* 001(d2) 203 : FL,8086 */
        {I_RCR, 2, {RM_GPR|BITS8,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+23972, 54},
    /*   9 : RCR rm16,reg_cx [m-:       o16 d3 /3                         ] ND,FL,8086 */
        /* 320 001(d3) 203 : FL,8086 */
        {I_RCR, 2, {RM_GPR|BITS16,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11408, 54},
    /*  10 : RCR rm32,reg_cx [m-:       o32 d3 /3                         ] ND,FL,386 */
        /* 321 001(d3) 203 : FL,386 */
        {I_RCR, 2, {RM_GPR|BITS32,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11438, 55},
    /*  11 : RCR rm64,reg_cx [m-:       o64 d3 /3                         ] ND,LONG,FL,PROT,X86_64 */
        /* 324 001(d3) 203 : LONG,FL,PROT,X86_64 */
        {I_RCR, 2, {RM_GPR|BITS64,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11468, 56},
    /*  12 : RCR rm8,reg_ecx [m-:       o8 d2 /3                          ] ND,FL,8086 */
        /* 001(d2) 203 : FL,8086 */
        {I_RCR, 2, {RM_GPR|BITS8,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+23972, 54},
    /*  13 : RCR rm16,reg_ecx [m-:       o16 d3 /3                         ] ND,FL,8086 */
        /* 320 001(d3) 203 : FL,8086 */
        {I_RCR, 2, {RM_GPR|BITS16,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11408, 54},
    /*  14 : RCR rm32,reg_ecx [m-:       o32 d3 /3                         ] ND,FL,386 */
        /* 321 001(d3) 203 : FL,386 */
        {I_RCR, 2, {RM_GPR|BITS32,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11438, 55},
    /*  15 : RCR rm64,reg_ecx [m-:       o64 d3 /3                         ] ND,LONG,FL,PROT,X86_64 */
        /* 324 001(d3) 203 : LONG,FL,PROT,X86_64 */
        {I_RCR, 2, {RM_GPR|BITS64,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11468, 56},
    /*  16 : RCR rm8,reg_rcx [m-:       o8 d2 /3                          ] ND,FL,8086 */
        /* 001(d2) 203 : FL,8086 */
        {I_RCR, 2, {RM_GPR|BITS8,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+23972, 54},
    /*  17 : RCR rm16,reg_rcx [m-:       o16 d3 /3                         ] ND,FL,8086 */
        /* 320 001(d3) 203 : FL,8086 */
        {I_RCR, 2, {RM_GPR|BITS16,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11408, 54},
    /*  18 : RCR rm32,reg_rcx [m-:       o32 d3 /3                         ] ND,FL,386 */
        /* 321 001(d3) 203 : FL,386 */
        {I_RCR, 2, {RM_GPR|BITS32,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11438, 55},
    /*  19 : RCR rm64,reg_rcx [m-:       o64 d3 /3                         ] ND,LONG,FL,PROT,X86_64 */
        /* 324 001(d3) 203 : LONG,FL,PROT,X86_64 */
        {I_RCR, 2, {RM_GPR|BITS64,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11468, 56},
    /*  20 : RCR rm8,imm8 [mi:       o8 c0 /3 ib,u                     ] FL,186 */
        /* 001(c0) 203 025 : FL,186 */
        {I_RCR, 2, {RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+11498, 57},
    /*  21 : RCR rm16,imm8 [mi:       o16 c1 /3 ib,u                    ] FL,186 */
        /* 320 001(c1) 203 025 : FL,186 */
        {I_RCR, 2, {RM_GPR|BITS16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1734, 57},
    /*  22 : RCR rm32,imm8 [mi:       o32 c1 /3 ib,u                    ] FL,386 */
        /* 321 001(c1) 203 025 : FL,386 */
        {I_RCR, 2, {RM_GPR|BITS32,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1767, 55},
    /*  23 : RCR rm64,imm8 [mi:       o64 c1 /3 ib,u                    ] LONG,FL,PROT,X86_64 */
        /* 324 001(c1) 203 025 : LONG,FL,PROT,X86_64 */
        {I_RCR, 2, {RM_GPR|BITS64,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1800, 56},
    /*  24 : RCR reg8?,rm8,unity [vm-:      evex.nd1.nf.l0.m4.o8 d0 /3        ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d0) 213 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 3, {REG_GPR|BITS8,RM_GPR|BITS8,UNITY|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+23922, 35},
    /*  25 : RCR rm8,unity [m-:      evex.nd0.nf.l0.m4.o8 d0 /3        ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(d0) 203 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {RM_GPR|BITS8,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+23931, 62},
    /*  26 : RCR reg8?,unity [v+m-:      evex.nd1.nf.l0.m4.o8 d0 /3        ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d0) 203 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {REG_GPR|BITS8,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+23940, 63},
    /*  27 : RCR reg16?,rm16,unity [vm-:      evex.nd1.nf.l0.m4.o16 d1 /3       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d1) 213 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 3, {REG_GPR|BITS16,RM_GPR|BITS16,UNITY|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+11293, 38},
    /*  28 : RCR rm16,unity [m-:      evex.nd0.nf.l0.m4.o16 d1 /3       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(d1) 203 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {RM_GPR|BITS16,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11303, 64},
    /*  29 : RCR reg16?,unity [v+m-:      evex.nd1.nf.l0.m4.o16 d1 /3       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d1) 203 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {REG_GPR|BITS16,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11313, 65},
    /*  30 : RCR reg32?,rm32,unity [vm-:      evex.nd1.nf.l0.m4.o32 d1 /3       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d1) 213 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,UNITY|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+11323, 41},
    /*  31 : RCR rm32,unity [m-:      evex.nd0.nf.l0.m4.o32 d1 /3       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(d1) 203 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {RM_GPR|BITS32,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11333, 66},
    /*  32 : RCR reg32?,unity [v+m-:      evex.nd1.nf.l0.m4.o32 d1 /3       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d1) 203 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {REG_GPR|BITS32,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11343, 67},
    /*  33 : RCR reg64?,rm64,unity [vm-:      evex.nd1.nf.l0.m4.o64 d1 /3       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d1) 213 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,UNITY|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+11353, 41},
    /*  34 : RCR rm64,unity [m-:      evex.nd0.nf.l0.m4.o64 d1 /3       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(d1) 203 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {RM_GPR|BITS64,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11363, 66},
    /*  35 : RCR reg64?,unity [v+m-:      evex.nd1.nf.l0.m4.o64 d1 /3       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d1) 203 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {REG_GPR|BITS64,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11373, 67},
    /*  36 : RCR reg8?,rm8,reg_cl [vm-:      evex.nd1.nf.l0.m4.o8 d2 /3        ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 213 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 3, {REG_GPR|BITS8,RM_GPR|BITS8,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+23949, 35},
    /*  37 : RCR rm8,reg_cl [m-:      evex.nd0.nf.l0.m4.o8 d2 /3        ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(d2) 203 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {RM_GPR|BITS8,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+23958, 62},
    /*  38 : RCR reg8?,reg_cl [v+m-:      evex.nd1.nf.l0.m4.o8 d2 /3        ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 203 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {REG_GPR|BITS8,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+23967, 63},
    /*  39 : RCR reg16?,rm16,reg_cl [vm-:      evex.nd1.nf.l0.m4.o16 d3 /3       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 213 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 3, {REG_GPR|BITS16,RM_GPR|BITS16,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+11383, 38},
    /*  40 : RCR rm16,reg_cl [m-:      evex.nd0.nf.l0.m4.o16 d3 /3       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(d3) 203 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {RM_GPR|BITS16,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11393, 64},
    /*  41 : RCR reg16?,reg_cl [v+m-:      evex.nd1.nf.l0.m4.o16 d3 /3       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 203 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {REG_GPR|BITS16,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11403, 65},
    /*  42 : RCR reg32?,rm32,reg_cl [vm-:      evex.nd1.nf.l0.m4.o32 d3 /3       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 213 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+11413, 41},
    /*  43 : RCR rm32,reg_cl [m-:      evex.nd0.nf.l0.m4.o32 d3 /3       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(d3) 203 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {RM_GPR|BITS32,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11423, 66},
    /*  44 : RCR reg32?,reg_cl [v+m-:      evex.nd1.nf.l0.m4.o32 d3 /3       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 203 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {REG_GPR|BITS32,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11433, 67},
    /*  45 : RCR reg64?,rm64,reg_cl [vm-:      evex.nd1.nf.l0.m4.o64 d3 /3       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 213 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+11443, 41},
    /*  46 : RCR rm64,reg_cl [m-:      evex.nd0.nf.l0.m4.o64 d3 /3       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(d3) 203 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {RM_GPR|BITS64,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11453, 66},
    /*  47 : RCR reg64?,reg_cl [v+m-:      evex.nd1.nf.l0.m4.o64 d3 /3       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 203 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {REG_GPR|BITS64,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11463, 67},
    /*  48 : RCR reg8?,rm8,reg_cx [vm-:      evex.nd1.nf.l0.m4.o8 d2 /3        ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 213 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 3, {REG_GPR|BITS8,RM_GPR|BITS8,REG_CX,0,0}, NO_DECORATOR, nasm_bytecodes+23949, 35},
    /*  49 : RCR rm8,reg_cx [m-:      evex.nd0.nf.l0.m4.o8 d2 /3        ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(d2) 203 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {RM_GPR|BITS8,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+23958, 62},
    /*  50 : RCR reg8?,reg_cx [v+m-:      evex.nd1.nf.l0.m4.o8 d2 /3        ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 203 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {REG_GPR|BITS8,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+23967, 63},
    /*  51 : RCR reg16?,rm16,reg_cx [vm-:      evex.nd1.nf.l0.m4.o16 d3 /3       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 213 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 3, {REG_GPR|BITS16,RM_GPR|BITS16,REG_CX,0,0}, NO_DECORATOR, nasm_bytecodes+11383, 38},
    /*  52 : RCR rm16,reg_cx [m-:      evex.nd0.nf.l0.m4.o16 d3 /3       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(d3) 203 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {RM_GPR|BITS16,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11393, 64},
    /*  53 : RCR reg16?,reg_cx [v+m-:      evex.nd1.nf.l0.m4.o16 d3 /3       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 203 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {REG_GPR|BITS16,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11403, 65},
    /*  54 : RCR reg32?,rm32,reg_cx [vm-:      evex.nd1.nf.l0.m4.o32 d3 /3       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 213 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_CX,0,0}, NO_DECORATOR, nasm_bytecodes+11413, 41},
    /*  55 : RCR rm32,reg_cx [m-:      evex.nd0.nf.l0.m4.o32 d3 /3       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(d3) 203 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {RM_GPR|BITS32,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11423, 66},
    /*  56 : RCR reg32?,reg_cx [v+m-:      evex.nd1.nf.l0.m4.o32 d3 /3       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 203 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {REG_GPR|BITS32,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11433, 67},
    /*  57 : RCR reg64?,rm64,reg_cx [vm-:      evex.nd1.nf.l0.m4.o64 d3 /3       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 213 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_CX,0,0}, NO_DECORATOR, nasm_bytecodes+11443, 41},
    /*  58 : RCR rm64,reg_cx [m-:      evex.nd0.nf.l0.m4.o64 d3 /3       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(d3) 203 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {RM_GPR|BITS64,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11453, 66},
    /*  59 : RCR reg64?,reg_cx [v+m-:      evex.nd1.nf.l0.m4.o64 d3 /3       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 203 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {REG_GPR|BITS64,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11463, 67},
    /*  60 : RCR reg8?,rm8,reg_ecx [vm-:      evex.nd1.nf.l0.m4.o8 d2 /3        ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 213 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 3, {REG_GPR|BITS8,RM_GPR|BITS8,REG_ECX,0,0}, NO_DECORATOR, nasm_bytecodes+23949, 35},
    /*  61 : RCR rm8,reg_ecx [m-:      evex.nd0.nf.l0.m4.o8 d2 /3        ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(d2) 203 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {RM_GPR|BITS8,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+23958, 62},
    /*  62 : RCR reg8?,reg_ecx [v+m-:      evex.nd1.nf.l0.m4.o8 d2 /3        ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 203 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {REG_GPR|BITS8,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+23967, 63},
    /*  63 : RCR reg16?,rm16,reg_ecx [vm-:      evex.nd1.nf.l0.m4.o16 d3 /3       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 213 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 3, {REG_GPR|BITS16,RM_GPR|BITS16,REG_ECX,0,0}, NO_DECORATOR, nasm_bytecodes+11383, 38},
    /*  64 : RCR rm16,reg_ecx [m-:      evex.nd0.nf.l0.m4.o16 d3 /3       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(d3) 203 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {RM_GPR|BITS16,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11393, 64},
    /*  65 : RCR reg16?,reg_ecx [v+m-:      evex.nd1.nf.l0.m4.o16 d3 /3       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 203 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {REG_GPR|BITS16,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11403, 65},
    /*  66 : RCR reg32?,rm32,reg_ecx [vm-:      evex.nd1.nf.l0.m4.o32 d3 /3       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 213 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_ECX,0,0}, NO_DECORATOR, nasm_bytecodes+11413, 41},
    /*  67 : RCR rm32,reg_ecx [m-:      evex.nd0.nf.l0.m4.o32 d3 /3       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(d3) 203 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {RM_GPR|BITS32,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11423, 66},
    /*  68 : RCR reg32?,reg_ecx [v+m-:      evex.nd1.nf.l0.m4.o32 d3 /3       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 203 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {REG_GPR|BITS32,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11433, 67},
    /*  69 : RCR reg64?,rm64,reg_ecx [vm-:      evex.nd1.nf.l0.m4.o64 d3 /3       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 213 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_ECX,0,0}, NO_DECORATOR, nasm_bytecodes+11443, 41},
    /*  70 : RCR rm64,reg_ecx [m-:      evex.nd0.nf.l0.m4.o64 d3 /3       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(d3) 203 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {RM_GPR|BITS64,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11453, 66},
    /*  71 : RCR reg64?,reg_ecx [v+m-:      evex.nd1.nf.l0.m4.o64 d3 /3       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 203 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {REG_GPR|BITS64,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11463, 67},
    /*  72 : RCR reg8?,rm8,reg_rcx [vm-:      evex.nd1.nf.l0.m4.o8 d2 /3        ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 213 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 3, {REG_GPR|BITS8,RM_GPR|BITS8,REG_RCX,0,0}, NO_DECORATOR, nasm_bytecodes+23949, 35},
    /*  73 : RCR rm8,reg_rcx [m-:      evex.nd0.nf.l0.m4.o8 d2 /3        ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(d2) 203 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {RM_GPR|BITS8,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+23958, 62},
    /*  74 : RCR reg8?,reg_rcx [v+m-:      evex.nd1.nf.l0.m4.o8 d2 /3        ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 203 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {REG_GPR|BITS8,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+23967, 63},
    /*  75 : RCR reg16?,rm16,reg_rcx [vm-:      evex.nd1.nf.l0.m4.o16 d3 /3       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 213 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 3, {REG_GPR|BITS16,RM_GPR|BITS16,REG_RCX,0,0}, NO_DECORATOR, nasm_bytecodes+11383, 38},
    /*  76 : RCR rm16,reg_rcx [m-:      evex.nd0.nf.l0.m4.o16 d3 /3       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(d3) 203 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {RM_GPR|BITS16,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11393, 64},
    /*  77 : RCR reg16?,reg_rcx [v+m-:      evex.nd1.nf.l0.m4.o16 d3 /3       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 203 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {REG_GPR|BITS16,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11403, 65},
    /*  78 : RCR reg32?,rm32,reg_rcx [vm-:      evex.nd1.nf.l0.m4.o32 d3 /3       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 213 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_RCX,0,0}, NO_DECORATOR, nasm_bytecodes+11413, 41},
    /*  79 : RCR rm32,reg_rcx [m-:      evex.nd0.nf.l0.m4.o32 d3 /3       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(d3) 203 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {RM_GPR|BITS32,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11423, 66},
    /*  80 : RCR reg32?,reg_rcx [v+m-:      evex.nd1.nf.l0.m4.o32 d3 /3       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 203 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {REG_GPR|BITS32,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11433, 67},
    /*  81 : RCR reg64?,rm64,reg_rcx [vm-:      evex.nd1.nf.l0.m4.o64 d3 /3       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 213 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_RCX,0,0}, NO_DECORATOR, nasm_bytecodes+11443, 41},
    /*  82 : RCR rm64,reg_rcx [m-:      evex.nd0.nf.l0.m4.o64 d3 /3       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(d3) 203 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {RM_GPR|BITS64,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11453, 66},
    /*  83 : RCR reg64?,reg_rcx [v+m-:      evex.nd1.nf.l0.m4.o64 d3 /3       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 203 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {REG_GPR|BITS64,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11463, 67},
    /*  84 : RCR reg8?,rm8,imm8 [vmi:      evex.nd1.nf.l0.m4.o8 c0 /3 ib,u   ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(c0) 213 026 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 3, {REG_GPR|BITS8,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+11473, 35},
    /*  85 : RCR rm8,imm8 [mi:      evex.nd0.nf.l0.m4.o8 c0 /3 ib,u   ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(c0) 203 025 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+11483, 62},
    /*  86 : RCR reg8?,imm8 [v+mi:      evex.nd1.nf.l0.m4.o8 c0 /3 ib,u   ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(c0) 203 025 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {REG_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+11493, 63},
    /*  87 : RCR reg16?,rm16,imm8 [vmi:      evex.nd1.nf.l0.m4.o16 c1 /3 ib,u  ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(c1) 213 026 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 3, {REG_GPR|BITS16,RM_GPR|BITS16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+1707, 38},
    /*  88 : RCR rm16,imm8 [mi:      evex.nd0.nf.l0.m4.o16 c1 /3 ib,u  ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(c1) 203 025 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {RM_GPR|BITS16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1718, 64},
    /*  89 : RCR reg16?,imm8 [v+mi:      evex.nd1.nf.l0.m4.o16 c1 /3 ib,u  ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(c1) 203 025 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {REG_GPR|BITS16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1729, 65},
    /*  90 : RCR reg32?,rm32,imm8 [vmi:      evex.nd1.nf.l0.m4.o32 c1 /3 ib,u  ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(c1) 213 026 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+1740, 41},
    /*  91 : RCR rm32,imm8 [mi:      evex.nd0.nf.l0.m4.o32 c1 /3 ib,u  ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(c1) 203 025 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {RM_GPR|BITS32,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1751, 66},
    /*  92 : RCR reg32?,imm8 [v+mi:      evex.nd1.nf.l0.m4.o32 c1 /3 ib,u  ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(c1) 203 025 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {REG_GPR|BITS32,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1762, 67},
    /*  93 : RCR reg64?,rm64,imm8 [vmi:      evex.nd1.nf.l0.m4.o64 c1 /3 ib,u  ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(c1) 213 026 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+1773, 41},
    /*  94 : RCR rm64,imm8 [mi:      evex.nd0.nf.l0.m4.o64 c1 /3 ib,u  ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(c1) 203 025 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {RM_GPR|BITS64,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1784, 66},
    /*  95 : RCR reg64?,imm8 [v+mi:      evex.nd1.nf.l0.m4.o64 c1 /3 ib,u  ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(c1) 203 025 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_RCR, 2, {REG_GPR|BITS64,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1795, 67},
};

static const struct itemplate instrux_SHL[136] = {
    /*   0 : SHL rm8,unity [m-:       o8 d0 /4                          ] FL,8086 */
        /* 001(d0) 204 : FL,8086 */
        {I_SHL, 2, {RM_GPR|BITS8,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+23999, 54},
    /*   1 : SHL rm16,unity [m-:       o16 d1 /4                         ] FL,8086 */
        /* 320 001(d1) 204 : FL,8086 */
        {I_SHL, 2, {RM_GPR|BITS16,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11528, 54},
    /*   2 : SHL rm32,unity [m-:       o32 d1 /4                         ] FL,386 */
        /* 321 001(d1) 204 : FL,386 */
        {I_SHL, 2, {RM_GPR|BITS32,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11558, 55},
    /*   3 : SHL rm64,unity [m-:       o64 d1 /4                         ] LONG,FL,PROT,X86_64 */
        /* 324 001(d1) 204 : LONG,FL,PROT,X86_64 */
        {I_SHL, 2, {RM_GPR|BITS64,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11588, 56},
    /*   4 : SHL rm8,reg_cl [m-:       o8 d2 /4                          ] FL,8086 */
        /* 001(d2) 204 : FL,8086 */
        {I_SHL, 2, {RM_GPR|BITS8,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+24026, 54},
    /*   5 : SHL rm16,reg_cl [m-:       o16 d3 /4                         ] FL,8086 */
        /* 320 001(d3) 204 : FL,8086 */
        {I_SHL, 2, {RM_GPR|BITS16,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11618, 54},
    /*   6 : SHL rm32,reg_cl [m-:       o32 d3 /4                         ] FL,386 */
        /* 321 001(d3) 204 : FL,386 */
        {I_SHL, 2, {RM_GPR|BITS32,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11648, 55},
    /*   7 : SHL rm64,reg_cl [m-:       o64 d3 /4                         ] LONG,FL,PROT,X86_64 */
        /* 324 001(d3) 204 : LONG,FL,PROT,X86_64 */
        {I_SHL, 2, {RM_GPR|BITS64,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11678, 56},
    /*   8 : SHL rm8,reg_cx [m-:       o8 d2 /4                          ] ND,FL,8086 */
        /* 001(d2) 204 : FL,8086 */
        {I_SHL, 2, {RM_GPR|BITS8,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+24026, 54},
    /*   9 : SHL rm16,reg_cx [m-:       o16 d3 /4                         ] ND,FL,8086 */
        /* 320 001(d3) 204 : FL,8086 */
        {I_SHL, 2, {RM_GPR|BITS16,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11618, 54},
    /*  10 : SHL rm32,reg_cx [m-:       o32 d3 /4                         ] ND,FL,386 */
        /* 321 001(d3) 204 : FL,386 */
        {I_SHL, 2, {RM_GPR|BITS32,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11648, 55},
    /*  11 : SHL rm64,reg_cx [m-:       o64 d3 /4                         ] ND,LONG,FL,PROT,X86_64 */
        /* 324 001(d3) 204 : LONG,FL,PROT,X86_64 */
        {I_SHL, 2, {RM_GPR|BITS64,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11678, 56},
    /*  12 : SHL rm8,reg_ecx [m-:       o8 d2 /4                          ] ND,FL,8086 */
        /* 001(d2) 204 : FL,8086 */
        {I_SHL, 2, {RM_GPR|BITS8,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+24026, 54},
    /*  13 : SHL rm16,reg_ecx [m-:       o16 d3 /4                         ] ND,FL,8086 */
        /* 320 001(d3) 204 : FL,8086 */
        {I_SHL, 2, {RM_GPR|BITS16,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11618, 54},
    /*  14 : SHL rm32,reg_ecx [m-:       o32 d3 /4                         ] ND,FL,386 */
        /* 321 001(d3) 204 : FL,386 */
        {I_SHL, 2, {RM_GPR|BITS32,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11648, 55},
    /*  15 : SHL rm64,reg_ecx [m-:       o64 d3 /4                         ] ND,LONG,FL,PROT,X86_64 */
        /* 324 001(d3) 204 : LONG,FL,PROT,X86_64 */
        {I_SHL, 2, {RM_GPR|BITS64,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11678, 56},
    /*  16 : SHL rm8,reg_rcx [m-:       o8 d2 /4                          ] ND,FL,8086 */
        /* 001(d2) 204 : FL,8086 */
        {I_SHL, 2, {RM_GPR|BITS8,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+24026, 54},
    /*  17 : SHL rm16,reg_rcx [m-:       o16 d3 /4                         ] ND,FL,8086 */
        /* 320 001(d3) 204 : FL,8086 */
        {I_SHL, 2, {RM_GPR|BITS16,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11618, 54},
    /*  18 : SHL rm32,reg_rcx [m-:       o32 d3 /4                         ] ND,FL,386 */
        /* 321 001(d3) 204 : FL,386 */
        {I_SHL, 2, {RM_GPR|BITS32,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11648, 55},
    /*  19 : SHL rm64,reg_rcx [m-:       o64 d3 /4                         ] ND,LONG,FL,PROT,X86_64 */
        /* 324 001(d3) 204 : LONG,FL,PROT,X86_64 */
        {I_SHL, 2, {RM_GPR|BITS64,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11678, 56},
    /*  20 : SHL rm8,imm8 [mi:       o8 c0 /4 ib,u                     ] FL,186 */
        /* 001(c0) 204 025 : FL,186 */
        {I_SHL, 2, {RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+11708, 57},
    /*  21 : SHL rm16,imm8 [mi:       o16 c1 /4 ib,u                    ] FL,186 */
        /* 320 001(c1) 204 025 : FL,186 */
        {I_SHL, 2, {RM_GPR|BITS16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1833, 57},
    /*  22 : SHL rm32,imm8 [mi:       o32 c1 /4 ib,u                    ] FL,386 */
        /* 321 001(c1) 204 025 : FL,386 */
        {I_SHL, 2, {RM_GPR|BITS32,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1866, 55},
    /*  23 : SHL rm64,imm8 [mi:       o64 c1 /4 ib,u                    ] LONG,FL,PROT,X86_64 */
        /* 324 001(c1) 204 025 : LONG,FL,PROT,X86_64 */
        {I_SHL, 2, {RM_GPR|BITS64,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1899, 56},
    /*  24 : SHL reg32,rm32*,reg8 [rmv:      vex.lz.66.0f38.w0 f7 /r           ] ND,SM0,SM1,OPT,NF,NF_R,BMI2,FUTURE */
        /* 262(002 001) 001(f7) 110 : SM0,SM1,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SHL, 3, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,REG_GPR|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55087, 60},
    /*  25 : SHL reg32,reg8 [r+mv:      vex.lz.66.0f38.w0 f7 /r           ] ND,SM0,OPT,NF,NF_R,BMI2,FUTURE */
        /* 261(002 001) 001(f7) 100 : SM0,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SHL, 2, {REG_GPR|BITS32|RN_L16,REG_GPR|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55094, 61},
    /*  26 : SHL reg32,rm32*,reg16 [rmv:      vex.lz.66.0f38.w0 f7 /r           ] ND,SM0,SM1,OPT,NF,NF_R,BMI2,FUTURE */
        /* 262(002 001) 001(f7) 110 : SM0,SM1,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SHL, 3, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,REG_GPR|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55087, 60},
    /*  27 : SHL reg32,reg16 [r+mv:      vex.lz.66.0f38.w0 f7 /r           ] ND,SM0,OPT,NF,NF_R,BMI2,FUTURE */
        /* 261(002 001) 001(f7) 100 : SM0,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SHL, 2, {REG_GPR|BITS32|RN_L16,REG_GPR|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55094, 61},
    /*  28 : SHL reg32,rm32*,reg32 [rmv:      vex.lz.66.0f38.w0 f7 /r           ] ND,SM0,SM1,OPT,NF,NF_R,BMI2,FUTURE */
        /* 262(002 001) 001(f7) 110 : SM0,SM1,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SHL, 3, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55087, 60},
    /*  29 : SHL reg32,reg32 [r+mv:      vex.lz.66.0f38.w0 f7 /r           ] ND,SM0,OPT,NF,NF_R,BMI2,FUTURE */
        /* 261(002 001) 001(f7) 100 : SM0,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SHL, 2, {REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55094, 61},
    /*  30 : SHL reg32,rm32*,reg64 [rmv:      vex.lz.66.0f38.w0 f7 /r           ] ND,SM0,SM1,OPT,NF,NF_R,BMI2,FUTURE */
        /* 262(002 001) 001(f7) 110 : SM0,SM1,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SHL, 3, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55087, 60},
    /*  31 : SHL reg32,reg64 [r+mv:      vex.lz.66.0f38.w0 f7 /r           ] ND,SM0,OPT,NF,NF_R,BMI2,FUTURE */
        /* 261(002 001) 001(f7) 100 : SM0,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SHL, 2, {REG_GPR|BITS32|RN_L16,REG_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55094, 61},
    /*  32 : SHL reg64,rm64*,reg8 [rmv:      vex.lz.66.0f38.w1 f7 /r           ] ND,SM0,SM1,OPT,NF,NF_R,BMI2,FUTURE */
        /* 262(002 201) 001(f7) 110 : SM0,SM1,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SHL, 3, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,REG_GPR|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55129, 60},
    /*  33 : SHL reg64,reg8 [r+mv:      vex.lz.66.0f38.w1 f7 /r           ] ND,SM0,OPT,NF,NF_R,BMI2,FUTURE */
        /* 261(002 201) 001(f7) 100 : SM0,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SHL, 2, {REG_GPR|BITS64|RN_L16,REG_GPR|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55136, 61},
    /*  34 : SHL reg64,rm64*,reg16 [rmv:      vex.lz.66.0f38.w1 f7 /r           ] ND,SM0,SM1,OPT,NF,NF_R,BMI2,FUTURE */
        /* 262(002 201) 001(f7) 110 : SM0,SM1,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SHL, 3, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,REG_GPR|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55129, 60},
    /*  35 : SHL reg64,reg16 [r+mv:      vex.lz.66.0f38.w1 f7 /r           ] ND,SM0,OPT,NF,NF_R,BMI2,FUTURE */
        /* 261(002 201) 001(f7) 100 : SM0,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SHL, 2, {REG_GPR|BITS64|RN_L16,REG_GPR|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55136, 61},
    /*  36 : SHL reg64,rm64*,reg32 [rmv:      vex.lz.66.0f38.w1 f7 /r           ] ND,SM0,SM1,OPT,NF,NF_R,BMI2,FUTURE */
        /* 262(002 201) 001(f7) 110 : SM0,SM1,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SHL, 3, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55129, 60},
    /*  37 : SHL reg64,reg32 [r+mv:      vex.lz.66.0f38.w1 f7 /r           ] ND,SM0,OPT,NF,NF_R,BMI2,FUTURE */
        /* 261(002 201) 001(f7) 100 : SM0,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SHL, 2, {REG_GPR|BITS64|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55136, 61},
    /*  38 : SHL reg64,rm64*,reg64 [rmv:      vex.lz.66.0f38.w1 f7 /r           ] ND,SM0,SM1,OPT,NF,NF_R,BMI2,FUTURE */
        /* 262(002 201) 001(f7) 110 : SM0,SM1,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SHL, 3, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55129, 60},
    /*  39 : SHL reg64,reg64 [r+mv:      vex.lz.66.0f38.w1 f7 /r           ] ND,SM0,OPT,NF,NF_R,BMI2,FUTURE */
        /* 261(002 201) 001(f7) 100 : SM0,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SHL, 2, {REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55136, 61},
    /*  40 : SHL reg8?,rm8,unity [vm-:      evex.nd1.nf.l0.m4.o8 d0 /4        ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d0) 214 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 3, {REG_GPR|BITS8,RM_GPR|BITS8,UNITY|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+23976, 35},
    /*  41 : SHL rm8,unity [m-:      evex.nd0.nf.l0.m4.o8 d0 /4        ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(d0) 204 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {RM_GPR|BITS8,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+23985, 62},
    /*  42 : SHL reg8?,unity [v+m-:      evex.nd1.nf.l0.m4.o8 d0 /4        ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d0) 204 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {REG_GPR|BITS8,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+23994, 63},
    /*  43 : SHL reg16?,rm16,unity [vm-:      evex.nd1.nf.l0.m4.o16 d1 /4       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d1) 214 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 3, {REG_GPR|BITS16,RM_GPR|BITS16,UNITY|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+11503, 38},
    /*  44 : SHL rm16,unity [m-:      evex.nd0.nf.l0.m4.o16 d1 /4       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(d1) 204 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {RM_GPR|BITS16,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11513, 64},
    /*  45 : SHL reg16?,unity [v+m-:      evex.nd1.nf.l0.m4.o16 d1 /4       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d1) 204 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {REG_GPR|BITS16,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11523, 65},
    /*  46 : SHL reg32?,rm32,unity [vm-:      evex.nd1.nf.l0.m4.o32 d1 /4       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d1) 214 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,UNITY|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+11533, 41},
    /*  47 : SHL rm32,unity [m-:      evex.nd0.nf.l0.m4.o32 d1 /4       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(d1) 204 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {RM_GPR|BITS32,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11543, 66},
    /*  48 : SHL reg32?,unity [v+m-:      evex.nd1.nf.l0.m4.o32 d1 /4       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d1) 204 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {REG_GPR|BITS32,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11553, 67},
    /*  49 : SHL reg64?,rm64,unity [vm-:      evex.nd1.nf.l0.m4.o64 d1 /4       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d1) 214 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 3, {REG_GPR|BITS64,RM_GPR|BITS64,UNITY|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+11563, 41},
    /*  50 : SHL rm64,unity [m-:      evex.nd0.nf.l0.m4.o64 d1 /4       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(d1) 204 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {RM_GPR|BITS64,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11573, 66},
    /*  51 : SHL reg64?,unity [v+m-:      evex.nd1.nf.l0.m4.o64 d1 /4       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d1) 204 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {REG_GPR|BITS64,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11583, 67},
    /*  52 : SHL reg8?,rm8,reg_cl [vm-:      evex.nd1.nf.l0.m4.o8 d2 /4        ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 214 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 3, {REG_GPR|BITS8,RM_GPR|BITS8,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+24003, 35},
    /*  53 : SHL rm8,reg_cl [m-:      evex.nd0.nf.l0.m4.o8 d2 /4        ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(d2) 204 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {RM_GPR|BITS8,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+24012, 62},
    /*  54 : SHL reg8?,reg_cl [v+m-:      evex.nd1.nf.l0.m4.o8 d2 /4        ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 204 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {REG_GPR|BITS8,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+24021, 63},
    /*  55 : SHL reg16?,rm16,reg_cl [vm-:      evex.nd1.nf.l0.m4.o16 d3 /4       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 214 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 3, {REG_GPR|BITS16,RM_GPR|BITS16,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+11593, 38},
    /*  56 : SHL rm16,reg_cl [m-:      evex.nd0.nf.l0.m4.o16 d3 /4       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(d3) 204 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {RM_GPR|BITS16,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11603, 64},
    /*  57 : SHL reg16?,reg_cl [v+m-:      evex.nd1.nf.l0.m4.o16 d3 /4       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 204 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {REG_GPR|BITS16,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11613, 65},
    /*  58 : SHL reg32?,rm32,reg_cl [vm-:      evex.nd1.nf.l0.m4.o32 d3 /4       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 214 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+11623, 41},
    /*  59 : SHL rm32,reg_cl [m-:      evex.nd0.nf.l0.m4.o32 d3 /4       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(d3) 204 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {RM_GPR|BITS32,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11633, 66},
    /*  60 : SHL reg32?,reg_cl [v+m-:      evex.nd1.nf.l0.m4.o32 d3 /4       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 204 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {REG_GPR|BITS32,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11643, 67},
    /*  61 : SHL reg64?,rm64,reg_cl [vm-:      evex.nd1.nf.l0.m4.o64 d3 /4       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 214 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+11653, 41},
    /*  62 : SHL rm64,reg_cl [m-:      evex.nd0.nf.l0.m4.o64 d3 /4       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(d3) 204 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {RM_GPR|BITS64,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11663, 66},
    /*  63 : SHL reg64?,reg_cl [v+m-:      evex.nd1.nf.l0.m4.o64 d3 /4       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 204 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {REG_GPR|BITS64,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11673, 67},
    /*  64 : SHL reg8?,rm8,reg_cx [vm-:      evex.nd1.nf.l0.m4.o8 d2 /4        ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 214 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 3, {REG_GPR|BITS8,RM_GPR|BITS8,REG_CX,0,0}, NO_DECORATOR, nasm_bytecodes+24003, 35},
    /*  65 : SHL rm8,reg_cx [m-:      evex.nd0.nf.l0.m4.o8 d2 /4        ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(d2) 204 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {RM_GPR|BITS8,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+24012, 62},
    /*  66 : SHL reg8?,reg_cx [v+m-:      evex.nd1.nf.l0.m4.o8 d2 /4        ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 204 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {REG_GPR|BITS8,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+24021, 63},
    /*  67 : SHL reg16?,rm16,reg_cx [vm-:      evex.nd1.nf.l0.m4.o16 d3 /4       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 214 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 3, {REG_GPR|BITS16,RM_GPR|BITS16,REG_CX,0,0}, NO_DECORATOR, nasm_bytecodes+11593, 38},
    /*  68 : SHL rm16,reg_cx [m-:      evex.nd0.nf.l0.m4.o16 d3 /4       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(d3) 204 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {RM_GPR|BITS16,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11603, 64},
    /*  69 : SHL reg16?,reg_cx [v+m-:      evex.nd1.nf.l0.m4.o16 d3 /4       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 204 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {REG_GPR|BITS16,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11613, 65},
    /*  70 : SHL reg32?,rm32,reg_cx [vm-:      evex.nd1.nf.l0.m4.o32 d3 /4       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 214 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_CX,0,0}, NO_DECORATOR, nasm_bytecodes+11623, 41},
    /*  71 : SHL rm32,reg_cx [m-:      evex.nd0.nf.l0.m4.o32 d3 /4       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(d3) 204 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {RM_GPR|BITS32,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11633, 66},
    /*  72 : SHL reg32?,reg_cx [v+m-:      evex.nd1.nf.l0.m4.o32 d3 /4       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 204 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {REG_GPR|BITS32,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11643, 67},
    /*  73 : SHL reg64?,rm64,reg_cx [vm-:      evex.nd1.nf.l0.m4.o64 d3 /4       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 214 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_CX,0,0}, NO_DECORATOR, nasm_bytecodes+11653, 41},
    /*  74 : SHL rm64,reg_cx [m-:      evex.nd0.nf.l0.m4.o64 d3 /4       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(d3) 204 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {RM_GPR|BITS64,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11663, 66},
    /*  75 : SHL reg64?,reg_cx [v+m-:      evex.nd1.nf.l0.m4.o64 d3 /4       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 204 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {REG_GPR|BITS64,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11673, 67},
    /*  76 : SHL reg8?,rm8,reg_ecx [vm-:      evex.nd1.nf.l0.m4.o8 d2 /4        ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 214 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 3, {REG_GPR|BITS8,RM_GPR|BITS8,REG_ECX,0,0}, NO_DECORATOR, nasm_bytecodes+24003, 35},
    /*  77 : SHL rm8,reg_ecx [m-:      evex.nd0.nf.l0.m4.o8 d2 /4        ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(d2) 204 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {RM_GPR|BITS8,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+24012, 62},
    /*  78 : SHL reg8?,reg_ecx [v+m-:      evex.nd1.nf.l0.m4.o8 d2 /4        ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 204 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {REG_GPR|BITS8,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+24021, 63},
    /*  79 : SHL reg16?,rm16,reg_ecx [vm-:      evex.nd1.nf.l0.m4.o16 d3 /4       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 214 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 3, {REG_GPR|BITS16,RM_GPR|BITS16,REG_ECX,0,0}, NO_DECORATOR, nasm_bytecodes+11593, 38},
    /*  80 : SHL rm16,reg_ecx [m-:      evex.nd0.nf.l0.m4.o16 d3 /4       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(d3) 204 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {RM_GPR|BITS16,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11603, 64},
    /*  81 : SHL reg16?,reg_ecx [v+m-:      evex.nd1.nf.l0.m4.o16 d3 /4       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 204 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {REG_GPR|BITS16,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11613, 65},
    /*  82 : SHL reg32?,rm32,reg_ecx [vm-:      evex.nd1.nf.l0.m4.o32 d3 /4       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 214 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_ECX,0,0}, NO_DECORATOR, nasm_bytecodes+11623, 41},
    /*  83 : SHL rm32,reg_ecx [m-:      evex.nd0.nf.l0.m4.o32 d3 /4       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(d3) 204 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {RM_GPR|BITS32,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11633, 66},
    /*  84 : SHL reg32?,reg_ecx [v+m-:      evex.nd1.nf.l0.m4.o32 d3 /4       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 204 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {REG_GPR|BITS32,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11643, 67},
    /*  85 : SHL reg64?,rm64,reg_ecx [vm-:      evex.nd1.nf.l0.m4.o64 d3 /4       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 214 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_ECX,0,0}, NO_DECORATOR, nasm_bytecodes+11653, 41},
    /*  86 : SHL rm64,reg_ecx [m-:      evex.nd0.nf.l0.m4.o64 d3 /4       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(d3) 204 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {RM_GPR|BITS64,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11663, 66},
    /*  87 : SHL reg64?,reg_ecx [v+m-:      evex.nd1.nf.l0.m4.o64 d3 /4       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 204 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {REG_GPR|BITS64,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11673, 67},
    /*  88 : SHL reg8?,rm8,reg_rcx [vm-:      evex.nd1.nf.l0.m4.o8 d2 /4        ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 214 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 3, {REG_GPR|BITS8,RM_GPR|BITS8,REG_RCX,0,0}, NO_DECORATOR, nasm_bytecodes+24003, 35},
    /*  89 : SHL rm8,reg_rcx [m-:      evex.nd0.nf.l0.m4.o8 d2 /4        ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(d2) 204 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {RM_GPR|BITS8,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+24012, 62},
    /*  90 : SHL reg8?,reg_rcx [v+m-:      evex.nd1.nf.l0.m4.o8 d2 /4        ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 204 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {REG_GPR|BITS8,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+24021, 63},
    /*  91 : SHL reg16?,rm16,reg_rcx [vm-:      evex.nd1.nf.l0.m4.o16 d3 /4       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 214 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 3, {REG_GPR|BITS16,RM_GPR|BITS16,REG_RCX,0,0}, NO_DECORATOR, nasm_bytecodes+11593, 38},
    /*  92 : SHL rm16,reg_rcx [m-:      evex.nd0.nf.l0.m4.o16 d3 /4       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(d3) 204 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {RM_GPR|BITS16,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11603, 64},
    /*  93 : SHL reg16?,reg_rcx [v+m-:      evex.nd1.nf.l0.m4.o16 d3 /4       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 204 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {REG_GPR|BITS16,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11613, 65},
    /*  94 : SHL reg32?,rm32,reg_rcx [vm-:      evex.nd1.nf.l0.m4.o32 d3 /4       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 214 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_RCX,0,0}, NO_DECORATOR, nasm_bytecodes+11623, 41},
    /*  95 : SHL rm32,reg_rcx [m-:      evex.nd0.nf.l0.m4.o32 d3 /4       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(d3) 204 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {RM_GPR|BITS32,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11633, 66},
    /*  96 : SHL reg32?,reg_rcx [v+m-:      evex.nd1.nf.l0.m4.o32 d3 /4       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 204 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {REG_GPR|BITS32,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11643, 67},
    /*  97 : SHL reg64?,rm64,reg_rcx [vm-:      evex.nd1.nf.l0.m4.o64 d3 /4       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 214 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_RCX,0,0}, NO_DECORATOR, nasm_bytecodes+11653, 41},
    /*  98 : SHL rm64,reg_rcx [m-:      evex.nd0.nf.l0.m4.o64 d3 /4       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(d3) 204 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {RM_GPR|BITS64,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11663, 66},
    /*  99 : SHL reg64?,reg_rcx [v+m-:      evex.nd1.nf.l0.m4.o64 d3 /4       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 204 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {REG_GPR|BITS64,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11673, 67},
    /* 100 : SHL reg8?,rm8,imm8 [vmi:      evex.nd1.nf.l0.m4.o8 c0 /4 ib,u   ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(c0) 214 026 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 3, {REG_GPR|BITS8,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+11683, 35},
    /* 101 : SHL rm8,imm8 [mi:      evex.nd0.nf.l0.m4.o8 c0 /4 ib,u   ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(c0) 204 025 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+11693, 62},
    /* 102 : SHL reg8?,imm8 [v+mi:      evex.nd1.nf.l0.m4.o8 c0 /4 ib,u   ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(c0) 204 025 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {REG_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+11703, 63},
    /* 103 : SHL reg16?,rm16,imm8 [vmi:      evex.nd1.nf.l0.m4.o16 c1 /4 ib,u  ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(c1) 214 026 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 3, {REG_GPR|BITS16,RM_GPR|BITS16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+1806, 38},
    /* 104 : SHL rm16,imm8 [mi:      evex.nd0.nf.l0.m4.o16 c1 /4 ib,u  ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(c1) 204 025 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {RM_GPR|BITS16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1817, 64},
    /* 105 : SHL reg16?,imm8 [v+mi:      evex.nd1.nf.l0.m4.o16 c1 /4 ib,u  ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(c1) 204 025 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {REG_GPR|BITS16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1828, 65},
    /* 106 : SHL reg32?,rm32,imm8 [vmi:      evex.nd1.nf.l0.m4.o32 c1 /4 ib,u  ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(c1) 214 026 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+1839, 41},
    /* 107 : SHL rm32,imm8 [mi:      evex.nd0.nf.l0.m4.o32 c1 /4 ib,u  ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(c1) 204 025 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {RM_GPR|BITS32,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1850, 66},
    /* 108 : SHL reg32?,imm8 [v+mi:      evex.nd1.nf.l0.m4.o32 c1 /4 ib,u  ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(c1) 204 025 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {REG_GPR|BITS32,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1861, 67},
    /* 109 : SHL reg64?,rm64,imm8 [vmi:      evex.nd1.nf.l0.m4.o64 c1 /4 ib,u  ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(c1) 214 026 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 3, {REG_GPR|BITS64,RM_GPR|BITS64,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+1872, 41},
    /* 110 : SHL rm64,imm8 [mi:      evex.nd0.nf.l0.m4.o64 c1 /4 ib,u  ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(c1) 204 025 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {RM_GPR|BITS64,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1883, 66},
    /* 111 : SHL reg64?,imm8 [v+mi:      evex.nd1.nf.l0.m4.o64 c1 /4 ib,u  ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(c1) 204 025 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHL, 2, {REG_GPR|BITS64,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1894, 67},
    /* 112 : SHL reg32,rm32*,reg8 [rmv:      evex.lz.66.0f38.w0 f7 /r          ] ND,SM0,SM1,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 7d 08) 300 001(f7) 110 : SM0,SM1,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24138, 70},
    /* 113 : SHL reg32,reg8 [r+mv:      evex.lz.66.0f38.w0 f7 /r          ] ND,SM0,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 7d 08) 300 001(f7) 100 : SM0,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHL, 2, {REG_GPR|BITS32,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+24147, 71},
    /* 114 : SHL reg32,rm32*,reg16 [rmv:      evex.lz.66.0f38.w0 f7 /r          ] ND,SM0,SM1,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 7d 08) 300 001(f7) 110 : SM0,SM1,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+24138, 70},
    /* 115 : SHL reg32,reg16 [r+mv:      evex.lz.66.0f38.w0 f7 /r          ] ND,SM0,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 7d 08) 300 001(f7) 100 : SM0,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHL, 2, {REG_GPR|BITS32,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+24147, 71},
    /* 116 : SHL reg32,rm32*,reg32 [rmv:      evex.lz.66.0f38.w0 f7 /r          ] ND,SM0,SM1,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 7d 08) 300 001(f7) 110 : SM0,SM1,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+24138, 70},
    /* 117 : SHL reg32,reg32 [r+mv:      evex.lz.66.0f38.w0 f7 /r          ] ND,SM0,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 7d 08) 300 001(f7) 100 : SM0,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHL, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+24147, 71},
    /* 118 : SHL reg32,rm32*,reg64 [rmv:      evex.lz.66.0f38.w0 f7 /r          ] ND,SM0,SM1,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 7d 08) 300 001(f7) 110 : SM0,SM1,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+24138, 70},
    /* 119 : SHL reg32,reg64 [r+mv:      evex.lz.66.0f38.w0 f7 /r          ] ND,SM0,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 7d 08) 300 001(f7) 100 : SM0,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHL, 2, {REG_GPR|BITS32,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+24147, 71},
    /* 120 : SHL reg64,rm64*,reg8 [rmv:      evex.lz.66.0f38.w1 f7 /r          ] ND,SM0,SM1,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 fd 08) 300 001(f7) 110 : SM0,SM1,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHL, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24192, 70},
    /* 121 : SHL reg64,reg8 [r+mv:      evex.lz.66.0f38.w1 f7 /r          ] ND,SM0,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 fd 08) 300 001(f7) 100 : SM0,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHL, 2, {REG_GPR|BITS64,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+24201, 71},
    /* 122 : SHL reg64,rm64*,reg16 [rmv:      evex.lz.66.0f38.w1 f7 /r          ] ND,SM0,SM1,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 fd 08) 300 001(f7) 110 : SM0,SM1,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHL, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+24192, 70},
    /* 123 : SHL reg64,reg16 [r+mv:      evex.lz.66.0f38.w1 f7 /r          ] ND,SM0,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 fd 08) 300 001(f7) 100 : SM0,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHL, 2, {REG_GPR|BITS64,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+24201, 71},
    /* 124 : SHL reg64,rm64*,reg32 [rmv:      evex.lz.66.0f38.w1 f7 /r          ] ND,SM0,SM1,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 fd 08) 300 001(f7) 110 : SM0,SM1,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHL, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+24192, 70},
    /* 125 : SHL reg64,reg32 [r+mv:      evex.lz.66.0f38.w1 f7 /r          ] ND,SM0,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 fd 08) 300 001(f7) 100 : SM0,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHL, 2, {REG_GPR|BITS64,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+24201, 71},
    /* 126 : SHL reg64,rm64*,reg64 [rmv:      evex.lz.66.0f38.w1 f7 /r          ] ND,SM0,SM1,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 fd 08) 300 001(f7) 110 : SM0,SM1,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHL, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+24192, 70},
    /* 127 : SHL reg64,reg64 [r+mv:      evex.lz.66.0f38.w1 f7 /r          ] ND,SM0,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 fd 08) 300 001(f7) 100 : SM0,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHL, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+24201, 71},
    /* 128 : SHL kreg8,kreg8,imm8 [rmi:      vex.l0.66.0f3a.w0 32 /r ib       ] ND,SM0-1,ZU,FL,AVX512DQ,FUTURE */
        /* 270(003 001) 001(32) 110 022 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512DQ,FUTURE */
        {I_SHL, 3, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54573, 518},
    /* 129 : SHL kreg8,kreg8,imm8 [rmi:      evex.l0.66.0f3a.w0 32 /r ib       ] ND,SM0-1,ZU,FL,AVX512DQ,FUTURE,APX */
        /* 250(f3 7d 08) 300 001(32) 110 022 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_SHL, 3, {OPMASKREG|BITS8,OPMASKREG|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18053, 519},
    /* 130 : SHL kreg16,kreg16,imm8 [rmi:      vex.l0.66.0f3a.w1 32 /r ib       ] ND,SM0-1,ZU,FL,AVX512F,FUTURE */
        /* 270(003 201) 001(32) 110 022 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512F,FUTURE */
        {I_SHL, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54581, 530},
    /* 131 : SHL kreg16,kreg16,imm8 [rmi:      evex.l0.66.0f3a.w1 32 /r ib       ] ND,SM0-1,ZU,FL,AVX512F,FUTURE,APX */
        /* 250(f3 fd 08) 300 001(32) 110 022 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_SHL, 3, {OPMASKREG|BITS16,OPMASKREG|BITS16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18063, 531},
    /* 132 : SHL kreg32,kreg32,imm8 [rmi:      vex.l0.66.0f3a.w0 33 /r ib       ] ND,SM0-1,ZU,FL,AVX512BW,FUTURE */
        /* 270(003 001) 001(33) 110 022 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_SHL, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54589, 522},
    /* 133 : SHL kreg32,kreg32,imm8 [rmi:      evex.l0.66.0f3a.w0 33 /r ib       ] ND,SM0-1,ZU,FL,AVX512BW,FUTURE,APX */
        /* 250(f3 7d 08) 300 001(33) 110 022 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_SHL, 3, {OPMASKREG|BITS32,OPMASKREG|BITS32,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18073, 523},
    /* 134 : SHL kreg64,kreg64,imm8 [rmi:      vex.l0.66.0f3a.w1 33 /r ib       ] ND,SM0-1,ZU,FL,AVX512BW,FUTURE */
        /* 270(003 201) 001(33) 110 022 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_SHL, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54597, 522},
    /* 135 : SHL kreg64,kreg64,imm8 [rmi:      evex.l0.66.0f3a.w1 33 /r ib       ] ND,SM0-1,ZU,FL,AVX512BW,FUTURE,APX */
        /* 250(f3 fd 08) 300 001(33) 110 022 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_SHL, 3, {OPMASKREG|BITS64,OPMASKREG|BITS64,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18083, 523},
};

static const struct itemplate instrux_SAL[128] = {
    /*   0 : SAL rm8,unity [m-:       o8 d0 /4                          ] FL,8086 */
        /* 001(d0) 204 : FL,8086 */
        {I_SAL, 2, {RM_GPR|BITS8,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+23999, 54},
    /*   1 : SAL rm16,unity [m-:       o16 d1 /4                         ] FL,8086 */
        /* 320 001(d1) 204 : FL,8086 */
        {I_SAL, 2, {RM_GPR|BITS16,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11528, 54},
    /*   2 : SAL rm32,unity [m-:       o32 d1 /4                         ] FL,386 */
        /* 321 001(d1) 204 : FL,386 */
        {I_SAL, 2, {RM_GPR|BITS32,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11558, 55},
    /*   3 : SAL rm64,unity [m-:       o64 d1 /4                         ] LONG,FL,PROT,X86_64 */
        /* 324 001(d1) 204 : LONG,FL,PROT,X86_64 */
        {I_SAL, 2, {RM_GPR|BITS64,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11588, 56},
    /*   4 : SAL rm8,reg_cl [m-:       o8 d2 /4                          ] FL,8086 */
        /* 001(d2) 204 : FL,8086 */
        {I_SAL, 2, {RM_GPR|BITS8,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+24026, 54},
    /*   5 : SAL rm16,reg_cl [m-:       o16 d3 /4                         ] FL,8086 */
        /* 320 001(d3) 204 : FL,8086 */
        {I_SAL, 2, {RM_GPR|BITS16,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11618, 54},
    /*   6 : SAL rm32,reg_cl [m-:       o32 d3 /4                         ] FL,386 */
        /* 321 001(d3) 204 : FL,386 */
        {I_SAL, 2, {RM_GPR|BITS32,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11648, 55},
    /*   7 : SAL rm64,reg_cl [m-:       o64 d3 /4                         ] LONG,FL,PROT,X86_64 */
        /* 324 001(d3) 204 : LONG,FL,PROT,X86_64 */
        {I_SAL, 2, {RM_GPR|BITS64,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11678, 56},
    /*   8 : SAL rm8,reg_cx [m-:       o8 d2 /4                          ] ND,FL,8086 */
        /* 001(d2) 204 : FL,8086 */
        {I_SAL, 2, {RM_GPR|BITS8,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+24026, 54},
    /*   9 : SAL rm16,reg_cx [m-:       o16 d3 /4                         ] ND,FL,8086 */
        /* 320 001(d3) 204 : FL,8086 */
        {I_SAL, 2, {RM_GPR|BITS16,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11618, 54},
    /*  10 : SAL rm32,reg_cx [m-:       o32 d3 /4                         ] ND,FL,386 */
        /* 321 001(d3) 204 : FL,386 */
        {I_SAL, 2, {RM_GPR|BITS32,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11648, 55},
    /*  11 : SAL rm64,reg_cx [m-:       o64 d3 /4                         ] ND,LONG,FL,PROT,X86_64 */
        /* 324 001(d3) 204 : LONG,FL,PROT,X86_64 */
        {I_SAL, 2, {RM_GPR|BITS64,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11678, 56},
    /*  12 : SAL rm8,reg_ecx [m-:       o8 d2 /4                          ] ND,FL,8086 */
        /* 001(d2) 204 : FL,8086 */
        {I_SAL, 2, {RM_GPR|BITS8,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+24026, 54},
    /*  13 : SAL rm16,reg_ecx [m-:       o16 d3 /4                         ] ND,FL,8086 */
        /* 320 001(d3) 204 : FL,8086 */
        {I_SAL, 2, {RM_GPR|BITS16,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11618, 54},
    /*  14 : SAL rm32,reg_ecx [m-:       o32 d3 /4                         ] ND,FL,386 */
        /* 321 001(d3) 204 : FL,386 */
        {I_SAL, 2, {RM_GPR|BITS32,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11648, 55},
    /*  15 : SAL rm64,reg_ecx [m-:       o64 d3 /4                         ] ND,LONG,FL,PROT,X86_64 */
        /* 324 001(d3) 204 : LONG,FL,PROT,X86_64 */
        {I_SAL, 2, {RM_GPR|BITS64,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11678, 56},
    /*  16 : SAL rm8,reg_rcx [m-:       o8 d2 /4                          ] ND,FL,8086 */
        /* 001(d2) 204 : FL,8086 */
        {I_SAL, 2, {RM_GPR|BITS8,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+24026, 54},
    /*  17 : SAL rm16,reg_rcx [m-:       o16 d3 /4                         ] ND,FL,8086 */
        /* 320 001(d3) 204 : FL,8086 */
        {I_SAL, 2, {RM_GPR|BITS16,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11618, 54},
    /*  18 : SAL rm32,reg_rcx [m-:       o32 d3 /4                         ] ND,FL,386 */
        /* 321 001(d3) 204 : FL,386 */
        {I_SAL, 2, {RM_GPR|BITS32,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11648, 55},
    /*  19 : SAL rm64,reg_rcx [m-:       o64 d3 /4                         ] ND,LONG,FL,PROT,X86_64 */
        /* 324 001(d3) 204 : LONG,FL,PROT,X86_64 */
        {I_SAL, 2, {RM_GPR|BITS64,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11678, 56},
    /*  20 : SAL rm8,imm8 [mi:       o8 c0 /4 ib,u                     ] FL,186 */
        /* 001(c0) 204 025 : FL,186 */
        {I_SAL, 2, {RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+11708, 57},
    /*  21 : SAL rm16,imm8 [mi:       o16 c1 /4 ib,u                    ] FL,186 */
        /* 320 001(c1) 204 025 : FL,186 */
        {I_SAL, 2, {RM_GPR|BITS16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1833, 57},
    /*  22 : SAL rm32,imm8 [mi:       o32 c1 /4 ib,u                    ] FL,386 */
        /* 321 001(c1) 204 025 : FL,386 */
        {I_SAL, 2, {RM_GPR|BITS32,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1866, 55},
    /*  23 : SAL rm64,imm8 [mi:       o64 c1 /4 ib,u                    ] LONG,FL,PROT,X86_64 */
        /* 324 001(c1) 204 025 : LONG,FL,PROT,X86_64 */
        {I_SAL, 2, {RM_GPR|BITS64,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1899, 56},
    /*  24 : SAL reg32,rm32*,reg8 [rmv:      vex.lz.66.0f38.w0 f7 /r           ] ND,SM0,SM1,OPT,NF,NF_R,BMI2,FUTURE */
        /* 262(002 001) 001(f7) 110 : SM0,SM1,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SAL, 3, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,REG_GPR|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55087, 60},
    /*  25 : SAL reg32,reg8 [r+mv:      vex.lz.66.0f38.w0 f7 /r           ] ND,SM0,OPT,NF,NF_R,BMI2,FUTURE */
        /* 261(002 001) 001(f7) 100 : SM0,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SAL, 2, {REG_GPR|BITS32|RN_L16,REG_GPR|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55094, 61},
    /*  26 : SAL reg32,rm32*,reg16 [rmv:      vex.lz.66.0f38.w0 f7 /r           ] ND,SM0,SM1,OPT,NF,NF_R,BMI2,FUTURE */
        /* 262(002 001) 001(f7) 110 : SM0,SM1,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SAL, 3, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,REG_GPR|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55087, 60},
    /*  27 : SAL reg32,reg16 [r+mv:      vex.lz.66.0f38.w0 f7 /r           ] ND,SM0,OPT,NF,NF_R,BMI2,FUTURE */
        /* 261(002 001) 001(f7) 100 : SM0,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SAL, 2, {REG_GPR|BITS32|RN_L16,REG_GPR|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55094, 61},
    /*  28 : SAL reg32,rm32*,reg32 [rmv:      vex.lz.66.0f38.w0 f7 /r           ] ND,SM0,SM1,OPT,NF,NF_R,BMI2,FUTURE */
        /* 262(002 001) 001(f7) 110 : SM0,SM1,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SAL, 3, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55087, 60},
    /*  29 : SAL reg32,reg32 [r+mv:      vex.lz.66.0f38.w0 f7 /r           ] ND,SM0,OPT,NF,NF_R,BMI2,FUTURE */
        /* 261(002 001) 001(f7) 100 : SM0,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SAL, 2, {REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55094, 61},
    /*  30 : SAL reg32,rm32*,reg64 [rmv:      vex.lz.66.0f38.w0 f7 /r           ] ND,SM0,SM1,OPT,NF,NF_R,BMI2,FUTURE */
        /* 262(002 001) 001(f7) 110 : SM0,SM1,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SAL, 3, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55087, 60},
    /*  31 : SAL reg32,reg64 [r+mv:      vex.lz.66.0f38.w0 f7 /r           ] ND,SM0,OPT,NF,NF_R,BMI2,FUTURE */
        /* 261(002 001) 001(f7) 100 : SM0,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SAL, 2, {REG_GPR|BITS32|RN_L16,REG_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55094, 61},
    /*  32 : SAL reg64,rm64*,reg8 [rmv:      vex.lz.66.0f38.w1 f7 /r           ] ND,SM0,SM1,OPT,NF,NF_R,BMI2,FUTURE */
        /* 262(002 201) 001(f7) 110 : SM0,SM1,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SAL, 3, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,REG_GPR|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55129, 60},
    /*  33 : SAL reg64,reg8 [r+mv:      vex.lz.66.0f38.w1 f7 /r           ] ND,SM0,OPT,NF,NF_R,BMI2,FUTURE */
        /* 261(002 201) 001(f7) 100 : SM0,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SAL, 2, {REG_GPR|BITS64|RN_L16,REG_GPR|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55136, 61},
    /*  34 : SAL reg64,rm64*,reg16 [rmv:      vex.lz.66.0f38.w1 f7 /r           ] ND,SM0,SM1,OPT,NF,NF_R,BMI2,FUTURE */
        /* 262(002 201) 001(f7) 110 : SM0,SM1,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SAL, 3, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,REG_GPR|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55129, 60},
    /*  35 : SAL reg64,reg16 [r+mv:      vex.lz.66.0f38.w1 f7 /r           ] ND,SM0,OPT,NF,NF_R,BMI2,FUTURE */
        /* 261(002 201) 001(f7) 100 : SM0,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SAL, 2, {REG_GPR|BITS64|RN_L16,REG_GPR|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55136, 61},
    /*  36 : SAL reg64,rm64*,reg32 [rmv:      vex.lz.66.0f38.w1 f7 /r           ] ND,SM0,SM1,OPT,NF,NF_R,BMI2,FUTURE */
        /* 262(002 201) 001(f7) 110 : SM0,SM1,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SAL, 3, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55129, 60},
    /*  37 : SAL reg64,reg32 [r+mv:      vex.lz.66.0f38.w1 f7 /r           ] ND,SM0,OPT,NF,NF_R,BMI2,FUTURE */
        /* 261(002 201) 001(f7) 100 : SM0,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SAL, 2, {REG_GPR|BITS64|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55136, 61},
    /*  38 : SAL reg64,rm64*,reg64 [rmv:      vex.lz.66.0f38.w1 f7 /r           ] ND,SM0,SM1,OPT,NF,NF_R,BMI2,FUTURE */
        /* 262(002 201) 001(f7) 110 : SM0,SM1,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SAL, 3, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55129, 60},
    /*  39 : SAL reg64,reg64 [r+mv:      vex.lz.66.0f38.w1 f7 /r           ] ND,SM0,OPT,NF,NF_R,BMI2,FUTURE */
        /* 261(002 201) 001(f7) 100 : SM0,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SAL, 2, {REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55136, 61},
    /*  40 : SAL reg8?,rm8,unity [vm-:      evex.nd1.nf.l0.m4.o8 d0 /4        ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d0) 214 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 3, {REG_GPR|BITS8,RM_GPR|BITS8,UNITY|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+23976, 35},
    /*  41 : SAL rm8,unity [m-:      evex.nd0.nf.l0.m4.o8 d0 /4        ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(d0) 204 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {RM_GPR|BITS8,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+23985, 62},
    /*  42 : SAL reg8?,unity [v+m-:      evex.nd1.nf.l0.m4.o8 d0 /4        ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d0) 204 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {REG_GPR|BITS8,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+23994, 63},
    /*  43 : SAL reg16?,rm16,unity [vm-:      evex.nd1.nf.l0.m4.o16 d1 /4       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d1) 214 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 3, {REG_GPR|BITS16,RM_GPR|BITS16,UNITY|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+11503, 38},
    /*  44 : SAL rm16,unity [m-:      evex.nd0.nf.l0.m4.o16 d1 /4       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(d1) 204 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {RM_GPR|BITS16,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11513, 64},
    /*  45 : SAL reg16?,unity [v+m-:      evex.nd1.nf.l0.m4.o16 d1 /4       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d1) 204 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {REG_GPR|BITS16,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11523, 65},
    /*  46 : SAL reg32?,rm32,unity [vm-:      evex.nd1.nf.l0.m4.o32 d1 /4       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d1) 214 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,UNITY|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+11533, 41},
    /*  47 : SAL rm32,unity [m-:      evex.nd0.nf.l0.m4.o32 d1 /4       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(d1) 204 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {RM_GPR|BITS32,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11543, 66},
    /*  48 : SAL reg32?,unity [v+m-:      evex.nd1.nf.l0.m4.o32 d1 /4       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d1) 204 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {REG_GPR|BITS32,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11553, 67},
    /*  49 : SAL reg64?,rm64,unity [vm-:      evex.nd1.nf.l0.m4.o64 d1 /4       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d1) 214 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 3, {REG_GPR|BITS64,RM_GPR|BITS64,UNITY|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+11563, 41},
    /*  50 : SAL rm64,unity [m-:      evex.nd0.nf.l0.m4.o64 d1 /4       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(d1) 204 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {RM_GPR|BITS64,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11573, 66},
    /*  51 : SAL reg64?,unity [v+m-:      evex.nd1.nf.l0.m4.o64 d1 /4       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d1) 204 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {REG_GPR|BITS64,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11583, 67},
    /*  52 : SAL reg8?,rm8,reg_cl [vm-:      evex.nd1.nf.l0.m4.o8 d2 /4        ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 214 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 3, {REG_GPR|BITS8,RM_GPR|BITS8,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+24003, 35},
    /*  53 : SAL rm8,reg_cl [m-:      evex.nd0.nf.l0.m4.o8 d2 /4        ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(d2) 204 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {RM_GPR|BITS8,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+24012, 62},
    /*  54 : SAL reg8?,reg_cl [v+m-:      evex.nd1.nf.l0.m4.o8 d2 /4        ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 204 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {REG_GPR|BITS8,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+24021, 63},
    /*  55 : SAL reg16?,rm16,reg_cl [vm-:      evex.nd1.nf.l0.m4.o16 d3 /4       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 214 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 3, {REG_GPR|BITS16,RM_GPR|BITS16,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+11593, 38},
    /*  56 : SAL rm16,reg_cl [m-:      evex.nd0.nf.l0.m4.o16 d3 /4       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(d3) 204 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {RM_GPR|BITS16,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11603, 64},
    /*  57 : SAL reg16?,reg_cl [v+m-:      evex.nd1.nf.l0.m4.o16 d3 /4       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 204 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {REG_GPR|BITS16,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11613, 65},
    /*  58 : SAL reg32?,rm32,reg_cl [vm-:      evex.nd1.nf.l0.m4.o32 d3 /4       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 214 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+11623, 41},
    /*  59 : SAL rm32,reg_cl [m-:      evex.nd0.nf.l0.m4.o32 d3 /4       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(d3) 204 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {RM_GPR|BITS32,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11633, 66},
    /*  60 : SAL reg32?,reg_cl [v+m-:      evex.nd1.nf.l0.m4.o32 d3 /4       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 204 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {REG_GPR|BITS32,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11643, 67},
    /*  61 : SAL reg64?,rm64,reg_cl [vm-:      evex.nd1.nf.l0.m4.o64 d3 /4       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 214 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+11653, 41},
    /*  62 : SAL rm64,reg_cl [m-:      evex.nd0.nf.l0.m4.o64 d3 /4       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(d3) 204 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {RM_GPR|BITS64,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11663, 66},
    /*  63 : SAL reg64?,reg_cl [v+m-:      evex.nd1.nf.l0.m4.o64 d3 /4       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 204 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {REG_GPR|BITS64,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11673, 67},
    /*  64 : SAL reg8?,rm8,reg_cx [vm-:      evex.nd1.nf.l0.m4.o8 d2 /4        ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 214 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 3, {REG_GPR|BITS8,RM_GPR|BITS8,REG_CX,0,0}, NO_DECORATOR, nasm_bytecodes+24003, 35},
    /*  65 : SAL rm8,reg_cx [m-:      evex.nd0.nf.l0.m4.o8 d2 /4        ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(d2) 204 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {RM_GPR|BITS8,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+24012, 62},
    /*  66 : SAL reg8?,reg_cx [v+m-:      evex.nd1.nf.l0.m4.o8 d2 /4        ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 204 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {REG_GPR|BITS8,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+24021, 63},
    /*  67 : SAL reg16?,rm16,reg_cx [vm-:      evex.nd1.nf.l0.m4.o16 d3 /4       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 214 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 3, {REG_GPR|BITS16,RM_GPR|BITS16,REG_CX,0,0}, NO_DECORATOR, nasm_bytecodes+11593, 38},
    /*  68 : SAL rm16,reg_cx [m-:      evex.nd0.nf.l0.m4.o16 d3 /4       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(d3) 204 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {RM_GPR|BITS16,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11603, 64},
    /*  69 : SAL reg16?,reg_cx [v+m-:      evex.nd1.nf.l0.m4.o16 d3 /4       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 204 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {REG_GPR|BITS16,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11613, 65},
    /*  70 : SAL reg32?,rm32,reg_cx [vm-:      evex.nd1.nf.l0.m4.o32 d3 /4       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 214 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_CX,0,0}, NO_DECORATOR, nasm_bytecodes+11623, 41},
    /*  71 : SAL rm32,reg_cx [m-:      evex.nd0.nf.l0.m4.o32 d3 /4       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(d3) 204 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {RM_GPR|BITS32,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11633, 66},
    /*  72 : SAL reg32?,reg_cx [v+m-:      evex.nd1.nf.l0.m4.o32 d3 /4       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 204 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {REG_GPR|BITS32,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11643, 67},
    /*  73 : SAL reg64?,rm64,reg_cx [vm-:      evex.nd1.nf.l0.m4.o64 d3 /4       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 214 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_CX,0,0}, NO_DECORATOR, nasm_bytecodes+11653, 41},
    /*  74 : SAL rm64,reg_cx [m-:      evex.nd0.nf.l0.m4.o64 d3 /4       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(d3) 204 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {RM_GPR|BITS64,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11663, 66},
    /*  75 : SAL reg64?,reg_cx [v+m-:      evex.nd1.nf.l0.m4.o64 d3 /4       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 204 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {REG_GPR|BITS64,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11673, 67},
    /*  76 : SAL reg8?,rm8,reg_ecx [vm-:      evex.nd1.nf.l0.m4.o8 d2 /4        ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 214 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 3, {REG_GPR|BITS8,RM_GPR|BITS8,REG_ECX,0,0}, NO_DECORATOR, nasm_bytecodes+24003, 35},
    /*  77 : SAL rm8,reg_ecx [m-:      evex.nd0.nf.l0.m4.o8 d2 /4        ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(d2) 204 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {RM_GPR|BITS8,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+24012, 62},
    /*  78 : SAL reg8?,reg_ecx [v+m-:      evex.nd1.nf.l0.m4.o8 d2 /4        ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 204 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {REG_GPR|BITS8,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+24021, 63},
    /*  79 : SAL reg16?,rm16,reg_ecx [vm-:      evex.nd1.nf.l0.m4.o16 d3 /4       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 214 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 3, {REG_GPR|BITS16,RM_GPR|BITS16,REG_ECX,0,0}, NO_DECORATOR, nasm_bytecodes+11593, 38},
    /*  80 : SAL rm16,reg_ecx [m-:      evex.nd0.nf.l0.m4.o16 d3 /4       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(d3) 204 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {RM_GPR|BITS16,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11603, 64},
    /*  81 : SAL reg16?,reg_ecx [v+m-:      evex.nd1.nf.l0.m4.o16 d3 /4       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 204 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {REG_GPR|BITS16,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11613, 65},
    /*  82 : SAL reg32?,rm32,reg_ecx [vm-:      evex.nd1.nf.l0.m4.o32 d3 /4       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 214 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_ECX,0,0}, NO_DECORATOR, nasm_bytecodes+11623, 41},
    /*  83 : SAL rm32,reg_ecx [m-:      evex.nd0.nf.l0.m4.o32 d3 /4       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(d3) 204 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {RM_GPR|BITS32,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11633, 66},
    /*  84 : SAL reg32?,reg_ecx [v+m-:      evex.nd1.nf.l0.m4.o32 d3 /4       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 204 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {REG_GPR|BITS32,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11643, 67},
    /*  85 : SAL reg64?,rm64,reg_ecx [vm-:      evex.nd1.nf.l0.m4.o64 d3 /4       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 214 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_ECX,0,0}, NO_DECORATOR, nasm_bytecodes+11653, 41},
    /*  86 : SAL rm64,reg_ecx [m-:      evex.nd0.nf.l0.m4.o64 d3 /4       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(d3) 204 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {RM_GPR|BITS64,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11663, 66},
    /*  87 : SAL reg64?,reg_ecx [v+m-:      evex.nd1.nf.l0.m4.o64 d3 /4       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 204 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {REG_GPR|BITS64,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11673, 67},
    /*  88 : SAL reg8?,rm8,reg_rcx [vm-:      evex.nd1.nf.l0.m4.o8 d2 /4        ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 214 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 3, {REG_GPR|BITS8,RM_GPR|BITS8,REG_RCX,0,0}, NO_DECORATOR, nasm_bytecodes+24003, 35},
    /*  89 : SAL rm8,reg_rcx [m-:      evex.nd0.nf.l0.m4.o8 d2 /4        ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(d2) 204 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {RM_GPR|BITS8,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+24012, 62},
    /*  90 : SAL reg8?,reg_rcx [v+m-:      evex.nd1.nf.l0.m4.o8 d2 /4        ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 204 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {REG_GPR|BITS8,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+24021, 63},
    /*  91 : SAL reg16?,rm16,reg_rcx [vm-:      evex.nd1.nf.l0.m4.o16 d3 /4       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 214 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 3, {REG_GPR|BITS16,RM_GPR|BITS16,REG_RCX,0,0}, NO_DECORATOR, nasm_bytecodes+11593, 38},
    /*  92 : SAL rm16,reg_rcx [m-:      evex.nd0.nf.l0.m4.o16 d3 /4       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(d3) 204 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {RM_GPR|BITS16,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11603, 64},
    /*  93 : SAL reg16?,reg_rcx [v+m-:      evex.nd1.nf.l0.m4.o16 d3 /4       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 204 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {REG_GPR|BITS16,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11613, 65},
    /*  94 : SAL reg32?,rm32,reg_rcx [vm-:      evex.nd1.nf.l0.m4.o32 d3 /4       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 214 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_RCX,0,0}, NO_DECORATOR, nasm_bytecodes+11623, 41},
    /*  95 : SAL rm32,reg_rcx [m-:      evex.nd0.nf.l0.m4.o32 d3 /4       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(d3) 204 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {RM_GPR|BITS32,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11633, 66},
    /*  96 : SAL reg32?,reg_rcx [v+m-:      evex.nd1.nf.l0.m4.o32 d3 /4       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 204 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {REG_GPR|BITS32,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11643, 67},
    /*  97 : SAL reg64?,rm64,reg_rcx [vm-:      evex.nd1.nf.l0.m4.o64 d3 /4       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 214 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_RCX,0,0}, NO_DECORATOR, nasm_bytecodes+11653, 41},
    /*  98 : SAL rm64,reg_rcx [m-:      evex.nd0.nf.l0.m4.o64 d3 /4       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(d3) 204 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {RM_GPR|BITS64,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11663, 66},
    /*  99 : SAL reg64?,reg_rcx [v+m-:      evex.nd1.nf.l0.m4.o64 d3 /4       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 204 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {REG_GPR|BITS64,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11673, 67},
    /* 100 : SAL reg8?,rm8,imm8 [vmi:      evex.nd1.nf.l0.m4.o8 c0 /4 ib,u   ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(c0) 214 026 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 3, {REG_GPR|BITS8,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+11683, 35},
    /* 101 : SAL rm8,imm8 [mi:      evex.nd0.nf.l0.m4.o8 c0 /4 ib,u   ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(c0) 204 025 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+11693, 62},
    /* 102 : SAL reg8?,imm8 [v+mi:      evex.nd1.nf.l0.m4.o8 c0 /4 ib,u   ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(c0) 204 025 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {REG_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+11703, 63},
    /* 103 : SAL reg16?,rm16,imm8 [vmi:      evex.nd1.nf.l0.m4.o16 c1 /4 ib,u  ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(c1) 214 026 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 3, {REG_GPR|BITS16,RM_GPR|BITS16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+1806, 38},
    /* 104 : SAL rm16,imm8 [mi:      evex.nd0.nf.l0.m4.o16 c1 /4 ib,u  ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(c1) 204 025 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {RM_GPR|BITS16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1817, 64},
    /* 105 : SAL reg16?,imm8 [v+mi:      evex.nd1.nf.l0.m4.o16 c1 /4 ib,u  ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(c1) 204 025 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {REG_GPR|BITS16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1828, 65},
    /* 106 : SAL reg32?,rm32,imm8 [vmi:      evex.nd1.nf.l0.m4.o32 c1 /4 ib,u  ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(c1) 214 026 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+1839, 41},
    /* 107 : SAL rm32,imm8 [mi:      evex.nd0.nf.l0.m4.o32 c1 /4 ib,u  ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(c1) 204 025 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {RM_GPR|BITS32,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1850, 66},
    /* 108 : SAL reg32?,imm8 [v+mi:      evex.nd1.nf.l0.m4.o32 c1 /4 ib,u  ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(c1) 204 025 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {REG_GPR|BITS32,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1861, 67},
    /* 109 : SAL reg64?,rm64,imm8 [vmi:      evex.nd1.nf.l0.m4.o64 c1 /4 ib,u  ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(c1) 214 026 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 3, {REG_GPR|BITS64,RM_GPR|BITS64,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+1872, 41},
    /* 110 : SAL rm64,imm8 [mi:      evex.nd0.nf.l0.m4.o64 c1 /4 ib,u  ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(c1) 204 025 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {RM_GPR|BITS64,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1883, 66},
    /* 111 : SAL reg64?,imm8 [v+mi:      evex.nd1.nf.l0.m4.o64 c1 /4 ib,u  ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(c1) 204 025 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAL, 2, {REG_GPR|BITS64,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1894, 67},
    /* 112 : SAL reg32,rm32*,reg8 [rmv:      evex.lz.66.0f38.w0 f7 /r          ] ND,SM0,SM1,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 7d 08) 300 001(f7) 110 : SM0,SM1,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SAL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24138, 70},
    /* 113 : SAL reg32,reg8 [r+mv:      evex.lz.66.0f38.w0 f7 /r          ] ND,SM0,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 7d 08) 300 001(f7) 100 : SM0,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SAL, 2, {REG_GPR|BITS32,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+24147, 71},
    /* 114 : SAL reg32,rm32*,reg16 [rmv:      evex.lz.66.0f38.w0 f7 /r          ] ND,SM0,SM1,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 7d 08) 300 001(f7) 110 : SM0,SM1,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SAL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+24138, 70},
    /* 115 : SAL reg32,reg16 [r+mv:      evex.lz.66.0f38.w0 f7 /r          ] ND,SM0,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 7d 08) 300 001(f7) 100 : SM0,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SAL, 2, {REG_GPR|BITS32,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+24147, 71},
    /* 116 : SAL reg32,rm32*,reg32 [rmv:      evex.lz.66.0f38.w0 f7 /r          ] ND,SM0,SM1,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 7d 08) 300 001(f7) 110 : SM0,SM1,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SAL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+24138, 70},
    /* 117 : SAL reg32,reg32 [r+mv:      evex.lz.66.0f38.w0 f7 /r          ] ND,SM0,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 7d 08) 300 001(f7) 100 : SM0,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SAL, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+24147, 71},
    /* 118 : SAL reg32,rm32*,reg64 [rmv:      evex.lz.66.0f38.w0 f7 /r          ] ND,SM0,SM1,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 7d 08) 300 001(f7) 110 : SM0,SM1,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SAL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+24138, 70},
    /* 119 : SAL reg32,reg64 [r+mv:      evex.lz.66.0f38.w0 f7 /r          ] ND,SM0,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 7d 08) 300 001(f7) 100 : SM0,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SAL, 2, {REG_GPR|BITS32,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+24147, 71},
    /* 120 : SAL reg64,rm64*,reg8 [rmv:      evex.lz.66.0f38.w1 f7 /r          ] ND,SM0,SM1,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 fd 08) 300 001(f7) 110 : SM0,SM1,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SAL, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24192, 70},
    /* 121 : SAL reg64,reg8 [r+mv:      evex.lz.66.0f38.w1 f7 /r          ] ND,SM0,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 fd 08) 300 001(f7) 100 : SM0,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SAL, 2, {REG_GPR|BITS64,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+24201, 71},
    /* 122 : SAL reg64,rm64*,reg16 [rmv:      evex.lz.66.0f38.w1 f7 /r          ] ND,SM0,SM1,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 fd 08) 300 001(f7) 110 : SM0,SM1,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SAL, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+24192, 70},
    /* 123 : SAL reg64,reg16 [r+mv:      evex.lz.66.0f38.w1 f7 /r          ] ND,SM0,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 fd 08) 300 001(f7) 100 : SM0,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SAL, 2, {REG_GPR|BITS64,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+24201, 71},
    /* 124 : SAL reg64,rm64*,reg32 [rmv:      evex.lz.66.0f38.w1 f7 /r          ] ND,SM0,SM1,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 fd 08) 300 001(f7) 110 : SM0,SM1,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SAL, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+24192, 70},
    /* 125 : SAL reg64,reg32 [r+mv:      evex.lz.66.0f38.w1 f7 /r          ] ND,SM0,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 fd 08) 300 001(f7) 100 : SM0,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SAL, 2, {REG_GPR|BITS64,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+24201, 71},
    /* 126 : SAL reg64,rm64*,reg64 [rmv:      evex.lz.66.0f38.w1 f7 /r          ] ND,SM0,SM1,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 fd 08) 300 001(f7) 110 : SM0,SM1,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SAL, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+24192, 70},
    /* 127 : SAL reg64,reg64 [r+mv:      evex.lz.66.0f38.w1 f7 /r          ] ND,SM0,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 fd 08) 300 001(f7) 100 : SM0,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SAL, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+24201, 71},
};

static const struct itemplate instrux_SHR[136] = {
    /*   0 : SHR rm8,unity [m-:       o8 d0 /5                          ] FL,8086 */
        /* 001(d0) 205 : FL,8086 */
        {I_SHR, 2, {RM_GPR|BITS8,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+24053, 54},
    /*   1 : SHR rm16,unity [m-:       o16 d1 /5                         ] FL,8086 */
        /* 320 001(d1) 205 : FL,8086 */
        {I_SHR, 2, {RM_GPR|BITS16,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11738, 54},
    /*   2 : SHR rm32,unity [m-:       o32 d1 /5                         ] FL,386 */
        /* 321 001(d1) 205 : FL,386 */
        {I_SHR, 2, {RM_GPR|BITS32,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11768, 55},
    /*   3 : SHR rm64,unity [m-:       o64 d1 /5                         ] LONG,FL,PROT,X86_64 */
        /* 324 001(d1) 205 : LONG,FL,PROT,X86_64 */
        {I_SHR, 2, {RM_GPR|BITS64,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11798, 56},
    /*   4 : SHR rm8,reg_cl [m-:       o8 d2 /5                          ] FL,8086 */
        /* 001(d2) 205 : FL,8086 */
        {I_SHR, 2, {RM_GPR|BITS8,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+24080, 54},
    /*   5 : SHR rm16,reg_cl [m-:       o16 d3 /5                         ] FL,8086 */
        /* 320 001(d3) 205 : FL,8086 */
        {I_SHR, 2, {RM_GPR|BITS16,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11828, 54},
    /*   6 : SHR rm32,reg_cl [m-:       o32 d3 /5                         ] FL,386 */
        /* 321 001(d3) 205 : FL,386 */
        {I_SHR, 2, {RM_GPR|BITS32,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11858, 55},
    /*   7 : SHR rm64,reg_cl [m-:       o64 d3 /5                         ] LONG,FL,PROT,X86_64 */
        /* 324 001(d3) 205 : LONG,FL,PROT,X86_64 */
        {I_SHR, 2, {RM_GPR|BITS64,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11888, 56},
    /*   8 : SHR rm8,reg_cx [m-:       o8 d2 /5                          ] ND,FL,8086 */
        /* 001(d2) 205 : FL,8086 */
        {I_SHR, 2, {RM_GPR|BITS8,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+24080, 54},
    /*   9 : SHR rm16,reg_cx [m-:       o16 d3 /5                         ] ND,FL,8086 */
        /* 320 001(d3) 205 : FL,8086 */
        {I_SHR, 2, {RM_GPR|BITS16,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11828, 54},
    /*  10 : SHR rm32,reg_cx [m-:       o32 d3 /5                         ] ND,FL,386 */
        /* 321 001(d3) 205 : FL,386 */
        {I_SHR, 2, {RM_GPR|BITS32,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11858, 55},
    /*  11 : SHR rm64,reg_cx [m-:       o64 d3 /5                         ] ND,LONG,FL,PROT,X86_64 */
        /* 324 001(d3) 205 : LONG,FL,PROT,X86_64 */
        {I_SHR, 2, {RM_GPR|BITS64,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11888, 56},
    /*  12 : SHR rm8,reg_ecx [m-:       o8 d2 /5                          ] ND,FL,8086 */
        /* 001(d2) 205 : FL,8086 */
        {I_SHR, 2, {RM_GPR|BITS8,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+24080, 54},
    /*  13 : SHR rm16,reg_ecx [m-:       o16 d3 /5                         ] ND,FL,8086 */
        /* 320 001(d3) 205 : FL,8086 */
        {I_SHR, 2, {RM_GPR|BITS16,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11828, 54},
    /*  14 : SHR rm32,reg_ecx [m-:       o32 d3 /5                         ] ND,FL,386 */
        /* 321 001(d3) 205 : FL,386 */
        {I_SHR, 2, {RM_GPR|BITS32,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11858, 55},
    /*  15 : SHR rm64,reg_ecx [m-:       o64 d3 /5                         ] ND,LONG,FL,PROT,X86_64 */
        /* 324 001(d3) 205 : LONG,FL,PROT,X86_64 */
        {I_SHR, 2, {RM_GPR|BITS64,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11888, 56},
    /*  16 : SHR rm8,reg_rcx [m-:       o8 d2 /5                          ] ND,FL,8086 */
        /* 001(d2) 205 : FL,8086 */
        {I_SHR, 2, {RM_GPR|BITS8,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+24080, 54},
    /*  17 : SHR rm16,reg_rcx [m-:       o16 d3 /5                         ] ND,FL,8086 */
        /* 320 001(d3) 205 : FL,8086 */
        {I_SHR, 2, {RM_GPR|BITS16,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11828, 54},
    /*  18 : SHR rm32,reg_rcx [m-:       o32 d3 /5                         ] ND,FL,386 */
        /* 321 001(d3) 205 : FL,386 */
        {I_SHR, 2, {RM_GPR|BITS32,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11858, 55},
    /*  19 : SHR rm64,reg_rcx [m-:       o64 d3 /5                         ] ND,LONG,FL,PROT,X86_64 */
        /* 324 001(d3) 205 : LONG,FL,PROT,X86_64 */
        {I_SHR, 2, {RM_GPR|BITS64,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11888, 56},
    /*  20 : SHR rm8,imm8 [mi:       o8 c0 /5 ib,u                     ] FL,186 */
        /* 001(c0) 205 025 : FL,186 */
        {I_SHR, 2, {RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+11918, 57},
    /*  21 : SHR rm16,imm8 [mi:       o16 c1 /5 ib,u                    ] FL,186 */
        /* 320 001(c1) 205 025 : FL,186 */
        {I_SHR, 2, {RM_GPR|BITS16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1932, 57},
    /*  22 : SHR rm32,imm8 [mi:       o32 c1 /5 ib,u                    ] FL,386 */
        /* 321 001(c1) 205 025 : FL,386 */
        {I_SHR, 2, {RM_GPR|BITS32,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1965, 55},
    /*  23 : SHR rm64,imm8 [mi:       o64 c1 /5 ib,u                    ] LONG,FL,PROT,X86_64 */
        /* 324 001(c1) 205 025 : LONG,FL,PROT,X86_64 */
        {I_SHR, 2, {RM_GPR|BITS64,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1998, 56},
    /*  24 : SHR reg32,rm32*,reg8 [rmv:      vex.lz.f2.0f38.w0 f7 /r           ] ND,SM0,SM1,OPT,NF,NF_R,BMI2,FUTURE */
        /* 262(002 003) 001(f7) 110 : SM0,SM1,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SHR, 3, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,REG_GPR|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55115, 60},
    /*  25 : SHR reg32,reg8 [r+mv:      vex.lz.f2.0f38.w0 f7 /r           ] ND,SM0,OPT,NF,NF_R,BMI2,FUTURE */
        /* 261(002 003) 001(f7) 100 : SM0,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SHR, 2, {REG_GPR|BITS32|RN_L16,REG_GPR|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55122, 61},
    /*  26 : SHR reg32,rm32*,reg16 [rmv:      vex.lz.f2.0f38.w0 f7 /r           ] ND,SM0,SM1,OPT,NF,NF_R,BMI2,FUTURE */
        /* 262(002 003) 001(f7) 110 : SM0,SM1,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SHR, 3, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,REG_GPR|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55115, 60},
    /*  27 : SHR reg32,reg16 [r+mv:      vex.lz.f2.0f38.w0 f7 /r           ] ND,SM0,OPT,NF,NF_R,BMI2,FUTURE */
        /* 261(002 003) 001(f7) 100 : SM0,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SHR, 2, {REG_GPR|BITS32|RN_L16,REG_GPR|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55122, 61},
    /*  28 : SHR reg32,rm32*,reg32 [rmv:      vex.lz.f2.0f38.w0 f7 /r           ] ND,SM0,SM1,OPT,NF,NF_R,BMI2,FUTURE */
        /* 262(002 003) 001(f7) 110 : SM0,SM1,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SHR, 3, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55115, 60},
    /*  29 : SHR reg32,reg32 [r+mv:      vex.lz.f2.0f38.w0 f7 /r           ] ND,SM0,OPT,NF,NF_R,BMI2,FUTURE */
        /* 261(002 003) 001(f7) 100 : SM0,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SHR, 2, {REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55122, 61},
    /*  30 : SHR reg32,rm32*,reg64 [rmv:      vex.lz.f2.0f38.w0 f7 /r           ] ND,SM0,SM1,OPT,NF,NF_R,BMI2,FUTURE */
        /* 262(002 003) 001(f7) 110 : SM0,SM1,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SHR, 3, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55115, 60},
    /*  31 : SHR reg32,reg64 [r+mv:      vex.lz.f2.0f38.w0 f7 /r           ] ND,SM0,OPT,NF,NF_R,BMI2,FUTURE */
        /* 261(002 003) 001(f7) 100 : SM0,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SHR, 2, {REG_GPR|BITS32|RN_L16,REG_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55122, 61},
    /*  32 : SHR reg64,rm64*,reg8 [rmv:      vex.lz.f2.0f38.w1 f7 /r           ] ND,SM0,SM1,OPT,NF,NF_R,BMI2,FUTURE */
        /* 262(002 203) 001(f7) 110 : SM0,SM1,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SHR, 3, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,REG_GPR|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55157, 60},
    /*  33 : SHR reg64,reg8 [r+mv:      vex.lz.f2.0f38.w1 f7 /r           ] ND,SM0,OPT,NF,NF_R,BMI2,FUTURE */
        /* 261(002 203) 001(f7) 100 : SM0,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SHR, 2, {REG_GPR|BITS64|RN_L16,REG_GPR|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55164, 61},
    /*  34 : SHR reg64,rm64*,reg16 [rmv:      vex.lz.f2.0f38.w1 f7 /r           ] ND,SM0,SM1,OPT,NF,NF_R,BMI2,FUTURE */
        /* 262(002 203) 001(f7) 110 : SM0,SM1,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SHR, 3, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,REG_GPR|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55157, 60},
    /*  35 : SHR reg64,reg16 [r+mv:      vex.lz.f2.0f38.w1 f7 /r           ] ND,SM0,OPT,NF,NF_R,BMI2,FUTURE */
        /* 261(002 203) 001(f7) 100 : SM0,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SHR, 2, {REG_GPR|BITS64|RN_L16,REG_GPR|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55164, 61},
    /*  36 : SHR reg64,rm64*,reg32 [rmv:      vex.lz.f2.0f38.w1 f7 /r           ] ND,SM0,SM1,OPT,NF,NF_R,BMI2,FUTURE */
        /* 262(002 203) 001(f7) 110 : SM0,SM1,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SHR, 3, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55157, 60},
    /*  37 : SHR reg64,reg32 [r+mv:      vex.lz.f2.0f38.w1 f7 /r           ] ND,SM0,OPT,NF,NF_R,BMI2,FUTURE */
        /* 261(002 203) 001(f7) 100 : SM0,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SHR, 2, {REG_GPR|BITS64|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55164, 61},
    /*  38 : SHR reg64,rm64*,reg64 [rmv:      vex.lz.f2.0f38.w1 f7 /r           ] ND,SM0,SM1,OPT,NF,NF_R,BMI2,FUTURE */
        /* 262(002 203) 001(f7) 110 : SM0,SM1,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SHR, 3, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55157, 60},
    /*  39 : SHR reg64,reg64 [r+mv:      vex.lz.f2.0f38.w1 f7 /r           ] ND,SM0,OPT,NF,NF_R,BMI2,FUTURE */
        /* 261(002 203) 001(f7) 100 : SM0,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SHR, 2, {REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55164, 61},
    /*  40 : SHR reg8?,rm8,unity [vm-:      evex.nd1.nf.l0.m4.o8 d0 /5        ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d0) 215 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 3, {REG_GPR|BITS8,RM_GPR|BITS8,UNITY|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+24030, 35},
    /*  41 : SHR rm8,unity [m-:      evex.nd0.nf.l0.m4.o8 d0 /5        ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(d0) 205 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {RM_GPR|BITS8,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+24039, 62},
    /*  42 : SHR reg8?,unity [v+m-:      evex.nd1.nf.l0.m4.o8 d0 /5        ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d0) 205 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {REG_GPR|BITS8,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+24048, 63},
    /*  43 : SHR reg16?,rm16,unity [vm-:      evex.nd1.nf.l0.m4.o16 d1 /5       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d1) 215 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 3, {REG_GPR|BITS16,RM_GPR|BITS16,UNITY|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+11713, 38},
    /*  44 : SHR rm16,unity [m-:      evex.nd0.nf.l0.m4.o16 d1 /5       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(d1) 205 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {RM_GPR|BITS16,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11723, 64},
    /*  45 : SHR reg16?,unity [v+m-:      evex.nd1.nf.l0.m4.o16 d1 /5       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d1) 205 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {REG_GPR|BITS16,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11733, 65},
    /*  46 : SHR reg32?,rm32,unity [vm-:      evex.nd1.nf.l0.m4.o32 d1 /5       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d1) 215 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,UNITY|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+11743, 41},
    /*  47 : SHR rm32,unity [m-:      evex.nd0.nf.l0.m4.o32 d1 /5       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(d1) 205 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {RM_GPR|BITS32,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11753, 66},
    /*  48 : SHR reg32?,unity [v+m-:      evex.nd1.nf.l0.m4.o32 d1 /5       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d1) 205 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {REG_GPR|BITS32,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11763, 67},
    /*  49 : SHR reg64?,rm64,unity [vm-:      evex.nd1.nf.l0.m4.o64 d1 /5       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d1) 215 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,UNITY|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+11773, 41},
    /*  50 : SHR rm64,unity [m-:      evex.nd0.nf.l0.m4.o64 d1 /5       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(d1) 205 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {RM_GPR|BITS64,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11783, 66},
    /*  51 : SHR reg64?,unity [v+m-:      evex.nd1.nf.l0.m4.o64 d1 /5       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d1) 205 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {REG_GPR|BITS64,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11793, 67},
    /*  52 : SHR reg8?,rm8,reg_cl [vm-:      evex.nd1.nf.l0.m4.o8 d2 /5        ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 215 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 3, {REG_GPR|BITS8,RM_GPR|BITS8,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+24057, 35},
    /*  53 : SHR rm8,reg_cl [m-:      evex.nd0.nf.l0.m4.o8 d2 /5        ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(d2) 205 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {RM_GPR|BITS8,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+24066, 62},
    /*  54 : SHR reg8?,reg_cl [v+m-:      evex.nd1.nf.l0.m4.o8 d2 /5        ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 205 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {REG_GPR|BITS8,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+24075, 63},
    /*  55 : SHR reg16?,rm16,reg_cl [vm-:      evex.nd1.nf.l0.m4.o16 d3 /5       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 215 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 3, {REG_GPR|BITS16,RM_GPR|BITS16,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+11803, 38},
    /*  56 : SHR rm16,reg_cl [m-:      evex.nd0.nf.l0.m4.o16 d3 /5       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(d3) 205 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {RM_GPR|BITS16,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11813, 64},
    /*  57 : SHR reg16?,reg_cl [v+m-:      evex.nd1.nf.l0.m4.o16 d3 /5       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 205 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {REG_GPR|BITS16,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11823, 65},
    /*  58 : SHR reg32?,rm32,reg_cl [vm-:      evex.nd1.nf.l0.m4.o32 d3 /5       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 215 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+11833, 41},
    /*  59 : SHR rm32,reg_cl [m-:      evex.nd0.nf.l0.m4.o32 d3 /5       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(d3) 205 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {RM_GPR|BITS32,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11843, 66},
    /*  60 : SHR reg32?,reg_cl [v+m-:      evex.nd1.nf.l0.m4.o32 d3 /5       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 205 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {REG_GPR|BITS32,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11853, 67},
    /*  61 : SHR reg64?,rm64,reg_cl [vm-:      evex.nd1.nf.l0.m4.o64 d3 /5       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 215 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+11863, 41},
    /*  62 : SHR rm64,reg_cl [m-:      evex.nd0.nf.l0.m4.o64 d3 /5       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(d3) 205 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {RM_GPR|BITS64,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11873, 66},
    /*  63 : SHR reg64?,reg_cl [v+m-:      evex.nd1.nf.l0.m4.o64 d3 /5       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 205 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {REG_GPR|BITS64,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11883, 67},
    /*  64 : SHR reg8?,rm8,reg_cx [vm-:      evex.nd1.nf.l0.m4.o8 d2 /5        ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 215 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 3, {REG_GPR|BITS8,RM_GPR|BITS8,REG_CX,0,0}, NO_DECORATOR, nasm_bytecodes+24057, 35},
    /*  65 : SHR rm8,reg_cx [m-:      evex.nd0.nf.l0.m4.o8 d2 /5        ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(d2) 205 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {RM_GPR|BITS8,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+24066, 62},
    /*  66 : SHR reg8?,reg_cx [v+m-:      evex.nd1.nf.l0.m4.o8 d2 /5        ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 205 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {REG_GPR|BITS8,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+24075, 63},
    /*  67 : SHR reg16?,rm16,reg_cx [vm-:      evex.nd1.nf.l0.m4.o16 d3 /5       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 215 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 3, {REG_GPR|BITS16,RM_GPR|BITS16,REG_CX,0,0}, NO_DECORATOR, nasm_bytecodes+11803, 38},
    /*  68 : SHR rm16,reg_cx [m-:      evex.nd0.nf.l0.m4.o16 d3 /5       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(d3) 205 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {RM_GPR|BITS16,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11813, 64},
    /*  69 : SHR reg16?,reg_cx [v+m-:      evex.nd1.nf.l0.m4.o16 d3 /5       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 205 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {REG_GPR|BITS16,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11823, 65},
    /*  70 : SHR reg32?,rm32,reg_cx [vm-:      evex.nd1.nf.l0.m4.o32 d3 /5       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 215 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_CX,0,0}, NO_DECORATOR, nasm_bytecodes+11833, 41},
    /*  71 : SHR rm32,reg_cx [m-:      evex.nd0.nf.l0.m4.o32 d3 /5       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(d3) 205 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {RM_GPR|BITS32,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11843, 66},
    /*  72 : SHR reg32?,reg_cx [v+m-:      evex.nd1.nf.l0.m4.o32 d3 /5       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 205 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {REG_GPR|BITS32,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11853, 67},
    /*  73 : SHR reg64?,rm64,reg_cx [vm-:      evex.nd1.nf.l0.m4.o64 d3 /5       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 215 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_CX,0,0}, NO_DECORATOR, nasm_bytecodes+11863, 41},
    /*  74 : SHR rm64,reg_cx [m-:      evex.nd0.nf.l0.m4.o64 d3 /5       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(d3) 205 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {RM_GPR|BITS64,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11873, 66},
    /*  75 : SHR reg64?,reg_cx [v+m-:      evex.nd1.nf.l0.m4.o64 d3 /5       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 205 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {REG_GPR|BITS64,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11883, 67},
    /*  76 : SHR reg8?,rm8,reg_ecx [vm-:      evex.nd1.nf.l0.m4.o8 d2 /5        ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 215 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 3, {REG_GPR|BITS8,RM_GPR|BITS8,REG_ECX,0,0}, NO_DECORATOR, nasm_bytecodes+24057, 35},
    /*  77 : SHR rm8,reg_ecx [m-:      evex.nd0.nf.l0.m4.o8 d2 /5        ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(d2) 205 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {RM_GPR|BITS8,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+24066, 62},
    /*  78 : SHR reg8?,reg_ecx [v+m-:      evex.nd1.nf.l0.m4.o8 d2 /5        ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 205 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {REG_GPR|BITS8,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+24075, 63},
    /*  79 : SHR reg16?,rm16,reg_ecx [vm-:      evex.nd1.nf.l0.m4.o16 d3 /5       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 215 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 3, {REG_GPR|BITS16,RM_GPR|BITS16,REG_ECX,0,0}, NO_DECORATOR, nasm_bytecodes+11803, 38},
    /*  80 : SHR rm16,reg_ecx [m-:      evex.nd0.nf.l0.m4.o16 d3 /5       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(d3) 205 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {RM_GPR|BITS16,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11813, 64},
    /*  81 : SHR reg16?,reg_ecx [v+m-:      evex.nd1.nf.l0.m4.o16 d3 /5       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 205 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {REG_GPR|BITS16,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11823, 65},
    /*  82 : SHR reg32?,rm32,reg_ecx [vm-:      evex.nd1.nf.l0.m4.o32 d3 /5       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 215 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_ECX,0,0}, NO_DECORATOR, nasm_bytecodes+11833, 41},
    /*  83 : SHR rm32,reg_ecx [m-:      evex.nd0.nf.l0.m4.o32 d3 /5       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(d3) 205 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {RM_GPR|BITS32,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11843, 66},
    /*  84 : SHR reg32?,reg_ecx [v+m-:      evex.nd1.nf.l0.m4.o32 d3 /5       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 205 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {REG_GPR|BITS32,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11853, 67},
    /*  85 : SHR reg64?,rm64,reg_ecx [vm-:      evex.nd1.nf.l0.m4.o64 d3 /5       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 215 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_ECX,0,0}, NO_DECORATOR, nasm_bytecodes+11863, 41},
    /*  86 : SHR rm64,reg_ecx [m-:      evex.nd0.nf.l0.m4.o64 d3 /5       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(d3) 205 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {RM_GPR|BITS64,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11873, 66},
    /*  87 : SHR reg64?,reg_ecx [v+m-:      evex.nd1.nf.l0.m4.o64 d3 /5       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 205 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {REG_GPR|BITS64,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11883, 67},
    /*  88 : SHR reg8?,rm8,reg_rcx [vm-:      evex.nd1.nf.l0.m4.o8 d2 /5        ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 215 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 3, {REG_GPR|BITS8,RM_GPR|BITS8,REG_RCX,0,0}, NO_DECORATOR, nasm_bytecodes+24057, 35},
    /*  89 : SHR rm8,reg_rcx [m-:      evex.nd0.nf.l0.m4.o8 d2 /5        ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(d2) 205 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {RM_GPR|BITS8,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+24066, 62},
    /*  90 : SHR reg8?,reg_rcx [v+m-:      evex.nd1.nf.l0.m4.o8 d2 /5        ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 205 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {REG_GPR|BITS8,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+24075, 63},
    /*  91 : SHR reg16?,rm16,reg_rcx [vm-:      evex.nd1.nf.l0.m4.o16 d3 /5       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 215 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 3, {REG_GPR|BITS16,RM_GPR|BITS16,REG_RCX,0,0}, NO_DECORATOR, nasm_bytecodes+11803, 38},
    /*  92 : SHR rm16,reg_rcx [m-:      evex.nd0.nf.l0.m4.o16 d3 /5       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(d3) 205 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {RM_GPR|BITS16,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11813, 64},
    /*  93 : SHR reg16?,reg_rcx [v+m-:      evex.nd1.nf.l0.m4.o16 d3 /5       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 205 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {REG_GPR|BITS16,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11823, 65},
    /*  94 : SHR reg32?,rm32,reg_rcx [vm-:      evex.nd1.nf.l0.m4.o32 d3 /5       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 215 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_RCX,0,0}, NO_DECORATOR, nasm_bytecodes+11833, 41},
    /*  95 : SHR rm32,reg_rcx [m-:      evex.nd0.nf.l0.m4.o32 d3 /5       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(d3) 205 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {RM_GPR|BITS32,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11843, 66},
    /*  96 : SHR reg32?,reg_rcx [v+m-:      evex.nd1.nf.l0.m4.o32 d3 /5       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 205 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {REG_GPR|BITS32,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11853, 67},
    /*  97 : SHR reg64?,rm64,reg_rcx [vm-:      evex.nd1.nf.l0.m4.o64 d3 /5       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 215 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_RCX,0,0}, NO_DECORATOR, nasm_bytecodes+11863, 41},
    /*  98 : SHR rm64,reg_rcx [m-:      evex.nd0.nf.l0.m4.o64 d3 /5       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(d3) 205 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {RM_GPR|BITS64,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11873, 66},
    /*  99 : SHR reg64?,reg_rcx [v+m-:      evex.nd1.nf.l0.m4.o64 d3 /5       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 205 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {REG_GPR|BITS64,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+11883, 67},
    /* 100 : SHR reg8?,rm8,imm8 [vmi:      evex.nd1.nf.l0.m4.o8 c0 /5 ib,u   ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(c0) 215 026 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 3, {REG_GPR|BITS8,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+11893, 35},
    /* 101 : SHR rm8,imm8 [mi:      evex.nd0.nf.l0.m4.o8 c0 /5 ib,u   ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(c0) 205 025 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+11903, 62},
    /* 102 : SHR reg8?,imm8 [v+mi:      evex.nd1.nf.l0.m4.o8 c0 /5 ib,u   ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(c0) 205 025 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {REG_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+11913, 63},
    /* 103 : SHR reg16?,rm16,imm8 [vmi:      evex.nd1.nf.l0.m4.o16 c1 /5 ib,u  ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(c1) 215 026 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 3, {REG_GPR|BITS16,RM_GPR|BITS16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+1905, 38},
    /* 104 : SHR rm16,imm8 [mi:      evex.nd0.nf.l0.m4.o16 c1 /5 ib,u  ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(c1) 205 025 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {RM_GPR|BITS16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1916, 64},
    /* 105 : SHR reg16?,imm8 [v+mi:      evex.nd1.nf.l0.m4.o16 c1 /5 ib,u  ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(c1) 205 025 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {REG_GPR|BITS16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1927, 65},
    /* 106 : SHR reg32?,rm32,imm8 [vmi:      evex.nd1.nf.l0.m4.o32 c1 /5 ib,u  ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(c1) 215 026 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+1938, 41},
    /* 107 : SHR rm32,imm8 [mi:      evex.nd0.nf.l0.m4.o32 c1 /5 ib,u  ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(c1) 205 025 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {RM_GPR|BITS32,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1949, 66},
    /* 108 : SHR reg32?,imm8 [v+mi:      evex.nd1.nf.l0.m4.o32 c1 /5 ib,u  ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(c1) 205 025 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {REG_GPR|BITS32,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1960, 67},
    /* 109 : SHR reg64?,rm64,imm8 [vmi:      evex.nd1.nf.l0.m4.o64 c1 /5 ib,u  ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(c1) 215 026 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+1971, 41},
    /* 110 : SHR rm64,imm8 [mi:      evex.nd0.nf.l0.m4.o64 c1 /5 ib,u  ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(c1) 205 025 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {RM_GPR|BITS64,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1982, 66},
    /* 111 : SHR reg64?,imm8 [v+mi:      evex.nd1.nf.l0.m4.o64 c1 /5 ib,u  ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(c1) 205 025 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SHR, 2, {REG_GPR|BITS64,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+1993, 67},
    /* 112 : SHR reg32,rm32*,reg8 [rmv:      evex.lz.f2.0f38.w0 f7 /r          ] ND,SM0,SM1,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 7f 08) 300 001(f7) 110 : SM0,SM1,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24174, 70},
    /* 113 : SHR reg32,reg8 [r+mv:      evex.lz.f2.0f38.w0 f7 /r          ] ND,SM0,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 7f 08) 300 001(f7) 100 : SM0,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHR, 2, {REG_GPR|BITS32,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+24183, 71},
    /* 114 : SHR reg32,rm32*,reg16 [rmv:      evex.lz.f2.0f38.w0 f7 /r          ] ND,SM0,SM1,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 7f 08) 300 001(f7) 110 : SM0,SM1,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+24174, 70},
    /* 115 : SHR reg32,reg16 [r+mv:      evex.lz.f2.0f38.w0 f7 /r          ] ND,SM0,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 7f 08) 300 001(f7) 100 : SM0,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHR, 2, {REG_GPR|BITS32,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+24183, 71},
    /* 116 : SHR reg32,rm32*,reg32 [rmv:      evex.lz.f2.0f38.w0 f7 /r          ] ND,SM0,SM1,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 7f 08) 300 001(f7) 110 : SM0,SM1,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+24174, 70},
    /* 117 : SHR reg32,reg32 [r+mv:      evex.lz.f2.0f38.w0 f7 /r          ] ND,SM0,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 7f 08) 300 001(f7) 100 : SM0,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHR, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+24183, 71},
    /* 118 : SHR reg32,rm32*,reg64 [rmv:      evex.lz.f2.0f38.w0 f7 /r          ] ND,SM0,SM1,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 7f 08) 300 001(f7) 110 : SM0,SM1,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+24174, 70},
    /* 119 : SHR reg32,reg64 [r+mv:      evex.lz.f2.0f38.w0 f7 /r          ] ND,SM0,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 7f 08) 300 001(f7) 100 : SM0,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHR, 2, {REG_GPR|BITS32,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+24183, 71},
    /* 120 : SHR reg64,rm64*,reg8 [rmv:      evex.lz.f2.0f38.w1 f7 /r          ] ND,SM0,SM1,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 ff 08) 300 001(f7) 110 : SM0,SM1,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24228, 70},
    /* 121 : SHR reg64,reg8 [r+mv:      evex.lz.f2.0f38.w1 f7 /r          ] ND,SM0,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 ff 08) 300 001(f7) 100 : SM0,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHR, 2, {REG_GPR|BITS64,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+24237, 71},
    /* 122 : SHR reg64,rm64*,reg16 [rmv:      evex.lz.f2.0f38.w1 f7 /r          ] ND,SM0,SM1,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 ff 08) 300 001(f7) 110 : SM0,SM1,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+24228, 70},
    /* 123 : SHR reg64,reg16 [r+mv:      evex.lz.f2.0f38.w1 f7 /r          ] ND,SM0,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 ff 08) 300 001(f7) 100 : SM0,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHR, 2, {REG_GPR|BITS64,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+24237, 71},
    /* 124 : SHR reg64,rm64*,reg32 [rmv:      evex.lz.f2.0f38.w1 f7 /r          ] ND,SM0,SM1,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 ff 08) 300 001(f7) 110 : SM0,SM1,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+24228, 70},
    /* 125 : SHR reg64,reg32 [r+mv:      evex.lz.f2.0f38.w1 f7 /r          ] ND,SM0,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 ff 08) 300 001(f7) 100 : SM0,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHR, 2, {REG_GPR|BITS64,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+24237, 71},
    /* 126 : SHR reg64,rm64*,reg64 [rmv:      evex.lz.f2.0f38.w1 f7 /r          ] ND,SM0,SM1,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 ff 08) 300 001(f7) 110 : SM0,SM1,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+24228, 70},
    /* 127 : SHR reg64,reg64 [r+mv:      evex.lz.f2.0f38.w1 f7 /r          ] ND,SM0,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 ff 08) 300 001(f7) 100 : SM0,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHR, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+24237, 71},
    /* 128 : SHR kreg8,kreg8,imm8 [rmi:      vex.l0.66.0f3a.w0 30 /r ib       ] ND,SM0-1,ZU,FL,AVX512DQ,FUTURE */
        /* 270(003 001) 001(30) 110 022 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512DQ,FUTURE */
        {I_SHR, 3, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54605, 518},
    /* 129 : SHR kreg8,kreg8,imm8 [rmi:      evex.l0.66.0f3a.w0 30 /r ib       ] ND,SM0-1,ZU,FL,AVX512DQ,FUTURE,APX */
        /* 250(f3 7d 08) 300 001(30) 110 022 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_SHR, 3, {OPMASKREG|BITS8,OPMASKREG|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18093, 519},
    /* 130 : SHR kreg16,kreg16,imm8 [rmi:      vex.l0.66.0f3a.w1 30 /r ib       ] ND,SM0-1,ZU,FL,AVX512F,FUTURE */
        /* 270(003 201) 001(30) 110 022 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512F,FUTURE */
        {I_SHR, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54613, 530},
    /* 131 : SHR kreg16,kreg16,imm8 [rmi:      evex.l0.66.0f3a.w1 30 /r ib       ] ND,SM0-1,ZU,FL,AVX512F,FUTURE,APX */
        /* 250(f3 fd 08) 300 001(30) 110 022 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_SHR, 3, {OPMASKREG|BITS16,OPMASKREG|BITS16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18103, 531},
    /* 132 : SHR kreg32,kreg32,imm8 [rmi:      vex.l0.66.0f3a.w0 31 /r ib       ] ND,SM0-1,ZU,FL,AVX512BW,FUTURE */
        /* 270(003 001) 001(31) 110 022 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_SHR, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54621, 522},
    /* 133 : SHR kreg32,kreg32,imm8 [rmi:      evex.l0.66.0f3a.w0 31 /r ib       ] ND,SM0-1,ZU,FL,AVX512BW,FUTURE,APX */
        /* 250(f3 7d 08) 300 001(31) 110 022 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_SHR, 3, {OPMASKREG|BITS32,OPMASKREG|BITS32,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18113, 523},
    /* 134 : SHR kreg64,kreg64,imm8 [rmi:      vex.l0.66.0f3a.w1 31 /r ib       ] ND,SM0-1,ZU,FL,AVX512BW,FUTURE */
        /* 270(003 201) 001(31) 110 022 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_SHR, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54629, 522},
    /* 135 : SHR kreg64,kreg64,imm8 [rmi:      evex.l0.66.0f3a.w1 31 /r ib       ] ND,SM0-1,ZU,FL,AVX512BW,FUTURE,APX */
        /* 250(f3 fd 08) 300 001(31) 110 022 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_SHR, 3, {OPMASKREG|BITS64,OPMASKREG|BITS64,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18123, 523},
};

static const struct itemplate instrux_SAR[128] = {
    /*   0 : SAR rm8,unity [m-:       o8 d0 /7                          ] FL,8086 */
        /* 001(d0) 207 : FL,8086 */
        {I_SAR, 2, {RM_GPR|BITS8,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+24107, 54},
    /*   1 : SAR rm16,unity [m-:       o16 d1 /7                         ] FL,8086 */
        /* 320 001(d1) 207 : FL,8086 */
        {I_SAR, 2, {RM_GPR|BITS16,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11948, 54},
    /*   2 : SAR rm32,unity [m-:       o32 d1 /7                         ] FL,386 */
        /* 321 001(d1) 207 : FL,386 */
        {I_SAR, 2, {RM_GPR|BITS32,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11978, 55},
    /*   3 : SAR rm64,unity [m-:       o64 d1 /7                         ] LONG,FL,PROT,X86_64 */
        /* 324 001(d1) 207 : LONG,FL,PROT,X86_64 */
        {I_SAR, 2, {RM_GPR|BITS64,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+12008, 56},
    /*   4 : SAR rm8,reg_cl [m-:       o8 d2 /7                          ] FL,8086 */
        /* 001(d2) 207 : FL,8086 */
        {I_SAR, 2, {RM_GPR|BITS8,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+24134, 54},
    /*   5 : SAR rm16,reg_cl [m-:       o16 d3 /7                         ] FL,8086 */
        /* 320 001(d3) 207 : FL,8086 */
        {I_SAR, 2, {RM_GPR|BITS16,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+12038, 54},
    /*   6 : SAR rm32,reg_cl [m-:       o32 d3 /7                         ] FL,386 */
        /* 321 001(d3) 207 : FL,386 */
        {I_SAR, 2, {RM_GPR|BITS32,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+12068, 55},
    /*   7 : SAR rm64,reg_cl [m-:       o64 d3 /7                         ] LONG,FL,PROT,X86_64 */
        /* 324 001(d3) 207 : LONG,FL,PROT,X86_64 */
        {I_SAR, 2, {RM_GPR|BITS64,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+12098, 56},
    /*   8 : SAR rm8,reg_cx [m-:       o8 d2 /7                          ] ND,FL,8086 */
        /* 001(d2) 207 : FL,8086 */
        {I_SAR, 2, {RM_GPR|BITS8,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+24134, 54},
    /*   9 : SAR rm16,reg_cx [m-:       o16 d3 /7                         ] ND,FL,8086 */
        /* 320 001(d3) 207 : FL,8086 */
        {I_SAR, 2, {RM_GPR|BITS16,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12038, 54},
    /*  10 : SAR rm32,reg_cx [m-:       o32 d3 /7                         ] ND,FL,386 */
        /* 321 001(d3) 207 : FL,386 */
        {I_SAR, 2, {RM_GPR|BITS32,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12068, 55},
    /*  11 : SAR rm64,reg_cx [m-:       o64 d3 /7                         ] ND,LONG,FL,PROT,X86_64 */
        /* 324 001(d3) 207 : LONG,FL,PROT,X86_64 */
        {I_SAR, 2, {RM_GPR|BITS64,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12098, 56},
    /*  12 : SAR rm8,reg_ecx [m-:       o8 d2 /7                          ] ND,FL,8086 */
        /* 001(d2) 207 : FL,8086 */
        {I_SAR, 2, {RM_GPR|BITS8,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+24134, 54},
    /*  13 : SAR rm16,reg_ecx [m-:       o16 d3 /7                         ] ND,FL,8086 */
        /* 320 001(d3) 207 : FL,8086 */
        {I_SAR, 2, {RM_GPR|BITS16,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12038, 54},
    /*  14 : SAR rm32,reg_ecx [m-:       o32 d3 /7                         ] ND,FL,386 */
        /* 321 001(d3) 207 : FL,386 */
        {I_SAR, 2, {RM_GPR|BITS32,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12068, 55},
    /*  15 : SAR rm64,reg_ecx [m-:       o64 d3 /7                         ] ND,LONG,FL,PROT,X86_64 */
        /* 324 001(d3) 207 : LONG,FL,PROT,X86_64 */
        {I_SAR, 2, {RM_GPR|BITS64,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12098, 56},
    /*  16 : SAR rm8,reg_rcx [m-:       o8 d2 /7                          ] ND,FL,8086 */
        /* 001(d2) 207 : FL,8086 */
        {I_SAR, 2, {RM_GPR|BITS8,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+24134, 54},
    /*  17 : SAR rm16,reg_rcx [m-:       o16 d3 /7                         ] ND,FL,8086 */
        /* 320 001(d3) 207 : FL,8086 */
        {I_SAR, 2, {RM_GPR|BITS16,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12038, 54},
    /*  18 : SAR rm32,reg_rcx [m-:       o32 d3 /7                         ] ND,FL,386 */
        /* 321 001(d3) 207 : FL,386 */
        {I_SAR, 2, {RM_GPR|BITS32,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12068, 55},
    /*  19 : SAR rm64,reg_rcx [m-:       o64 d3 /7                         ] ND,LONG,FL,PROT,X86_64 */
        /* 324 001(d3) 207 : LONG,FL,PROT,X86_64 */
        {I_SAR, 2, {RM_GPR|BITS64,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12098, 56},
    /*  20 : SAR rm8,imm8 [mi:       o8 c0 /7 ib,u                     ] FL,186 */
        /* 001(c0) 207 025 : FL,186 */
        {I_SAR, 2, {RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+12128, 57},
    /*  21 : SAR rm16,imm8 [mi:       o16 c1 /7 ib,u                    ] FL,186 */
        /* 320 001(c1) 207 025 : FL,186 */
        {I_SAR, 2, {RM_GPR|BITS16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+2031, 57},
    /*  22 : SAR rm32,imm8 [mi:       o32 c1 /7 ib,u                    ] FL,386 */
        /* 321 001(c1) 207 025 : FL,386 */
        {I_SAR, 2, {RM_GPR|BITS32,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+2064, 55},
    /*  23 : SAR rm64,imm8 [mi:       o64 c1 /7 ib,u                    ] LONG,FL,PROT,X86_64 */
        /* 324 001(c1) 207 025 : LONG,FL,PROT,X86_64 */
        {I_SAR, 2, {RM_GPR|BITS64,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+2097, 56},
    /*  24 : SAR reg32,rm32*,reg8 [rmv:      vex.lz.f3.0f38.w0 f7 /r           ] ND,SM0,SM1,OPT,NF,NF_R,BMI2,FUTURE */
        /* 262(002 002) 001(f7) 110 : SM0,SM1,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SAR, 3, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,REG_GPR|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55101, 60},
    /*  25 : SAR reg32,reg8 [r+mv:      vex.lz.f3.0f38.w0 f7 /r           ] ND,SM0,OPT,NF,NF_R,BMI2,FUTURE */
        /* 261(002 002) 001(f7) 100 : SM0,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SAR, 2, {REG_GPR|BITS32|RN_L16,REG_GPR|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55108, 61},
    /*  26 : SAR reg32,rm32*,reg16 [rmv:      vex.lz.f3.0f38.w0 f7 /r           ] ND,SM0,SM1,OPT,NF,NF_R,BMI2,FUTURE */
        /* 262(002 002) 001(f7) 110 : SM0,SM1,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SAR, 3, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,REG_GPR|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55101, 60},
    /*  27 : SAR reg32,reg16 [r+mv:      vex.lz.f3.0f38.w0 f7 /r           ] ND,SM0,OPT,NF,NF_R,BMI2,FUTURE */
        /* 261(002 002) 001(f7) 100 : SM0,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SAR, 2, {REG_GPR|BITS32|RN_L16,REG_GPR|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55108, 61},
    /*  28 : SAR reg32,rm32*,reg32 [rmv:      vex.lz.f3.0f38.w0 f7 /r           ] ND,SM0,SM1,OPT,NF,NF_R,BMI2,FUTURE */
        /* 262(002 002) 001(f7) 110 : SM0,SM1,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SAR, 3, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55101, 60},
    /*  29 : SAR reg32,reg32 [r+mv:      vex.lz.f3.0f38.w0 f7 /r           ] ND,SM0,OPT,NF,NF_R,BMI2,FUTURE */
        /* 261(002 002) 001(f7) 100 : SM0,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SAR, 2, {REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55108, 61},
    /*  30 : SAR reg32,rm32*,reg64 [rmv:      vex.lz.f3.0f38.w0 f7 /r           ] ND,SM0,SM1,OPT,NF,NF_R,BMI2,FUTURE */
        /* 262(002 002) 001(f7) 110 : SM0,SM1,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SAR, 3, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55101, 60},
    /*  31 : SAR reg32,reg64 [r+mv:      vex.lz.f3.0f38.w0 f7 /r           ] ND,SM0,OPT,NF,NF_R,BMI2,FUTURE */
        /* 261(002 002) 001(f7) 100 : SM0,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SAR, 2, {REG_GPR|BITS32|RN_L16,REG_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55108, 61},
    /*  32 : SAR reg64,rm64*,reg8 [rmv:      vex.lz.f3.0f38.w1 f7 /r           ] ND,SM0,SM1,OPT,NF,NF_R,BMI2,FUTURE */
        /* 262(002 202) 001(f7) 110 : SM0,SM1,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SAR, 3, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,REG_GPR|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55143, 60},
    /*  33 : SAR reg64,reg8 [r+mv:      vex.lz.f3.0f38.w1 f7 /r           ] ND,SM0,OPT,NF,NF_R,BMI2,FUTURE */
        /* 261(002 202) 001(f7) 100 : SM0,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SAR, 2, {REG_GPR|BITS64|RN_L16,REG_GPR|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55150, 61},
    /*  34 : SAR reg64,rm64*,reg16 [rmv:      vex.lz.f3.0f38.w1 f7 /r           ] ND,SM0,SM1,OPT,NF,NF_R,BMI2,FUTURE */
        /* 262(002 202) 001(f7) 110 : SM0,SM1,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SAR, 3, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,REG_GPR|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55143, 60},
    /*  35 : SAR reg64,reg16 [r+mv:      vex.lz.f3.0f38.w1 f7 /r           ] ND,SM0,OPT,NF,NF_R,BMI2,FUTURE */
        /* 261(002 202) 001(f7) 100 : SM0,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SAR, 2, {REG_GPR|BITS64|RN_L16,REG_GPR|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55150, 61},
    /*  36 : SAR reg64,rm64*,reg32 [rmv:      vex.lz.f3.0f38.w1 f7 /r           ] ND,SM0,SM1,OPT,NF,NF_R,BMI2,FUTURE */
        /* 262(002 202) 001(f7) 110 : SM0,SM1,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SAR, 3, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55143, 60},
    /*  37 : SAR reg64,reg32 [r+mv:      vex.lz.f3.0f38.w1 f7 /r           ] ND,SM0,OPT,NF,NF_R,BMI2,FUTURE */
        /* 261(002 202) 001(f7) 100 : SM0,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SAR, 2, {REG_GPR|BITS64|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55150, 61},
    /*  38 : SAR reg64,rm64*,reg64 [rmv:      vex.lz.f3.0f38.w1 f7 /r           ] ND,SM0,SM1,OPT,NF,NF_R,BMI2,FUTURE */
        /* 262(002 202) 001(f7) 110 : SM0,SM1,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SAR, 3, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55143, 60},
    /*  39 : SAR reg64,reg64 [r+mv:      vex.lz.f3.0f38.w1 f7 /r           ] ND,SM0,OPT,NF,NF_R,BMI2,FUTURE */
        /* 261(002 202) 001(f7) 100 : SM0,OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_SAR, 2, {REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55150, 61},
    /*  40 : SAR reg8?,rm8,unity [vm-:      evex.nd1.nf.l0.m4.o8 d0 /7        ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d0) 217 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 3, {REG_GPR|BITS8,RM_GPR|BITS8,UNITY|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+24084, 35},
    /*  41 : SAR rm8,unity [m-:      evex.nd0.nf.l0.m4.o8 d0 /7        ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(d0) 207 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {RM_GPR|BITS8,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+24093, 62},
    /*  42 : SAR reg8?,unity [v+m-:      evex.nd1.nf.l0.m4.o8 d0 /7        ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d0) 207 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {REG_GPR|BITS8,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+24102, 63},
    /*  43 : SAR reg16?,rm16,unity [vm-:      evex.nd1.nf.l0.m4.o16 d1 /7       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d1) 217 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 3, {REG_GPR|BITS16,RM_GPR|BITS16,UNITY|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+11923, 38},
    /*  44 : SAR rm16,unity [m-:      evex.nd0.nf.l0.m4.o16 d1 /7       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(d1) 207 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {RM_GPR|BITS16,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11933, 64},
    /*  45 : SAR reg16?,unity [v+m-:      evex.nd1.nf.l0.m4.o16 d1 /7       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d1) 207 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {REG_GPR|BITS16,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11943, 65},
    /*  46 : SAR reg32?,rm32,unity [vm-:      evex.nd1.nf.l0.m4.o32 d1 /7       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d1) 217 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,UNITY|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+11953, 41},
    /*  47 : SAR rm32,unity [m-:      evex.nd0.nf.l0.m4.o32 d1 /7       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(d1) 207 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {RM_GPR|BITS32,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11963, 66},
    /*  48 : SAR reg32?,unity [v+m-:      evex.nd1.nf.l0.m4.o32 d1 /7       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d1) 207 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {REG_GPR|BITS32,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11973, 67},
    /*  49 : SAR reg64?,rm64,unity [vm-:      evex.nd1.nf.l0.m4.o64 d1 /7       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d1) 217 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,UNITY|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+11983, 41},
    /*  50 : SAR rm64,unity [m-:      evex.nd0.nf.l0.m4.o64 d1 /7       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(d1) 207 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {RM_GPR|BITS64,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+11993, 66},
    /*  51 : SAR reg64?,unity [v+m-:      evex.nd1.nf.l0.m4.o64 d1 /7       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d1) 207 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {REG_GPR|BITS64,UNITY|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+12003, 67},
    /*  52 : SAR reg8?,rm8,reg_cl [vm-:      evex.nd1.nf.l0.m4.o8 d2 /7        ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 217 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 3, {REG_GPR|BITS8,RM_GPR|BITS8,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+24111, 35},
    /*  53 : SAR rm8,reg_cl [m-:      evex.nd0.nf.l0.m4.o8 d2 /7        ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(d2) 207 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {RM_GPR|BITS8,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+24120, 62},
    /*  54 : SAR reg8?,reg_cl [v+m-:      evex.nd1.nf.l0.m4.o8 d2 /7        ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 207 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {REG_GPR|BITS8,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+24129, 63},
    /*  55 : SAR reg16?,rm16,reg_cl [vm-:      evex.nd1.nf.l0.m4.o16 d3 /7       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 217 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 3, {REG_GPR|BITS16,RM_GPR|BITS16,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+12013, 38},
    /*  56 : SAR rm16,reg_cl [m-:      evex.nd0.nf.l0.m4.o16 d3 /7       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(d3) 207 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {RM_GPR|BITS16,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+12023, 64},
    /*  57 : SAR reg16?,reg_cl [v+m-:      evex.nd1.nf.l0.m4.o16 d3 /7       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 207 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {REG_GPR|BITS16,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+12033, 65},
    /*  58 : SAR reg32?,rm32,reg_cl [vm-:      evex.nd1.nf.l0.m4.o32 d3 /7       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 217 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+12043, 41},
    /*  59 : SAR rm32,reg_cl [m-:      evex.nd0.nf.l0.m4.o32 d3 /7       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(d3) 207 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {RM_GPR|BITS32,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+12053, 66},
    /*  60 : SAR reg32?,reg_cl [v+m-:      evex.nd1.nf.l0.m4.o32 d3 /7       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 207 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {REG_GPR|BITS32,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+12063, 67},
    /*  61 : SAR reg64?,rm64,reg_cl [vm-:      evex.nd1.nf.l0.m4.o64 d3 /7       ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 217 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+12073, 41},
    /*  62 : SAR rm64,reg_cl [m-:      evex.nd0.nf.l0.m4.o64 d3 /7       ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(d3) 207 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {RM_GPR|BITS64,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+12083, 66},
    /*  63 : SAR reg64?,reg_cl [v+m-:      evex.nd1.nf.l0.m4.o64 d3 /7       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 207 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {REG_GPR|BITS64,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+12093, 67},
    /*  64 : SAR reg8?,rm8,reg_cx [vm-:      evex.nd1.nf.l0.m4.o8 d2 /7        ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 217 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 3, {REG_GPR|BITS8,RM_GPR|BITS8,REG_CX,0,0}, NO_DECORATOR, nasm_bytecodes+24111, 35},
    /*  65 : SAR rm8,reg_cx [m-:      evex.nd0.nf.l0.m4.o8 d2 /7        ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(d2) 207 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {RM_GPR|BITS8,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+24120, 62},
    /*  66 : SAR reg8?,reg_cx [v+m-:      evex.nd1.nf.l0.m4.o8 d2 /7        ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 207 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {REG_GPR|BITS8,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+24129, 63},
    /*  67 : SAR reg16?,rm16,reg_cx [vm-:      evex.nd1.nf.l0.m4.o16 d3 /7       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 217 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 3, {REG_GPR|BITS16,RM_GPR|BITS16,REG_CX,0,0}, NO_DECORATOR, nasm_bytecodes+12013, 38},
    /*  68 : SAR rm16,reg_cx [m-:      evex.nd0.nf.l0.m4.o16 d3 /7       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(d3) 207 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {RM_GPR|BITS16,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12023, 64},
    /*  69 : SAR reg16?,reg_cx [v+m-:      evex.nd1.nf.l0.m4.o16 d3 /7       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 207 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {REG_GPR|BITS16,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12033, 65},
    /*  70 : SAR reg32?,rm32,reg_cx [vm-:      evex.nd1.nf.l0.m4.o32 d3 /7       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 217 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_CX,0,0}, NO_DECORATOR, nasm_bytecodes+12043, 41},
    /*  71 : SAR rm32,reg_cx [m-:      evex.nd0.nf.l0.m4.o32 d3 /7       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(d3) 207 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {RM_GPR|BITS32,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12053, 66},
    /*  72 : SAR reg32?,reg_cx [v+m-:      evex.nd1.nf.l0.m4.o32 d3 /7       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 207 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {REG_GPR|BITS32,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12063, 67},
    /*  73 : SAR reg64?,rm64,reg_cx [vm-:      evex.nd1.nf.l0.m4.o64 d3 /7       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 217 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_CX,0,0}, NO_DECORATOR, nasm_bytecodes+12073, 41},
    /*  74 : SAR rm64,reg_cx [m-:      evex.nd0.nf.l0.m4.o64 d3 /7       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(d3) 207 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {RM_GPR|BITS64,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12083, 66},
    /*  75 : SAR reg64?,reg_cx [v+m-:      evex.nd1.nf.l0.m4.o64 d3 /7       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 207 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {REG_GPR|BITS64,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12093, 67},
    /*  76 : SAR reg8?,rm8,reg_ecx [vm-:      evex.nd1.nf.l0.m4.o8 d2 /7        ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 217 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 3, {REG_GPR|BITS8,RM_GPR|BITS8,REG_ECX,0,0}, NO_DECORATOR, nasm_bytecodes+24111, 35},
    /*  77 : SAR rm8,reg_ecx [m-:      evex.nd0.nf.l0.m4.o8 d2 /7        ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(d2) 207 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {RM_GPR|BITS8,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+24120, 62},
    /*  78 : SAR reg8?,reg_ecx [v+m-:      evex.nd1.nf.l0.m4.o8 d2 /7        ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 207 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {REG_GPR|BITS8,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+24129, 63},
    /*  79 : SAR reg16?,rm16,reg_ecx [vm-:      evex.nd1.nf.l0.m4.o16 d3 /7       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 217 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 3, {REG_GPR|BITS16,RM_GPR|BITS16,REG_ECX,0,0}, NO_DECORATOR, nasm_bytecodes+12013, 38},
    /*  80 : SAR rm16,reg_ecx [m-:      evex.nd0.nf.l0.m4.o16 d3 /7       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(d3) 207 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {RM_GPR|BITS16,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12023, 64},
    /*  81 : SAR reg16?,reg_ecx [v+m-:      evex.nd1.nf.l0.m4.o16 d3 /7       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 207 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {REG_GPR|BITS16,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12033, 65},
    /*  82 : SAR reg32?,rm32,reg_ecx [vm-:      evex.nd1.nf.l0.m4.o32 d3 /7       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 217 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_ECX,0,0}, NO_DECORATOR, nasm_bytecodes+12043, 41},
    /*  83 : SAR rm32,reg_ecx [m-:      evex.nd0.nf.l0.m4.o32 d3 /7       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(d3) 207 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {RM_GPR|BITS32,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12053, 66},
    /*  84 : SAR reg32?,reg_ecx [v+m-:      evex.nd1.nf.l0.m4.o32 d3 /7       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 207 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {REG_GPR|BITS32,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12063, 67},
    /*  85 : SAR reg64?,rm64,reg_ecx [vm-:      evex.nd1.nf.l0.m4.o64 d3 /7       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 217 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_ECX,0,0}, NO_DECORATOR, nasm_bytecodes+12073, 41},
    /*  86 : SAR rm64,reg_ecx [m-:      evex.nd0.nf.l0.m4.o64 d3 /7       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(d3) 207 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {RM_GPR|BITS64,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12083, 66},
    /*  87 : SAR reg64?,reg_ecx [v+m-:      evex.nd1.nf.l0.m4.o64 d3 /7       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 207 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {REG_GPR|BITS64,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12093, 67},
    /*  88 : SAR reg8?,rm8,reg_rcx [vm-:      evex.nd1.nf.l0.m4.o8 d2 /7        ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 217 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 3, {REG_GPR|BITS8,RM_GPR|BITS8,REG_RCX,0,0}, NO_DECORATOR, nasm_bytecodes+24111, 35},
    /*  89 : SAR rm8,reg_rcx [m-:      evex.nd0.nf.l0.m4.o8 d2 /7        ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(d2) 207 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {RM_GPR|BITS8,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+24120, 62},
    /*  90 : SAR reg8?,reg_rcx [v+m-:      evex.nd1.nf.l0.m4.o8 d2 /7        ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(d2) 207 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {REG_GPR|BITS8,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+24129, 63},
    /*  91 : SAR reg16?,rm16,reg_rcx [vm-:      evex.nd1.nf.l0.m4.o16 d3 /7       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 217 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 3, {REG_GPR|BITS16,RM_GPR|BITS16,REG_RCX,0,0}, NO_DECORATOR, nasm_bytecodes+12013, 38},
    /*  92 : SAR rm16,reg_rcx [m-:      evex.nd0.nf.l0.m4.o16 d3 /7       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(d3) 207 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {RM_GPR|BITS16,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12023, 64},
    /*  93 : SAR reg16?,reg_rcx [v+m-:      evex.nd1.nf.l0.m4.o16 d3 /7       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(d3) 207 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {REG_GPR|BITS16,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12033, 65},
    /*  94 : SAR reg32?,rm32,reg_rcx [vm-:      evex.nd1.nf.l0.m4.o32 d3 /7       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 217 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_RCX,0,0}, NO_DECORATOR, nasm_bytecodes+12043, 41},
    /*  95 : SAR rm32,reg_rcx [m-:      evex.nd0.nf.l0.m4.o32 d3 /7       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(d3) 207 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {RM_GPR|BITS32,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12053, 66},
    /*  96 : SAR reg32?,reg_rcx [v+m-:      evex.nd1.nf.l0.m4.o32 d3 /7       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(d3) 207 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {REG_GPR|BITS32,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12063, 67},
    /*  97 : SAR reg64?,rm64,reg_rcx [vm-:      evex.nd1.nf.l0.m4.o64 d3 /7       ] ND,SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 217 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_RCX,0,0}, NO_DECORATOR, nasm_bytecodes+12073, 41},
    /*  98 : SAR rm64,reg_rcx [m-:      evex.nd0.nf.l0.m4.o64 d3 /7       ] ND,SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(d3) 207 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {RM_GPR|BITS64,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12083, 66},
    /*  99 : SAR reg64?,reg_rcx [v+m-:      evex.nd1.nf.l0.m4.o64 d3 /7       ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(d3) 207 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {REG_GPR|BITS64,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12093, 67},
    /* 100 : SAR reg8?,rm8,imm8 [vmi:      evex.nd1.nf.l0.m4.o8 c0 /7 ib,u   ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(c0) 217 026 : SM0,SM1,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 3, {REG_GPR|BITS8,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+12103, 35},
    /* 101 : SAR rm8,imm8 [mi:      evex.nd0.nf.l0.m4.o8 c0 /7 ib,u   ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(c0) 207 025 : SM0,NF,NF_E,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+12113, 62},
    /* 102 : SAR reg8?,imm8 [v+mi:      evex.nd1.nf.l0.m4.o8 c0 /7 ib,u   ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(c0) 207 025 : SM0,NF,NF_E,ZU,WIG,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {REG_GPR|BITS8,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+12123, 63},
    /* 103 : SAR reg16?,rm16,imm8 [vmi:      evex.nd1.nf.l0.m4.o16 c1 /7 ib,u  ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(c1) 217 026 : SM0,SM1,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 3, {REG_GPR|BITS16,RM_GPR|BITS16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+2004, 38},
    /* 104 : SAR rm16,imm8 [mi:      evex.nd0.nf.l0.m4.o16 c1 /7 ib,u  ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(c1) 207 025 : SM0,NF,NF_E,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {RM_GPR|BITS16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+2015, 64},
    /* 105 : SAR reg16?,imm8 [v+mi:      evex.nd1.nf.l0.m4.o16 c1 /7 ib,u  ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(c1) 207 025 : SM0,NF,NF_E,ZU,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {REG_GPR|BITS16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+2026, 65},
    /* 106 : SAR reg32?,rm32,imm8 [vmi:      evex.nd1.nf.l0.m4.o32 c1 /7 ib,u  ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(c1) 217 026 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+2037, 41},
    /* 107 : SAR rm32,imm8 [mi:      evex.nd0.nf.l0.m4.o32 c1 /7 ib,u  ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(c1) 207 025 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {RM_GPR|BITS32,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+2048, 66},
    /* 108 : SAR reg32?,imm8 [v+mi:      evex.nd1.nf.l0.m4.o32 c1 /7 ib,u  ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(c1) 207 025 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {REG_GPR|BITS32,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+2059, 67},
    /* 109 : SAR reg64?,rm64,imm8 [vmi:      evex.nd1.nf.l0.m4.o64 c1 /7 ib,u  ] SM0,SM1,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(c1) 217 026 : SM0,SM1,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+2070, 41},
    /* 110 : SAR rm64,imm8 [mi:      evex.nd0.nf.l0.m4.o64 c1 /7 ib,u  ] SM0,NF,LONG,FL,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(c1) 207 025 : SM0,NF,NF_E,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {RM_GPR|BITS64,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+2081, 66},
    /* 111 : SAR reg64?,imm8 [v+mi:      evex.nd1.nf.l0.m4.o64 c1 /7 ib,u  ] ND,SM0,NF,ZU,LONG,FL,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(c1) 207 025 : SM0,NF,NF_E,ZU,WW,LONG,FL,EVEX,PROT,APX,X86_64 */
        {I_SAR, 2, {REG_GPR|BITS64,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+2092, 67},
    /* 112 : SAR reg32,rm32*,reg8 [rmv:      evex.lz.f3.0f38.w0 f7 /r          ] ND,SM0,SM1,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 7e 08) 300 001(f7) 110 : SM0,SM1,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SAR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24156, 70},
    /* 113 : SAR reg32,reg8 [r+mv:      evex.lz.f3.0f38.w0 f7 /r          ] ND,SM0,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 7e 08) 300 001(f7) 100 : SM0,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SAR, 2, {REG_GPR|BITS32,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+24165, 71},
    /* 114 : SAR reg32,rm32*,reg16 [rmv:      evex.lz.f3.0f38.w0 f7 /r          ] ND,SM0,SM1,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 7e 08) 300 001(f7) 110 : SM0,SM1,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SAR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+24156, 70},
    /* 115 : SAR reg32,reg16 [r+mv:      evex.lz.f3.0f38.w0 f7 /r          ] ND,SM0,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 7e 08) 300 001(f7) 100 : SM0,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SAR, 2, {REG_GPR|BITS32,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+24165, 71},
    /* 116 : SAR reg32,rm32*,reg32 [rmv:      evex.lz.f3.0f38.w0 f7 /r          ] ND,SM0,SM1,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 7e 08) 300 001(f7) 110 : SM0,SM1,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SAR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+24156, 70},
    /* 117 : SAR reg32,reg32 [r+mv:      evex.lz.f3.0f38.w0 f7 /r          ] ND,SM0,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 7e 08) 300 001(f7) 100 : SM0,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SAR, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+24165, 71},
    /* 118 : SAR reg32,rm32*,reg64 [rmv:      evex.lz.f3.0f38.w0 f7 /r          ] ND,SM0,SM1,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 7e 08) 300 001(f7) 110 : SM0,SM1,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SAR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+24156, 70},
    /* 119 : SAR reg32,reg64 [r+mv:      evex.lz.f3.0f38.w0 f7 /r          ] ND,SM0,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 7e 08) 300 001(f7) 100 : SM0,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SAR, 2, {REG_GPR|BITS32,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+24165, 71},
    /* 120 : SAR reg64,rm64*,reg8 [rmv:      evex.lz.f3.0f38.w1 f7 /r          ] ND,SM0,SM1,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 fe 08) 300 001(f7) 110 : SM0,SM1,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SAR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24210, 70},
    /* 121 : SAR reg64,reg8 [r+mv:      evex.lz.f3.0f38.w1 f7 /r          ] ND,SM0,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 fe 08) 300 001(f7) 100 : SM0,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SAR, 2, {REG_GPR|BITS64,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+24219, 71},
    /* 122 : SAR reg64,rm64*,reg16 [rmv:      evex.lz.f3.0f38.w1 f7 /r          ] ND,SM0,SM1,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 fe 08) 300 001(f7) 110 : SM0,SM1,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SAR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+24210, 70},
    /* 123 : SAR reg64,reg16 [r+mv:      evex.lz.f3.0f38.w1 f7 /r          ] ND,SM0,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 fe 08) 300 001(f7) 100 : SM0,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SAR, 2, {REG_GPR|BITS64,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+24219, 71},
    /* 124 : SAR reg64,rm64*,reg32 [rmv:      evex.lz.f3.0f38.w1 f7 /r          ] ND,SM0,SM1,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 fe 08) 300 001(f7) 110 : SM0,SM1,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SAR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+24210, 70},
    /* 125 : SAR reg64,reg32 [r+mv:      evex.lz.f3.0f38.w1 f7 /r          ] ND,SM0,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 fe 08) 300 001(f7) 100 : SM0,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SAR, 2, {REG_GPR|BITS64,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+24219, 71},
    /* 126 : SAR reg64,rm64*,reg64 [rmv:      evex.lz.f3.0f38.w1 f7 /r          ] ND,SM0,SM1,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 fe 08) 300 001(f7) 110 : SM0,SM1,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SAR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+24210, 70},
    /* 127 : SAR reg64,reg64 [r+mv:      evex.lz.f3.0f38.w1 f7 /r          ] ND,SM0,OPT,NF,NF_R,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 fe 08) 300 001(f7) 100 : SM0,OPT,NF,NF_R,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SAR, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+24219, 71},
};

static const struct itemplate instrux_RORX[4] = {
    /*   0 : RORX reg32,rm32,imm8 [rmi:      vex.lz.f2.0f3a.w0 f0 /r ib        ] SM0-1,BMI2,FUTURE */
        /* 270(003 003) 001(f0) 110 022 : SM0,SM1,NOAPX,VEX,BMI2,FUTURE */
        {I_RORX, 3, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51093, 58},
    /*   1 : RORX reg64,rm64,imm8 [rmi:      vex.lz.f2.0f3a.w1 f0 /r ib        ] SM0-1,BMI2,FUTURE */
        /* 270(003 203) 001(f0) 110 022 : SM0,SM1,NOAPX,VEX,BMI2,FUTURE */
        {I_RORX, 3, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51101, 58},
    /*   2 : RORX reg32,rm32,imm8 [rmi:      evex.lz.f2.0f3a.w0 f0 /r ib       ] SM0-1,LONG,PROT,BMI2,APX,X86_64 */
        /* 250(f3 7f 08) 300 001(f0) 110 022 : SM0,SM1,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_RORX, 3, {REG_GPR|BITS32,RM_GPR|BITS32,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+12133, 68},
    /*   3 : RORX reg64,rm64,imm8 [rmi:      evex.lz.f2.0f3a.w1 f0 /r ib       ] SM0-1,LONG,PROT,BMI2,APX,X86_64 */
        /* 250(f3 ff 08) 300 001(f0) 110 022 : SM0,SM1,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_RORX, 3, {REG_GPR|BITS64,RM_GPR|BITS64,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+12143, 68},
};

static const struct itemplate instrux_ROLX[4] = {
    /*   0 : ROLX reg32,rm32,imm_known8 [rmi:      vex.lz.f2.0f3a.w0 f0 /r ib^1f     ] SM0-1,BMI2,FUTURE */
        /* 270(003 003) 001(f0) 110 306 000 037 : SM0,SM1,NOAPX,VEX,BMI2,FUTURE */
        {I_ROLX, 3, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,IMM_KNOWN|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+10643, 58},
    /*   1 : ROLX reg64,rm64,imm_known8 [rmi:      vex.lz.f2.0f3a.w1 f0 /r ib^3f     ] SM0-1,BMI2,FUTURE */
        /* 270(003 203) 001(f0) 110 306 000 077 : SM0,SM1,NOAPX,VEX,BMI2,FUTURE */
        {I_ROLX, 3, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,IMM_KNOWN|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+10653, 58},
    /*   2 : ROLX reg32,rm32,imm_known8 [rmi:      evex.lz.f2.0f3a.w0 f0 /r ib^1f    ] SM0-1,LONG,PROT,BMI2,APX,X86_64 */
        /* 250(f3 7f 08) 300 001(f0) 110 306 000 037 : SM0,SM1,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_ROLX, 3, {REG_GPR|BITS32,RM_GPR|BITS32,IMM_KNOWN|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+0, 68},
    /*   3 : ROLX reg64,rm64,imm_known8 [rmi:      evex.lz.f2.0f3a.w1 f0 /r ib^3f    ] SM0-1,LONG,PROT,BMI2,APX,X86_64 */
        /* 250(f3 ff 08) 300 001(f0) 110 306 000 077 : SM0,SM1,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_ROLX, 3, {REG_GPR|BITS64,RM_GPR|BITS64,IMM_KNOWN|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+12, 68},
};

static const struct itemplate instrux_SHLX[32] = {
    /*   0 : SHLX reg32,rm32*,reg8 [rmv:      vex.lz.66.0f38.w0 f7 /r           ] ND,SM0,SM1,BMI2,FUTURE */
        /* 262(002 001) 001(f7) 110 : SM0,SM1,NOAPX,VEX,BMI2,FUTURE */
        {I_SHLX, 3, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,REG_GPR|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55087, 58},
    /*   1 : SHLX reg32,reg8 [r+mv:      vex.lz.66.0f38.w0 f7 /r           ] ND,SM0,BMI2,FUTURE */
        /* 261(002 001) 001(f7) 100 : SM0,NOAPX,VEX,BMI2,FUTURE */
        {I_SHLX, 2, {REG_GPR|BITS32|RN_L16,REG_GPR|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55094, 59},
    /*   2 : SHLX reg32,rm32*,reg16 [rmv:      vex.lz.66.0f38.w0 f7 /r           ] ND,SM0,SM1,BMI2,FUTURE */
        /* 262(002 001) 001(f7) 110 : SM0,SM1,NOAPX,VEX,BMI2,FUTURE */
        {I_SHLX, 3, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,REG_GPR|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55087, 58},
    /*   3 : SHLX reg32,reg16 [r+mv:      vex.lz.66.0f38.w0 f7 /r           ] ND,SM0,BMI2,FUTURE */
        /* 261(002 001) 001(f7) 100 : SM0,NOAPX,VEX,BMI2,FUTURE */
        {I_SHLX, 2, {REG_GPR|BITS32|RN_L16,REG_GPR|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55094, 59},
    /*   4 : SHLX reg32,rm32*,reg32 [rmv:      vex.lz.66.0f38.w0 f7 /r           ] SM0,SM1,BMI2,FUTURE */
        /* 262(002 001) 001(f7) 110 : SM0,SM1,NOAPX,VEX,BMI2,FUTURE */
        {I_SHLX, 3, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55087, 58},
    /*   5 : SHLX reg32,reg32 [r+mv:      vex.lz.66.0f38.w0 f7 /r           ] ND,SM0,BMI2,FUTURE */
        /* 261(002 001) 001(f7) 100 : SM0,NOAPX,VEX,BMI2,FUTURE */
        {I_SHLX, 2, {REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55094, 59},
    /*   6 : SHLX reg32,rm32*,reg64 [rmv:      vex.lz.66.0f38.w0 f7 /r           ] ND,SM0,SM1,BMI2,FUTURE */
        /* 262(002 001) 001(f7) 110 : SM0,SM1,NOAPX,VEX,BMI2,FUTURE */
        {I_SHLX, 3, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55087, 58},
    /*   7 : SHLX reg32,reg64 [r+mv:      vex.lz.66.0f38.w0 f7 /r           ] ND,SM0,BMI2,FUTURE */
        /* 261(002 001) 001(f7) 100 : SM0,NOAPX,VEX,BMI2,FUTURE */
        {I_SHLX, 2, {REG_GPR|BITS32|RN_L16,REG_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55094, 59},
    /*   8 : SHLX reg64,rm64*,reg8 [rmv:      vex.lz.66.0f38.w1 f7 /r           ] ND,SM0,SM1,BMI2,FUTURE */
        /* 262(002 201) 001(f7) 110 : SM0,SM1,NOAPX,VEX,BMI2,FUTURE */
        {I_SHLX, 3, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,REG_GPR|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55129, 58},
    /*   9 : SHLX reg64,reg8 [r+mv:      vex.lz.66.0f38.w1 f7 /r           ] ND,SM0,BMI2,FUTURE */
        /* 261(002 201) 001(f7) 100 : SM0,NOAPX,VEX,BMI2,FUTURE */
        {I_SHLX, 2, {REG_GPR|BITS64|RN_L16,REG_GPR|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55136, 59},
    /*  10 : SHLX reg64,rm64*,reg16 [rmv:      vex.lz.66.0f38.w1 f7 /r           ] ND,SM0,SM1,BMI2,FUTURE */
        /* 262(002 201) 001(f7) 110 : SM0,SM1,NOAPX,VEX,BMI2,FUTURE */
        {I_SHLX, 3, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,REG_GPR|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55129, 58},
    /*  11 : SHLX reg64,reg16 [r+mv:      vex.lz.66.0f38.w1 f7 /r           ] ND,SM0,BMI2,FUTURE */
        /* 261(002 201) 001(f7) 100 : SM0,NOAPX,VEX,BMI2,FUTURE */
        {I_SHLX, 2, {REG_GPR|BITS64|RN_L16,REG_GPR|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55136, 59},
    /*  12 : SHLX reg64,rm64*,reg32 [rmv:      vex.lz.66.0f38.w1 f7 /r           ] ND,SM0,SM1,BMI2,FUTURE */
        /* 262(002 201) 001(f7) 110 : SM0,SM1,NOAPX,VEX,BMI2,FUTURE */
        {I_SHLX, 3, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55129, 58},
    /*  13 : SHLX reg64,reg32 [r+mv:      vex.lz.66.0f38.w1 f7 /r           ] ND,SM0,BMI2,FUTURE */
        /* 261(002 201) 001(f7) 100 : SM0,NOAPX,VEX,BMI2,FUTURE */
        {I_SHLX, 2, {REG_GPR|BITS64|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55136, 59},
    /*  14 : SHLX reg64,rm64*,reg64 [rmv:      vex.lz.66.0f38.w1 f7 /r           ] SM0,SM1,BMI2,FUTURE */
        /* 262(002 201) 001(f7) 110 : SM0,SM1,NOAPX,VEX,BMI2,FUTURE */
        {I_SHLX, 3, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55129, 58},
    /*  15 : SHLX reg64,reg64 [r+mv:      vex.lz.66.0f38.w1 f7 /r           ] ND,SM0,BMI2,FUTURE */
        /* 261(002 201) 001(f7) 100 : SM0,NOAPX,VEX,BMI2,FUTURE */
        {I_SHLX, 2, {REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55136, 59},
    /*  16 : SHLX reg32,rm32*,reg8 [rmv:      evex.lz.66.0f38.w0 f7 /r          ] ND,SM0,SM1,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 7d 08) 300 001(f7) 110 : SM0,SM1,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHLX, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24138, 68},
    /*  17 : SHLX reg32,reg8 [r+mv:      evex.lz.66.0f38.w0 f7 /r          ] ND,SM0,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 7d 08) 300 001(f7) 100 : SM0,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHLX, 2, {REG_GPR|BITS32,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+24147, 69},
    /*  18 : SHLX reg32,rm32*,reg16 [rmv:      evex.lz.66.0f38.w0 f7 /r          ] ND,SM0,SM1,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 7d 08) 300 001(f7) 110 : SM0,SM1,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHLX, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+24138, 68},
    /*  19 : SHLX reg32,reg16 [r+mv:      evex.lz.66.0f38.w0 f7 /r          ] ND,SM0,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 7d 08) 300 001(f7) 100 : SM0,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHLX, 2, {REG_GPR|BITS32,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+24147, 69},
    /*  20 : SHLX reg32,rm32*,reg32 [rmv:      evex.lz.66.0f38.w0 f7 /r          ] SM0,SM1,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 7d 08) 300 001(f7) 110 : SM0,SM1,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHLX, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+24138, 68},
    /*  21 : SHLX reg32,reg32 [r+mv:      evex.lz.66.0f38.w0 f7 /r          ] ND,SM0,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 7d 08) 300 001(f7) 100 : SM0,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHLX, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+24147, 69},
    /*  22 : SHLX reg32,rm32*,reg64 [rmv:      evex.lz.66.0f38.w0 f7 /r          ] ND,SM0,SM1,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 7d 08) 300 001(f7) 110 : SM0,SM1,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHLX, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+24138, 68},
    /*  23 : SHLX reg32,reg64 [r+mv:      evex.lz.66.0f38.w0 f7 /r          ] ND,SM0,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 7d 08) 300 001(f7) 100 : SM0,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHLX, 2, {REG_GPR|BITS32,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+24147, 69},
    /*  24 : SHLX reg64,rm64*,reg8 [rmv:      evex.lz.66.0f38.w1 f7 /r          ] ND,SM0,SM1,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 fd 08) 300 001(f7) 110 : SM0,SM1,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHLX, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24192, 68},
    /*  25 : SHLX reg64,reg8 [r+mv:      evex.lz.66.0f38.w1 f7 /r          ] ND,SM0,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 fd 08) 300 001(f7) 100 : SM0,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHLX, 2, {REG_GPR|BITS64,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+24201, 69},
    /*  26 : SHLX reg64,rm64*,reg16 [rmv:      evex.lz.66.0f38.w1 f7 /r          ] ND,SM0,SM1,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 fd 08) 300 001(f7) 110 : SM0,SM1,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHLX, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+24192, 68},
    /*  27 : SHLX reg64,reg16 [r+mv:      evex.lz.66.0f38.w1 f7 /r          ] ND,SM0,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 fd 08) 300 001(f7) 100 : SM0,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHLX, 2, {REG_GPR|BITS64,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+24201, 69},
    /*  28 : SHLX reg64,rm64*,reg32 [rmv:      evex.lz.66.0f38.w1 f7 /r          ] ND,SM0,SM1,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 fd 08) 300 001(f7) 110 : SM0,SM1,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHLX, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+24192, 68},
    /*  29 : SHLX reg64,reg32 [r+mv:      evex.lz.66.0f38.w1 f7 /r          ] ND,SM0,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 fd 08) 300 001(f7) 100 : SM0,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHLX, 2, {REG_GPR|BITS64,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+24201, 69},
    /*  30 : SHLX reg64,rm64*,reg64 [rmv:      evex.lz.66.0f38.w1 f7 /r          ] SM0,SM1,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 fd 08) 300 001(f7) 110 : SM0,SM1,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHLX, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+24192, 68},
    /*  31 : SHLX reg64,reg64 [r+mv:      evex.lz.66.0f38.w1 f7 /r          ] ND,SM0,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 fd 08) 300 001(f7) 100 : SM0,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHLX, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+24201, 69},
};

static const struct itemplate instrux_SALX[32] = {
    /*   0 : SALX reg32,rm32*,reg8 [rmv:      vex.lz.66.0f38.w0 f7 /r           ] ND,SM0,SM1,BMI2,FUTURE */
        /* 262(002 001) 001(f7) 110 : SM0,SM1,NOAPX,VEX,BMI2,FUTURE */
        {I_SALX, 3, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,REG_GPR|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55087, 58},
    /*   1 : SALX reg32,reg8 [r+mv:      vex.lz.66.0f38.w0 f7 /r           ] ND,SM0,BMI2,FUTURE */
        /* 261(002 001) 001(f7) 100 : SM0,NOAPX,VEX,BMI2,FUTURE */
        {I_SALX, 2, {REG_GPR|BITS32|RN_L16,REG_GPR|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55094, 59},
    /*   2 : SALX reg32,rm32*,reg16 [rmv:      vex.lz.66.0f38.w0 f7 /r           ] ND,SM0,SM1,BMI2,FUTURE */
        /* 262(002 001) 001(f7) 110 : SM0,SM1,NOAPX,VEX,BMI2,FUTURE */
        {I_SALX, 3, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,REG_GPR|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55087, 58},
    /*   3 : SALX reg32,reg16 [r+mv:      vex.lz.66.0f38.w0 f7 /r           ] ND,SM0,BMI2,FUTURE */
        /* 261(002 001) 001(f7) 100 : SM0,NOAPX,VEX,BMI2,FUTURE */
        {I_SALX, 2, {REG_GPR|BITS32|RN_L16,REG_GPR|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55094, 59},
    /*   4 : SALX reg32,rm32*,reg32 [rmv:      vex.lz.66.0f38.w0 f7 /r           ] ND,SM0,SM1,BMI2,FUTURE */
        /* 262(002 001) 001(f7) 110 : SM0,SM1,NOAPX,VEX,BMI2,FUTURE */
        {I_SALX, 3, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55087, 58},
    /*   5 : SALX reg32,reg32 [r+mv:      vex.lz.66.0f38.w0 f7 /r           ] ND,SM0,BMI2,FUTURE */
        /* 261(002 001) 001(f7) 100 : SM0,NOAPX,VEX,BMI2,FUTURE */
        {I_SALX, 2, {REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55094, 59},
    /*   6 : SALX reg32,rm32*,reg64 [rmv:      vex.lz.66.0f38.w0 f7 /r           ] ND,SM0,SM1,BMI2,FUTURE */
        /* 262(002 001) 001(f7) 110 : SM0,SM1,NOAPX,VEX,BMI2,FUTURE */
        {I_SALX, 3, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55087, 58},
    /*   7 : SALX reg32,reg64 [r+mv:      vex.lz.66.0f38.w0 f7 /r           ] ND,SM0,BMI2,FUTURE */
        /* 261(002 001) 001(f7) 100 : SM0,NOAPX,VEX,BMI2,FUTURE */
        {I_SALX, 2, {REG_GPR|BITS32|RN_L16,REG_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55094, 59},
    /*   8 : SALX reg64,rm64*,reg8 [rmv:      vex.lz.66.0f38.w1 f7 /r           ] ND,SM0,SM1,BMI2,FUTURE */
        /* 262(002 201) 001(f7) 110 : SM0,SM1,NOAPX,VEX,BMI2,FUTURE */
        {I_SALX, 3, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,REG_GPR|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55129, 58},
    /*   9 : SALX reg64,reg8 [r+mv:      vex.lz.66.0f38.w1 f7 /r           ] ND,SM0,BMI2,FUTURE */
        /* 261(002 201) 001(f7) 100 : SM0,NOAPX,VEX,BMI2,FUTURE */
        {I_SALX, 2, {REG_GPR|BITS64|RN_L16,REG_GPR|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55136, 59},
    /*  10 : SALX reg64,rm64*,reg16 [rmv:      vex.lz.66.0f38.w1 f7 /r           ] ND,SM0,SM1,BMI2,FUTURE */
        /* 262(002 201) 001(f7) 110 : SM0,SM1,NOAPX,VEX,BMI2,FUTURE */
        {I_SALX, 3, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,REG_GPR|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55129, 58},
    /*  11 : SALX reg64,reg16 [r+mv:      vex.lz.66.0f38.w1 f7 /r           ] ND,SM0,BMI2,FUTURE */
        /* 261(002 201) 001(f7) 100 : SM0,NOAPX,VEX,BMI2,FUTURE */
        {I_SALX, 2, {REG_GPR|BITS64|RN_L16,REG_GPR|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55136, 59},
    /*  12 : SALX reg64,rm64*,reg32 [rmv:      vex.lz.66.0f38.w1 f7 /r           ] ND,SM0,SM1,BMI2,FUTURE */
        /* 262(002 201) 001(f7) 110 : SM0,SM1,NOAPX,VEX,BMI2,FUTURE */
        {I_SALX, 3, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55129, 58},
    /*  13 : SALX reg64,reg32 [r+mv:      vex.lz.66.0f38.w1 f7 /r           ] ND,SM0,BMI2,FUTURE */
        /* 261(002 201) 001(f7) 100 : SM0,NOAPX,VEX,BMI2,FUTURE */
        {I_SALX, 2, {REG_GPR|BITS64|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55136, 59},
    /*  14 : SALX reg64,rm64*,reg64 [rmv:      vex.lz.66.0f38.w1 f7 /r           ] ND,SM0,SM1,BMI2,FUTURE */
        /* 262(002 201) 001(f7) 110 : SM0,SM1,NOAPX,VEX,BMI2,FUTURE */
        {I_SALX, 3, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55129, 58},
    /*  15 : SALX reg64,reg64 [r+mv:      vex.lz.66.0f38.w1 f7 /r           ] ND,SM0,BMI2,FUTURE */
        /* 261(002 201) 001(f7) 100 : SM0,NOAPX,VEX,BMI2,FUTURE */
        {I_SALX, 2, {REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55136, 59},
    /*  16 : SALX reg32,rm32*,reg8 [rmv:      evex.lz.66.0f38.w0 f7 /r          ] ND,SM0,SM1,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 7d 08) 300 001(f7) 110 : SM0,SM1,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SALX, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24138, 68},
    /*  17 : SALX reg32,reg8 [r+mv:      evex.lz.66.0f38.w0 f7 /r          ] ND,SM0,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 7d 08) 300 001(f7) 100 : SM0,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SALX, 2, {REG_GPR|BITS32,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+24147, 69},
    /*  18 : SALX reg32,rm32*,reg16 [rmv:      evex.lz.66.0f38.w0 f7 /r          ] ND,SM0,SM1,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 7d 08) 300 001(f7) 110 : SM0,SM1,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SALX, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+24138, 68},
    /*  19 : SALX reg32,reg16 [r+mv:      evex.lz.66.0f38.w0 f7 /r          ] ND,SM0,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 7d 08) 300 001(f7) 100 : SM0,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SALX, 2, {REG_GPR|BITS32,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+24147, 69},
    /*  20 : SALX reg32,rm32*,reg32 [rmv:      evex.lz.66.0f38.w0 f7 /r          ] ND,SM0,SM1,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 7d 08) 300 001(f7) 110 : SM0,SM1,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SALX, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+24138, 68},
    /*  21 : SALX reg32,reg32 [r+mv:      evex.lz.66.0f38.w0 f7 /r          ] ND,SM0,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 7d 08) 300 001(f7) 100 : SM0,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SALX, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+24147, 69},
    /*  22 : SALX reg32,rm32*,reg64 [rmv:      evex.lz.66.0f38.w0 f7 /r          ] ND,SM0,SM1,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 7d 08) 300 001(f7) 110 : SM0,SM1,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SALX, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+24138, 68},
    /*  23 : SALX reg32,reg64 [r+mv:      evex.lz.66.0f38.w0 f7 /r          ] ND,SM0,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 7d 08) 300 001(f7) 100 : SM0,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SALX, 2, {REG_GPR|BITS32,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+24147, 69},
    /*  24 : SALX reg64,rm64*,reg8 [rmv:      evex.lz.66.0f38.w1 f7 /r          ] ND,SM0,SM1,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 fd 08) 300 001(f7) 110 : SM0,SM1,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SALX, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24192, 68},
    /*  25 : SALX reg64,reg8 [r+mv:      evex.lz.66.0f38.w1 f7 /r          ] ND,SM0,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 fd 08) 300 001(f7) 100 : SM0,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SALX, 2, {REG_GPR|BITS64,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+24201, 69},
    /*  26 : SALX reg64,rm64*,reg16 [rmv:      evex.lz.66.0f38.w1 f7 /r          ] ND,SM0,SM1,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 fd 08) 300 001(f7) 110 : SM0,SM1,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SALX, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+24192, 68},
    /*  27 : SALX reg64,reg16 [r+mv:      evex.lz.66.0f38.w1 f7 /r          ] ND,SM0,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 fd 08) 300 001(f7) 100 : SM0,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SALX, 2, {REG_GPR|BITS64,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+24201, 69},
    /*  28 : SALX reg64,rm64*,reg32 [rmv:      evex.lz.66.0f38.w1 f7 /r          ] ND,SM0,SM1,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 fd 08) 300 001(f7) 110 : SM0,SM1,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SALX, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+24192, 68},
    /*  29 : SALX reg64,reg32 [r+mv:      evex.lz.66.0f38.w1 f7 /r          ] ND,SM0,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 fd 08) 300 001(f7) 100 : SM0,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SALX, 2, {REG_GPR|BITS64,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+24201, 69},
    /*  30 : SALX reg64,rm64*,reg64 [rmv:      evex.lz.66.0f38.w1 f7 /r          ] ND,SM0,SM1,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 fd 08) 300 001(f7) 110 : SM0,SM1,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SALX, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+24192, 68},
    /*  31 : SALX reg64,reg64 [r+mv:      evex.lz.66.0f38.w1 f7 /r          ] ND,SM0,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 fd 08) 300 001(f7) 100 : SM0,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SALX, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+24201, 69},
};

static const struct itemplate instrux_SARX[32] = {
    /*   0 : SARX reg32,rm32*,reg8 [rmv:      vex.lz.f3.0f38.w0 f7 /r           ] ND,SM0,SM1,BMI2,FUTURE */
        /* 262(002 002) 001(f7) 110 : SM0,SM1,NOAPX,VEX,BMI2,FUTURE */
        {I_SARX, 3, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,REG_GPR|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55101, 58},
    /*   1 : SARX reg32,reg8 [r+mv:      vex.lz.f3.0f38.w0 f7 /r           ] ND,SM0,BMI2,FUTURE */
        /* 261(002 002) 001(f7) 100 : SM0,NOAPX,VEX,BMI2,FUTURE */
        {I_SARX, 2, {REG_GPR|BITS32|RN_L16,REG_GPR|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55108, 59},
    /*   2 : SARX reg32,rm32*,reg16 [rmv:      vex.lz.f3.0f38.w0 f7 /r           ] ND,SM0,SM1,BMI2,FUTURE */
        /* 262(002 002) 001(f7) 110 : SM0,SM1,NOAPX,VEX,BMI2,FUTURE */
        {I_SARX, 3, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,REG_GPR|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55101, 58},
    /*   3 : SARX reg32,reg16 [r+mv:      vex.lz.f3.0f38.w0 f7 /r           ] ND,SM0,BMI2,FUTURE */
        /* 261(002 002) 001(f7) 100 : SM0,NOAPX,VEX,BMI2,FUTURE */
        {I_SARX, 2, {REG_GPR|BITS32|RN_L16,REG_GPR|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55108, 59},
    /*   4 : SARX reg32,rm32*,reg32 [rmv:      vex.lz.f3.0f38.w0 f7 /r           ] SM0,SM1,BMI2,FUTURE */
        /* 262(002 002) 001(f7) 110 : SM0,SM1,NOAPX,VEX,BMI2,FUTURE */
        {I_SARX, 3, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55101, 58},
    /*   5 : SARX reg32,reg32 [r+mv:      vex.lz.f3.0f38.w0 f7 /r           ] ND,SM0,BMI2,FUTURE */
        /* 261(002 002) 001(f7) 100 : SM0,NOAPX,VEX,BMI2,FUTURE */
        {I_SARX, 2, {REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55108, 59},
    /*   6 : SARX reg32,rm32*,reg64 [rmv:      vex.lz.f3.0f38.w0 f7 /r           ] ND,SM0,SM1,BMI2,FUTURE */
        /* 262(002 002) 001(f7) 110 : SM0,SM1,NOAPX,VEX,BMI2,FUTURE */
        {I_SARX, 3, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55101, 58},
    /*   7 : SARX reg32,reg64 [r+mv:      vex.lz.f3.0f38.w0 f7 /r           ] ND,SM0,BMI2,FUTURE */
        /* 261(002 002) 001(f7) 100 : SM0,NOAPX,VEX,BMI2,FUTURE */
        {I_SARX, 2, {REG_GPR|BITS32|RN_L16,REG_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55108, 59},
    /*   8 : SARX reg64,rm64*,reg8 [rmv:      vex.lz.f3.0f38.w1 f7 /r           ] ND,SM0,SM1,BMI2,FUTURE */
        /* 262(002 202) 001(f7) 110 : SM0,SM1,NOAPX,VEX,BMI2,FUTURE */
        {I_SARX, 3, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,REG_GPR|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55143, 58},
    /*   9 : SARX reg64,reg8 [r+mv:      vex.lz.f3.0f38.w1 f7 /r           ] ND,SM0,BMI2,FUTURE */
        /* 261(002 202) 001(f7) 100 : SM0,NOAPX,VEX,BMI2,FUTURE */
        {I_SARX, 2, {REG_GPR|BITS64|RN_L16,REG_GPR|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55150, 59},
    /*  10 : SARX reg64,rm64*,reg16 [rmv:      vex.lz.f3.0f38.w1 f7 /r           ] ND,SM0,SM1,BMI2,FUTURE */
        /* 262(002 202) 001(f7) 110 : SM0,SM1,NOAPX,VEX,BMI2,FUTURE */
        {I_SARX, 3, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,REG_GPR|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55143, 58},
    /*  11 : SARX reg64,reg16 [r+mv:      vex.lz.f3.0f38.w1 f7 /r           ] ND,SM0,BMI2,FUTURE */
        /* 261(002 202) 001(f7) 100 : SM0,NOAPX,VEX,BMI2,FUTURE */
        {I_SARX, 2, {REG_GPR|BITS64|RN_L16,REG_GPR|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55150, 59},
    /*  12 : SARX reg64,rm64*,reg32 [rmv:      vex.lz.f3.0f38.w1 f7 /r           ] ND,SM0,SM1,BMI2,FUTURE */
        /* 262(002 202) 001(f7) 110 : SM0,SM1,NOAPX,VEX,BMI2,FUTURE */
        {I_SARX, 3, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55143, 58},
    /*  13 : SARX reg64,reg32 [r+mv:      vex.lz.f3.0f38.w1 f7 /r           ] ND,SM0,BMI2,FUTURE */
        /* 261(002 202) 001(f7) 100 : SM0,NOAPX,VEX,BMI2,FUTURE */
        {I_SARX, 2, {REG_GPR|BITS64|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55150, 59},
    /*  14 : SARX reg64,rm64*,reg64 [rmv:      vex.lz.f3.0f38.w1 f7 /r           ] SM0,SM1,BMI2,FUTURE */
        /* 262(002 202) 001(f7) 110 : SM0,SM1,NOAPX,VEX,BMI2,FUTURE */
        {I_SARX, 3, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55143, 58},
    /*  15 : SARX reg64,reg64 [r+mv:      vex.lz.f3.0f38.w1 f7 /r           ] ND,SM0,BMI2,FUTURE */
        /* 261(002 202) 001(f7) 100 : SM0,NOAPX,VEX,BMI2,FUTURE */
        {I_SARX, 2, {REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55150, 59},
    /*  16 : SARX reg32,rm32*,reg8 [rmv:      evex.lz.f3.0f38.w0 f7 /r          ] ND,SM0,SM1,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 7e 08) 300 001(f7) 110 : SM0,SM1,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SARX, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24156, 68},
    /*  17 : SARX reg32,reg8 [r+mv:      evex.lz.f3.0f38.w0 f7 /r          ] ND,SM0,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 7e 08) 300 001(f7) 100 : SM0,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SARX, 2, {REG_GPR|BITS32,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+24165, 69},
    /*  18 : SARX reg32,rm32*,reg16 [rmv:      evex.lz.f3.0f38.w0 f7 /r          ] ND,SM0,SM1,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 7e 08) 300 001(f7) 110 : SM0,SM1,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SARX, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+24156, 68},
    /*  19 : SARX reg32,reg16 [r+mv:      evex.lz.f3.0f38.w0 f7 /r          ] ND,SM0,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 7e 08) 300 001(f7) 100 : SM0,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SARX, 2, {REG_GPR|BITS32,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+24165, 69},
    /*  20 : SARX reg32,rm32*,reg32 [rmv:      evex.lz.f3.0f38.w0 f7 /r          ] SM0,SM1,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 7e 08) 300 001(f7) 110 : SM0,SM1,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SARX, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+24156, 68},
    /*  21 : SARX reg32,reg32 [r+mv:      evex.lz.f3.0f38.w0 f7 /r          ] ND,SM0,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 7e 08) 300 001(f7) 100 : SM0,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SARX, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+24165, 69},
    /*  22 : SARX reg32,rm32*,reg64 [rmv:      evex.lz.f3.0f38.w0 f7 /r          ] ND,SM0,SM1,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 7e 08) 300 001(f7) 110 : SM0,SM1,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SARX, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+24156, 68},
    /*  23 : SARX reg32,reg64 [r+mv:      evex.lz.f3.0f38.w0 f7 /r          ] ND,SM0,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 7e 08) 300 001(f7) 100 : SM0,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SARX, 2, {REG_GPR|BITS32,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+24165, 69},
    /*  24 : SARX reg64,rm64*,reg8 [rmv:      evex.lz.f3.0f38.w1 f7 /r          ] ND,SM0,SM1,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 fe 08) 300 001(f7) 110 : SM0,SM1,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SARX, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24210, 68},
    /*  25 : SARX reg64,reg8 [r+mv:      evex.lz.f3.0f38.w1 f7 /r          ] ND,SM0,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 fe 08) 300 001(f7) 100 : SM0,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SARX, 2, {REG_GPR|BITS64,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+24219, 69},
    /*  26 : SARX reg64,rm64*,reg16 [rmv:      evex.lz.f3.0f38.w1 f7 /r          ] ND,SM0,SM1,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 fe 08) 300 001(f7) 110 : SM0,SM1,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SARX, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+24210, 68},
    /*  27 : SARX reg64,reg16 [r+mv:      evex.lz.f3.0f38.w1 f7 /r          ] ND,SM0,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 fe 08) 300 001(f7) 100 : SM0,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SARX, 2, {REG_GPR|BITS64,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+24219, 69},
    /*  28 : SARX reg64,rm64*,reg32 [rmv:      evex.lz.f3.0f38.w1 f7 /r          ] ND,SM0,SM1,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 fe 08) 300 001(f7) 110 : SM0,SM1,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SARX, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+24210, 68},
    /*  29 : SARX reg64,reg32 [r+mv:      evex.lz.f3.0f38.w1 f7 /r          ] ND,SM0,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 fe 08) 300 001(f7) 100 : SM0,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SARX, 2, {REG_GPR|BITS64,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+24219, 69},
    /*  30 : SARX reg64,rm64*,reg64 [rmv:      evex.lz.f3.0f38.w1 f7 /r          ] SM0,SM1,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 fe 08) 300 001(f7) 110 : SM0,SM1,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SARX, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+24210, 68},
    /*  31 : SARX reg64,reg64 [r+mv:      evex.lz.f3.0f38.w1 f7 /r          ] ND,SM0,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 fe 08) 300 001(f7) 100 : SM0,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SARX, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+24219, 69},
};

static const struct itemplate instrux_SHRX[32] = {
    /*   0 : SHRX reg32,rm32*,reg8 [rmv:      vex.lz.f2.0f38.w0 f7 /r           ] ND,SM0,SM1,BMI2,FUTURE */
        /* 262(002 003) 001(f7) 110 : SM0,SM1,NOAPX,VEX,BMI2,FUTURE */
        {I_SHRX, 3, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,REG_GPR|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55115, 58},
    /*   1 : SHRX reg32,reg8 [r+mv:      vex.lz.f2.0f38.w0 f7 /r           ] ND,SM0,BMI2,FUTURE */
        /* 261(002 003) 001(f7) 100 : SM0,NOAPX,VEX,BMI2,FUTURE */
        {I_SHRX, 2, {REG_GPR|BITS32|RN_L16,REG_GPR|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55122, 59},
    /*   2 : SHRX reg32,rm32*,reg16 [rmv:      vex.lz.f2.0f38.w0 f7 /r           ] ND,SM0,SM1,BMI2,FUTURE */
        /* 262(002 003) 001(f7) 110 : SM0,SM1,NOAPX,VEX,BMI2,FUTURE */
        {I_SHRX, 3, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,REG_GPR|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55115, 58},
    /*   3 : SHRX reg32,reg16 [r+mv:      vex.lz.f2.0f38.w0 f7 /r           ] ND,SM0,BMI2,FUTURE */
        /* 261(002 003) 001(f7) 100 : SM0,NOAPX,VEX,BMI2,FUTURE */
        {I_SHRX, 2, {REG_GPR|BITS32|RN_L16,REG_GPR|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55122, 59},
    /*   4 : SHRX reg32,rm32*,reg32 [rmv:      vex.lz.f2.0f38.w0 f7 /r           ] SM0,SM1,BMI2,FUTURE */
        /* 262(002 003) 001(f7) 110 : SM0,SM1,NOAPX,VEX,BMI2,FUTURE */
        {I_SHRX, 3, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55115, 58},
    /*   5 : SHRX reg32,reg32 [r+mv:      vex.lz.f2.0f38.w0 f7 /r           ] ND,SM0,BMI2,FUTURE */
        /* 261(002 003) 001(f7) 100 : SM0,NOAPX,VEX,BMI2,FUTURE */
        {I_SHRX, 2, {REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55122, 59},
    /*   6 : SHRX reg32,rm32*,reg64 [rmv:      vex.lz.f2.0f38.w0 f7 /r           ] ND,SM0,SM1,BMI2,FUTURE */
        /* 262(002 003) 001(f7) 110 : SM0,SM1,NOAPX,VEX,BMI2,FUTURE */
        {I_SHRX, 3, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55115, 58},
    /*   7 : SHRX reg32,reg64 [r+mv:      vex.lz.f2.0f38.w0 f7 /r           ] ND,SM0,BMI2,FUTURE */
        /* 261(002 003) 001(f7) 100 : SM0,NOAPX,VEX,BMI2,FUTURE */
        {I_SHRX, 2, {REG_GPR|BITS32|RN_L16,REG_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55122, 59},
    /*   8 : SHRX reg64,rm64*,reg8 [rmv:      vex.lz.f2.0f38.w1 f7 /r           ] ND,SM0,SM1,BMI2,FUTURE */
        /* 262(002 203) 001(f7) 110 : SM0,SM1,NOAPX,VEX,BMI2,FUTURE */
        {I_SHRX, 3, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,REG_GPR|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55157, 58},
    /*   9 : SHRX reg64,reg8 [r+mv:      vex.lz.f2.0f38.w1 f7 /r           ] ND,SM0,BMI2,FUTURE */
        /* 261(002 203) 001(f7) 100 : SM0,NOAPX,VEX,BMI2,FUTURE */
        {I_SHRX, 2, {REG_GPR|BITS64|RN_L16,REG_GPR|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55164, 59},
    /*  10 : SHRX reg64,rm64*,reg16 [rmv:      vex.lz.f2.0f38.w1 f7 /r           ] ND,SM0,SM1,BMI2,FUTURE */
        /* 262(002 203) 001(f7) 110 : SM0,SM1,NOAPX,VEX,BMI2,FUTURE */
        {I_SHRX, 3, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,REG_GPR|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55157, 58},
    /*  11 : SHRX reg64,reg16 [r+mv:      vex.lz.f2.0f38.w1 f7 /r           ] ND,SM0,BMI2,FUTURE */
        /* 261(002 203) 001(f7) 100 : SM0,NOAPX,VEX,BMI2,FUTURE */
        {I_SHRX, 2, {REG_GPR|BITS64|RN_L16,REG_GPR|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55164, 59},
    /*  12 : SHRX reg64,rm64*,reg32 [rmv:      vex.lz.f2.0f38.w1 f7 /r           ] ND,SM0,SM1,BMI2,FUTURE */
        /* 262(002 203) 001(f7) 110 : SM0,SM1,NOAPX,VEX,BMI2,FUTURE */
        {I_SHRX, 3, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55157, 58},
    /*  13 : SHRX reg64,reg32 [r+mv:      vex.lz.f2.0f38.w1 f7 /r           ] ND,SM0,BMI2,FUTURE */
        /* 261(002 203) 001(f7) 100 : SM0,NOAPX,VEX,BMI2,FUTURE */
        {I_SHRX, 2, {REG_GPR|BITS64|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55164, 59},
    /*  14 : SHRX reg64,rm64*,reg64 [rmv:      vex.lz.f2.0f38.w1 f7 /r           ] SM0,SM1,BMI2,FUTURE */
        /* 262(002 203) 001(f7) 110 : SM0,SM1,NOAPX,VEX,BMI2,FUTURE */
        {I_SHRX, 3, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55157, 58},
    /*  15 : SHRX reg64,reg64 [r+mv:      vex.lz.f2.0f38.w1 f7 /r           ] ND,SM0,BMI2,FUTURE */
        /* 261(002 203) 001(f7) 100 : SM0,NOAPX,VEX,BMI2,FUTURE */
        {I_SHRX, 2, {REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55164, 59},
    /*  16 : SHRX reg32,rm32*,reg8 [rmv:      evex.lz.f2.0f38.w0 f7 /r          ] ND,SM0,SM1,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 7f 08) 300 001(f7) 110 : SM0,SM1,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHRX, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24174, 68},
    /*  17 : SHRX reg32,reg8 [r+mv:      evex.lz.f2.0f38.w0 f7 /r          ] ND,SM0,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 7f 08) 300 001(f7) 100 : SM0,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHRX, 2, {REG_GPR|BITS32,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+24183, 69},
    /*  18 : SHRX reg32,rm32*,reg16 [rmv:      evex.lz.f2.0f38.w0 f7 /r          ] ND,SM0,SM1,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 7f 08) 300 001(f7) 110 : SM0,SM1,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHRX, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+24174, 68},
    /*  19 : SHRX reg32,reg16 [r+mv:      evex.lz.f2.0f38.w0 f7 /r          ] ND,SM0,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 7f 08) 300 001(f7) 100 : SM0,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHRX, 2, {REG_GPR|BITS32,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+24183, 69},
    /*  20 : SHRX reg32,rm32*,reg32 [rmv:      evex.lz.f2.0f38.w0 f7 /r          ] SM0,SM1,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 7f 08) 300 001(f7) 110 : SM0,SM1,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHRX, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+24174, 68},
    /*  21 : SHRX reg32,reg32 [r+mv:      evex.lz.f2.0f38.w0 f7 /r          ] ND,SM0,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 7f 08) 300 001(f7) 100 : SM0,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHRX, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+24183, 69},
    /*  22 : SHRX reg32,rm32*,reg64 [rmv:      evex.lz.f2.0f38.w0 f7 /r          ] ND,SM0,SM1,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 7f 08) 300 001(f7) 110 : SM0,SM1,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHRX, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+24174, 68},
    /*  23 : SHRX reg32,reg64 [r+mv:      evex.lz.f2.0f38.w0 f7 /r          ] ND,SM0,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 7f 08) 300 001(f7) 100 : SM0,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHRX, 2, {REG_GPR|BITS32,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+24183, 69},
    /*  24 : SHRX reg64,rm64*,reg8 [rmv:      evex.lz.f2.0f38.w1 f7 /r          ] ND,SM0,SM1,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 ff 08) 300 001(f7) 110 : SM0,SM1,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHRX, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24228, 68},
    /*  25 : SHRX reg64,reg8 [r+mv:      evex.lz.f2.0f38.w1 f7 /r          ] ND,SM0,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 ff 08) 300 001(f7) 100 : SM0,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHRX, 2, {REG_GPR|BITS64,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+24237, 69},
    /*  26 : SHRX reg64,rm64*,reg16 [rmv:      evex.lz.f2.0f38.w1 f7 /r          ] ND,SM0,SM1,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 ff 08) 300 001(f7) 110 : SM0,SM1,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHRX, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+24228, 68},
    /*  27 : SHRX reg64,reg16 [r+mv:      evex.lz.f2.0f38.w1 f7 /r          ] ND,SM0,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 ff 08) 300 001(f7) 100 : SM0,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHRX, 2, {REG_GPR|BITS64,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+24237, 69},
    /*  28 : SHRX reg64,rm64*,reg32 [rmv:      evex.lz.f2.0f38.w1 f7 /r          ] ND,SM0,SM1,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 ff 08) 300 001(f7) 110 : SM0,SM1,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHRX, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+24228, 68},
    /*  29 : SHRX reg64,reg32 [r+mv:      evex.lz.f2.0f38.w1 f7 /r          ] ND,SM0,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 ff 08) 300 001(f7) 100 : SM0,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHRX, 2, {REG_GPR|BITS64,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+24237, 69},
    /*  30 : SHRX reg64,rm64*,reg64 [rmv:      evex.lz.f2.0f38.w1 f7 /r          ] SM0,SM1,LONG,PROT,BMI2,APX,X86_64 */
        /* 242(f2 ff 08) 300 001(f7) 110 : SM0,SM1,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHRX, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+24228, 68},
    /*  31 : SHRX reg64,reg64 [r+mv:      evex.lz.f2.0f38.w1 f7 /r          ] ND,SM0,LONG,PROT,BMI2,APX,X86_64 */
        /* 241(f2 ff 08) 300 001(f7) 100 : SM0,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_SHRX, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+24237, 69},
};

static const struct itemplate instrux_INC[18] = {
    /*   0 : INC reg16 [r:        o16 40+r                          ] NOREX,NOAPX,NOLONG,FL,8086 */
        /* 320 010 100 : NOREX,NOAPX,NOLONG,FL,8086 */
        {I_INC, 1, {REG_GPR|BITS16|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72489, 72},
    /*   1 : INC reg32 [r:        o32 40+r                          ] NOREX,NOAPX,NOLONG,FL,386 */
        /* 321 010 100 : NOREX,NOAPX,NOLONG,FL,386 */
        {I_INC, 1, {REG_GPR|BITS32|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72493, 73},
    /*   2 : INC rm8 [m:        hle o8 fe /0                      ] LOCK,FL,8086 */
        /* 273 001(fe) 200 : LOCK,FL,8086 */
        {I_INC, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71463, 74},
    /*   3 : INC rm16 [m:        hle o16 ff /0                     ] LOCK,FL,8086 */
        /* 273 320 001(ff) 200 : LOCK,FL,8086 */
        {I_INC, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66494, 74},
    /*   4 : INC rm32 [m:        hle o32 ff /0                     ] LOCK,FL,386 */
        /* 273 321 001(ff) 200 : LOCK,FL,386 */
        {I_INC, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66500, 75},
    /*   5 : INC rm64 [m:        hle o64 ff /0                     ] LOCK,LONG,FL,PROT,X86_64 */
        /* 273 324 001(ff) 200 : LOCK,LONG,FL,PROT,X86_64 */
        {I_INC, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66506, 76},
    /*   6 : INC reg8?,rm8 [vm:       evex.nf.nd1.l0.m4.o8 fe /0        ] NF,ZU,LOCK,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(fe) 210 : NF,NF_E,ZU,WIG,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_INC, 2, {REG_GPR|BITS8,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+24246, 77},
    /*   7 : INC rm8 [m:       evex.nf.nd0.l0.m4.o8 fe /0        ] NF,LOCK,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(fe) 200 : NF,NF_E,WIG,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_INC, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+24255, 78},
    /*   8 : INC reg8? [v+m:       evex.nf.nd1.l0.m4.o8 fe /0        ] ND,NF,ZU,LOCK,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(fe) 200 : NF,NF_E,ZU,WIG,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_INC, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+24264, 77},
    /*   9 : INC reg16?,rm16 [vm:       evex.nf.nd1.l0.m4.o16 ff /0       ] NF,ZU,LOCK,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(ff) 210 : NF,NF_E,ZU,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_INC, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12153, 79},
    /*  10 : INC rm16 [m:       evex.nf.nd0.l0.m4.o16 ff /0       ] NF,LOCK,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(ff) 200 : NF,NF_E,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_INC, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12163, 80},
    /*  11 : INC reg16? [v+m:       evex.nf.nd1.l0.m4.o16 ff /0       ] ND,NF,ZU,LOCK,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(ff) 200 : NF,NF_E,ZU,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_INC, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12173, 79},
    /*  12 : INC reg32?,rm32 [vm:       evex.nf.nd1.l0.m4.o32 ff /0       ] NF,ZU,LOCK,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(ff) 210 : NF,NF_E,ZU,WW,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_INC, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+12183, 81},
    /*  13 : INC rm32 [m:       evex.nf.nd0.l0.m4.o32 ff /0       ] NF,LOCK,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(ff) 200 : NF,NF_E,WW,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_INC, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12193, 82},
    /*  14 : INC reg32? [v+m:       evex.nf.nd1.l0.m4.o32 ff /0       ] ND,NF,ZU,LOCK,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(ff) 200 : NF,NF_E,ZU,WW,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_INC, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12203, 81},
    /*  15 : INC reg64?,rm64 [vm:       evex.nf.nd1.l0.m4.o64 ff /0       ] NF,ZU,LOCK,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(ff) 210 : NF,NF_E,ZU,WW,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_INC, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+12213, 81},
    /*  16 : INC rm64 [m:       evex.nf.nd0.l0.m4.o64 ff /0       ] NF,LOCK,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(ff) 200 : NF,NF_E,WW,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_INC, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12223, 82},
    /*  17 : INC reg64? [v+m:       evex.nf.nd1.l0.m4.o64 ff /0       ] ND,NF,ZU,LOCK,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(ff) 200 : NF,NF_E,ZU,WW,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_INC, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12233, 81},
};

static const struct itemplate instrux_DEC[18] = {
    /*   0 : DEC reg16 [r:        o16 48+r                          ] NOREX,NOAPX,NOLONG,FL,8086 */
        /* 320 010 110 : NOREX,NOAPX,NOLONG,FL,8086 */
        {I_DEC, 1, {REG_GPR|BITS16|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72497, 72},
    /*   1 : DEC reg32 [r:        o32 48+r                          ] NOREX,NOAPX,NOLONG,FL,386 */
        /* 321 010 110 : NOREX,NOAPX,NOLONG,FL,386 */
        {I_DEC, 1, {REG_GPR|BITS32|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72501, 73},
    /*   2 : DEC rm8 [m:        hle o8 fe /1                      ] LOCK,FL,8086 */
        /* 273 001(fe) 201 : LOCK,FL,8086 */
        {I_DEC, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71468, 74},
    /*   3 : DEC rm16 [m:        hle o16 ff /1                     ] LOCK,FL,8086 */
        /* 273 320 001(ff) 201 : LOCK,FL,8086 */
        {I_DEC, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66512, 74},
    /*   4 : DEC rm32 [m:        hle o32 ff /1                     ] LOCK,FL,386 */
        /* 273 321 001(ff) 201 : LOCK,FL,386 */
        {I_DEC, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66518, 75},
    /*   5 : DEC rm64 [m:        hle o64 ff /1                     ] LOCK,LONG,FL,PROT,X86_64 */
        /* 273 324 001(ff) 201 : LOCK,LONG,FL,PROT,X86_64 */
        {I_DEC, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66524, 76},
    /*   6 : DEC reg8?,rm8 [vm:       evex.nf.nd1.l0.m4.o8 fe /1        ] NF,ZU,LOCK,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(fe) 211 : NF,NF_E,ZU,WIG,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_DEC, 2, {REG_GPR|BITS8,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+24273, 77},
    /*   7 : DEC rm8 [m:       evex.nf.nd0.l0.m4.o8 fe /1        ] NF,LOCK,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(fe) 201 : NF,NF_E,WIG,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_DEC, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+24282, 78},
    /*   8 : DEC reg8? [v+m:       evex.nf.nd1.l0.m4.o8 fe /1        ] ND,NF,ZU,LOCK,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(fe) 201 : NF,NF_E,ZU,WIG,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_DEC, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+24291, 77},
    /*   9 : DEC reg16?,rm16 [vm:       evex.nf.nd1.l0.m4.o16 ff /1       ] NF,ZU,LOCK,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(ff) 211 : NF,NF_E,ZU,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_DEC, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12243, 79},
    /*  10 : DEC rm16 [m:       evex.nf.nd0.l0.m4.o16 ff /1       ] NF,LOCK,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(ff) 201 : NF,NF_E,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_DEC, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12253, 80},
    /*  11 : DEC reg16? [v+m:       evex.nf.nd1.l0.m4.o16 ff /1       ] ND,NF,ZU,LOCK,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(ff) 201 : NF,NF_E,ZU,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_DEC, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12263, 79},
    /*  12 : DEC reg32?,rm32 [vm:       evex.nf.nd1.l0.m4.o32 ff /1       ] NF,ZU,LOCK,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(ff) 211 : NF,NF_E,ZU,WW,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_DEC, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+12273, 81},
    /*  13 : DEC rm32 [m:       evex.nf.nd0.l0.m4.o32 ff /1       ] NF,LOCK,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(ff) 201 : NF,NF_E,WW,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_DEC, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12283, 82},
    /*  14 : DEC reg32? [v+m:       evex.nf.nd1.l0.m4.o32 ff /1       ] ND,NF,ZU,LOCK,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(ff) 201 : NF,NF_E,ZU,WW,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_DEC, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12293, 81},
    /*  15 : DEC reg64?,rm64 [vm:       evex.nf.nd1.l0.m4.o64 ff /1       ] NF,ZU,LOCK,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(ff) 211 : NF,NF_E,ZU,WW,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_DEC, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+12303, 81},
    /*  16 : DEC rm64 [m:       evex.nf.nd0.l0.m4.o64 ff /1       ] NF,LOCK,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(ff) 201 : NF,NF_E,WW,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_DEC, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12313, 82},
    /*  17 : DEC reg64? [v+m:       evex.nf.nd1.l0.m4.o64 ff /1       ] ND,NF,ZU,LOCK,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(ff) 201 : NF,NF_E,ZU,WW,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_DEC, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12323, 81},
};

static const struct itemplate instrux_IMUL[38] = {
    /*   0 : IMUL rm8 [m:        o8 f6 /5                          ] FL,8086 */
        /* 001(f6) 205 : FL,8086 */
        {I_IMUL, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+24305, 54},
    /*   1 : IMUL rm16 [m:        o16 f7 /5                         ] FL,8086 */
        /* 320 001(f7) 205 : FL,8086 */
        {I_IMUL, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12338, 54},
    /*   2 : IMUL rm32 [m:        o32 f7 /5                         ] FL,386 */
        /* 321 001(f7) 205 : FL,386 */
        {I_IMUL, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12348, 55},
    /*   3 : IMUL rm64 [m:        o64 f7 /5                         ] LONG,FL,PROT,X86_64 */
        /* 324 001(f7) 205 : LONG,FL,PROT,X86_64 */
        {I_IMUL, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12358, 56},
    /*   4 : IMUL rm8 [m:        evex.nf.nd0.l0.m4.o8 f6 /5        ] SM0,NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(f6) 205 : SM0,NF,NF_E,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_IMUL, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+24300, 83},
    /*   5 : IMUL rm16 [m:        evex.nf.nd0.l0.m4.o16 f7 /5       ] SM0,NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(f7) 205 : SM0,NF,NF_E,LONG,EVEX,PROT,APX,X86_64 */
        {I_IMUL, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12333, 84},
    /*   6 : IMUL rm32 [m:        evex.nf.nd0.l0.m4.o32 f7 /5       ] SM0,NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(f7) 205 : SM0,NF,NF_E,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_IMUL, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12343, 85},
    /*   7 : IMUL rm64 [m:        evex.nf.nd0.l0.m4.o64 f7 /5       ] SM0,NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(f7) 205 : SM0,NF,NF_E,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_IMUL, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12353, 85},
    /*   8 : IMUL reg16,rm16 [rm:       o16 0f af /r                      ] SM0-1,FL,386 */
        /* 320 355 001(af) 110 : SM0,SM1,FL,386 */
        {I_IMUL, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66530, 29},
    /*   9 : IMUL reg32,rm32 [rm:       o32 0f af /r                      ] SM0-1,FL,386 */
        /* 321 355 001(af) 110 : SM0,SM1,FL,386 */
        {I_IMUL, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+66536, 29},
    /*  10 : IMUL reg64,rm64 [rm:       o64 0f af /r                      ] SM0-1,LONG,FL,PROT,X86_64 */
        /* 324 355 001(af) 110 : SM0,SM1,LONG,FL,PROT,X86_64 */
        {I_IMUL, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+66542, 30},
    /*  11 : IMUL reg16,rm16*,sbyteword16 [rmi:      o16 6b /r ib,s                    ] SM0,SM1,SM2,FL,186 */
        /* 320 001(6b) 110 276 : SM0,SM1,SM2,FL,186 */
        {I_IMUL, 3, {REG_GPR|BITS16,RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2108, 86},
    /*  12 : IMUL reg16,sbyteword16 [r+mi:      o16 6b /r ib,s                    ] ND,SM0,SM1,FL,186 */
        /* 320 001(6b) 100 275 : SM0,SM1,FL,186 */
        {I_IMUL, 2, {REG_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+66548, 87},
    /*  13 : IMUL reg32,rm32*,sbytedword32 [rmi:      o32 6b /r ib,s                    ] SM0,SM1,SM2,FL,386 */
        /* 321 001(6b) 110 276 : SM0,SM1,SM2,FL,386 */
        {I_IMUL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2119, 88},
    /*  14 : IMUL reg32,sbytedword32 [r+mi:      o32 6b /r ib,s                    ] ND,SM0,SM1,FL,386 */
        /* 321 001(6b) 100 275 : SM0,SM1,FL,386 */
        {I_IMUL, 2, {REG_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+66554, 29},
    /*  15 : IMUL reg64,rm64*,sbytedword64 [rmi:      o64 6b /r ib,s                    ] SM0,SM1,SM2,LONG,FL,PROT,X86_64 */
        /* 324 001(6b) 110 276 : SM0,SM1,SM2,LONG,FL,PROT,X86_64 */
        {I_IMUL, 3, {REG_GPR|BITS64,RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2130, 89},
    /*  16 : IMUL reg64,sbytedword64 [r+mi:      o64 6b /r ib,s                    ] ND,SM0,SM1,LONG,FL,PROT,X86_64 */
        /* 324 001(6b) 100 275 : SM0,SM1,LONG,FL,PROT,X86_64 */
        {I_IMUL, 2, {REG_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+66560, 30},
    /*  17 : IMUL reg16,rm16*,imm16 [rmi:      o16 69 /r iw                      ] SM0,SM1,SM2,FL,186 */
        /* 320 001(69) 110 032 : SM0,SM1,SM2,FL,186 */
        {I_IMUL, 3, {REG_GPR|BITS16,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+2141, 86},
    /*  18 : IMUL reg16,imm16 [r+mi:      o16 69 /r iw                      ] ND,SM0,SM1,FL,186 */
        /* 320 001(69) 100 031 : SM0,SM1,FL,186 */
        {I_IMUL, 2, {REG_GPR|BITS16,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66566, 87},
    /*  19 : IMUL reg32,rm32*,imm32 [rmi:      o32 69 /r id                      ] SM0,SM1,SM2,FL,386 */
        /* 321 001(69) 110 042 : SM0,SM1,SM2,FL,386 */
        {I_IMUL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+2152, 88},
    /*  20 : IMUL reg32,imm32 [r+mi:      o32 69 /r id                      ] ND,SM0,SM1,FL,386 */
        /* 321 001(69) 100 041 : SM0,SM1,FL,386 */
        {I_IMUL, 2, {REG_GPR|BITS32,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+66572, 29},
    /*  21 : IMUL reg64,rm64*,sdword64 [rmi:      o64 69 /r id,s                    ] SM0,SM1,SM2,LONG,FL,PROT,X86_64 */
        /* 324 001(69) 110 256 : SM0,SM1,SM2,LONG,FL,PROT,X86_64 */
        {I_IMUL, 3, {REG_GPR|BITS64,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2163, 89},
    /*  22 : IMUL reg64,sdword64 [r+mi:      o64 69 /r id,s                    ] ND,SM0,SM1,LONG,FL,PROT,X86_64 */
        /* 324 001(69) 100 255 : SM0,SM1,LONG,FL,PROT,X86_64 */
        {I_IMUL, 2, {REG_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+66578, 30},
    /*  23 : IMUL reg16?,reg16,rm16 [vrm:      evex.nf.nd1.l0.m4.o16 af /r       ] SM0,SM1,SM2,NF,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(af) 121 : SM0,SM1,SM2,NF,NF_E,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_IMUL, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+12363, 90},
    /*  24 : IMUL reg16,rm16 [rm:      evex.nf.nd0.l0.m4.o16 af /r       ] SM0,SM1,NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(af) 110 : SM0,SM1,NF,NF_E,LONG,EVEX,PROT,APX,X86_64 */
        {I_IMUL, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12373, 91},
    /*  25 : IMUL reg16?,rm16 [v+rm:      evex.nf.nd1.l0.m4.o16 af /r       ] ND,SM0,SM1,NF,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(af) 110 : SM0,SM1,NF,NF_E,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_IMUL, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12383, 92},
    /*  26 : IMUL reg32?,reg32,rm32 [vrm:      evex.nf.nd1.l0.m4.o32 af /r       ] SM0,SM1,SM2,NF,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(af) 121 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_IMUL, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+12393, 93},
    /*  27 : IMUL reg32,rm32 [rm:      evex.nf.nd0.l0.m4.o32 af /r       ] SM0,SM1,NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(af) 110 : SM0,SM1,NF,NF_E,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_IMUL, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+12403, 94},
    /*  28 : IMUL reg32?,rm32 [v+rm:      evex.nf.nd1.l0.m4.o32 af /r       ] ND,SM0,SM1,NF,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(af) 110 : SM0,SM1,NF,NF_E,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_IMUL, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+12413, 95},
    /*  29 : IMUL reg64?,reg64,rm64 [vrm:      evex.nf.nd1.l0.m4.o64 af /r       ] SM0,SM1,SM2,NF,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(af) 121 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_IMUL, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+12423, 93},
    /*  30 : IMUL reg64,rm64 [rm:      evex.nf.nd0.l0.m4.o64 af /r       ] SM0,SM1,NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(af) 110 : SM0,SM1,NF,NF_E,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_IMUL, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+12433, 94},
    /*  31 : IMUL reg64?,rm64 [v+rm:      evex.nf.nd1.l0.m4.o64 af /r       ] ND,SM0,SM1,NF,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(af) 110 : SM0,SM1,NF,NF_E,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_IMUL, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+12443, 95},
    /*  32 : IMUL reg16,rm16,sbyteword16 [rmi:      evex.nf.zu.l0.m4.o16 6b /r ib,s   ] SM0-2,NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(6b) 110 276 : SM0,SM1,SM2,NF,NF_E,ZU,ZU_E,LONG,EVEX,PROT,APX,X86_64 */
        {I_IMUL, 3, {REG_GPR|BITS16,RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2103, 96},
    /*  33 : IMUL reg32,rm32,sbytedword32 [rmi:      evex.nf.zu.l0.m4.o32 6b /r ib,s   ] SM0-2,NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(6b) 110 276 : SM0,SM1,SM2,NF,NF_E,ZU,ZU_E,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_IMUL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2114, 97},
    /*  34 : IMUL reg64,rm64,sbytedword64 [rmi:      evex.nf.zu.l0.m4.o64 6b /r ib,s   ] SM0-2,NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(6b) 110 276 : SM0,SM1,SM2,NF,NF_E,ZU,ZU_E,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_IMUL, 3, {REG_GPR|BITS64,RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2125, 97},
    /*  35 : IMUL reg16,rm16,imm16 [rmi:      evex.nf.zu.l0.m4.o16 69 /r iw     ] SM0-2,NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(69) 110 032 : SM0,SM1,SM2,NF,NF_E,ZU,ZU_E,LONG,EVEX,PROT,APX,X86_64 */
        {I_IMUL, 3, {REG_GPR|BITS16,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+2136, 96},
    /*  36 : IMUL reg32,rm32,imm32 [rmi:      evex.nf.zu.l0.m4.o32 69 /r id     ] SM0-2,NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(69) 110 042 : SM0,SM1,SM2,NF,NF_E,ZU,ZU_E,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_IMUL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+2147, 97},
    /*  37 : IMUL reg64,rm64,sdword64 [rmi:      evex.nf.zu.l0.m4.o64 69 /r id,s   ] SM0-2,NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(69) 110 256 : SM0,SM1,SM2,NF,NF_E,ZU,ZU_E,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_IMUL, 3, {REG_GPR|BITS64,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2158, 97},
};

static const struct itemplate instrux_MUL[42] = {
    /*   0 : MUL rm8 [m:        o8 f6 /4                          ] FL,8086 */
        /* 001(f6) 204 : FL,8086 */
        {I_MUL, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+24350, 54},
    /*   1 : MUL rm16 [m:        o16 f7 /4                         ] FL,8086 */
        /* 320 001(f7) 204 : FL,8086 */
        {I_MUL, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12458, 54},
    /*   2 : MUL rm32 [m:        o32 f7 /4                         ] FL,386 */
        /* 321 001(f7) 204 : FL,386 */
        {I_MUL, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12468, 55},
    /*   3 : MUL rm64 [m:        o64 f7 /4                         ] LONG,FL,PROT,X86_64 */
        /* 324 001(f7) 204 : LONG,FL,PROT,X86_64 */
        {I_MUL, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12478, 56},
    /*   4 : MUL reg32,reg32*,rm32 [rvm:      vex.ndd.lz.f2.0f38.w0 f6 /r       ] ND,OPT,NF,NF_R,BMI2,FUTURE */
        /* 261(002 003) 001(f6) 120 : OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_MUL, 3, {REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55171, 102},
    /*   5 : MUL reg32,rm32 [r+vm:      vex.ndd.lz.f2.0f38.w0 f6 /r       ] ND,OPT,NF,NF_R,BMI2,FUTURE */
        /* 260(002 003) 001(f6) 110 : OPT,NOAPX,NF,NF_R,VEX,BMI2,FUTURE */
        {I_MUL, 2, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55178, 102},
    /*   6 : MUL reg64,reg64*,rm64 [rvm:      vex.ndd.lz.f2.0f38.w1 f6 /r       ] ND,OPT,NF,NF_R,LONG,PROT,BMI2,X86_64 */
        /* 261(002 203) 001(f6) 120 : OPT,NOAPX,NF,NF_R,LONG,VEX,PROT,BMI2,X86_64 */
        {I_MUL, 3, {REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55185, 103},
    /*   7 : MUL reg64,rm64 [r+vm:      vex.ndd.lz.f2.0f38.w1 f6 /r       ] ND,OPT,NF,NF_R,LONG,PROT,BMI2,X86_64 */
        /* 260(002 203) 001(f6) 110 : OPT,NOAPX,NF,NF_R,LONG,VEX,PROT,BMI2,X86_64 */
        {I_MUL, 2, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55192, 103},
    /*   8 : MUL rm8 [m:        evex.nf.nd0.l0.m4.o8 f6 /4        ] SM0,NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(f6) 204 : SM0,NF,NF_E,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_MUL, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+24345, 83},
    /*   9 : MUL rm16 [m:        evex.nf.nd0.l0.m4.o16 f7 /4       ] SM0,NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(f7) 204 : SM0,NF,NF_E,LONG,EVEX,PROT,APX,X86_64 */
        {I_MUL, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12453, 84},
    /*  10 : MUL rm32 [m:        evex.nf.nd0.l0.m4.o32 f7 /4       ] SM0,NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(f7) 204 : SM0,NF,NF_E,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_MUL, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12463, 85},
    /*  11 : MUL rm64 [m:        evex.nf.nd0.l0.m4.o64 f7 /4       ] SM0,NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(f7) 204 : SM0,NF,NF_E,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_MUL, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12473, 85},
    /*  12 : MUL reg16,rm16 [rm:       o16 0f af /r                      ] ND,SM0-1,FL,386 */
        /* 320 355 001(af) 110 : SM0,SM1,FL,386 */
        {I_MUL, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66530, 29},
    /*  13 : MUL reg32,rm32 [rm:       o32 0f af /r                      ] ND,SM0-1,FL,386 */
        /* 321 355 001(af) 110 : SM0,SM1,FL,386 */
        {I_MUL, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+66536, 29},
    /*  14 : MUL reg64,rm64 [rm:       o64 0f af /r                      ] ND,SM0-1,LONG,FL,PROT,X86_64 */
        /* 324 355 001(af) 110 : SM0,SM1,LONG,FL,PROT,X86_64 */
        {I_MUL, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+66542, 30},
    /*  15 : MUL reg16,rm16*,sbyteword16 [rmi:      o16 6b /r ib,s                    ] ND,SM0,SM1,SM2,FL,186 */
        /* 320 001(6b) 110 276 : SM0,SM1,SM2,FL,186 */
        {I_MUL, 3, {REG_GPR|BITS16,RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2108, 86},
    /*  16 : MUL reg16,sbyteword16 [r+mi:      o16 6b /r ib,s                    ] ND,SM0,SM1,FL,186 */
        /* 320 001(6b) 100 275 : SM0,SM1,FL,186 */
        {I_MUL, 2, {REG_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+66548, 87},
    /*  17 : MUL reg32,rm32*,sbytedword32 [rmi:      o32 6b /r ib,s                    ] ND,SM0,SM1,SM2,FL,386 */
        /* 321 001(6b) 110 276 : SM0,SM1,SM2,FL,386 */
        {I_MUL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2119, 88},
    /*  18 : MUL reg32,sbytedword32 [r+mi:      o32 6b /r ib,s                    ] ND,SM0,SM1,FL,386 */
        /* 321 001(6b) 100 275 : SM0,SM1,FL,386 */
        {I_MUL, 2, {REG_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+66554, 29},
    /*  19 : MUL reg64,rm64*,sbytedword64 [rmi:      o64 6b /r ib,s                    ] ND,SM0,SM1,SM2,LONG,FL,PROT,X86_64 */
        /* 324 001(6b) 110 276 : SM0,SM1,SM2,LONG,FL,PROT,X86_64 */
        {I_MUL, 3, {REG_GPR|BITS64,RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2130, 89},
    /*  20 : MUL reg64,sbytedword64 [r+mi:      o64 6b /r ib,s                    ] ND,SM0,SM1,LONG,FL,PROT,X86_64 */
        /* 324 001(6b) 100 275 : SM0,SM1,LONG,FL,PROT,X86_64 */
        {I_MUL, 2, {REG_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+66560, 30},
    /*  21 : MUL reg16,rm16*,imm16 [rmi:      o16 69 /r iw                      ] ND,SM0,SM1,SM2,FL,186 */
        /* 320 001(69) 110 032 : SM0,SM1,SM2,FL,186 */
        {I_MUL, 3, {REG_GPR|BITS16,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+2141, 86},
    /*  22 : MUL reg16,imm16 [r+mi:      o16 69 /r iw                      ] ND,SM0,SM1,FL,186 */
        /* 320 001(69) 100 031 : SM0,SM1,FL,186 */
        {I_MUL, 2, {REG_GPR|BITS16,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66566, 87},
    /*  23 : MUL reg32,rm32*,imm32 [rmi:      o32 69 /r id                      ] ND,SM0,SM1,SM2,FL,386 */
        /* 321 001(69) 110 042 : SM0,SM1,SM2,FL,386 */
        {I_MUL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+2152, 88},
    /*  24 : MUL reg32,imm32 [r+mi:      o32 69 /r id                      ] ND,SM0,SM1,FL,386 */
        /* 321 001(69) 100 041 : SM0,SM1,FL,386 */
        {I_MUL, 2, {REG_GPR|BITS32,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+66572, 29},
    /*  25 : MUL reg64,rm64*,sdword64 [rmi:      o64 69 /r id,s                    ] ND,SM0,SM1,SM2,LONG,FL,PROT,X86_64 */
        /* 324 001(69) 110 256 : SM0,SM1,SM2,LONG,FL,PROT,X86_64 */
        {I_MUL, 3, {REG_GPR|BITS64,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2163, 89},
    /*  26 : MUL reg64,sdword64 [r+mi:      o64 69 /r id,s                    ] ND,SM0,SM1,LONG,FL,PROT,X86_64 */
        /* 324 001(69) 100 255 : SM0,SM1,LONG,FL,PROT,X86_64 */
        {I_MUL, 2, {REG_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+66578, 30},
    /*  27 : MUL reg16?,reg16,rm16 [vrm:      evex.nf.nd1.l0.m4.o16 af /r       ] ND,SM0,SM1,SM2,NF,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(af) 121 : SM0,SM1,SM2,NF,NF_E,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_MUL, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+12363, 90},
    /*  28 : MUL reg16,rm16 [rm:      evex.nf.nd0.l0.m4.o16 af /r       ] ND,SM0,SM1,NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(af) 110 : SM0,SM1,NF,NF_E,LONG,EVEX,PROT,APX,X86_64 */
        {I_MUL, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12373, 91},
    /*  29 : MUL reg16?,rm16 [v+rm:      evex.nf.nd1.l0.m4.o16 af /r       ] ND,SM0,SM1,NF,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(af) 110 : SM0,SM1,NF,NF_E,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_MUL, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12383, 92},
    /*  30 : MUL reg32?,reg32,rm32 [vrm:      evex.nf.nd1.l0.m4.o32 af /r       ] ND,SM0,SM1,SM2,NF,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(af) 121 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_MUL, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+12393, 93},
    /*  31 : MUL reg32,rm32 [rm:      evex.nf.nd0.l0.m4.o32 af /r       ] ND,SM0,SM1,NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(af) 110 : SM0,SM1,NF,NF_E,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_MUL, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+12403, 94},
    /*  32 : MUL reg32?,rm32 [v+rm:      evex.nf.nd1.l0.m4.o32 af /r       ] ND,SM0,SM1,NF,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(af) 110 : SM0,SM1,NF,NF_E,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_MUL, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+12413, 95},
    /*  33 : MUL reg64?,reg64,rm64 [vrm:      evex.nf.nd1.l0.m4.o64 af /r       ] ND,SM0,SM1,SM2,NF,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(af) 121 : SM0,SM1,SM2,NF,NF_E,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_MUL, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+12423, 93},
    /*  34 : MUL reg64,rm64 [rm:      evex.nf.nd0.l0.m4.o64 af /r       ] ND,SM0,SM1,NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(af) 110 : SM0,SM1,NF,NF_E,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_MUL, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+12433, 94},
    /*  35 : MUL reg64?,rm64 [v+rm:      evex.nf.nd1.l0.m4.o64 af /r       ] ND,SM0,SM1,NF,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(af) 110 : SM0,SM1,NF,NF_E,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_MUL, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+12443, 95},
    /*  36 : MUL reg16,rm16,sbyteword16 [rmi:      evex.nf.zu.l0.m4.o16 6b /r ib,s   ] ND,SM0-2,NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(6b) 110 276 : SM0,SM1,SM2,NF,NF_E,ZU,ZU_E,LONG,EVEX,PROT,APX,X86_64 */
        {I_MUL, 3, {REG_GPR|BITS16,RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2103, 96},
    /*  37 : MUL reg32,rm32,sbytedword32 [rmi:      evex.nf.zu.l0.m4.o32 6b /r ib,s   ] ND,SM0-2,NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(6b) 110 276 : SM0,SM1,SM2,NF,NF_E,ZU,ZU_E,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_MUL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2114, 97},
    /*  38 : MUL reg64,rm64,sbytedword64 [rmi:      evex.nf.zu.l0.m4.o64 6b /r ib,s   ] ND,SM0-2,NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(6b) 110 276 : SM0,SM1,SM2,NF,NF_E,ZU,ZU_E,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_MUL, 3, {REG_GPR|BITS64,RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2125, 97},
    /*  39 : MUL reg16,rm16,imm16 [rmi:      evex.nf.zu.l0.m4.o16 69 /r iw     ] ND,SM0-2,NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(69) 110 032 : SM0,SM1,SM2,NF,NF_E,ZU,ZU_E,LONG,EVEX,PROT,APX,X86_64 */
        {I_MUL, 3, {REG_GPR|BITS16,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+2136, 96},
    /*  40 : MUL reg32,rm32,imm32 [rmi:      evex.nf.zu.l0.m4.o32 69 /r id     ] ND,SM0-2,NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(69) 110 042 : SM0,SM1,SM2,NF,NF_E,ZU,ZU_E,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_MUL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+2147, 97},
    /*  41 : MUL reg64,rm64,sdword64 [rmi:      evex.nf.zu.l0.m4.o64 69 /r id,s   ] ND,SM0-2,NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(69) 110 256 : SM0,SM1,SM2,NF,NF_E,ZU,ZU_E,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_MUL, 3, {REG_GPR|BITS64,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2158, 97},
};

static const struct itemplate instrux_MULX[8] = {
    /*   0 : MULX reg32,reg32*,rm32 [rvm:      vex.ndd.lz.f2.0f38.w0 f6 /r      ] BMI2,FUTURE */
        /* 261(002 003) 001(f6) 120 : NOAPX,VEX,BMI2,FUTURE */
        {I_MULX, 3, {REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55171, 98},
    /*   1 : MULX reg32,reg32*,rm32 [rvm:      evex.ndd.lz.f2.0f38.w0 f6 /r      ] BMI2,FUTURE,APX */
        /* 241(f2 7f 08) 300 001(f6) 120 : LONG,EVEX,PROT,BMI2,APX,FUTURE */
        {I_MULX, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+24309, 99},
    /*   2 : MULX reg32,rm32 [r+vm:      vex.ndd.lz.f2.0f38.w0 f6 /r      ] ND,BMI2,FUTURE */
        /* 260(002 003) 001(f6) 110 : NOAPX,VEX,BMI2,FUTURE */
        {I_MULX, 2, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55178, 98},
    /*   3 : MULX reg32,rm32 [r+vm:      evex.ndd.lz.f2.0f38.w0 f6 /r      ] ND,BMI2,FUTURE,APX */
        /* 240(f2 7f 08) 300 001(f6) 110 : LONG,EVEX,PROT,BMI2,APX,FUTURE */
        {I_MULX, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+24318, 99},
    /*   4 : MULX reg64,reg64*,rm64 [rvm:      vex.ndd.lz.f2.0f38.w1 f6 /r      ] LONG,PROT,BMI2,X86_64 */
        /* 261(002 203) 001(f6) 120 : NOAPX,LONG,VEX,PROT,BMI2,X86_64 */
        {I_MULX, 3, {REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55185, 100},
    /*   5 : MULX reg64,reg64*,rm64 [rvm:      evex.ndd.lz.f2.0f38.w1 f6 /r      ] LONG,PROT,BMI2,X86_64,APX */
        /* 241(f2 ff 08) 300 001(f6) 120 : LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_MULX, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+24327, 101},
    /*   6 : MULX reg64,rm64 [r+vm:      vex.ndd.lz.f2.0f38.w1 f6 /r      ] ND,LONG,PROT,BMI2,X86_64 */
        /* 260(002 203) 001(f6) 110 : NOAPX,LONG,VEX,PROT,BMI2,X86_64 */
        {I_MULX, 2, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55192, 100},
    /*   7 : MULX reg64,rm64 [r+vm:      evex.ndd.lz.f2.0f38.w1 f6 /r      ] ND,LONG,PROT,BMI2,X86_64,APX */
        /* 240(f2 ff 08) 300 001(f6) 110 : LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_MULX, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+24336, 101},
};

static const struct itemplate instrux_IDIV[8] = {
    /*   0 : IDIV rm8 [m:        o8 f6 /7                          ] FL,8086 */
        /* 001(f6) 207 : FL,8086 */
        {I_IDIV, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+24359, 54},
    /*   1 : IDIV rm16 [m:        o16 f7 /7                         ] FL,8086 */
        /* 320 001(f7) 207 : FL,8086 */
        {I_IDIV, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12488, 54},
    /*   2 : IDIV rm32 [m:        o32 f7 /7                         ] FL,386 */
        /* 321 001(f7) 207 : FL,386 */
        {I_IDIV, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12498, 55},
    /*   3 : IDIV rm64 [m:        o64 f7 /7                         ] LONG,FL,PROT,X86_64 */
        /* 324 001(f7) 207 : LONG,FL,PROT,X86_64 */
        {I_IDIV, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12508, 56},
    /*   4 : IDIV rm8 [m:        evex.nf.nd0.l0.m4.o8 f6 /7        ] NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(f6) 207 : NF,NF_E,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_IDIV, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+24354, 104},
    /*   5 : IDIV rm16 [m:        evex.nf.nd0.l0.m4.o16 f7 /7       ] NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(f7) 207 : NF,NF_E,LONG,EVEX,PROT,APX,X86_64 */
        {I_IDIV, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12483, 105},
    /*   6 : IDIV rm32 [m:        evex.nf.nd0.l0.m4.o32 f7 /7       ] NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(f7) 207 : NF,NF_E,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_IDIV, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12493, 106},
    /*   7 : IDIV rm64 [m:        evex.nf.nd0.l0.m4.o64 f7 /7       ] NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(f7) 207 : NF,NF_E,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_IDIV, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12503, 106},
};

static const struct itemplate instrux_DIV[8] = {
    /*   0 : DIV rm8 [m:        o8 f6 /6                          ] FL,8086 */
        /* 001(f6) 206 : FL,8086 */
        {I_DIV, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+24368, 54},
    /*   1 : DIV rm16 [m:        o16 f7 /6                         ] FL,8086 */
        /* 320 001(f7) 206 : FL,8086 */
        {I_DIV, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12518, 54},
    /*   2 : DIV rm32 [m:        o32 f7 /6                         ] FL,386 */
        /* 321 001(f7) 206 : FL,386 */
        {I_DIV, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12528, 55},
    /*   3 : DIV rm64 [m:        o64 f7 /6                         ] LONG,FL,PROT,X86_64 */
        /* 324 001(f7) 206 : LONG,FL,PROT,X86_64 */
        {I_DIV, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12538, 56},
    /*   4 : DIV rm8 [m:        evex.nf.nd0.l0.m4.o8 f6 /6        ] NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(f6) 206 : NF,NF_E,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_DIV, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+24363, 104},
    /*   5 : DIV rm16 [m:        evex.nf.nd0.l0.m4.o16 f7 /6       ] NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(f7) 206 : NF,NF_E,LONG,EVEX,PROT,APX,X86_64 */
        {I_DIV, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12513, 105},
    /*   6 : DIV rm32 [m:        evex.nf.nd0.l0.m4.o32 f7 /6       ] NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(f7) 206 : NF,NF_E,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_DIV, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12523, 106},
    /*   7 : DIV rm64 [m:        evex.nf.nd0.l0.m4.o64 f7 /6       ] NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(f7) 206 : NF,NF_E,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_DIV, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12533, 106},
};

static const struct itemplate instrux_NEG[16] = {
    /*   0 : NEG rm8 [m:        hle o8 f6 /3                      ] LOCK,FL,8086 */
        /* 273 001(f6) 203 : LOCK,FL,8086 */
        {I_NEG, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71473, 74},
    /*   1 : NEG rm16 [m:        hle o16 f7 /3                     ] LOCK,FL,8086 */
        /* 273 320 001(f7) 203 : LOCK,FL,8086 */
        {I_NEG, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66584, 74},
    /*   2 : NEG rm32 [m:        hle o32 f7 /3                     ] LOCK,FL,386 */
        /* 273 321 001(f7) 203 : LOCK,FL,386 */
        {I_NEG, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66590, 75},
    /*   3 : NEG rm64 [m:        hle o64 f7 /3                     ] LOCK,LONG,FL,PROT,X86_64 */
        /* 273 324 001(f7) 203 : LOCK,LONG,FL,PROT,X86_64 */
        {I_NEG, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66596, 76},
    /*   4 : NEG reg8?,rm8 [vm:       evex.nf.nd1.l0.m4.o8 f6 /3        ] NF,ZU,LOCK,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(f6) 213 : NF,NF_E,ZU,WIG,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_NEG, 2, {REG_GPR|BITS8,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+24372, 77},
    /*   5 : NEG rm8 [m:       evex.nf.nd0.l0.m4.o8 f6 /3        ] NF,LOCK,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(f6) 203 : NF,NF_E,WIG,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_NEG, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+24381, 78},
    /*   6 : NEG reg8? [v+m:       evex.nf.nd1.l0.m4.o8 f6 /3        ] ND,NF,ZU,LOCK,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(f6) 203 : NF,NF_E,ZU,WIG,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_NEG, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+24390, 77},
    /*   7 : NEG reg16?,rm16 [vm:       evex.nf.nd1.l0.m4.o16 f7 /3       ] NF,ZU,LOCK,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(f7) 213 : NF,NF_E,ZU,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_NEG, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12543, 79},
    /*   8 : NEG rm16 [m:       evex.nf.nd0.l0.m4.o16 f7 /3       ] NF,LOCK,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(f7) 203 : NF,NF_E,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_NEG, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12553, 80},
    /*   9 : NEG reg16? [v+m:       evex.nf.nd1.l0.m4.o16 f7 /3       ] ND,NF,ZU,LOCK,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(f7) 203 : NF,NF_E,ZU,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_NEG, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12563, 79},
    /*  10 : NEG reg32?,rm32 [vm:       evex.nf.nd1.l0.m4.o32 f7 /3       ] NF,ZU,LOCK,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(f7) 213 : NF,NF_E,ZU,WW,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_NEG, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+12573, 81},
    /*  11 : NEG rm32 [m:       evex.nf.nd0.l0.m4.o32 f7 /3       ] NF,LOCK,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(f7) 203 : NF,NF_E,WW,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_NEG, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12583, 82},
    /*  12 : NEG reg32? [v+m:       evex.nf.nd1.l0.m4.o32 f7 /3       ] ND,NF,ZU,LOCK,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(f7) 203 : NF,NF_E,ZU,WW,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_NEG, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12593, 81},
    /*  13 : NEG reg64?,rm64 [vm:       evex.nf.nd1.l0.m4.o64 f7 /3       ] NF,ZU,LOCK,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(f7) 213 : NF,NF_E,ZU,WW,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_NEG, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+12603, 81},
    /*  14 : NEG rm64 [m:       evex.nf.nd0.l0.m4.o64 f7 /3       ] NF,LOCK,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(f7) 203 : NF,NF_E,WW,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_NEG, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12613, 82},
    /*  15 : NEG reg64? [v+m:       evex.nf.nd1.l0.m4.o64 f7 /3       ] ND,NF,ZU,LOCK,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(f7) 203 : NF,NF_E,ZU,WW,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_NEG, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12623, 81},
};

static const struct itemplate instrux_NOT[32] = {
    /*   0 : NOT rm8 [m:        hle o8 f6 /2                      ] LOCK,8086 */
        /* 273 001(f6) 202 : LOCK,8086 */
        {I_NOT, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71478, 107},
    /*   1 : NOT rm16 [m:        hle o16 f7 /2                     ] LOCK,8086 */
        /* 273 320 001(f7) 202 : LOCK,8086 */
        {I_NOT, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66602, 107},
    /*   2 : NOT rm32 [m:        hle o32 f7 /2                     ] LOCK,386 */
        /* 273 321 001(f7) 202 : LOCK,386 */
        {I_NOT, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66608, 108},
    /*   3 : NOT rm64 [m:        hle o64 f7 /2                     ] LOCK,LONG,PROT,X86_64 */
        /* 273 324 001(f7) 202 : LOCK,LONG,PROT,X86_64 */
        {I_NOT, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66614, 109},
    /*   4 : NOT reg8?,rm8 [vm:       evex.nf0.nd1.l0.m4.o8 f6 /2       ] ZU,LOCK,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(f6) 212 : ZU,WIG,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_NOT, 2, {REG_GPR|BITS8,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+24399, 110},
    /*   5 : NOT rm8 [m:       evex.nf0.nd0.l0.m4.o8 f6 /2       ] LOCK,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(f6) 202 : WIG,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_NOT, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+24408, 111},
    /*   6 : NOT reg8? [v+m:       evex.nf0.nd1.l0.m4.o8 f6 /2       ] ND,ZU,LOCK,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 001(f6) 202 : ZU,WIG,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_NOT, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+24417, 110},
    /*   7 : NOT reg16?,rm16 [vm:       evex.nf0.nd1.l0.m4.o16 f7 /2      ] ZU,LOCK,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(f7) 212 : ZU,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_NOT, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12633, 112},
    /*   8 : NOT rm16 [m:       evex.nf0.nd0.l0.m4.o16 f7 /2      ] LOCK,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(f7) 202 : LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_NOT, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12643, 113},
    /*   9 : NOT reg16? [v+m:       evex.nf0.nd1.l0.m4.o16 f7 /2      ] ND,ZU,LOCK,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(f7) 202 : ZU,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_NOT, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12653, 112},
    /*  10 : NOT reg32?,rm32 [vm:       evex.nf0.nd1.l0.m4.o32 f7 /2      ] ZU,LOCK,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(f7) 212 : ZU,WW,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_NOT, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+12663, 114},
    /*  11 : NOT rm32 [m:       evex.nf0.nd0.l0.m4.o32 f7 /2      ] LOCK,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(f7) 202 : WW,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_NOT, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12673, 115},
    /*  12 : NOT reg32? [v+m:       evex.nf0.nd1.l0.m4.o32 f7 /2      ] ND,ZU,LOCK,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(f7) 202 : ZU,WW,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_NOT, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12683, 114},
    /*  13 : NOT reg64?,rm64 [vm:       evex.nf0.nd1.l0.m4.o64 f7 /2      ] ZU,LOCK,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(f7) 212 : ZU,WW,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_NOT, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+12693, 114},
    /*  14 : NOT rm64 [m:       evex.nf0.nd0.l0.m4.o64 f7 /2      ] LOCK,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(f7) 202 : WW,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_NOT, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12703, 115},
    /*  15 : NOT reg64? [v+m:       evex.nf0.nd1.l0.m4.o64 f7 /2      ] ND,ZU,LOCK,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(f7) 202 : ZU,WW,LOCK,LONG,EVEX,PROT,APX,X86_64 */
        {I_NOT, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12713, 114},
    /*  16 : NOT kreg8,kreg8* [rm:       vex.l0.0f.ko8 44 /r              ] ND,SM0,SM1,ZU,AVX512DQ,FUTURE */
        /* 270(001 001) 001(44) 110 : SM0,SM1,NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_NOT, 2, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65398, 510},
    /*  17 : NOT kreg8,kreg8* [rm:       evex.l0.0f.ko8 44 /r              ] ND,SM0,SM1,ZU,AVX512DQ,FUTURE,APX */
        /* 250(f1 7d 08) 300 001(44) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_NOT, 2, {OPMASKREG|BITS8,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+30024, 511},
    /*  18 : NOT kreg8 [r+m:       vex.l0.0f.ko8 44 /r              ] ND,SM0,ZU,AVX512DQ,FUTURE */
        /* 270(001 001) 001(44) 100 : SM0,NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_NOT, 1, {OPMASKREG|BITS8|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+65405, 532},
    /*  19 : NOT kreg8 [r+m:       evex.l0.0f.ko8 44 /r              ] ND,SM0,ZU,AVX512DQ,FUTURE,APX */
        /* 250(f1 7d 08) 300 001(44) 100 : SM0,ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_NOT, 1, {OPMASKREG|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+30033, 533},
    /*  20 : NOT kreg16,kreg16* [rm:       vex.l0.0f.ko16 44 /r             ] ND,SM0,SM1,ZU,AVX512F,FUTURE */
        /* 270(001 000) 001(44) 110 : SM0,SM1,NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_NOT, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65412, 526},
    /*  21 : NOT kreg16,kreg16* [rm:       evex.l0.0f.ko16 44 /r             ] ND,SM0,SM1,ZU,AVX512F,FUTURE,APX */
        /* 250(f1 7c 08) 300 001(44) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_NOT, 2, {OPMASKREG|BITS16,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+30042, 527},
    /*  22 : NOT kreg16 [r+m:       vex.l0.0f.ko16 44 /r             ] ND,SM0,ZU,AVX512F,FUTURE */
        /* 270(001 000) 001(44) 100 : SM0,NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_NOT, 1, {OPMASKREG|BITS16|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+65419, 534},
    /*  23 : NOT kreg16 [r+m:       evex.l0.0f.ko16 44 /r             ] ND,SM0,ZU,AVX512F,FUTURE,APX */
        /* 250(f1 7c 08) 300 001(44) 100 : SM0,ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_NOT, 1, {OPMASKREG|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+30051, 535},
    /*  24 : NOT kreg32,kreg32* [rm:       vex.l0.0f.ko32 44 /r             ] ND,SM0,SM1,ZU,AVX512BW,FUTURE */
        /* 270(001 201) 001(44) 110 : SM0,SM1,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_NOT, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65426, 514},
    /*  25 : NOT kreg32,kreg32* [rm:       evex.l0.0f.ko32 44 /r             ] ND,SM0,SM1,ZU,AVX512BW,FUTURE,APX */
        /* 250(f1 fd 08) 300 001(44) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_NOT, 2, {OPMASKREG|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+30060, 515},
    /*  26 : NOT kreg32 [r+m:       vex.l0.0f.ko32 44 /r             ] ND,SM0,ZU,AVX512BW,FUTURE */
        /* 270(001 201) 001(44) 100 : SM0,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_NOT, 1, {OPMASKREG|BITS32|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+65433, 536},
    /*  27 : NOT kreg32 [r+m:       evex.l0.0f.ko32 44 /r             ] ND,SM0,ZU,AVX512BW,FUTURE,APX */
        /* 250(f1 fd 08) 300 001(44) 100 : SM0,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_NOT, 1, {OPMASKREG|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+30069, 537},
    /*  28 : NOT kreg64,kreg64* [rm:       vex.l0.0f.ko64 44 /r             ] ND,SM0,SM1,ZU,AVX512BW,FUTURE */
        /* 270(001 200) 001(44) 110 : SM0,SM1,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_NOT, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65440, 514},
    /*  29 : NOT kreg64,kreg64* [rm:       evex.l0.0f.ko64 44 /r             ] ND,SM0,SM1,ZU,AVX512BW,FUTURE,APX */
        /* 250(f1 fc 08) 300 001(44) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_NOT, 2, {OPMASKREG|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+30078, 515},
    /*  30 : NOT kreg64 [r+m:       vex.l0.0f.ko64 44 /r             ] ND,SM0,ZU,AVX512BW,FUTURE */
        /* 270(001 200) 001(44) 100 : SM0,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_NOT, 1, {OPMASKREG|BITS64|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+65447, 536},
    /*  31 : NOT kreg64 [r+m:       evex.l0.0f.ko64 44 /r             ] ND,SM0,ZU,AVX512BW,FUTURE,APX */
        /* 250(f1 fc 08) 300 001(44) 100 : SM0,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_NOT, 1, {OPMASKREG|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+30087, 537},
};

static const struct itemplate instrux_ADCX[6] = {
    /*   0 : ADCX reg32,rm32 [rm:       66 w0 0f38 f6 /r                  ] ZU,FL,ADX,FUTURE */
        /* 361 317 356 001(f6) 110 : NOAPX,ZU,FL,ADX,FUTURE */
        {I_ADCX, 2, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55199, 116},
    /*   1 : ADCX reg64,rm64 [rm:       66 w1 0f38 f6 /r                  ] ZU,LONG,FL,PROT,ADX,X86_64 */
        /* 361 324 356 001(f6) 110 : NOAPX,ZU,LONG,FL,PROT,ADX,X86_64 */
        {I_ADCX, 2, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55206, 117},
    /*   2 : ADCX reg32?,reg32,rm32 [vrm:      evex.nd1.l0.66.m4.w0 66 /r        ] ZU,LONG,FL,PROT,APX,ADX,X86_64 */
        /* 240(f4 7d 18) 300 001(66) 121 : ZU,LONG,FL,EVEX,PROT,APX,ADX,X86_64 */
        {I_ADCX, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+24426, 118},
    /*   3 : ADCX reg32,rm32 [rm:      evex.nd0.l0.66.m4.w0 66 /r        ] ZU,LONG,FL,PROT,APX,ADX,X86_64 */
        /* 250(f4 7d 08) 300 001(66) 110 : ZU,LONG,FL,EVEX,PROT,APX,ADX,X86_64 */
        {I_ADCX, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+24435, 118},
    /*   4 : ADCX reg64?,reg64,rm64 [vrm:      evex.nd1.l0.66.m4.w1 66 /r        ] ZU,LONG,FL,PROT,APX,ADX,X86_64 */
        /* 240(f4 fd 18) 300 001(66) 121 : ZU,LONG,FL,EVEX,PROT,APX,ADX,X86_64 */
        {I_ADCX, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+24444, 118},
    /*   5 : ADCX reg64,rm64 [rm:      evex.nd0.l0.66.m4.w1 66 /r        ] ZU,LONG,FL,PROT,APX,ADX,X86_64 */
        /* 250(f4 fd 08) 300 001(66) 110 : ZU,LONG,FL,EVEX,PROT,APX,ADX,X86_64 */
        {I_ADCX, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+24453, 118},
};

static const struct itemplate instrux_ADOX[6] = {
    /*   0 : ADOX reg32,rm32 [rm:       f3 !osp w0 0f38 f6 /r             ] ZU,FL,ADX,FUTURE */
        /* 333 364 317 356 001(f6) 110 : NOAPX,ZU,FL,ADX,FUTURE */
        {I_ADOX, 2, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+51109, 116},
    /*   1 : ADOX reg64,rm64 [rm:       f3 !osp w1 0f38 f6 /r             ] ZU,LONG,FL,PROT,ADX,X86_64 */
        /* 333 364 324 356 001(f6) 110 : NOAPX,ZU,LONG,FL,PROT,ADX,X86_64 */
        {I_ADOX, 2, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+51117, 117},
    /*   2 : ADOX reg32?,reg32,rm32 [vrm:      evex.nd1.l0.f3.m4.w0 66 /r        ] ZU,LONG,FL,PROT,APX,ADX,X86_64 */
        /* 240(f4 7e 18) 300 001(66) 121 : ZU,LONG,FL,EVEX,PROT,APX,ADX,X86_64 */
        {I_ADOX, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+24462, 118},
    /*   3 : ADOX reg32,rm32 [rm:      evex.nd0.l0.f3.m4.w0 66 /r        ] ZU,LONG,FL,PROT,APX,ADX,X86_64 */
        /* 250(f4 7e 08) 300 001(66) 110 : ZU,LONG,FL,EVEX,PROT,APX,ADX,X86_64 */
        {I_ADOX, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+24471, 118},
    /*   4 : ADOX reg64?,reg64,rm64 [vrm:      evex.nd1.l0.f3.m4.w1 66 /r        ] ZU,LONG,FL,PROT,APX,ADX,X86_64 */
        /* 240(f4 fe 18) 300 001(66) 121 : ZU,LONG,FL,EVEX,PROT,APX,ADX,X86_64 */
        {I_ADOX, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+24480, 118},
    /*   5 : ADOX reg64,rm64 [rm:      evex.nd0.l0.f3.m4.w1 66 /r        ] ZU,LONG,FL,PROT,APX,ADX,X86_64 */
        /* 250(f4 fe 08) 300 001(66) 110 : ZU,LONG,FL,EVEX,PROT,APX,ADX,X86_64 */
        {I_ADOX, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+24489, 118},
};

static const struct itemplate instrux_SHLD[26] = {
    /*   0 : SHLD rm16,reg16,imm8 [mri:      o16 0f a4 /r ib,u                 ] SM0-1,FL,386 */
        /* 320 355 001(a4) 101 026 : SM0,SM1,FL,386 */
        {I_SHLD, 3, {RM_GPR|BITS16,REG_GPR|BITS16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+55213, 29},
    /*   1 : SHLD rm32,reg32,imm8 [mri:      o32 0f a4 /r ib,u                 ] SM0-1,FL,386 */
        /* 321 355 001(a4) 101 026 : SM0,SM1,FL,386 */
        {I_SHLD, 3, {RM_GPR|BITS32,REG_GPR|BITS32,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+55220, 29},
    /*   2 : SHLD rm64,reg64,imm8 [mri:      o64 0f a4 /r ib,u                 ] SM0-1,LONG,FL,PROT,X86_64 */
        /* 324 355 001(a4) 101 026 : SM0,SM1,LONG,FL,PROT,X86_64 */
        {I_SHLD, 3, {RM_GPR|BITS64,REG_GPR|BITS64,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+55227, 30},
    /*   3 : SHLD rm16,reg16,reg_cl [mr-:      o16 0f a5 /r                      ] SM0-1,FL,386 */
        /* 320 355 001(a5) 101 : SM0,SM1,FL,386 */
        {I_SHLD, 3, {RM_GPR|BITS16,REG_GPR|BITS16,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+66620, 29},
    /*   4 : SHLD rm32,reg32,reg_cl [mr-:      o32 0f a5 /r                      ] SM0-1,FL,386 */
        /* 321 355 001(a5) 101 : SM0,SM1,FL,386 */
        {I_SHLD, 3, {RM_GPR|BITS32,REG_GPR|BITS32,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+66626, 29},
    /*   5 : SHLD rm64,reg64,reg_cl [mr-:      o64 0f a5 /r                      ] SM0-1,LONG,FL,PROT,X86_64 */
        /* 324 355 001(a5) 101 : SM0,SM1,LONG,FL,PROT,X86_64 */
        {I_SHLD, 3, {RM_GPR|BITS64,REG_GPR|BITS64,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+66632, 30},
    /*   6 : SHLD reg16?,rm16,reg16,imm8 [vmri:     evex.nd1.nf.l0.m4.o16 24 /r ib,u  ] SM0,SM1,NF,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(24) 112 027 : SM0,SM1,NF,NF_E,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_SHLD, 4, {REG_GPR|BITS16,RM_GPR|BITS16,REG_GPR|BITS16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+2169, 92},
    /*   7 : SHLD rm16,reg16,imm8 [mri:     evex.nd0.nf.l0.m4.o16 24 /r ib,u  ] SM0,NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(24) 101 026 : SM0,NF,NF_E,LONG,EVEX,PROT,APX,X86_64 */
        {I_SHLD, 3, {RM_GPR|BITS16,REG_GPR|BITS16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+2180, 84},
    /*   8 : SHLD reg16?,reg16,imm8 [v+mri:     evex.nd1.nf.l0.m4.o16 24 /r ib,u  ] ND,SM0,NF,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(24) 101 026 : SM0,NF,NF_E,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_SHLD, 3, {REG_GPR|BITS16,REG_GPR|BITS16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+2191, 119},
    /*   9 : SHLD reg32?,rm32,reg32,imm8 [vmri:     evex.nd1.nf.l0.m4.o32 24 /r ib,u  ] SM0,SM1,NF,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(24) 112 027 : SM0,SM1,NF,NF_E,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_SHLD, 4, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS32,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+2202, 95},
    /*  10 : SHLD rm32,reg32,imm8 [mri:     evex.nd0.nf.l0.m4.o32 24 /r ib,u  ] SM0,NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(24) 101 026 : SM0,NF,NF_E,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_SHLD, 3, {RM_GPR|BITS32,REG_GPR|BITS32,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+2213, 85},
    /*  11 : SHLD reg32?,reg32,imm8 [v+mri:     evex.nd1.nf.l0.m4.o32 24 /r ib,u  ] ND,SM0,NF,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(24) 101 026 : SM0,NF,NF_E,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_SHLD, 3, {REG_GPR|BITS32,REG_GPR|BITS32,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+2224, 120},
    /*  12 : SHLD reg64?,rm64,reg64,imm8 [vmri:     evex.nd1.nf.l0.m4.o64 24 /r ib,u  ] SM0,SM1,NF,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(24) 112 027 : SM0,SM1,NF,NF_E,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_SHLD, 4, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS64,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+2235, 95},
    /*  13 : SHLD rm64,reg64,imm8 [mri:     evex.nd0.nf.l0.m4.o64 24 /r ib,u  ] SM0,NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(24) 101 026 : SM0,NF,NF_E,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_SHLD, 3, {RM_GPR|BITS64,REG_GPR|BITS64,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+2246, 85},
    /*  14 : SHLD reg64?,reg64,imm8 [v+mri:     evex.nd1.nf.l0.m4.o64 24 /r ib,u  ] ND,SM0,NF,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(24) 101 026 : SM0,NF,NF_E,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_SHLD, 3, {REG_GPR|BITS64,REG_GPR|BITS64,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+2257, 120},
    /*  15 : SHLD reg16?,rm16,reg16,reg_cl [vmr-:     evex.nd1.nf.l0.m4.o16 a5 /r       ] SM0,SM1,NF,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(a5) 112 : SM0,SM1,NF,NF_E,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_SHLD, 4, {REG_GPR|BITS16,RM_GPR|BITS16,REG_GPR|BITS16,REG_CL,0}, NO_DECORATOR, nasm_bytecodes+12723, 92},
    /*  16 : SHLD rm16,reg16,reg_cl [mr-:     evex.nd0.nf.l0.m4.o16 a5 /r       ] SM0,NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(a5) 101 : SM0,NF,NF_E,LONG,EVEX,PROT,APX,X86_64 */
        {I_SHLD, 3, {RM_GPR|BITS16,REG_GPR|BITS16,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+12733, 84},
    /*  17 : SHLD reg16?,reg16,reg_cl [v+mr-:     evex.nd1.nf.l0.m4.o16 a5 /r       ] ND,SM0,NF,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(a5) 101 : SM0,NF,NF_E,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_SHLD, 3, {REG_GPR|BITS16,REG_GPR|BITS16,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+12743, 119},
    /*  18 : SHLD reg32?,rm32,reg32,reg_cl [vmr-:     evex.nd1.nf.l0.m4.o32 a5 /r       ] SM0,SM1,NF,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(a5) 112 : SM0,SM1,NF,NF_E,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_SHLD, 4, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS32,REG_CL,0}, NO_DECORATOR, nasm_bytecodes+12753, 95},
    /*  19 : SHLD rm32,reg32,reg_cl [mr-:     evex.nd0.nf.l0.m4.o32 a5 /r       ] SM0,NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(a5) 101 : SM0,NF,NF_E,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_SHLD, 3, {RM_GPR|BITS32,REG_GPR|BITS32,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+12763, 85},
    /*  20 : SHLD reg32?,reg32,reg_cl [v+mr-:     evex.nd1.nf.l0.m4.o32 a5 /r       ] ND,SM0,NF,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(a5) 101 : SM0,NF,NF_E,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_SHLD, 3, {REG_GPR|BITS32,REG_GPR|BITS32,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+12773, 120},
    /*  21 : SHLD reg64?,rm64,reg64,reg_cl [vmr-:     evex.nd1.nf.l0.m4.o64 a5 /r       ] SM0,SM1,NF,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(a5) 112 : SM0,SM1,NF,NF_E,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_SHLD, 4, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS64,REG_CL,0}, NO_DECORATOR, nasm_bytecodes+12783, 95},
    /*  22 : SHLD rm64,reg64,reg_cl [mr-:     evex.nd0.nf.l0.m4.o64 a5 /r       ] SM0,NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(a5) 101 : SM0,NF,NF_E,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_SHLD, 3, {RM_GPR|BITS64,REG_GPR|BITS64,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+12793, 85},
    /*  23 : SHLD reg64?,reg64,reg_cl [v+mr-:     evex.nd1.nf.l0.m4.o64 a5 /r       ] ND,SM0,NF,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(a5) 101 : SM0,NF,NF_E,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_SHLD, 3, {REG_GPR|BITS64,REG_GPR|BITS64,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+12803, 120},
    /*  24 : SHLD kreg32,kreg32,imm8 [rmi:      vex.l0.66.0f3a.w0 33 /r ib       ] ND,ZU,FL,AVX512BW,FUTURE */
        /* 270(003 001) 001(33) 110 022 : NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_SHLD, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54589, 542},
    /*  25 : SHLD kreg32,kreg32,imm8 [rmi:      evex.l0.66.0f3a.w0 33 /r ib       ] ND,ZU,FL,AVX512BW,FUTURE,APX */
        /* 250(f3 7d 08) 300 001(33) 110 022 : ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_SHLD, 3, {OPMASKREG|BITS32,OPMASKREG|BITS32,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18073, 543},
};

static const struct itemplate instrux_SHRD[26] = {
    /*   0 : SHRD rm16,reg16,imm8 [mri:      o16 0f ac /r ib,u                 ] SM0-1,FL,386 */
        /* 320 355 001(ac) 101 026 : SM0,SM1,FL,386 */
        {I_SHRD, 3, {RM_GPR|BITS16,REG_GPR|BITS16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+55234, 29},
    /*   1 : SHRD rm32,reg32,imm8 [mri:      o32 0f ac /r ib,u                 ] SM0-1,FL,386 */
        /* 321 355 001(ac) 101 026 : SM0,SM1,FL,386 */
        {I_SHRD, 3, {RM_GPR|BITS32,REG_GPR|BITS32,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+55241, 29},
    /*   2 : SHRD rm64,reg64,imm8 [mri:      o64 0f ac /r ib,u                 ] SM0-1,LONG,FL,PROT,X86_64 */
        /* 324 355 001(ac) 101 026 : SM0,SM1,LONG,FL,PROT,X86_64 */
        {I_SHRD, 3, {RM_GPR|BITS64,REG_GPR|BITS64,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+55248, 30},
    /*   3 : SHRD rm16,reg16,reg_cl [mr-:      o16 0f ad /r                      ] SM0-1,FL,386 */
        /* 320 355 001(ad) 101 : SM0,SM1,FL,386 */
        {I_SHRD, 3, {RM_GPR|BITS16,REG_GPR|BITS16,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+66638, 29},
    /*   4 : SHRD rm32,reg32,reg_cl [mr-:      o32 0f ad /r                      ] SM0-1,FL,386 */
        /* 321 355 001(ad) 101 : SM0,SM1,FL,386 */
        {I_SHRD, 3, {RM_GPR|BITS32,REG_GPR|BITS32,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+66644, 29},
    /*   5 : SHRD rm64,reg64,reg_cl [mr-:      o64 0f ad /r                      ] SM0-1,LONG,FL,PROT,X86_64 */
        /* 324 355 001(ad) 101 : SM0,SM1,LONG,FL,PROT,X86_64 */
        {I_SHRD, 3, {RM_GPR|BITS64,REG_GPR|BITS64,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+66650, 30},
    /*   6 : SHRD reg16?,rm16,reg16,imm8 [vmri:     evex.nd1.nf.l0.m4.o16 2c /r ib,u  ] SM0,SM1,NF,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(2c) 112 027 : SM0,SM1,NF,NF_E,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_SHRD, 4, {REG_GPR|BITS16,RM_GPR|BITS16,REG_GPR|BITS16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+2268, 92},
    /*   7 : SHRD rm16,reg16,imm8 [mri:     evex.nd0.nf.l0.m4.o16 2c /r ib,u  ] SM0,NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(2c) 101 026 : SM0,NF,NF_E,LONG,EVEX,PROT,APX,X86_64 */
        {I_SHRD, 3, {RM_GPR|BITS16,REG_GPR|BITS16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+2279, 84},
    /*   8 : SHRD reg16?,reg16,imm8 [v+mri:     evex.nd1.nf.l0.m4.o16 2c /r ib,u  ] ND,SM0,NF,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(2c) 101 026 : SM0,NF,NF_E,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_SHRD, 3, {REG_GPR|BITS16,REG_GPR|BITS16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+2290, 119},
    /*   9 : SHRD reg32?,rm32,reg32,imm8 [vmri:     evex.nd1.nf.l0.m4.o32 2c /r ib,u  ] SM0,SM1,NF,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(2c) 112 027 : SM0,SM1,NF,NF_E,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_SHRD, 4, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS32,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+2301, 95},
    /*  10 : SHRD rm32,reg32,imm8 [mri:     evex.nd0.nf.l0.m4.o32 2c /r ib,u  ] SM0,NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(2c) 101 026 : SM0,NF,NF_E,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_SHRD, 3, {RM_GPR|BITS32,REG_GPR|BITS32,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+2312, 85},
    /*  11 : SHRD reg32?,reg32,imm8 [v+mri:     evex.nd1.nf.l0.m4.o32 2c /r ib,u  ] ND,SM0,NF,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(2c) 101 026 : SM0,NF,NF_E,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_SHRD, 3, {REG_GPR|BITS32,REG_GPR|BITS32,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+2323, 120},
    /*  12 : SHRD reg64?,rm64,reg64,imm8 [vmri:     evex.nd1.nf.l0.m4.o64 2c /r ib,u  ] SM0,SM1,NF,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(2c) 112 027 : SM0,SM1,NF,NF_E,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_SHRD, 4, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS64,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+2334, 95},
    /*  13 : SHRD rm64,reg64,imm8 [mri:     evex.nd0.nf.l0.m4.o64 2c /r ib,u  ] SM0,NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(2c) 101 026 : SM0,NF,NF_E,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_SHRD, 3, {RM_GPR|BITS64,REG_GPR|BITS64,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+2345, 85},
    /*  14 : SHRD reg64?,reg64,imm8 [v+mri:     evex.nd1.nf.l0.m4.o64 2c /r ib,u  ] ND,SM0,NF,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(2c) 101 026 : SM0,NF,NF_E,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_SHRD, 3, {REG_GPR|BITS64,REG_GPR|BITS64,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+2356, 120},
    /*  15 : SHRD reg16?,rm16,reg16,reg_cl [vmr-:     evex.nd1.nf.l0.m4.o16 ad /r       ] SM0,SM1,NF,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(ad) 112 : SM0,SM1,NF,NF_E,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_SHRD, 4, {REG_GPR|BITS16,RM_GPR|BITS16,REG_GPR|BITS16,REG_CL,0}, NO_DECORATOR, nasm_bytecodes+12813, 92},
    /*  16 : SHRD rm16,reg16,reg_cl [mr-:     evex.nd0.nf.l0.m4.o16 ad /r       ] SM0,NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(ad) 101 : SM0,NF,NF_E,LONG,EVEX,PROT,APX,X86_64 */
        {I_SHRD, 3, {RM_GPR|BITS16,REG_GPR|BITS16,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+12823, 84},
    /*  17 : SHRD reg16?,reg16,reg_cl [v+mr-:     evex.nd1.nf.l0.m4.o16 ad /r       ] ND,SM0,NF,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(ad) 101 : SM0,NF,NF_E,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_SHRD, 3, {REG_GPR|BITS16,REG_GPR|BITS16,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+12833, 119},
    /*  18 : SHRD reg32?,rm32,reg32,reg_cl [vmr-:     evex.nd1.nf.l0.m4.o32 ad /r       ] SM0,SM1,NF,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(ad) 112 : SM0,SM1,NF,NF_E,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_SHRD, 4, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS32,REG_CL,0}, NO_DECORATOR, nasm_bytecodes+12843, 95},
    /*  19 : SHRD rm32,reg32,reg_cl [mr-:     evex.nd0.nf.l0.m4.o32 ad /r       ] SM0,NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(ad) 101 : SM0,NF,NF_E,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_SHRD, 3, {RM_GPR|BITS32,REG_GPR|BITS32,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+12853, 85},
    /*  20 : SHRD reg32?,reg32,reg_cl [v+mr-:     evex.nd1.nf.l0.m4.o32 ad /r       ] ND,SM0,NF,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(ad) 101 : SM0,NF,NF_E,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_SHRD, 3, {REG_GPR|BITS32,REG_GPR|BITS32,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+12863, 120},
    /*  21 : SHRD reg64?,rm64,reg64,reg_cl [vmr-:     evex.nd1.nf.l0.m4.o64 ad /r       ] SM0,SM1,NF,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(ad) 112 : SM0,SM1,NF,NF_E,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_SHRD, 4, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS64,REG_CL,0}, NO_DECORATOR, nasm_bytecodes+12873, 95},
    /*  22 : SHRD rm64,reg64,reg_cl [mr-:     evex.nd0.nf.l0.m4.o64 ad /r       ] SM0,NF,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(ad) 101 : SM0,NF,NF_E,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_SHRD, 3, {RM_GPR|BITS64,REG_GPR|BITS64,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+12883, 85},
    /*  23 : SHRD reg64?,reg64,reg_cl [v+mr-:     evex.nd1.nf.l0.m4.o64 ad /r       ] ND,SM0,NF,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(ad) 101 : SM0,NF,NF_E,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_SHRD, 3, {REG_GPR|BITS64,REG_GPR|BITS64,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+12893, 120},
    /*  24 : SHRD kreg32,kreg32,imm8 [rmi:      vex.l0.66.0f3a.w0 31 /r ib       ] ND,ZU,FL,AVX512BW,FUTURE */
        /* 270(003 001) 001(31) 110 022 : NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_SHRD, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54621, 542},
    /*  25 : SHRD kreg32,kreg32,imm8 [rmi:      evex.l0.66.0f3a.w0 31 /r ib       ] ND,ZU,FL,AVX512BW,FUTURE,APX */
        /* 250(f3 7d 08) 300 001(31) 110 022 : ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_SHRD, 3, {OPMASKREG|BITS32,OPMASKREG|BITS32,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18113, 543},
};

static const struct itemplate instrux_BT[6] = {
    /*   0 : BT rm16,reg16 [mr:       o16 0f a3 /r                      ] SM0-1,FL,386 */
        /* 320 355 001(a3) 101 : SM0,SM1,FL,386 */
        {I_BT, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66656, 29},
    /*   1 : BT rm32,reg32 [mr:       o32 0f a3 /r                      ] SM0-1,FL,386 */
        /* 321 355 001(a3) 101 : SM0,SM1,FL,386 */
        {I_BT, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+66662, 29},
    /*   2 : BT rm64,reg64 [mr:       o64 0f a3 /r                      ] SM0-1,LONG,FL,PROT,X86_64 */
        /* 324 355 001(a3) 101 : SM0,SM1,LONG,FL,PROT,X86_64 */
        {I_BT, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+66668, 30},
    /*   3 : BT rm16,imm8 [mi:       o16 0f ba /4 ib,u                 ] FL,386 */
        /* 320 355 001(ba) 204 025 : FL,386 */
        {I_BT, 2, {RM_GPR|BITS16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+55255, 55},
    /*   4 : BT rm32,imm8 [mi:       o32 0f ba /4 ib,u                 ] FL,386 */
        /* 321 355 001(ba) 204 025 : FL,386 */
        {I_BT, 2, {RM_GPR|BITS32,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+55262, 55},
    /*   5 : BT rm64,imm8 [mi:       o64 0f ba /4 ib,u                 ] LONG,FL,PROT,X86_64 */
        /* 324 355 001(ba) 204 025 : LONG,FL,PROT,X86_64 */
        {I_BT, 2, {RM_GPR|BITS64,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+55269, 56},
};

static const struct itemplate instrux_BTC[6] = {
    /*   0 : BTC rm16,reg16 [mr:       o16 0f bb /r                      ] SM0-1,LOCK,FL,386 */
        /* 320 355 001(bb) 101 : SM0,SM1,LOCK,FL,386 */
        {I_BTC, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66674, 26},
    /*   1 : BTC rm32,reg32 [mr:       o32 0f bb /r                      ] SM0-1,LOCK,FL,386 */
        /* 321 355 001(bb) 101 : SM0,SM1,LOCK,FL,386 */
        {I_BTC, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+66680, 26},
    /*   2 : BTC rm64,reg64 [mr:       o64 0f bb /r                      ] SM0-1,LOCK,LONG,FL,PROT,X86_64 */
        /* 324 355 001(bb) 101 : SM0,SM1,LOCK,LONG,FL,PROT,X86_64 */
        {I_BTC, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+66686, 27},
    /*   3 : BTC rm16,imm8 [mi:       o16 0f ba /7 ib,u                 ] LOCK,FL,386 */
        /* 320 355 001(ba) 207 025 : LOCK,FL,386 */
        {I_BTC, 2, {RM_GPR|BITS16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+55276, 75},
    /*   4 : BTC rm32,imm8 [mi:       o32 0f ba /7 ib,u                 ] LOCK,FL,386 */
        /* 321 355 001(ba) 207 025 : LOCK,FL,386 */
        {I_BTC, 2, {RM_GPR|BITS32,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+55283, 75},
    /*   5 : BTC rm64,imm8 [mi:       o64 0f ba /7 ib,u                 ] LOCK,LONG,FL,PROT,X86_64 */
        /* 324 355 001(ba) 207 025 : LOCK,LONG,FL,PROT,X86_64 */
        {I_BTC, 2, {RM_GPR|BITS64,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+55290, 76},
};

static const struct itemplate instrux_BTR[6] = {
    /*   0 : BTR rm16,reg16 [mr:       o16 0f b3 /r                      ] SM0-1,LOCK,FL,386 */
        /* 320 355 001(b3) 101 : SM0,SM1,LOCK,FL,386 */
        {I_BTR, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66692, 26},
    /*   1 : BTR rm32,reg32 [mr:       o32 0f b3 /r                      ] SM0-1,LOCK,FL,386 */
        /* 321 355 001(b3) 101 : SM0,SM1,LOCK,FL,386 */
        {I_BTR, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+66698, 26},
    /*   2 : BTR rm64,reg64 [mr:       o64 0f b3 /r                      ] SM0-1,LOCK,LONG,FL,PROT,X86_64 */
        /* 324 355 001(b3) 101 : SM0,SM1,LOCK,LONG,FL,PROT,X86_64 */
        {I_BTR, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+66704, 27},
    /*   3 : BTR rm16,imm8 [mi:       o16 0f ba /6 ib,u                 ] LOCK,FL,386 */
        /* 320 355 001(ba) 206 025 : LOCK,FL,386 */
        {I_BTR, 2, {RM_GPR|BITS16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+55297, 75},
    /*   4 : BTR rm32,imm8 [mi:       o32 0f ba /6 ib,u                 ] LOCK,FL,386 */
        /* 321 355 001(ba) 206 025 : LOCK,FL,386 */
        {I_BTR, 2, {RM_GPR|BITS32,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+55304, 75},
    /*   5 : BTR rm64,imm8 [mi:       o64 0f ba /6 ib,u                 ] LOCK,LONG,FL,PROT,X86_64 */
        /* 324 355 001(ba) 206 025 : LOCK,LONG,FL,PROT,X86_64 */
        {I_BTR, 2, {RM_GPR|BITS64,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+55311, 76},
};

static const struct itemplate instrux_BTS[6] = {
    /*   0 : BTS rm16,reg16 [mr:       o16 0f ab /r                      ] SM0-1,LOCK,FL,386 */
        /* 320 355 001(ab) 101 : SM0,SM1,LOCK,FL,386 */
        {I_BTS, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66710, 26},
    /*   1 : BTS rm32,reg32 [mr:       o32 0f ab /r                      ] SM0-1,LOCK,FL,386 */
        /* 321 355 001(ab) 101 : SM0,SM1,LOCK,FL,386 */
        {I_BTS, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+66716, 26},
    /*   2 : BTS rm64,reg64 [mr:       o64 0f ab /r                      ] SM0-1,LOCK,LONG,FL,PROT,X86_64 */
        /* 324 355 001(ab) 101 : SM0,SM1,LOCK,LONG,FL,PROT,X86_64 */
        {I_BTS, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+66722, 27},
    /*   3 : BTS rm16,imm8 [mi:       o16 0f ba /5 ib,u                 ] LOCK,FL,386 */
        /* 320 355 001(ba) 205 025 : LOCK,FL,386 */
        {I_BTS, 2, {RM_GPR|BITS16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+55318, 75},
    /*   4 : BTS rm32,imm8 [mi:       o32 0f ba /5 ib,u                 ] LOCK,FL,386 */
        /* 321 355 001(ba) 205 025 : LOCK,FL,386 */
        {I_BTS, 2, {RM_GPR|BITS32,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+55325, 75},
    /*   5 : BTS rm64,imm8 [mi:       o64 0f ba /5 ib,u                 ] LOCK,LONG,FL,PROT,X86_64 */
        /* 324 355 001(ba) 205 025 : LOCK,LONG,FL,PROT,X86_64 */
        {I_BTS, 2, {RM_GPR|BITS64,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+55332, 76},
};

static const struct itemplate instrux_BSF[3] = {
    /*   0 : BSF reg16,rm16 [rm:       o16 nof3 0f bc /r                 ] SM0-1,386 */
        /* 320 326 355 001(bc) 110 : SM0,SM1,386 */
        {I_BSF, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55339, 13},
    /*   1 : BSF reg32,rm32 [rm:       o32 nof3 0f bc /r                 ] SM0-1,386 */
        /* 321 326 355 001(bc) 110 : SM0,SM1,386 */
        {I_BSF, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+55346, 13},
    /*   2 : BSF reg64,rm64 [rm:       o64 nof3 0f bc /r                 ] SM0-1,LONG,PROT,X86_64 */
        /* 324 326 355 001(bc) 110 : SM0,SM1,LONG,PROT,X86_64 */
        {I_BSF, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+55353, 14},
};

static const struct itemplate instrux_BSR[3] = {
    /*   0 : BSR reg16,rm16 [rm:       o16 nof3 0f bd /r                 ] SM0-1,386 */
        /* 320 326 355 001(bd) 110 : SM0,SM1,386 */
        {I_BSR, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55360, 13},
    /*   1 : BSR reg32,rm32 [rm:       o32 nof3 0f bd /r                 ] SM0-1,386 */
        /* 321 326 355 001(bd) 110 : SM0,SM1,386 */
        {I_BSR, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+55367, 13},
    /*   2 : BSR reg64,rm64 [rm:       o64 nof3 0f bd /r                 ] SM0-1,LONG,PROT,X86_64 */
        /* 324 326 355 001(bd) 110 : SM0,SM1,LONG,PROT,X86_64 */
        {I_BSR, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+55374, 14},
};

static const struct itemplate instrux_IBTS[2] = {
    /*   0 : IBTS rm16,reg16 [mr:       o16 0f a7 /r                      ] ND,NOREX,NOAPX,NOLONG,UNDOC,OBSOLETE,386 */
        /* 320 355 001(a7) 101 : NOREX,NOAPX,NOLONG,UNDOC,OBSOLETE,386 */
        {I_IBTS, 2, {RM_GPR|BITS16|RN_L16,REG_GPR|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66728, 121},
    /*   1 : IBTS rm32,reg32 [mr:       o32 0f a7 /r                      ] ND,NOREX,NOAPX,NOLONG,UNDOC,OBSOLETE,386 */
        /* 321 355 001(a7) 101 : NOREX,NOAPX,NOLONG,UNDOC,OBSOLETE,386 */
        {I_IBTS, 2, {RM_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66734, 121},
};

static const struct itemplate instrux_XBTS[2] = {
    /*   0 : XBTS rm16,reg16 [mr:       o16 0f a6 /r                      ] ND,NOREX,NOAPX,NOLONG,UNDOC,OBSOLETE,386 */
        /* 320 355 001(a6) 101 : NOREX,NOAPX,NOLONG,UNDOC,OBSOLETE,386 */
        {I_XBTS, 2, {RM_GPR|BITS16|RN_L16,REG_GPR|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66740, 121},
    /*   1 : XBTS rm32,reg32 [mr:       o32 0f a6 /r                      ] ND,NOREX,NOAPX,NOLONG,UNDOC,OBSOLETE,386 */
        /* 321 355 001(a6) 101 : NOREX,NOAPX,NOLONG,UNDOC,OBSOLETE,386 */
        {I_XBTS, 2, {RM_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66746, 121},
};

static const struct itemplate instrux_LZCNT[6] = {
    /*   0 : LZCNT reg16,rm16 [rm:       o16 f3i 0f bd /r                  ] SM0-1,FL,LZCNT,FUTURE */
        /* 320 333 355 001(bd) 110 : SM0,SM1,FL,LZCNT,FUTURE */
        {I_LZCNT, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55381, 122},
    /*   1 : LZCNT reg32,rm32 [rm:       o32 f3i 0f bd /r                  ] SM0-1,FL,LZCNT,FUTURE */
        /* 321 333 355 001(bd) 110 : SM0,SM1,FL,LZCNT,FUTURE */
        {I_LZCNT, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+55388, 122},
    /*   2 : LZCNT reg64,rm64 [rm:       o64 f3i 0f bd /r                  ] SM0-1,LONG,FL,PROT,LZCNT,X86_64 */
        /* 324 333 355 001(bd) 110 : SM0,SM1,LONG,FL,PROT,LZCNT,X86_64 */
        {I_LZCNT, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+55395, 123},
    /*   3 : LZCNT reg16,rm16 [rm:       evex.nd0.nf.l0.m4.o16 f5 /r       ] SM0-1,NF,LONG,PROT,APX,LZCNT,X86_64 */
        /* 250(f4 7d 08) 300 320 001(f5) 110 : SM0,SM1,NF,NF_E,LONG,EVEX,PROT,APX,LZCNT,X86_64 */
        {I_LZCNT, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12903, 124},
    /*   4 : LZCNT reg32,rm32 [rm:       evex.nd0.nf.l0.m4.o32 f5 /r       ] SM0-1,NF,LONG,PROT,APX,LZCNT,X86_64 */
        /* 250(f4 7c 08) 300 321 001(f5) 110 : SM0,SM1,NF,NF_E,WW,LONG,EVEX,PROT,APX,LZCNT,X86_64 */
        {I_LZCNT, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+12913, 125},
    /*   5 : LZCNT reg64,rm64 [rm:       evex.nd0.nf.l0.m4.o64 f5 /r       ] SM0-1,NF,LONG,PROT,APX,LZCNT,X86_64 */
        /* 250(f4 fc 08) 300 324 001(f5) 110 : SM0,SM1,NF,NF_E,WW,LONG,EVEX,PROT,APX,LZCNT,X86_64 */
        {I_LZCNT, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+12923, 125},
};

static const struct itemplate instrux_TZCNT[6] = {
    /*   0 : TZCNT reg16,rm16 [rm:       o16 f3i 0f bc /r                  ] SM0-1,FL,BMI1,FUTURE */
        /* 320 333 355 001(bc) 110 : SM0,SM1,FL,BMI1,FUTURE */
        {I_TZCNT, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55402, 126},
    /*   1 : TZCNT reg32,rm32 [rm:       o32 f3i 0f bc /r                  ] SM0-1,FL,BMI1,FUTURE */
        /* 321 333 355 001(bc) 110 : SM0,SM1,FL,BMI1,FUTURE */
        {I_TZCNT, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+55409, 126},
    /*   2 : TZCNT reg64,rm64 [rm:       o64 f3i 0f bc /r                  ] SM0-1,LONG,FL,PROT,BMI1,X86_64 */
        /* 324 333 355 001(bc) 110 : SM0,SM1,LONG,FL,PROT,BMI1,X86_64 */
        {I_TZCNT, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+55416, 127},
    /*   3 : TZCNT reg16,rm16 [rm:       evex.nd0.nf.l0.m4.o16 f4 /r       ] SM0-1,NF,LONG,PROT,BMI1,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(f4) 110 : SM0,SM1,NF,NF_E,LONG,EVEX,PROT,BMI1,APX,X86_64 */
        {I_TZCNT, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12933, 128},
    /*   4 : TZCNT reg32,rm32 [rm:       evex.nd0.nf.l0.m4.o32 f4 /r       ] SM0-1,NF,LONG,PROT,BMI1,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(f4) 110 : SM0,SM1,NF,NF_E,WW,LONG,EVEX,PROT,BMI1,APX,X86_64 */
        {I_TZCNT, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+12943, 129},
    /*   5 : TZCNT reg64,rm64 [rm:       evex.nd0.nf.l0.m4.o64 f4 /r       ] SM0-1,NF,LONG,PROT,BMI1,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(f4) 110 : SM0,SM1,NF,NF_E,WW,LONG,EVEX,PROT,BMI1,APX,X86_64 */
        {I_TZCNT, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+12953, 129},
};

static const struct itemplate instrux_ANDN[24] = {
    /*   0 : ANDN reg32,reg32*,rm32 [rvm:      vex.nds.lz.0f38.w0 f2 /r          ] SM0,SM1,SM2,FL,BMI1,FUTURE */
        /* 261(002 000) 001(f2) 120 : SM0,SM1,SM2,NOAPX,FL,VEX,BMI1,FUTURE */
        {I_ANDN, 3, {REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55423, 130},
    /*   1 : ANDN reg32,rm32 [r+vm:      vex.nds.lz.0f38.w0 f2 /r          ] ND,SM0,SM1,FL,BMI1,FUTURE */
        /* 260(002 000) 001(f2) 110 : SM0,SM1,NOAPX,FL,VEX,BMI1,FUTURE */
        {I_ANDN, 2, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55430, 131},
    /*   2 : ANDN reg64,reg64*,rm64 [rvm:      vex.nds.lz.0f38.w1 f2 /r          ] SM0,SM1,SM2,LONG,FL,PROT,BMI1,X86_64 */
        /* 261(002 200) 001(f2) 120 : SM0,SM1,SM2,NOAPX,LONG,FL,VEX,PROT,BMI1,X86_64 */
        {I_ANDN, 3, {REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55437, 132},
    /*   3 : ANDN reg64,rm64 [r+vm:      vex.nds.lz.0f38.w1 f2 /r          ] ND,SM0,SM1,LONG,FL,PROT,BMI1,X86_64 */
        /* 260(002 200) 001(f2) 110 : SM0,SM1,NOAPX,LONG,FL,VEX,PROT,BMI1,X86_64 */
        {I_ANDN, 2, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55444, 133},
    /*   4 : ANDN reg32,reg32*,rm32 [rvm:      evex.np.nf.lz.0f38.w0 f2 /r       ] SM0,SM1,SM2,NF,LONG,PROT,BMI1,APX,X86_64 */
        /* 241(f2 7c 08) 300 001(f2) 120 : SM0,SM1,SM2,NF,NF_E,LONG,EVEX,PROT,BMI1,APX,X86_64 */
        {I_ANDN, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+24498, 134},
    /*   5 : ANDN reg32,rm32 [r+vm:      evex.np.nf.lz.0f38.w0 f2 /r       ] ND,SM0,SM1,NF,LONG,PROT,BMI1,APX,X86_64 */
        /* 240(f2 7c 08) 300 001(f2) 110 : SM0,SM1,NF,NF_E,LONG,EVEX,PROT,BMI1,APX,X86_64 */
        {I_ANDN, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+24507, 128},
    /*   6 : ANDN reg64,reg64*,rm64 [rvm:      evex.np.nf.lz.0f38.w1 f2 /r       ] SM0,SM1,SM2,NF,LONG,PROT,BMI1,APX,X86_64 */
        /* 241(f2 fc 08) 300 001(f2) 120 : SM0,SM1,SM2,NF,NF_E,LONG,EVEX,PROT,BMI1,APX,X86_64 */
        {I_ANDN, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+24516, 134},
    /*   7 : ANDN reg64,rm64 [r+vm:      evex.np.nf.lz.0f38.w1 f2 /r       ] ND,SM0,SM1,NF,LONG,PROT,BMI1,APX,X86_64 */
        /* 240(f2 fc 08) 300 001(f2) 110 : SM0,SM1,NF,NF_E,LONG,EVEX,PROT,BMI1,APX,X86_64 */
        {I_ANDN, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+24525, 128},
    /*   8 : ANDN kreg8,kreg8*,kreg8 [rvm:      vex.l1.0f.ko8 42 /r              ] ND,SM0,SM1,SM2,ZU,FL,AVX512DQ,FUTURE */
        /* 261(001 005) 001(42) 120 : SM0,SM1,SM2,NOAPX,ZU,FL,VEX,AVX512DQ,FUTURE */
        {I_ANDN, 3, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65342, 516},
    /*   9 : ANDN kreg8,kreg8*,kreg8 [rvm:      evex.l1.0f.ko8 42 /r              ] ND,SM0,SM1,SM2,ZU,FL,AVX512DQ,FUTURE,APX */
        /* 241(f1 7d 28) 300 001(42) 120 : SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_ANDN, 3, {OPMASKREG|BITS8,OPMASKREG|BITS8,OPMASKREG|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+29952, 517},
    /*  10 : ANDN kreg8,kreg8 [r+vm:      vex.l1.0f.ko8 42 /r              ] ND,SM0,SM1,ZU,FL,AVX512DQ,FUTURE */
        /* 260(001 005) 001(42) 110 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512DQ,FUTURE */
        {I_ANDN, 2, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65349, 518},
    /*  11 : ANDN kreg8,kreg8 [r+vm:      evex.l1.0f.ko8 42 /r              ] ND,SM0,SM1,ZU,FL,AVX512DQ,FUTURE,APX */
        /* 240(f1 7d 28) 300 001(42) 110 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_ANDN, 2, {OPMASKREG|BITS8,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+29961, 519},
    /*  12 : ANDN kreg16,kreg16*,kreg16 [rvm:      vex.l1.0f.ko16 42 /r             ] ND,SM0,SM1,SM2,ZU,FL,AVX512F,FUTURE */
        /* 261(001 004) 001(42) 120 : SM0,SM1,SM2,NOAPX,ZU,FL,VEX,AVX512F,FUTURE */
        {I_ANDN, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65356, 528},
    /*  13 : ANDN kreg16,kreg16*,kreg16 [rvm:      evex.l1.0f.ko16 42 /r             ] ND,SM0,SM1,SM2,ZU,FL,AVX512F,FUTURE,APX */
        /* 241(f1 7c 28) 300 001(42) 120 : SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_ANDN, 3, {OPMASKREG|BITS16,OPMASKREG|BITS16,OPMASKREG|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+29970, 529},
    /*  14 : ANDN kreg16,kreg16 [r+vm:      vex.l1.0f.ko16 42 /r             ] ND,SM0,SM1,ZU,FL,AVX512F,FUTURE */
        /* 260(001 004) 001(42) 110 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512F,FUTURE */
        {I_ANDN, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65363, 530},
    /*  15 : ANDN kreg16,kreg16 [r+vm:      evex.l1.0f.ko16 42 /r             ] ND,SM0,SM1,ZU,FL,AVX512F,FUTURE,APX */
        /* 240(f1 7c 28) 300 001(42) 110 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_ANDN, 2, {OPMASKREG|BITS16,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29979, 531},
    /*  16 : ANDN kreg32,kreg32*,kreg32 [rvm:      vex.l1.0f.ko32 42 /r             ] ND,SM0,SM1,SM2,ZU,FL,AVX512BW,FUTURE */
        /* 261(001 205) 001(42) 120 : SM0,SM1,SM2,NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_ANDN, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65370, 520},
    /*  17 : ANDN kreg32,kreg32*,kreg32 [rvm:      evex.l1.0f.ko32 42 /r             ] ND,SM0,SM1,SM2,ZU,FL,AVX512BW,FUTURE,APX */
        /* 241(f1 fd 28) 300 001(42) 120 : SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_ANDN, 3, {OPMASKREG|BITS32,OPMASKREG|BITS32,OPMASKREG|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+29988, 521},
    /*  18 : ANDN kreg32,kreg32 [r+vm:      vex.l1.0f.ko32 42 /r             ] ND,SM0,SM1,ZU,FL,AVX512BW,FUTURE */
        /* 260(001 205) 001(42) 110 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_ANDN, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65377, 522},
    /*  19 : ANDN kreg32,kreg32 [r+vm:      evex.l1.0f.ko32 42 /r             ] ND,SM0,SM1,ZU,FL,AVX512BW,FUTURE,APX */
        /* 240(f1 fd 28) 300 001(42) 110 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_ANDN, 2, {OPMASKREG|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+29997, 523},
    /*  20 : ANDN kreg64,kreg64*,kreg64 [rvm:      vex.l1.0f.ko64 42 /r             ] ND,SM0,SM1,SM2,ZU,FL,AVX512BW,FUTURE */
        /* 261(001 204) 001(42) 120 : SM0,SM1,SM2,NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_ANDN, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65384, 520},
    /*  21 : ANDN kreg64,kreg64*,kreg64 [rvm:      evex.l1.0f.ko64 42 /r             ] ND,SM0,SM1,SM2,ZU,FL,AVX512BW,FUTURE,APX */
        /* 241(f1 fc 28) 300 001(42) 120 : SM0,SM1,SM2,ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_ANDN, 3, {OPMASKREG|BITS64,OPMASKREG|BITS64,OPMASKREG|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+30006, 521},
    /*  22 : ANDN kreg64,kreg64 [r+vm:      vex.l1.0f.ko64 42 /r             ] ND,SM0,SM1,ZU,FL,AVX512BW,FUTURE */
        /* 260(001 204) 001(42) 110 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_ANDN, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65391, 522},
    /*  23 : ANDN kreg64,kreg64 [r+vm:      evex.l1.0f.ko64 42 /r             ] ND,SM0,SM1,ZU,FL,AVX512BW,FUTURE,APX */
        /* 240(f1 fc 28) 300 001(42) 110 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_ANDN, 2, {OPMASKREG|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+30015, 523},
};

static const struct itemplate instrux_BEXTR[12] = {
    /*   0 : BEXTR reg32,rm32*,reg32 [rmv:      vex.nds.lz.0f38.w0 f7 /r          ] SM0,SM1,SM2,FL,BMI1,FUTURE */
        /* 262(002 000) 001(f7) 110 : SM0,SM1,SM2,NOAPX,FL,VEX,BMI1,FUTURE */
        {I_BEXTR, 3, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55451, 130},
    /*   1 : BEXTR reg32,reg32 [r+mv:      vex.nds.lz.0f38.w0 f7 /r          ] ND,SM0,SM1,FL,BMI1,FUTURE */
        /* 261(002 000) 001(f7) 100 : SM0,SM1,NOAPX,FL,VEX,BMI1,FUTURE */
        {I_BEXTR, 2, {REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55458, 131},
    /*   2 : BEXTR reg64,rm64*,reg64 [rmv:      vex.nds.lz.0f38.w1 f7 /r          ] SM0,SM1,SM2,LONG,FL,PROT,BMI1,X86_64 */
        /* 262(002 200) 001(f7) 110 : SM0,SM1,SM2,NOAPX,LONG,FL,VEX,PROT,BMI1,X86_64 */
        {I_BEXTR, 3, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55465, 132},
    /*   3 : BEXTR reg64,reg64 [r+mv:      vex.nds.lz.0f38.w1 f7 /r          ] ND,SM0,SM1,LONG,FL,PROT,BMI1,X86_64 */
        /* 261(002 200) 001(f7) 100 : SM0,SM1,NOAPX,LONG,FL,VEX,PROT,BMI1,X86_64 */
        {I_BEXTR, 2, {REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55472, 133},
    /*   4 : BEXTR reg32,rm32*,reg32 [rmv:      evex.np.nf.lz.0f38.w0 f7 /r       ] SM0,SM1,SM2,NF,LONG,PROT,BMI1,APX,X86_64 */
        /* 242(f2 7c 08) 300 001(f7) 110 : SM0,SM1,SM2,NF,NF_E,LONG,EVEX,PROT,BMI1,APX,X86_64 */
        {I_BEXTR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+24534, 134},
    /*   5 : BEXTR reg32,reg32 [r+mv:      evex.np.nf.lz.0f38.w0 f7 /r       ] ND,SM0,SM1,NF,LONG,PROT,BMI1,APX,X86_64 */
        /* 241(f2 7c 08) 300 001(f7) 100 : SM0,SM1,NF,NF_E,LONG,EVEX,PROT,BMI1,APX,X86_64 */
        {I_BEXTR, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+24543, 128},
    /*   6 : BEXTR reg64,rm64*,reg64 [rmv:      evex.np.nf.lz.0f38.w1 f7 /r       ] SM0,SM1,SM2,NF,LONG,PROT,BMI1,APX,X86_64 */
        /* 242(f2 fc 08) 300 001(f7) 110 : SM0,SM1,SM2,NF,NF_E,LONG,EVEX,PROT,BMI1,APX,X86_64 */
        {I_BEXTR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+24552, 134},
    /*   7 : BEXTR reg64,reg64 [r+mv:      evex.np.nf.lz.0f38.w1 f7 /r       ] ND,SM0,SM1,NF,LONG,PROT,BMI1,APX,X86_64 */
        /* 241(f2 fc 08) 300 001(f7) 100 : SM0,SM1,NF,NF_E,LONG,EVEX,PROT,BMI1,APX,X86_64 */
        {I_BEXTR, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+24561, 128},
    /*   8 : BEXTR reg32,rm32*,imm32 [rmi:      xop.m10.lz.w0 10 /r id            ] SM0,SM1,FL,TBM,OBSOLETE,FUTURE,AMD */
        /* 270(112 000) 001(10) 110 042 : SM0,SM1,NOAPX,FL,VEX,TBM,OBSOLETE,FUTURE,AMD */
        {I_BEXTR, 3, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+51125, 145},
    /*   9 : BEXTR reg32,imm32 [r+mi:      xop.m10.lz.w0 10 /r id            ] ND,SM0,FL,TBM,OBSOLETE,FUTURE,AMD */
        /* 270(112 000) 001(10) 100 041 : SM0,NOAPX,FL,VEX,TBM,OBSOLETE,FUTURE,AMD */
        {I_BEXTR, 2, {REG_GPR|BITS32|RN_L16,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+51133, 146},
    /*  10 : BEXTR reg64,rm64*,imm32 [rmi:      xop.m10.lz.w1 10 /r id            ] SM0,SM1,LONG,FL,PROT,TBM,OBSOLETE,X86_64,AMD */
        /* 270(112 200) 001(10) 110 042 : SM0,SM1,NOAPX,LONG,FL,VEX,PROT,TBM,OBSOLETE,X86_64,AMD */
        {I_BEXTR, 3, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+51141, 147},
    /*  11 : BEXTR reg64,imm32 [r+mi:      xop.m10.lz.w1 10 /r id            ] ND,SM0,LONG,FL,PROT,TBM,OBSOLETE,X86_64,AMD */
        /* 270(112 200) 001(10) 100 041 : SM0,NOAPX,LONG,FL,VEX,PROT,TBM,OBSOLETE,X86_64,AMD */
        {I_BEXTR, 2, {REG_GPR|BITS64|RN_L16,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+51149, 148},
};

static const struct itemplate instrux_BLSMSK[4] = {
    /*   0 : BLSMSK reg32,rm32 [vm:       vex.ndd.lz.0f38.w0 f3 /2          ] SM0-1,FL,BMI1,FUTURE */
        /* 260(002 000) 001(f3) 212 : SM0,SM1,NOAPX,FL,VEX,BMI1,FUTURE */
        {I_BLSMSK, 2, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55479, 131},
    /*   1 : BLSMSK reg64,rm64 [vm:       vex.ndd.lz.0f38.w1 f3 /2          ] SM0-1,LONG,FL,PROT,BMI1,X86_64 */
        /* 260(002 200) 001(f3) 212 : SM0,SM1,NOAPX,LONG,FL,VEX,PROT,BMI1,X86_64 */
        {I_BLSMSK, 2, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55486, 133},
    /*   2 : BLSMSK reg32,rm32 [vm:       evex.np.nf.lz.0f38.w0 f3 /2       ] SM0-1,NF,LONG,PROT,BMI1,APX,X86_64 */
        /* 240(f2 7c 08) 300 001(f3) 212 : SM0,SM1,NF,NF_E,LONG,EVEX,PROT,BMI1,APX,X86_64 */
        {I_BLSMSK, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+24570, 128},
    /*   3 : BLSMSK reg64,rm64 [vm:       evex.np.nf.lz.0f38.w1 f3 /2       ] SM0-1,NF,LONG,PROT,BMI1,APX,X86_64 */
        /* 240(f2 fc 08) 300 001(f3) 212 : SM0,SM1,NF,NF_E,LONG,EVEX,PROT,BMI1,APX,X86_64 */
        {I_BLSMSK, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+24579, 128},
};

static const struct itemplate instrux_BLSR[4] = {
    /*   0 : BLSR reg32,rm32 [vm:       vex.ndd.lz.0f38.w0 f3 /1          ] SM0-1,FL,BMI1,FUTURE */
        /* 260(002 000) 001(f3) 211 : SM0,SM1,NOAPX,FL,VEX,BMI1,FUTURE */
        {I_BLSR, 2, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55493, 131},
    /*   1 : BLSR reg64,rm64 [vm:       vex.ndd.lz.0f38.w1 f3 /1          ] SM0-1,LONG,FL,PROT,BMI1,X86_64 */
        /* 260(002 200) 001(f3) 211 : SM0,SM1,NOAPX,LONG,FL,VEX,PROT,BMI1,X86_64 */
        {I_BLSR, 2, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55500, 133},
    /*   2 : BLSR reg32,rm32 [vm:       evex.np.nf.lz.0f38.w0 f3 /1       ] SM0-1,NF,LONG,PROT,BMI1,APX,X86_64 */
        /* 240(f2 7c 08) 300 001(f3) 211 : SM0,SM1,NF,NF_E,LONG,EVEX,PROT,BMI1,APX,X86_64 */
        {I_BLSR, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+24588, 128},
    /*   3 : BLSR reg64,rm64 [vm:       evex.np.nf.lz.0f38.w1 f3 /1       ] SM0-1,NF,LONG,PROT,BMI1,APX,X86_64 */
        /* 240(f2 fc 08) 300 001(f3) 211 : SM0,SM1,NF,NF_E,LONG,EVEX,PROT,BMI1,APX,X86_64 */
        {I_BLSR, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+24597, 128},
};

static const struct itemplate instrux_BLSI[4] = {
    /*   0 : BLSI reg32,rm32 [vm:       vex.ndd.lz.0f38.w0 f3 /3          ] SM0-1,FL,BMI1,FUTURE */
        /* 260(002 000) 001(f3) 213 : SM0,SM1,NOAPX,FL,VEX,BMI1,FUTURE */
        {I_BLSI, 2, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55507, 131},
    /*   1 : BLSI reg64,rm64 [vm:       vex.ndd.lz.0f38.w1 f3 /3          ] SM0-1,LONG,FL,PROT,BMI1,X86_64 */
        /* 260(002 200) 001(f3) 213 : SM0,SM1,NOAPX,LONG,FL,VEX,PROT,BMI1,X86_64 */
        {I_BLSI, 2, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55514, 133},
    /*   2 : BLSI reg32,rm32 [vm:       evex.np.nf.lz.0f38.w0 f3 /3       ] SM0-1,NF,LONG,PROT,BMI1,APX,X86_64 */
        /* 240(f2 7c 08) 300 001(f3) 213 : SM0,SM1,NF,NF_E,LONG,EVEX,PROT,BMI1,APX,X86_64 */
        {I_BLSI, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+24606, 128},
    /*   3 : BLSI reg64,rm64 [vm:       evex.np.nf.lz.0f38.w1 f3 /3       ] SM0-1,NF,LONG,PROT,BMI1,APX,X86_64 */
        /* 240(f2 fc 08) 300 001(f3) 213 : SM0,SM1,NF,NF_E,LONG,EVEX,PROT,BMI1,APX,X86_64 */
        {I_BLSI, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+24615, 128},
};

static const struct itemplate instrux_BZHI[8] = {
    /*   0 : BZHI reg32,rm32*,reg32 [rmv:      vex.nds.lz.0f38.w0 f5 /r          ] SM0,SM1,SM2,FL,BMI2,FUTURE */
        /* 262(002 000) 001(f5) 110 : SM0,SM1,SM2,NOAPX,FL,VEX,BMI2,FUTURE */
        {I_BZHI, 3, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55521, 135},
    /*   1 : BZHI reg32,reg32 [r+mv:      vex.nds.lz.0f38.w0 f5 /r          ] ND,SM0,SM1,FL,BMI2,FUTURE */
        /* 261(002 000) 001(f5) 100 : SM0,SM1,NOAPX,FL,VEX,BMI2,FUTURE */
        {I_BZHI, 2, {REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55528, 136},
    /*   2 : BZHI reg64,rm64*,reg64 [rmv:      vex.nds.lz.0f38.w1 f5 /r          ] SM0,SM1,SM2,LONG,FL,PROT,BMI2,X86_64 */
        /* 262(002 200) 001(f5) 110 : SM0,SM1,SM2,NOAPX,LONG,FL,VEX,PROT,BMI2,X86_64 */
        {I_BZHI, 3, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55535, 137},
    /*   3 : BZHI reg64,reg64 [r+mv:      vex.nds.lz.0f38.w1 f5 /r          ] ND,SM0,SM1,LONG,FL,PROT,BMI2,X86_64 */
        /* 261(002 200) 001(f5) 100 : SM0,SM1,NOAPX,LONG,FL,VEX,PROT,BMI2,X86_64 */
        {I_BZHI, 2, {REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55542, 138},
    /*   4 : BZHI reg32,rm32*,reg32 [rmv:      evex.np.nf.lz.0f38.w0 f5 /r       ] SM0,SM1,SM2,NF,LONG,PROT,BMI1,APX,X86_64 */
        /* 242(f2 7c 08) 300 001(f5) 110 : SM0,SM1,SM2,NF,NF_E,LONG,EVEX,PROT,BMI1,APX,X86_64 */
        {I_BZHI, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+24624, 134},
    /*   5 : BZHI reg32,reg32 [r+mv:      evex.np.nf.lz.0f38.w0 f5 /r       ] ND,SM0,SM1,NF,LONG,PROT,BMI1,APX,X86_64 */
        /* 241(f2 7c 08) 300 001(f5) 100 : SM0,SM1,NF,NF_E,LONG,EVEX,PROT,BMI1,APX,X86_64 */
        {I_BZHI, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+24633, 128},
    /*   6 : BZHI reg64,rm64*,reg64 [rmv:      evex.np.nf.lz.0f38.w1 f5 /r       ] SM0,SM1,SM2,NF,LONG,PROT,BMI1,APX,X86_64 */
        /* 242(f2 fc 08) 300 001(f5) 110 : SM0,SM1,SM2,NF,NF_E,LONG,EVEX,PROT,BMI1,APX,X86_64 */
        {I_BZHI, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+24642, 134},
    /*   7 : BZHI reg64,reg64 [r+mv:      evex.np.nf.lz.0f38.w1 f5 /r       ] ND,SM0,SM1,NF,LONG,PROT,BMI1,APX,X86_64 */
        /* 241(f2 fc 08) 300 001(f5) 100 : SM0,SM1,NF,NF_E,LONG,EVEX,PROT,BMI1,APX,X86_64 */
        {I_BZHI, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+24651, 128},
};

static const struct itemplate instrux_PDEP[8] = {
    /*   0 : PDEP reg32,reg32*,rm32 [rvm:      vex.nds.lz.f2.0f38.w0 f5 /r      ] SM0,SM1,SM2,BMI2,FUTURE */
        /* 261(002 003) 001(f5) 120 : SM0,SM1,SM2,NOAPX,VEX,BMI2,FUTURE */
        {I_PDEP, 3, {REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55549, 139},
    /*   1 : PDEP reg32,reg32*,rm32 [rvm:      evex.nds.lz.f2.0f38.w0 f5 /r      ] SM0,SM1,SM2,BMI2,FUTURE,APX */
        /* 241(f2 7f 08) 300 001(f5) 120 : SM0,SM1,SM2,LONG,EVEX,PROT,BMI2,APX,FUTURE */
        {I_PDEP, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+24660, 140},
    /*   2 : PDEP reg32,rm32 [r+vm:      vex.nds.lz.f2.0f38.w0 f5 /r      ] ND,SM0,SM1,BMI2,FUTURE */
        /* 260(002 003) 001(f5) 110 : SM0,SM1,NOAPX,VEX,BMI2,FUTURE */
        {I_PDEP, 2, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55556, 58},
    /*   3 : PDEP reg32,rm32 [r+vm:      evex.nds.lz.f2.0f38.w0 f5 /r      ] ND,SM0,SM1,BMI2,FUTURE,APX */
        /* 240(f2 7f 08) 300 001(f5) 110 : SM0,SM1,LONG,EVEX,PROT,BMI2,APX,FUTURE */
        {I_PDEP, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+24669, 141},
    /*   4 : PDEP reg64,reg64*,rm64 [rvm:      vex.nds.lz.f2.0f38.w1 f5 /r      ] SM0,SM1,SM2,LONG,PROT,BMI2,X86_64 */
        /* 261(002 203) 001(f5) 120 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,BMI2,X86_64 */
        {I_PDEP, 3, {REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55563, 142},
    /*   5 : PDEP reg64,reg64*,rm64 [rvm:      evex.nds.lz.f2.0f38.w1 f5 /r      ] SM0,SM1,SM2,LONG,PROT,BMI2,X86_64,APX */
        /* 241(f2 ff 08) 300 001(f5) 120 : SM0,SM1,SM2,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_PDEP, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+24678, 143},
    /*   6 : PDEP reg64,rm64 [r+vm:      vex.nds.lz.f2.0f38.w1 f5 /r      ] ND,SM0,SM1,LONG,PROT,BMI2,X86_64 */
        /* 260(002 203) 001(f5) 110 : SM0,SM1,NOAPX,LONG,VEX,PROT,BMI2,X86_64 */
        {I_PDEP, 2, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55570, 144},
    /*   7 : PDEP reg64,rm64 [r+vm:      evex.nds.lz.f2.0f38.w1 f5 /r      ] ND,SM0,SM1,LONG,PROT,BMI2,X86_64,APX */
        /* 240(f2 ff 08) 300 001(f5) 110 : SM0,SM1,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_PDEP, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+24687, 68},
};

static const struct itemplate instrux_PEXT[8] = {
    /*   0 : PEXT reg32,reg32*,rm32 [rvm:      vex.nds.lz.f3.0f38.w0 f5 /r      ] SM0,SM1,SM2,BMI2,FUTURE */
        /* 261(002 002) 001(f5) 120 : SM0,SM1,SM2,NOAPX,VEX,BMI2,FUTURE */
        {I_PEXT, 3, {REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55577, 139},
    /*   1 : PEXT reg32,reg32*,rm32 [rvm:      evex.nds.lz.f3.0f38.w0 f5 /r      ] SM0,SM1,SM2,BMI2,FUTURE,APX */
        /* 241(f2 7e 08) 300 001(f5) 120 : SM0,SM1,SM2,LONG,EVEX,PROT,BMI2,APX,FUTURE */
        {I_PEXT, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+24696, 140},
    /*   2 : PEXT reg32,rm32 [r+vm:      vex.nds.lz.f3.0f38.w0 f5 /r      ] ND,SM0,SM1,BMI2,FUTURE */
        /* 260(002 002) 001(f5) 110 : SM0,SM1,NOAPX,VEX,BMI2,FUTURE */
        {I_PEXT, 2, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55584, 58},
    /*   3 : PEXT reg32,rm32 [r+vm:      evex.nds.lz.f3.0f38.w0 f5 /r      ] ND,SM0,SM1,BMI2,FUTURE,APX */
        /* 240(f2 7e 08) 300 001(f5) 110 : SM0,SM1,LONG,EVEX,PROT,BMI2,APX,FUTURE */
        {I_PEXT, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+24705, 141},
    /*   4 : PEXT reg64,reg64*,rm64 [rvm:      vex.nds.lz.f3.0f38.w1 f5 /r      ] SM0,SM1,SM2,LONG,PROT,BMI2,X86_64 */
        /* 261(002 202) 001(f5) 120 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,BMI2,X86_64 */
        {I_PEXT, 3, {REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+55591, 142},
    /*   5 : PEXT reg64,reg64*,rm64 [rvm:      evex.nds.lz.f3.0f38.w1 f5 /r      ] SM0,SM1,SM2,LONG,PROT,BMI2,X86_64,APX */
        /* 241(f2 fe 08) 300 001(f5) 120 : SM0,SM1,SM2,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_PEXT, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+24714, 143},
    /*   6 : PEXT reg64,rm64 [r+vm:      vex.nds.lz.f3.0f38.w1 f5 /r      ] ND,SM0,SM1,LONG,PROT,BMI2,X86_64 */
        /* 260(002 202) 001(f5) 110 : SM0,SM1,NOAPX,LONG,VEX,PROT,BMI2,X86_64 */
        {I_PEXT, 2, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55598, 144},
    /*   7 : PEXT reg64,rm64 [r+vm:      evex.nds.lz.f3.0f38.w1 f5 /r      ] ND,SM0,SM1,LONG,PROT,BMI2,X86_64,APX */
        /* 240(f2 fe 08) 300 001(f5) 110 : SM0,SM1,LONG,EVEX,PROT,BMI2,APX,X86_64 */
        {I_PEXT, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+24723, 68},
};

static const struct itemplate instrux_BLCI[2] = {
    /*   0 : BLCI reg32,rm32 [vm:       xop.ndd.lz.m9.w0 02 /6            ] SM0-1,FL,TBM,OBSOLETE,FUTURE,AMD */
        /* 260(111 000) 001(02) 216 : SM0,SM1,NOAPX,FL,VEX,TBM,OBSOLETE,FUTURE,AMD */
        {I_BLCI, 2, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55605, 145},
    /*   1 : BLCI reg64,rm64 [vm:       xop.ndd.lz.m9.w1 02 /6            ] SM0-1,LONG,FL,PROT,TBM,OBSOLETE,X86_64,AMD */
        /* 260(111 200) 001(02) 216 : SM0,SM1,NOAPX,LONG,FL,VEX,PROT,TBM,OBSOLETE,X86_64,AMD */
        {I_BLCI, 2, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55612, 147},
};

static const struct itemplate instrux_BLCIC[2] = {
    /*   0 : BLCIC reg32,rm32 [vm:       xop.ndd.lz.m9.w0 01 /5            ] SM0-1,FL,TBM,OBSOLETE,FUTURE,AMD */
        /* 260(111 000) 001(01) 215 : SM0,SM1,NOAPX,FL,VEX,TBM,OBSOLETE,FUTURE,AMD */
        {I_BLCIC, 2, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55619, 145},
    /*   1 : BLCIC reg64,rm64 [vm:       xop.ndd.lz.m9.w1 01 /5            ] SM0-1,LONG,FL,PROT,TBM,OBSOLETE,X86_64,AMD */
        /* 260(111 200) 001(01) 215 : SM0,SM1,NOAPX,LONG,FL,VEX,PROT,TBM,OBSOLETE,X86_64,AMD */
        {I_BLCIC, 2, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55626, 147},
};

static const struct itemplate instrux_BLSIC[2] = {
    /*   0 : BLSIC reg32,rm32 [vm:       xop.ndd.lz.m9.w0 01 /6            ] SM0-1,FL,TBM,OBSOLETE,FUTURE,AMD */
        /* 260(111 000) 001(01) 216 : SM0,SM1,NOAPX,FL,VEX,TBM,OBSOLETE,FUTURE,AMD */
        {I_BLSIC, 2, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55633, 145},
    /*   1 : BLSIC reg64,rm64 [vm:       xop.ndd.lz.m9.w1 01 /6            ] SM0-1,LONG,FL,PROT,TBM,OBSOLETE,X86_64,AMD */
        /* 260(111 200) 001(01) 216 : SM0,SM1,NOAPX,LONG,FL,VEX,PROT,TBM,OBSOLETE,X86_64,AMD */
        {I_BLSIC, 2, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55640, 147},
};

static const struct itemplate instrux_BLCFILL[2] = {
    /*   0 : BLCFILL reg32,rm32 [vm:       xop.ndd.lz.m9.w0 01 /1            ] SM0-1,TBM,OBSOLETE,FUTURE,AMD */
        /* 260(111 000) 001(01) 211 : SM0,SM1,NOAPX,VEX,TBM,OBSOLETE,FUTURE,AMD */
        {I_BLCFILL, 2, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55647, 149},
    /*   1 : BLCFILL reg64,rm64 [vm:       xop.ndd.lz.m9.w1 01 /1            ] SM0-1,LONG,PROT,TBM,OBSOLETE,X86_64,AMD */
        /* 260(111 200) 001(01) 211 : SM0,SM1,NOAPX,LONG,VEX,PROT,TBM,OBSOLETE,X86_64,AMD */
        {I_BLCFILL, 2, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55654, 150},
};

static const struct itemplate instrux_BLSFILL[2] = {
    /*   0 : BLSFILL reg32,rm32 [vm:       xop.ndd.lz.m9.w0 01 /2            ] TBM,OBSOLETE,FUTURE,AMD */
        /* 260(111 000) 001(01) 212 : NOAPX,VEX,TBM,OBSOLETE,FUTURE,AMD */
        {I_BLSFILL, 2, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55661, 151},
    /*   1 : BLSFILL reg64,rm64 [vm:       xop.ndd.lz.m9.w1 01 /2            ] LONG,PROT,TBM,OBSOLETE,X86_64,AMD */
        /* 260(111 200) 001(01) 212 : NOAPX,LONG,VEX,PROT,TBM,OBSOLETE,X86_64,AMD */
        {I_BLSFILL, 2, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55668, 152},
};

static const struct itemplate instrux_BLCMSK[2] = {
    /*   0 : BLCMSK reg32,rm32 [vm:       xop.ndd.lz.m9.w0 02 /1            ] FL,TBM,OBSOLETE,FUTURE,AMD */
        /* 260(111 000) 001(02) 211 : NOAPX,FL,VEX,TBM,OBSOLETE,FUTURE,AMD */
        {I_BLCMSK, 2, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55675, 153},
    /*   1 : BLCMSK reg64,rm64 [vm:       xop.ndd.lz.m9.w1 02 /1            ] LONG,FL,PROT,TBM,OBSOLETE,X86_64,AMD */
        /* 260(111 200) 001(02) 211 : NOAPX,LONG,FL,VEX,PROT,TBM,OBSOLETE,X86_64,AMD */
        {I_BLCMSK, 2, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55682, 154},
};

static const struct itemplate instrux_BLCS[2] = {
    /*   0 : BLCS reg32,rm32 [vm:       xop.ndd.lz.m9.w0 01 /3            ] TBM,OBSOLETE,FUTURE,AMD */
        /* 260(111 000) 001(01) 213 : NOAPX,VEX,TBM,OBSOLETE,FUTURE,AMD */
        {I_BLCS, 2, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55689, 151},
    /*   1 : BLCS reg64,rm64 [vm:       xop.ndd.lz.m9.w1 01 /3            ] LONG,PROT,TBM,OBSOLETE,X86_64,AMD */
        /* 260(111 200) 001(01) 213 : NOAPX,LONG,VEX,PROT,TBM,OBSOLETE,X86_64,AMD */
        {I_BLCS, 2, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55696, 152},
};

static const struct itemplate instrux_TZMSK[2] = {
    /*   0 : TZMSK reg32,rm32 [vm:       xop.ndd.lz.m9.w0 01 /4            ] TBM,OBSOLETE,FUTURE,AMD */
        /* 260(111 000) 001(01) 214 : NOAPX,VEX,TBM,OBSOLETE,FUTURE,AMD */
        {I_TZMSK, 2, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55703, 151},
    /*   1 : TZMSK reg64,rm64 [vm:       xop.ndd.lz.m9.w1 01 /4            ] LONG,PROT,TBM,OBSOLETE,X86_64,AMD */
        /* 260(111 200) 001(01) 214 : NOAPX,LONG,VEX,PROT,TBM,OBSOLETE,X86_64,AMD */
        {I_TZMSK, 2, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55710, 152},
};

static const struct itemplate instrux_T1MSKC[2] = {
    /*   0 : T1MSKC reg32,rm32 [vm:       xop.ndd.lz.m9.w0 01 /7            ] TBM,OBSOLETE,FUTURE,AMD */
        /* 260(111 000) 001(01) 217 : NOAPX,VEX,TBM,OBSOLETE,FUTURE,AMD */
        {I_T1MSKC, 2, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55717, 151},
    /*   1 : T1MSKC reg64,rm64 [vm:       xop.ndd.lz.m9.w1 01 /7            ] LONG,PROT,TBM,OBSOLETE,X86_64,AMD */
        /* 260(111 200) 001(01) 217 : NOAPX,LONG,VEX,PROT,TBM,OBSOLETE,X86_64,AMD */
        {I_T1MSKC, 2, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55724, 152},
};

static const struct itemplate instrux_AAA[1] = {
    /*   0 : AAA void [          37                                ] NOREX,NOAPX,NOLONG,FL,8086 */
        /* 001(37) : NOREX,NOAPX,NOLONG,FL,8086 */
        {I_AAA, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73290, 72},
};

static const struct itemplate instrux_AAD[2] = {
    /*   0 : AAD void [          d5 0a                             ] NOREX,NOAPX,NOLONG,FL,8086 */
        /* 002(d5 0a) : NOREX,NOAPX,NOLONG,FL,8086 */
        {I_AAD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72505, 72},
    /*   1 : AAD imm8 [i:        d5 ib,u                           ] AR0,SB,NOREX,NOAPX,NOLONG,FL,8086 */
        /* 001(d5) 024 : AR0,SB,NOREX,NOAPX,NOLONG,FL,8086 */
        {I_AAD, 1, {IMM_NORMAL|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72509, 155},
};

static const struct itemplate instrux_AAM[2] = {
    /*   0 : AAM void [          d4 0a                             ] NOREX,NOAPX,NOLONG,FL,8086 */
        /* 002(d4 0a) : NOREX,NOAPX,NOLONG,FL,8086 */
        {I_AAM, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72513, 72},
    /*   1 : AAM imm8 [i:        d4 ib,u                           ] AR0,SB,NOREX,NOAPX,NOLONG,FL,8086 */
        /* 001(d4) 024 : AR0,SB,NOREX,NOAPX,NOLONG,FL,8086 */
        {I_AAM, 1, {IMM_NORMAL|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72517, 155},
};

static const struct itemplate instrux_AAS[1] = {
    /*   0 : AAS void [          3f                                ] NOREX,NOAPX,NOLONG,FL,8086 */
        /* 001(3f) : NOREX,NOAPX,NOLONG,FL,8086 */
        {I_AAS, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73293, 72},
};

static const struct itemplate instrux_DAA[1] = {
    /*   0 : DAA void [          27                                ] NOREX,NOAPX,NOLONG,FL,8086 */
        /* 001(27) : NOREX,NOAPX,NOLONG,FL,8086 */
        {I_DAA, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73296, 72},
};

static const struct itemplate instrux_DAS[1] = {
    /*   0 : DAS void [          2f                                ] NOREX,NOAPX,NOLONG,FL,8086 */
        /* 001(2f) : NOREX,NOAPX,NOLONG,FL,8086 */
        {I_DAS, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73299, 72},
};

static const struct itemplate instrux_BSWAP[6] = {
    /*   0 : BSWAP reg32 [r:        o32 0f c8+r                       ] 486 */
        /* 321 355 010 310 : 486 */
        {I_BSWAP, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71483, 156},
    /*   1 : BSWAP reg64 [r:        o64 0f c8+r                       ] LONG,PROT,X86_64 */
        /* 324 355 010 310 : LONG,PROT,X86_64 */
        {I_BSWAP, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71488, 24},
    /*   2 : BSWAP reg_ax [-:        86 c4                             ] ND,OPT,NOREX,NOAPX,8086 */
        /* 002(86 c4) : OPT,NOREX,NOAPX,8086 */
        {I_BSWAP, 1, {REG_AX|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72521, 157},
    /*   3 : BSWAP reg_cx [-:        86 cd                             ] ND,OPT,NOREX,NOAPX,8086 */
        /* 002(86 cd) : OPT,NOREX,NOAPX,8086 */
        {I_BSWAP, 1, {REG_CX|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72525, 157},
    /*   4 : BSWAP reg_dx [-:        86 d6                             ] ND,OPT,NOREX,NOAPX,8086 */
        /* 002(86 d6) : OPT,NOREX,NOAPX,8086 */
        {I_BSWAP, 1, {REG_DX|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72529, 157},
    /*   5 : BSWAP reg_bx [-:        86 df                             ] ND,OPT,NOREX,NOAPX,8086 */
        /* 002(86 df) : OPT,NOREX,NOAPX,8086 */
        {I_BSWAP, 1, {REG_BX|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72533, 157},
};

static const struct itemplate instrux_MOVBE[12] = {
    /*   0 : MOVBE reg16,mem16 [rm:       o16 norep 0f38 f0 /r              ] SM0-1,MOVBE,NEHALEM */
        /* 320 331 356 001(f0) 110 : SM0,SM1,NOAPX,MOVBE,NEHALEM */
        {I_MOVBE, 2, {REG_GPR|BITS16|RN_L16,MEMORY|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55731, 158},
    /*   1 : MOVBE reg32,mem32 [rm:       o32 norep 0f38 f0 /r              ] SM0-1,MOVBE,NEHALEM */
        /* 321 331 356 001(f0) 110 : SM0,SM1,NOAPX,MOVBE,NEHALEM */
        {I_MOVBE, 2, {REG_GPR|BITS32|RN_L16,MEMORY|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55738, 158},
    /*   2 : MOVBE reg64,mem64 [rm:       o64 norep 0f38 f0 /r              ] SM0-1,LONG,PROT,MOVBE,X86_64,NEHALEM */
        /* 324 331 356 001(f0) 110 : SM0,SM1,NOAPX,LONG,PROT,MOVBE,NEHALEM */
        {I_MOVBE, 2, {REG_GPR|BITS64|RN_L16,MEMORY|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55745, 159},
    /*   3 : MOVBE mem16,reg16 [mr:       o16 norep 0f38 f1 /r              ] SM0-1,MOVBE,NEHALEM */
        /* 320 331 356 001(f1) 101 : SM0,SM1,NOAPX,MOVBE,NEHALEM */
        {I_MOVBE, 2, {MEMORY|BITS16|RN_L16,REG_GPR|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55752, 158},
    /*   4 : MOVBE mem32,reg32 [mr:       o32 norep 0f38 f1 /r              ] SM0-1,MOVBE,NEHALEM */
        /* 321 331 356 001(f1) 101 : SM0,SM1,NOAPX,MOVBE,NEHALEM */
        {I_MOVBE, 2, {MEMORY|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55759, 158},
    /*   5 : MOVBE mem64,reg64 [mr:       o64 norep 0f38 f1 /r              ] SM0-1,LONG,PROT,MOVBE,X86_64,NEHALEM */
        /* 324 331 356 001(f1) 101 : SM0,SM1,NOAPX,LONG,PROT,MOVBE,NEHALEM */
        {I_MOVBE, 2, {MEMORY|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55766, 159},
    /*   6 : MOVBE reg16,mem16 [rm:       evex.nd0.nf0.l0.m4.o16 60 /r      ] SM0-1,LONG,PROT,APX,MOVBE,X86_64,NEHALEM */
        /* 250(f4 7d 08) 300 320 001(60) 110 : SM0,SM1,LONG,EVEX,PROT,APX,MOVBE,NEHALEM */
        {I_MOVBE, 2, {REG_GPR|BITS16,MEMORY|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12963, 160},
    /*   7 : MOVBE reg32,mem32 [rm:       evex.nd0.nf0.l0.m4.o32 60 /r      ] SM0-1,LONG,PROT,APX,MOVBE,X86_64,NEHALEM */
        /* 250(f4 7c 08) 300 321 001(60) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,MOVBE,NEHALEM */
        {I_MOVBE, 2, {REG_GPR|BITS32,MEMORY|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+12973, 161},
    /*   8 : MOVBE reg64,mem64 [rm:       evex.nd0.nf0.l0.m4.o64 60 /r      ] SM0-1,LONG,PROT,APX,MOVBE,X86_64,NEHALEM */
        /* 250(f4 fc 08) 300 324 001(60) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,MOVBE,NEHALEM */
        {I_MOVBE, 2, {REG_GPR|BITS64,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+12983, 161},
    /*   9 : MOVBE mem16,reg16 [mr:       evex.nd0.nf0.l0.m4.o16 61 /r      ] SM0-1,LONG,PROT,APX,MOVBE,X86_64,NEHALEM */
        /* 250(f4 7d 08) 300 320 001(61) 101 : SM0,SM1,LONG,EVEX,PROT,APX,MOVBE,NEHALEM */
        {I_MOVBE, 2, {MEMORY|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12993, 160},
    /*  10 : MOVBE mem32,reg32 [mr:       evex.nd0.nf0.l0.m4.o32 61 /r      ] SM0-1,LONG,PROT,APX,MOVBE,X86_64,NEHALEM */
        /* 250(f4 7c 08) 300 321 001(61) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,MOVBE,NEHALEM */
        {I_MOVBE, 2, {MEMORY|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+13003, 161},
    /*  11 : MOVBE mem64,reg64 [mr:       evex.nd0.nf0.l0.m4.o64 61 /r      ] SM0-1,LONG,PROT,APX,MOVBE,X86_64,NEHALEM */
        /* 250(f4 fc 08) 300 324 001(61) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,MOVBE,NEHALEM */
        {I_MOVBE, 2, {MEMORY|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+13013, 161},
};

static const struct itemplate instrux_CBW[1] = {
    /*   0 : CBW void [          o16 98                            ] 8086 */
        /* 320 001(98) : 8086 */
        {I_CBW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72537, 23},
};

static const struct itemplate instrux_CDQ[1] = {
    /*   0 : CDQ void [          o32 99                            ] 386 */
        /* 321 001(99) : 386 */
        {I_CDQ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72541, 3},
};

static const struct itemplate instrux_CDQE[1] = {
    /*   0 : CDQE void [          o64 98                            ] LONG,PROT,X86_64 */
        /* 324 001(98) : LONG,PROT,X86_64 */
        {I_CDQE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72545, 24},
};

static const struct itemplate instrux_CQO[1] = {
    /*   0 : CQO void [          o64 99                            ] LONG,PROT,X86_64 */
        /* 324 001(99) : LONG,PROT,X86_64 */
        {I_CQO, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72549, 24},
};

static const struct itemplate instrux_CWD[1] = {
    /*   0 : CWD void [          o16 99                            ] 8086 */
        /* 320 001(99) : 8086 */
        {I_CWD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72553, 23},
};

static const struct itemplate instrux_CWDE[1] = {
    /*   0 : CWDE void [          o32 98                            ] 386 */
        /* 321 001(98) : 386 */
        {I_CWDE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72557, 3},
};

static const struct itemplate instrux_MOVSX[12] = {
    /*   0 : MOVSX reg_ax,reg_al [--:       o16 98                            ] ND,OPT,8086 */
        /* 320 001(98) : OPT,8086 */
        {I_MOVSX, 2, {REG_AX,REG_AL,0,0,0}, NO_DECORATOR, nasm_bytecodes+72537, 162},
    /*   1 : MOVSX reg_eax,reg_ax [--:       o32 98                            ] ND,OPT,ZU,386 */
        /* 321 001(98) : OPT,ZU,386 */
        {I_MOVSX, 2, {REG_EAX,REG_AX,0,0,0}, NO_DECORATOR, nasm_bytecodes+72557, 163},
    /*   2 : MOVSX reg_rax,reg_eax [--:       o64 98                            ] ND,OPT,ZU,LONG,PROT,X86_64 */
        /* 324 001(98) : OPT,ZU,LONG,PROT,X86_64 */
        {I_MOVSX, 2, {REG_RAX,REG_EAX,0,0,0}, NO_DECORATOR, nasm_bytecodes+72545, 164},
    /*   3 : MOVSX reg16,rm8 [rm:       o16 0f be /r                      ] AR0-1,SX,386 */
        /* 320 355 001(be) 110 : AR0,AR1,SX,386 */
        {I_MOVSX, 2, {REG_GPR|BITS16,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+66752, 165},
    /*   4 : MOVSX reg32,rm8 [rm:       o32 0f be /r                      ] AR0-1,SX,386 */
        /* 321 355 001(be) 110 : AR0,AR1,SX,386 */
        {I_MOVSX, 2, {REG_GPR|BITS32,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+66758, 165},
    /*   5 : MOVSX reg64,rm8 [rm:       o64 0f be /r                      ] AR0-1,SX,LONG,PROT,X86_64 */
        /* 324 355 001(be) 110 : AR0,AR1,SX,LONG,PROT,X86_64 */
        {I_MOVSX, 2, {REG_GPR|BITS64,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+66764, 166},
    /*   6 : MOVSX reg16,rm16 [rm:       o16 0f bf /r                      ] AR0-1,SX,386 */
        /* 320 355 001(bf) 110 : AR0,AR1,SX,386 */
        {I_MOVSX, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66770, 165},
    /*   7 : MOVSX reg32,rm16 [rm:       o32 0f bf /r                      ] AR0-1,SX,386 */
        /* 321 355 001(bf) 110 : AR0,AR1,SX,386 */
        {I_MOVSX, 2, {REG_GPR|BITS32,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66776, 165},
    /*   8 : MOVSX reg64,rm16 [rm:       o64 0f bf /r                      ] AR0-1,SX,LONG,PROT,X86_64 */
        /* 324 355 001(bf) 110 : AR0,AR1,SX,LONG,PROT,X86_64 */
        {I_MOVSX, 2, {REG_GPR|BITS64,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66782, 166},
    /*   9 : MOVSX reg16,rm32 [rm:       o16 63 /r                         ] ND,AR0-1,SX,LONG,PROT,X86_64 */
        /* 320 001(63) 110 : AR0,AR1,SX,LONG,PROT,X86_64 */
        {I_MOVSX, 2, {REG_GPR|BITS16,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+71493, 166},
    /*  10 : MOVSX reg32,rm32 [rm:       o32 63 /r                         ] ND,AR0-1,SX,LONG,PROT,X86_64 */
        /* 321 001(63) 110 : AR0,AR1,SX,LONG,PROT,X86_64 */
        {I_MOVSX, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+71498, 166},
    /*  11 : MOVSX reg64,rm32 [rm:       o64 63 /r                         ] ND,AR0-1,SX,LONG,PROT,X86_64 */
        /* 324 001(63) 110 : AR0,AR1,SX,LONG,PROT,X86_64 */
        {I_MOVSX, 2, {REG_GPR|BITS64,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+71503, 166},
};

static const struct itemplate instrux_MOVSXB[4] = {
    /*   0 : MOVSXB reg_ax,reg_al [--:       o16 98                            ] ND,OPT,8086 */
        /* 320 001(98) : OPT,8086 */
        {I_MOVSXB, 2, {REG_AX,REG_AL,0,0,0}, NO_DECORATOR, nasm_bytecodes+72537, 162},
    /*   1 : MOVSXB reg16,rm8 [rm:       o16 0f be /r                      ] ND,386 */
        /* 320 355 001(be) 110 : 386 */
        {I_MOVSXB, 2, {REG_GPR|BITS16,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+66752, 3},
    /*   2 : MOVSXB reg32,rm8 [rm:       o32 0f be /r                      ] ND,386 */
        /* 321 355 001(be) 110 : 386 */
        {I_MOVSXB, 2, {REG_GPR|BITS32,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+66758, 3},
    /*   3 : MOVSXB reg64,rm8 [rm:       o64 0f be /r                      ] ND,LONG,PROT,X86_64 */
        /* 324 355 001(be) 110 : LONG,PROT,X86_64 */
        {I_MOVSXB, 2, {REG_GPR|BITS64,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+66764, 24},
};

static const struct itemplate instrux_MOVSXW[4] = {
    /*   0 : MOVSXW reg_eax,reg_ax [--:       o32 98                            ] ND,OPT,ZU,386 */
        /* 321 001(98) : OPT,ZU,386 */
        {I_MOVSXW, 2, {REG_EAX,REG_AX,0,0,0}, NO_DECORATOR, nasm_bytecodes+72557, 163},
    /*   1 : MOVSXW reg16,rm16 [rm:       o16 0f bf /r                      ] ND,386 */
        /* 320 355 001(bf) 110 : 386 */
        {I_MOVSXW, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66770, 3},
    /*   2 : MOVSXW reg32,rm16 [rm:       o32 0f bf /r                      ] ND,386 */
        /* 321 355 001(bf) 110 : 386 */
        {I_MOVSXW, 2, {REG_GPR|BITS32,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66776, 3},
    /*   3 : MOVSXW reg64,rm16 [rm:       o64 0f bf /r                      ] ND,LONG,PROT,X86_64 */
        /* 324 355 001(bf) 110 : LONG,PROT,X86_64 */
        {I_MOVSXW, 2, {REG_GPR|BITS64,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66782, 24},
};

static const struct itemplate instrux_MOVSXD[4] = {
    /*   0 : MOVSXD reg_rax,reg_eax [--:       o64 98                            ] ND,OPT,ZU,LONG,PROT,X86_64 */
        /* 324 001(98) : OPT,ZU,LONG,PROT,X86_64 */
        {I_MOVSXD, 2, {REG_RAX,REG_EAX,0,0,0}, NO_DECORATOR, nasm_bytecodes+72545, 164},
    /*   1 : MOVSXD reg16,rm32 [rm:       o16 63 /r                         ] LONG,PROT,X86_64 */
        /* 320 001(63) 110 : LONG,PROT,X86_64 */
        {I_MOVSXD, 2, {REG_GPR|BITS16,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+71493, 24},
    /*   2 : MOVSXD reg32,rm32 [rm:       o32 63 /r                         ] LONG,PROT,X86_64 */
        /* 321 001(63) 110 : LONG,PROT,X86_64 */
        {I_MOVSXD, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+71498, 24},
    /*   3 : MOVSXD reg64,rm32 [rm:       o64 63 /r                         ] LONG,PROT,X86_64 */
        /* 324 001(63) 110 : LONG,PROT,X86_64 */
        {I_MOVSXD, 2, {REG_GPR|BITS64,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+71503, 24},
};

static const struct itemplate instrux_MOVZX[9] = {
    /*   0 : MOVZX reg16,rm8 [rm:       o16 0f b6 /r                      ] AR0-1,SX,386 */
        /* 320 355 001(b6) 110 : AR0,AR1,SX,386 */
        {I_MOVZX, 2, {REG_GPR|BITS16,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+66788, 165},
    /*   1 : MOVZX reg32,rm8 [rm:       o32 0f b6 /r                      ] AR0-1,SX,386 */
        /* 321 355 001(b6) 110 : AR0,AR1,SX,386 */
        {I_MOVZX, 2, {REG_GPR|BITS32,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+66794, 165},
    /*   2 : MOVZX reg64,rm8 [rm:       o64 0f b6 /r                      ] AR0-1,SX,LONG,PROT,X86_64 */
        /* 324 355 001(b6) 110 : AR0,AR1,SX,LONG,PROT,X86_64 */
        {I_MOVZX, 2, {REG_GPR|BITS64,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+66800, 166},
    /*   3 : MOVZX reg16,rm16 [rm:       o16 0f b7 /r                      ] AR0-1,SX,386 */
        /* 320 355 001(b7) 110 : AR0,AR1,SX,386 */
        {I_MOVZX, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66806, 165},
    /*   4 : MOVZX reg32,rm16 [rm:       o32 0f b7 /r                      ] AR0-1,SX,386 */
        /* 321 355 001(b7) 110 : AR0,AR1,SX,386 */
        {I_MOVZX, 2, {REG_GPR|BITS32,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66812, 165},
    /*   5 : MOVZX reg64,rm16 [rm:       o64 0f b7 /r                      ] AR0-1,SX,LONG,PROT,X86_64 */
        /* 324 355 001(b7) 110 : AR0,AR1,SX,LONG,PROT,X86_64 */
        {I_MOVZX, 2, {REG_GPR|BITS64,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66818, 166},
    /*   6 : MOVZX reg16,rm32 [rm:       nw o16 8b /r                      ] ND,AR0-1,SX,OPT,8086 */
        /* 327 320 001(8b) 110 : AR0,AR1,NWSIZE,SX,OPT,8086 */
        {I_MOVZX, 2, {REG_GPR|BITS16,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+66824, 167},
    /*   7 : MOVZX reg32,rm32 [rm:       nw o32 8b /r                      ] ND,AR0-1,SX,OPT,386 */
        /* 327 321 001(8b) 110 : AR0,AR1,NWSIZE,SX,OPT,386 */
        {I_MOVZX, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+66830, 168},
    /*   8 : MOVZX reg64,rm32 [rm:       nw o64 8b /r                      ] ND,AR0-1,SX,OPT,LONG,PROT,X86_64 */
        /* 327 324 001(8b) 110 : AR0,AR1,NWSIZE,SX,OPT,LONG,PROT,X86_64 */
        {I_MOVZX, 2, {REG_GPR|BITS64,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+66836, 169},
};

static const struct itemplate instrux_MOVZXB[3] = {
    /*   0 : MOVZXB reg16,rm8 [rm:       o16 0f b6 /r                      ] ND,386 */
        /* 320 355 001(b6) 110 : 386 */
        {I_MOVZXB, 2, {REG_GPR|BITS16,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+66788, 3},
    /*   1 : MOVZXB reg32,rm8 [rm:       o32 0f b6 /r                      ] ND,386 */
        /* 321 355 001(b6) 110 : 386 */
        {I_MOVZXB, 2, {REG_GPR|BITS32,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+66794, 3},
    /*   2 : MOVZXB reg64,rm8 [rm:       o64 0f b6 /r                      ] ND,LONG,PROT,X86_64 */
        /* 324 355 001(b6) 110 : LONG,PROT,X86_64 */
        {I_MOVZXB, 2, {REG_GPR|BITS64,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+66800, 24},
};

static const struct itemplate instrux_MOVZXW[3] = {
    /*   0 : MOVZXW reg16,rm16 [rm:       o16 0f b7 /r                      ] ND,386 */
        /* 320 355 001(b7) 110 : 386 */
        {I_MOVZXW, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66806, 3},
    /*   1 : MOVZXW reg32,rm16 [rm:       o32 0f b7 /r                      ] ND,386 */
        /* 321 355 001(b7) 110 : 386 */
        {I_MOVZXW, 2, {REG_GPR|BITS32,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66812, 3},
    /*   2 : MOVZXW reg64,rm16 [rm:       o64 0f b7 /r                      ] ND,LONG,PROT,X86_64 */
        /* 324 355 001(b7) 110 : LONG,PROT,X86_64 */
        {I_MOVZXW, 2, {REG_GPR|BITS64,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66818, 24},
};

static const struct itemplate instrux_MOVZXD[3] = {
    /*   0 : MOVZXD reg16,rm32 [rm:       nw o16 8b /r                      ] ND,OPT,8086 */
        /* 327 320 001(8b) 110 : NWSIZE,OPT,8086 */
        {I_MOVZXD, 2, {REG_GPR|BITS16,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+66824, 170},
    /*   1 : MOVZXD reg32,rm32 [rm:       nw o32 8b /r                      ] ND,OPT,386 */
        /* 327 321 001(8b) 110 : NWSIZE,OPT,386 */
        {I_MOVZXD, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+66830, 171},
    /*   2 : MOVZXD reg64,rm32 [rm:       nw o64 8b /r                      ] ND,OPT,LONG,PROT,X86_64 */
        /* 327 324 001(8b) 110 : NWSIZE,OPT,LONG,PROT,X86_64 */
        {I_MOVZXD, 2, {REG_GPR|BITS64,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+66836, 172},
};

static const struct itemplate instrux_CMPXCHG[4] = {
    /*   0 : CMPXCHG rm8,reg8 [mr:       hle o8 0f b0 /r                   ] SM0-1,LOCK,FL,PENT */
        /* 273 355 001(b0) 101 : SM0,SM1,LOCK,FL,PENT */
        {I_CMPXCHG, 2, {RM_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+66842, 173},
    /*   1 : CMPXCHG rm16,reg16 [mr:       hle o16 0f b1 /r                  ] SM0-1,LOCK,FL,PENT */
        /* 273 320 355 001(b1) 101 : SM0,SM1,LOCK,FL,PENT */
        {I_CMPXCHG, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55773, 173},
    /*   2 : CMPXCHG rm32,reg32 [mr:       hle o32 0f b1 /r                  ] SM0-1,LOCK,FL,PENT */
        /* 273 321 355 001(b1) 101 : SM0,SM1,LOCK,FL,PENT */
        {I_CMPXCHG, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+55780, 173},
    /*   3 : CMPXCHG rm64,reg64 [mr:       hle o64 0f b1 /r                  ] SM0-1,LOCK,LONG,FL,PROT,X86_64 */
        /* 273 324 355 001(b1) 101 : SM0,SM1,LOCK,LONG,FL,PROT,X86_64 */
        {I_CMPXCHG, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+55787, 27},
};

static const struct itemplate instrux_CMPXCHG8B[1] = {
    /*   0 : CMPXCHG8B mem64 [m:        hle norexw 0f c7 /1               ] LOCK,FL,PENT */
        /* 273 317 355 001(c7) 201 : LOCK,FL,PENT */
        {I_CMPXCHG8B, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55794, 174},
};

static const struct itemplate instrux_CMPXCHG16B[1] = {
    /*   0 : CMPXCHG16B mem128 [m:        o64 0f c7 /1                      ] LOCK,LONG,FL,PROT,X86_64 */
        /* 324 355 001(c7) 201 : LOCK,LONG,FL,PROT,X86_64 */
        {I_CMPXCHG16B, 1, {MEMORY|BITS128,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66848, 76},
};

static const struct itemplate instrux_XADD[4] = {
    /*   0 : XADD rm8,reg8 [mr:       hle o8 0f c0 /r                   ] SM0-1,LOCK,FL,486 */
        /* 273 355 001(c0) 101 : SM0,SM1,LOCK,FL,486 */
        {I_XADD, 2, {RM_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+66854, 175},
    /*   1 : XADD rm16,reg16 [mr:       hle o16 0f c1 /r                  ] SM0-1,LOCK,FL,486 */
        /* 273 320 355 001(c1) 101 : SM0,SM1,LOCK,FL,486 */
        {I_XADD, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+55801, 175},
    /*   2 : XADD rm32,reg32 [mr:       hle o32 0f c1 /r                  ] SM0-1,LOCK,FL,486 */
        /* 273 321 355 001(c1) 101 : SM0,SM1,LOCK,FL,486 */
        {I_XADD, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+55808, 175},
    /*   3 : XADD rm64,reg64 [mr:       hle o64 0f c1 /r                  ] SM0-1,LOCK,LONG,FL,PROT,X86_64 */
        /* 273 324 355 001(c1) 101 : SM0,SM1,LOCK,LONG,FL,PROT,X86_64 */
        {I_XADD, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+55815, 27},
};

static const struct itemplate instrux_XCHG[15] = {
    /*   0 : XCHG reg_ax,reg16 [-r:       o16 90+r                          ] 8086 */
        /* 320 011 220 : 8086 */
        {I_XCHG, 2, {REG_AX,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+72561, 23},
    /*   1 : XCHG reg_rax,reg64 [-r:       o64 90+r                          ] ZU,LONG,PROT,X86_64 */
        /* 324 011 220 : ZU,LONG,PROT,X86_64 */
        {I_XCHG, 2, {REG_RAX,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+72565, 176},
    /*   2 : XCHG reg16,reg_ax [r-:       o16 90+r                          ] ND,8086 */
        /* 320 010 220 : 8086 */
        {I_XCHG, 2, {REG_GPR|BITS16,REG_AX,0,0,0}, NO_DECORATOR, nasm_bytecodes+72569, 23},
    /*   3 : XCHG reg64,reg_rax [r-:       o64 90+r                          ] ND,LONG,PROT,X86_64 */
        /* 324 010 220 : LONG,PROT,X86_64 */
        {I_XCHG, 2, {REG_GPR|BITS64,REG_RAX,0,0,0}, NO_DECORATOR, nasm_bytecodes+72573, 24},
    /*   4 : XCHG reg_eax,reg32na [-r:       o32 90+r                          ] ZU,386 */
        /* 321 011 220 : ZU,386 */
        {I_XCHG, 2, {REG_EAX,REG_NA|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+72577, 177},
    /*   5 : XCHG reg32na,reg_eax [r-:       o32 90+r                          ] ND,386 */
        /* 321 010 220 : 386 */
        {I_XCHG, 2, {REG_NA|BITS32,REG_EAX,0,0,0}, NO_DECORATOR, nasm_bytecodes+72581, 3},
    /*   6 : XCHG reg_eax,reg_eax [--:       o32 90                            ] ND,NOREX,NOAPX,ZU,NOLONG,386 */
        /* 321 001(90) : NOREX,NOAPX,ZU,NOLONG,386 */
        {I_XCHG, 2, {REG_EAX|RN_L16,REG_EAX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+72585, 178},
    /*   7 : XCHG reg8,rm8 [rm:       hlenl o8 86 /r                    ] SM0-1,LOCK1,8086 */
        /* 272 001(86) 110 : SM0,SM1,LOCK1,8086 */
        {I_XCHG, 2, {REG_GPR|BITS8,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+71508, 179},
    /*   8 : XCHG reg16,rm16 [rm:       hlenl o16 87 /r                   ] SM0-1,LOCK1,8086 */
        /* 272 320 001(87) 110 : SM0,SM1,LOCK1,8086 */
        {I_XCHG, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66860, 179},
    /*   9 : XCHG reg32,rm32 [rm:       hlenl o32 87 /r                   ] SM0-1,LOCK1,386 */
        /* 272 321 001(87) 110 : SM0,SM1,LOCK1,386 */
        {I_XCHG, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+66866, 180},
    /*  10 : XCHG reg64,rm64 [rm:       hlenl o64 87 /r                   ] SM0-1,LOCK1,LONG,PROT,X86_64 */
        /* 272 324 001(87) 110 : SM0,SM1,LOCK1,LONG,PROT,X86_64 */
        {I_XCHG, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+66872, 181},
    /*  11 : XCHG rm8,reg8 [mr:       hlenl o8 86 /r                    ] ND,SM0-1,LOCK,8086 */
        /* 272 001(86) 101 : SM0,SM1,LOCK,8086 */
        {I_XCHG, 2, {RM_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+71513, 182},
    /*  12 : XCHG rm16,reg16 [mr:       hlenl o16 87 /r                   ] ND,SM0-1,LOCK,8086 */
        /* 272 320 001(87) 101 : SM0,SM1,LOCK,8086 */
        {I_XCHG, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66878, 182},
    /*  13 : XCHG rm32,reg32 [mr:       hlenl o32 87 /r                   ] ND,SM0-1,LOCK,386 */
        /* 272 321 001(87) 101 : SM0,SM1,LOCK,386 */
        {I_XCHG, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+66884, 183},
    /*  14 : XCHG rm64,reg64 [mr:       hlenl o64 87 /r                   ] ND,SM0-1,LOCK,LONG,PROT,X86_64 */
        /* 272 324 001(87) 101 : SM0,SM1,LOCK,LONG,PROT,X86_64 */
        {I_XCHG, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+66890, 184},
};

static const struct itemplate instrux_CMPXCHG486[3] = {
    /*   0 : CMPXCHG486 rm8,reg8 [mr:       o8 0f a6 /r                       ] ND,SM0-1,NOREX,NOAPX,LOCK,NOLONG,FL,UNDOC,OBSOLETE,486 */
        /* 355 001(a6) 101 : SM0,SM1,NOREX,NOAPX,LOCK,NOLONG,FL,UNDOC,OBSOLETE,486 */
        {I_CMPXCHG486, 2, {RM_GPR|BITS8|RN_L16,REG_GPR|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66747, 185},
    /*   1 : CMPXCHG486 rm16,reg16 [mr:       o16 0f a7 /r                      ] ND,SM0-1,NOREX,NOAPX,LOCK,NOLONG,FL,UNDOC,OBSOLETE,486 */
        /* 320 355 001(a7) 101 : SM0,SM1,NOREX,NOAPX,LOCK,NOLONG,FL,UNDOC,OBSOLETE,486 */
        {I_CMPXCHG486, 2, {RM_GPR|BITS16|RN_L16,REG_GPR|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66728, 185},
    /*   2 : CMPXCHG486 rm32,reg32 [mr:       o32 0f a7 /r                      ] ND,SM0-1,NOREX,NOAPX,LOCK,NOLONG,FL,UNDOC,OBSOLETE,486 */
        /* 321 355 001(a7) 101 : SM0,SM1,NOREX,NOAPX,LOCK,NOLONG,FL,UNDOC,OBSOLETE,486 */
        {I_CMPXCHG486, 2, {RM_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66734, 185},
};

static const struct itemplate instrux_JMPABS[2] = {
    /*   0 : JMPABS imm64|near [i:        a64 np rex2 a1 iq                 ] LONG,PROT,APX,X86_64 */
        /* 313 360 350 001(a1) 054 : LONG,REX2,PROT,APX,X86_64 */
        {I_JMPABS, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55822, 186},
    /*   1 : JMPABS imm64|abs|near [i:        a64 np rex2 a1 iq                 ] ND,LONG,PROT,APX,X86_64 */
        /* 313 360 350 001(a1) 054 : LONG,REX2,PROT,APX,X86_64 */
        {I_JMPABS, 1, {IMM_NORMAL|BITS64|ABS|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55822, 186},
};

static const struct itemplate instrux_JMP[28] = {
    /*   0 : JMP imm64|abs|near [i:        a64 np rex2 a1 iq                 ] ND,LONG,PROT,APX,X86_64 */
        /* 313 360 350 001(a1) 054 : LONG,REX2,PROT,APX,X86_64 */
        {I_JMP, 1, {IMM_NORMAL|BITS64|ABS|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55822, 186},
    /*   1 : JMP imm16|short [i:        nw o16 eb rel8                    ] ND,AR0,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 327 320 001(eb) 050 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_JMP, 1, {IMM_NORMAL|BITS16|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55830, 187},
    /*   2 : JMP imm32|short [i:        nw o32 eb rel8                    ] ND,AR0,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 327 321 001(eb) 050 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_JMP, 1, {IMM_NORMAL|BITS32|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55837, 187},
    /*   3 : JMP imm64|short [i:        nw o64 eb rel8                    ] ND,AR0,OSIZE,NOAPX,LONG,PROT,X86_64 */
        /* 327 324 001(eb) 050 : AR0,NWSIZE,OSIZE,NOAPX,LONG,PROT,X86_64 */
        {I_JMP, 1, {IMM_NORMAL|BITS64|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55844, 188},
    /*   4 : JMP imm16|near [i:        jmp8 nw o16 eb rel8               ] AR0,OSIZE,JMP_RELAX,NOREX,NOAPX,NOLONG,8086 */
        /* 371 327 320 001(eb) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,NOREX,NOAPX,NOLONG,8086 */
        {I_JMP, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55829, 189},
    /*   5 : JMP imm32|near [i:        jmp8 nw o32 eb rel8               ] AR0,OSIZE,JMP_RELAX,NOREX,NOAPX,NOLONG,8086 */
        /* 371 327 321 001(eb) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,NOREX,NOAPX,NOLONG,8086 */
        {I_JMP, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55836, 189},
    /*   6 : JMP imm64|near [i:        jmp8 nw o64 eb rel8               ] AR0,OSIZE,JMP_RELAX,NOAPX,LONG,PROT,X86_64 */
        /* 371 327 324 001(eb) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,NOAPX,LONG,PROT,X86_64 */
        {I_JMP, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55843, 190},
    /*   7 : JMP imm32|near [i:        jmp8 nw o64 eb rel8               ] ND,AR0,SX,JMP_RELAX,NOAPX,LONG,PROT,X86_64 */
        /* 371 327 324 001(eb) 050 : AR0,NWSIZE,SX,JMP_RELAX,NOAPX,LONG,PROT,X86_64 */
        {I_JMP, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55843, 191},
    /*   8 : JMP imm16|near [i:        nw o16 e9 rel                     ] AR0,OSIZE,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 320 001(e9) 064 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JMP, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66896, 192},
    /*   9 : JMP imm32|near [i:        nw o32 e9 rel                     ] AR0,OSIZE,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 321 001(e9) 064 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JMP, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66902, 192},
    /*  10 : JMP imm64|near [i:        nw o64 e9 rel                     ] AR0,OSIZE,LONG,BND,PROT,X86_64 */
        /* 327 324 001(e9) 064 : AR0,NWSIZE,OSIZE,LONG,BND,PROT,X86_64 */
        {I_JMP, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66908, 193},
    /*  11 : JMP imm32|near [i:        nw o64 e9 rel                     ] ND,AR0,SX,LONG,BND,PROT,X86_64 */
        /* 327 324 001(e9) 064 : AR0,NWSIZE,SX,LONG,BND,PROT,X86_64 */
        {I_JMP, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66908, 194},
    /*  12 : JMP rm16|near [m:        nw o16 ff /4                      ] AR0,OSIZE,BND,8086 */
        /* 327 320 001(ff) 204 : AR0,NWSIZE,OSIZE,BND,8086 */
        {I_JMP, 1, {RM_GPR|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66914, 195},
    /*  13 : JMP rm32|near [m:        nw o32 ff /4                      ] AR0,OSIZE,BND,386 */
        /* 327 321 001(ff) 204 : AR0,NWSIZE,OSIZE,BND,386 */
        {I_JMP, 1, {RM_GPR|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66920, 196},
    /*  14 : JMP rm64|near [m:        nw o64 ff /4                      ] AR0,OSIZE,LONG,BND,PROT,X86_64 */
        /* 327 324 001(ff) 204 : AR0,NWSIZE,OSIZE,LONG,BND,PROT,X86_64 */
        {I_JMP, 1, {RM_GPR|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66926, 193},
    /*  15 : JMP imm16|far [i:        o16 ea iwd seg                    ] ND,AR0,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 320 001(ea) 034 074 : AR0,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_JMP, 1, {IMM_NORMAL|BITS16|FAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66932, 197},
    /*  16 : JMP imm32|far [i:        o32 ea iwd seg                    ] ND,AR0,OSIZE,NOREX,NOAPX,NOLONG,386 */
        /* 321 001(ea) 034 074 : AR0,OSIZE,NOREX,NOAPX,NOLONG,386 */
        {I_JMP, 1, {IMM_NORMAL|BITS32|FAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66938, 198},
    /*  17 : JMP imm16:imm16 [ji:       o16 ea iw iw                      ] ND,SM0-1,AR0,SX,NOREX,NOAPX,NOLONG,8086 */
        /* 320 001(ea) 031 030 : SM0,SM1,AR0,SX,NOREX,NOAPX,NOLONG,8086 */
        {I_JMP, 2, {IMM_NORMAL|BITS16|COLON,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66944, 199},
    /*  18 : JMP imm32:imm32 [ji:       o32 ea id iw                      ] ND,SM0-1,AR0,SX,NOREX,NOAPX,NOLONG,386 */
        /* 321 001(ea) 041 030 : SM0,SM1,AR0,SX,NOREX,NOAPX,NOLONG,386 */
        {I_JMP, 2, {IMM_NORMAL|BITS32|COLON,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+66950, 200},
    /*  19 : JMP imm16:imm16|far [ji:       o16 ea iw iw                      ] ND,SM0-1,AR0,SX,NOREX,NOAPX,NOLONG,8086 */
        /* 320 001(ea) 031 030 : SM0,SM1,AR0,SX,NOREX,NOAPX,NOLONG,8086 */
        {I_JMP, 2, {IMM_NORMAL|BITS16|COLON,IMM_NORMAL|BITS16|FAR,0,0,0}, NO_DECORATOR, nasm_bytecodes+66944, 199},
    /*  20 : JMP imm32:imm32|far [ji:       o32 ea id iw                      ] ND,SM0-1,AR0,SX,NOREX,NOAPX,NOLONG,386 */
        /* 321 001(ea) 041 030 : SM0,SM1,AR0,SX,NOREX,NOAPX,NOLONG,386 */
        {I_JMP, 2, {IMM_NORMAL|BITS32|COLON,IMM_NORMAL|BITS32|FAR,0,0,0}, NO_DECORATOR, nasm_bytecodes+66950, 200},
    /*  21 : JMP imm16:imm16 [ji:       o16 ea iw iw                      ] AR1,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 320 001(ea) 031 030 : AR1,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_JMP, 2, {IMM_NORMAL|BITS16|COLON,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66944, 201},
    /*  22 : JMP imm16:imm32 [ji:       o32 ea id iw                      ] AR1,OSIZE,NOREX,NOAPX,NOLONG,386 */
        /* 321 001(ea) 041 030 : AR1,OSIZE,NOREX,NOAPX,NOLONG,386 */
        {I_JMP, 2, {IMM_NORMAL|BITS16|COLON,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+66950, 202},
    /*  23 : JMP imm16:imm16|far [ji:       o16 ea iw iw                      ] ND,AR1,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 320 001(ea) 031 030 : AR1,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_JMP, 2, {IMM_NORMAL|BITS16|COLON,IMM_NORMAL|BITS16|FAR,0,0,0}, NO_DECORATOR, nasm_bytecodes+66944, 201},
    /*  24 : JMP imm16:imm32|far [ji:       o32 ea id iw                      ] ND,AR1,OSIZE,NOREX,NOAPX,NOLONG,386 */
        /* 321 001(ea) 041 030 : AR1,OSIZE,NOREX,NOAPX,NOLONG,386 */
        {I_JMP, 2, {IMM_NORMAL|BITS16|COLON,IMM_NORMAL|BITS32|FAR,0,0,0}, NO_DECORATOR, nasm_bytecodes+66950, 202},
    /*  25 : JMP mem16|far [m:        o16 ff /5                         ] AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 320 001(ff) 205 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_JMP, 1, {MEMORY|BITS16|RN_L16|FAR|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71518, 187},
    /*  26 : JMP mem32|far [m:        o32 ff /5                         ] AR0,NWSIZE,OSIZE,386 */
        /* 321 001(ff) 205 : AR0,NWSIZE,OSIZE,386 */
        {I_JMP, 1, {MEMORY|BITS32|FAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71523, 203},
    /*  27 : JMP mem64|far [m:        o64 ff /5                         ] AR0,NWSIZE,OSIZE,LONG,386,X86_64 */
        /* 324 001(ff) 205 : AR0,NWSIZE,OSIZE,LONG,PROT,X86_64 */
        {I_JMP, 1, {MEMORY|BITS64|FAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71528, 204},
};

static const struct itemplate instrux_JA[12] = {
    /*   0 : JA imm16|short [i:        nw o16 77 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 320 001(77) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JA, 1, {IMM_NORMAL|BITS16|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55851, 205},
    /*   1 : JA imm32|short [i:        nw o32 77 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 321 001(77) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JA, 1, {IMM_NORMAL|BITS32|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55963, 205},
    /*   2 : JA imm64|short [i:        nw o64 77 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 001(77) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JA, 1, {IMM_NORMAL|BITS64|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56075, 206},
    /*   3 : JA imm16|near [i:        jcc8 nw o16 77 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 370 327 320 001(77) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JA, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55850, 207},
    /*   4 : JA imm32|near [i:        jcc8 nw o32 77 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 370 327 321 001(77) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JA, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55962, 207},
    /*   5 : JA imm64|near [i:        jcc8 nw o64 77 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(77) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JA, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56074, 208},
    /*   6 : JA imm32|near [i:        jcc8 nw o64 77 rel8             ] ND,AR0,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(77) 050 : AR0,NWSIZE,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JA, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56074, 209},
    /*   7 : JA imm16|near [i:        nw o16 0f 87 rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        /* 327 320 355 001(87) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JA, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56186, 210},
    /*   8 : JA imm32|near [i:        nw o32 0f 87 rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        /* 327 321 355 001(87) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JA, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56298, 210},
    /*   9 : JA imm64|near [i:        nw o64 0f 87 rel                ] AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(87) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JA, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56410, 206},
    /*  10 : JA imm32|near [i:        nw o64 0f 87 rel                ] ND,AR0,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(87) 064 : AR0,NWSIZE,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JA, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56410, 211},
    /*  11 : JA imm [i:        76 jlen e9 rel                  ] ND,AR0,OSIZE,NOAPX,8086 */
        /* 001(76) 373 001(e9) 064 : AR0,OSIZE,NOAPX,8086 */
        {I_JA, 1, {IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56522, 212},
};

static const struct itemplate instrux_JAE[12] = {
    /*   0 : JAE imm16|short [i:        nw o16 73 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 320 001(73) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JAE, 1, {IMM_NORMAL|BITS16|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55858, 205},
    /*   1 : JAE imm32|short [i:        nw o32 73 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 321 001(73) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JAE, 1, {IMM_NORMAL|BITS32|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55970, 205},
    /*   2 : JAE imm64|short [i:        nw o64 73 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 001(73) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JAE, 1, {IMM_NORMAL|BITS64|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56082, 206},
    /*   3 : JAE imm16|near [i:        jcc8 nw o16 73 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086,ND */
        /* 370 327 320 001(73) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JAE, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55857, 207},
    /*   4 : JAE imm32|near [i:        jcc8 nw o32 73 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086,ND */
        /* 370 327 321 001(73) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JAE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55969, 207},
    /*   5 : JAE imm64|near [i:        jcc8 nw o64 73 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64,ND */
        /* 370 327 324 001(73) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JAE, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56081, 208},
    /*   6 : JAE imm32|near [i:        jcc8 nw o64 73 rel8             ] ND,AR0,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(73) 050 : AR0,NWSIZE,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JAE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56081, 209},
    /*   7 : JAE imm16|near [i:        nw o16 0f 83 rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386,ND */
        /* 327 320 355 001(83) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JAE, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56193, 210},
    /*   8 : JAE imm32|near [i:        nw o32 0f 83 rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386,ND */
        /* 327 321 355 001(83) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JAE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56305, 210},
    /*   9 : JAE imm64|near [i:        nw o64 0f 83 rel                ] AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64,ND */
        /* 327 324 355 001(83) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JAE, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56417, 206},
    /*  10 : JAE imm32|near [i:        nw o64 0f 83 rel                ] ND,AR0,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(83) 064 : AR0,NWSIZE,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JAE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56417, 211},
    /*  11 : JAE imm [i:        72 jlen e9 rel                  ] ND,AR0,OSIZE,NOAPX,8086 */
        /* 001(72) 373 001(e9) 064 : AR0,OSIZE,NOAPX,8086 */
        {I_JAE, 1, {IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56529, 212},
};

static const struct itemplate instrux_JB[12] = {
    /*   0 : JB imm16|short [i:        nw o16 72 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 320 001(72) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JB, 1, {IMM_NORMAL|BITS16|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55865, 205},
    /*   1 : JB imm32|short [i:        nw o32 72 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 321 001(72) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JB, 1, {IMM_NORMAL|BITS32|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55977, 205},
    /*   2 : JB imm64|short [i:        nw o64 72 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 001(72) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JB, 1, {IMM_NORMAL|BITS64|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56089, 206},
    /*   3 : JB imm16|near [i:        jcc8 nw o16 72 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086,ND */
        /* 370 327 320 001(72) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JB, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55864, 207},
    /*   4 : JB imm32|near [i:        jcc8 nw o32 72 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086,ND */
        /* 370 327 321 001(72) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JB, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55976, 207},
    /*   5 : JB imm64|near [i:        jcc8 nw o64 72 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64,ND */
        /* 370 327 324 001(72) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JB, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56088, 208},
    /*   6 : JB imm32|near [i:        jcc8 nw o64 72 rel8             ] ND,AR0,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(72) 050 : AR0,NWSIZE,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JB, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56088, 209},
    /*   7 : JB imm16|near [i:        nw o16 0f 82 rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386,ND */
        /* 327 320 355 001(82) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JB, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56200, 210},
    /*   8 : JB imm32|near [i:        nw o32 0f 82 rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386,ND */
        /* 327 321 355 001(82) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JB, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56312, 210},
    /*   9 : JB imm64|near [i:        nw o64 0f 82 rel                ] AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64,ND */
        /* 327 324 355 001(82) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JB, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56424, 206},
    /*  10 : JB imm32|near [i:        nw o64 0f 82 rel                ] ND,AR0,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(82) 064 : AR0,NWSIZE,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JB, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56424, 211},
    /*  11 : JB imm [i:        73 jlen e9 rel                  ] ND,AR0,OSIZE,NOAPX,8086 */
        /* 001(73) 373 001(e9) 064 : AR0,OSIZE,NOAPX,8086 */
        {I_JB, 1, {IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56536, 212},
};

static const struct itemplate instrux_JBE[12] = {
    /*   0 : JBE imm16|short [i:        nw o16 76 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 320 001(76) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JBE, 1, {IMM_NORMAL|BITS16|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55872, 205},
    /*   1 : JBE imm32|short [i:        nw o32 76 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 321 001(76) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JBE, 1, {IMM_NORMAL|BITS32|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55984, 205},
    /*   2 : JBE imm64|short [i:        nw o64 76 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 001(76) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JBE, 1, {IMM_NORMAL|BITS64|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56096, 206},
    /*   3 : JBE imm16|near [i:        jcc8 nw o16 76 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086,ND */
        /* 370 327 320 001(76) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JBE, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55871, 207},
    /*   4 : JBE imm32|near [i:        jcc8 nw o32 76 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086,ND */
        /* 370 327 321 001(76) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JBE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55983, 207},
    /*   5 : JBE imm64|near [i:        jcc8 nw o64 76 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64,ND */
        /* 370 327 324 001(76) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JBE, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56095, 208},
    /*   6 : JBE imm32|near [i:        jcc8 nw o64 76 rel8             ] ND,AR0,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(76) 050 : AR0,NWSIZE,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JBE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56095, 209},
    /*   7 : JBE imm16|near [i:        nw o16 0f 86 rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386,ND */
        /* 327 320 355 001(86) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JBE, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56207, 210},
    /*   8 : JBE imm32|near [i:        nw o32 0f 86 rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386,ND */
        /* 327 321 355 001(86) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JBE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56319, 210},
    /*   9 : JBE imm64|near [i:        nw o64 0f 86 rel                ] AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64,ND */
        /* 327 324 355 001(86) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JBE, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56431, 206},
    /*  10 : JBE imm32|near [i:        nw o64 0f 86 rel                ] ND,AR0,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(86) 064 : AR0,NWSIZE,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JBE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56431, 211},
    /*  11 : JBE imm [i:        77 jlen e9 rel                  ] ND,AR0,OSIZE,NOAPX,8086 */
        /* 001(77) 373 001(e9) 064 : AR0,OSIZE,NOAPX,8086 */
        {I_JBE, 1, {IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56543, 212},
};

static const struct itemplate instrux_JC[12] = {
    /*   0 : JC imm16|short [i:        nw o16 72 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 320 001(72) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JC, 1, {IMM_NORMAL|BITS16|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55865, 205},
    /*   1 : JC imm32|short [i:        nw o32 72 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 321 001(72) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JC, 1, {IMM_NORMAL|BITS32|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55977, 205},
    /*   2 : JC imm64|short [i:        nw o64 72 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 001(72) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JC, 1, {IMM_NORMAL|BITS64|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56089, 206},
    /*   3 : JC imm16|near [i:        jcc8 nw o16 72 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 370 327 320 001(72) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JC, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55864, 207},
    /*   4 : JC imm32|near [i:        jcc8 nw o32 72 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 370 327 321 001(72) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JC, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55976, 207},
    /*   5 : JC imm64|near [i:        jcc8 nw o64 72 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(72) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JC, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56088, 208},
    /*   6 : JC imm32|near [i:        jcc8 nw o64 72 rel8             ] ND,AR0,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(72) 050 : AR0,NWSIZE,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JC, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56088, 209},
    /*   7 : JC imm16|near [i:        nw o16 0f 82 rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        /* 327 320 355 001(82) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JC, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56200, 210},
    /*   8 : JC imm32|near [i:        nw o32 0f 82 rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        /* 327 321 355 001(82) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JC, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56312, 210},
    /*   9 : JC imm64|near [i:        nw o64 0f 82 rel                ] AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(82) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JC, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56424, 206},
    /*  10 : JC imm32|near [i:        nw o64 0f 82 rel                ] ND,AR0,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(82) 064 : AR0,NWSIZE,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JC, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56424, 211},
    /*  11 : JC imm [i:        73 jlen e9 rel                  ] ND,AR0,OSIZE,NOAPX,8086 */
        /* 001(73) 373 001(e9) 064 : AR0,OSIZE,NOAPX,8086 */
        {I_JC, 1, {IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56536, 212},
};

static const struct itemplate instrux_JE[12] = {
    /*   0 : JE imm16|short [i:        nw o16 74 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 320 001(74) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JE, 1, {IMM_NORMAL|BITS16|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55879, 205},
    /*   1 : JE imm32|short [i:        nw o32 74 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 321 001(74) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JE, 1, {IMM_NORMAL|BITS32|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55991, 205},
    /*   2 : JE imm64|short [i:        nw o64 74 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 001(74) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JE, 1, {IMM_NORMAL|BITS64|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56103, 206},
    /*   3 : JE imm16|near [i:        jcc8 nw o16 74 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086,ND */
        /* 370 327 320 001(74) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JE, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55878, 207},
    /*   4 : JE imm32|near [i:        jcc8 nw o32 74 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086,ND */
        /* 370 327 321 001(74) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55990, 207},
    /*   5 : JE imm64|near [i:        jcc8 nw o64 74 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64,ND */
        /* 370 327 324 001(74) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JE, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56102, 208},
    /*   6 : JE imm32|near [i:        jcc8 nw o64 74 rel8             ] ND,AR0,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(74) 050 : AR0,NWSIZE,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56102, 209},
    /*   7 : JE imm16|near [i:        nw o16 0f 84 rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386,ND */
        /* 327 320 355 001(84) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JE, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56214, 210},
    /*   8 : JE imm32|near [i:        nw o32 0f 84 rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386,ND */
        /* 327 321 355 001(84) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56326, 210},
    /*   9 : JE imm64|near [i:        nw o64 0f 84 rel                ] AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64,ND */
        /* 327 324 355 001(84) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JE, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56438, 206},
    /*  10 : JE imm32|near [i:        nw o64 0f 84 rel                ] ND,AR0,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(84) 064 : AR0,NWSIZE,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56438, 211},
    /*  11 : JE imm [i:        75 jlen e9 rel                  ] ND,AR0,OSIZE,NOAPX,8086 */
        /* 001(75) 373 001(e9) 064 : AR0,OSIZE,NOAPX,8086 */
        {I_JE, 1, {IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56550, 212},
};

static const struct itemplate instrux_JG[12] = {
    /*   0 : JG imm16|short [i:        nw o16 7f rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 320 001(7f) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JG, 1, {IMM_NORMAL|BITS16|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55886, 205},
    /*   1 : JG imm32|short [i:        nw o32 7f rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 321 001(7f) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JG, 1, {IMM_NORMAL|BITS32|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55998, 205},
    /*   2 : JG imm64|short [i:        nw o64 7f rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 001(7f) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JG, 1, {IMM_NORMAL|BITS64|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56110, 206},
    /*   3 : JG imm16|near [i:        jcc8 nw o16 7f rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 370 327 320 001(7f) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JG, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55885, 207},
    /*   4 : JG imm32|near [i:        jcc8 nw o32 7f rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 370 327 321 001(7f) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JG, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55997, 207},
    /*   5 : JG imm64|near [i:        jcc8 nw o64 7f rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(7f) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JG, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56109, 208},
    /*   6 : JG imm32|near [i:        jcc8 nw o64 7f rel8             ] ND,AR0,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(7f) 050 : AR0,NWSIZE,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JG, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56109, 209},
    /*   7 : JG imm16|near [i:        nw o16 0f 8f rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        /* 327 320 355 001(8f) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JG, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56221, 210},
    /*   8 : JG imm32|near [i:        nw o32 0f 8f rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        /* 327 321 355 001(8f) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JG, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56333, 210},
    /*   9 : JG imm64|near [i:        nw o64 0f 8f rel                ] AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(8f) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JG, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56445, 206},
    /*  10 : JG imm32|near [i:        nw o64 0f 8f rel                ] ND,AR0,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(8f) 064 : AR0,NWSIZE,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JG, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56445, 211},
    /*  11 : JG imm [i:        7e jlen e9 rel                  ] ND,AR0,OSIZE,NOAPX,8086 */
        /* 001(7e) 373 001(e9) 064 : AR0,OSIZE,NOAPX,8086 */
        {I_JG, 1, {IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56557, 212},
};

static const struct itemplate instrux_JGE[12] = {
    /*   0 : JGE imm16|short [i:        nw o16 7d rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 320 001(7d) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JGE, 1, {IMM_NORMAL|BITS16|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55893, 205},
    /*   1 : JGE imm32|short [i:        nw o32 7d rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 321 001(7d) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JGE, 1, {IMM_NORMAL|BITS32|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56005, 205},
    /*   2 : JGE imm64|short [i:        nw o64 7d rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 001(7d) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JGE, 1, {IMM_NORMAL|BITS64|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56117, 206},
    /*   3 : JGE imm16|near [i:        jcc8 nw o16 7d rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086,ND */
        /* 370 327 320 001(7d) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JGE, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55892, 207},
    /*   4 : JGE imm32|near [i:        jcc8 nw o32 7d rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086,ND */
        /* 370 327 321 001(7d) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JGE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56004, 207},
    /*   5 : JGE imm64|near [i:        jcc8 nw o64 7d rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64,ND */
        /* 370 327 324 001(7d) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JGE, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56116, 208},
    /*   6 : JGE imm32|near [i:        jcc8 nw o64 7d rel8             ] ND,AR0,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(7d) 050 : AR0,NWSIZE,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JGE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56116, 209},
    /*   7 : JGE imm16|near [i:        nw o16 0f 8d rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386,ND */
        /* 327 320 355 001(8d) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JGE, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56228, 210},
    /*   8 : JGE imm32|near [i:        nw o32 0f 8d rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386,ND */
        /* 327 321 355 001(8d) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JGE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56340, 210},
    /*   9 : JGE imm64|near [i:        nw o64 0f 8d rel                ] AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64,ND */
        /* 327 324 355 001(8d) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JGE, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56452, 206},
    /*  10 : JGE imm32|near [i:        nw o64 0f 8d rel                ] ND,AR0,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(8d) 064 : AR0,NWSIZE,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JGE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56452, 211},
    /*  11 : JGE imm [i:        7c jlen e9 rel                  ] ND,AR0,OSIZE,NOAPX,8086 */
        /* 001(7c) 373 001(e9) 064 : AR0,OSIZE,NOAPX,8086 */
        {I_JGE, 1, {IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56564, 212},
};

static const struct itemplate instrux_JL[12] = {
    /*   0 : JL imm16|short [i:        nw o16 7c rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 320 001(7c) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JL, 1, {IMM_NORMAL|BITS16|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55900, 205},
    /*   1 : JL imm32|short [i:        nw o32 7c rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 321 001(7c) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JL, 1, {IMM_NORMAL|BITS32|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56012, 205},
    /*   2 : JL imm64|short [i:        nw o64 7c rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 001(7c) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JL, 1, {IMM_NORMAL|BITS64|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56124, 206},
    /*   3 : JL imm16|near [i:        jcc8 nw o16 7c rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 370 327 320 001(7c) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JL, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55899, 207},
    /*   4 : JL imm32|near [i:        jcc8 nw o32 7c rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 370 327 321 001(7c) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JL, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56011, 207},
    /*   5 : JL imm64|near [i:        jcc8 nw o64 7c rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(7c) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JL, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56123, 208},
    /*   6 : JL imm32|near [i:        jcc8 nw o64 7c rel8             ] ND,AR0,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(7c) 050 : AR0,NWSIZE,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JL, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56123, 209},
    /*   7 : JL imm16|near [i:        nw o16 0f 8c rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        /* 327 320 355 001(8c) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JL, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56235, 210},
    /*   8 : JL imm32|near [i:        nw o32 0f 8c rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        /* 327 321 355 001(8c) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JL, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56347, 210},
    /*   9 : JL imm64|near [i:        nw o64 0f 8c rel                ] AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(8c) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JL, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56459, 206},
    /*  10 : JL imm32|near [i:        nw o64 0f 8c rel                ] ND,AR0,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(8c) 064 : AR0,NWSIZE,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JL, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56459, 211},
    /*  11 : JL imm [i:        7d jlen e9 rel                  ] ND,AR0,OSIZE,NOAPX,8086 */
        /* 001(7d) 373 001(e9) 064 : AR0,OSIZE,NOAPX,8086 */
        {I_JL, 1, {IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56571, 212},
};

static const struct itemplate instrux_JLE[12] = {
    /*   0 : JLE imm16|short [i:        nw o16 7e rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 320 001(7e) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JLE, 1, {IMM_NORMAL|BITS16|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55907, 205},
    /*   1 : JLE imm32|short [i:        nw o32 7e rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 321 001(7e) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JLE, 1, {IMM_NORMAL|BITS32|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56019, 205},
    /*   2 : JLE imm64|short [i:        nw o64 7e rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 001(7e) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JLE, 1, {IMM_NORMAL|BITS64|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56131, 206},
    /*   3 : JLE imm16|near [i:        jcc8 nw o16 7e rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086,ND */
        /* 370 327 320 001(7e) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JLE, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55906, 207},
    /*   4 : JLE imm32|near [i:        jcc8 nw o32 7e rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086,ND */
        /* 370 327 321 001(7e) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JLE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56018, 207},
    /*   5 : JLE imm64|near [i:        jcc8 nw o64 7e rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64,ND */
        /* 370 327 324 001(7e) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JLE, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56130, 208},
    /*   6 : JLE imm32|near [i:        jcc8 nw o64 7e rel8             ] ND,AR0,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(7e) 050 : AR0,NWSIZE,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JLE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56130, 209},
    /*   7 : JLE imm16|near [i:        nw o16 0f 8e rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386,ND */
        /* 327 320 355 001(8e) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JLE, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56242, 210},
    /*   8 : JLE imm32|near [i:        nw o32 0f 8e rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386,ND */
        /* 327 321 355 001(8e) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JLE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56354, 210},
    /*   9 : JLE imm64|near [i:        nw o64 0f 8e rel                ] AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64,ND */
        /* 327 324 355 001(8e) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JLE, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56466, 206},
    /*  10 : JLE imm32|near [i:        nw o64 0f 8e rel                ] ND,AR0,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(8e) 064 : AR0,NWSIZE,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JLE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56466, 211},
    /*  11 : JLE imm [i:        7f jlen e9 rel                  ] ND,AR0,OSIZE,NOAPX,8086 */
        /* 001(7f) 373 001(e9) 064 : AR0,OSIZE,NOAPX,8086 */
        {I_JLE, 1, {IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56578, 212},
};

static const struct itemplate instrux_JNA[12] = {
    /*   0 : JNA imm16|short [i:        nw o16 76 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 320 001(76) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNA, 1, {IMM_NORMAL|BITS16|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55872, 205},
    /*   1 : JNA imm32|short [i:        nw o32 76 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 321 001(76) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNA, 1, {IMM_NORMAL|BITS32|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55984, 205},
    /*   2 : JNA imm64|short [i:        nw o64 76 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 001(76) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNA, 1, {IMM_NORMAL|BITS64|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56096, 206},
    /*   3 : JNA imm16|near [i:        jcc8 nw o16 76 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 370 327 320 001(76) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNA, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55871, 207},
    /*   4 : JNA imm32|near [i:        jcc8 nw o32 76 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 370 327 321 001(76) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNA, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55983, 207},
    /*   5 : JNA imm64|near [i:        jcc8 nw o64 76 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(76) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNA, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56095, 208},
    /*   6 : JNA imm32|near [i:        jcc8 nw o64 76 rel8             ] ND,AR0,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(76) 050 : AR0,NWSIZE,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNA, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56095, 209},
    /*   7 : JNA imm16|near [i:        nw o16 0f 86 rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        /* 327 320 355 001(86) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JNA, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56207, 210},
    /*   8 : JNA imm32|near [i:        nw o32 0f 86 rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        /* 327 321 355 001(86) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JNA, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56319, 210},
    /*   9 : JNA imm64|near [i:        nw o64 0f 86 rel                ] AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(86) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNA, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56431, 206},
    /*  10 : JNA imm32|near [i:        nw o64 0f 86 rel                ] ND,AR0,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(86) 064 : AR0,NWSIZE,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNA, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56431, 211},
    /*  11 : JNA imm [i:        77 jlen e9 rel                  ] ND,AR0,OSIZE,NOAPX,8086 */
        /* 001(77) 373 001(e9) 064 : AR0,OSIZE,NOAPX,8086 */
        {I_JNA, 1, {IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56543, 212},
};

static const struct itemplate instrux_JNAE[12] = {
    /*   0 : JNAE imm16|short [i:        nw o16 72 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 320 001(72) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNAE, 1, {IMM_NORMAL|BITS16|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55865, 205},
    /*   1 : JNAE imm32|short [i:        nw o32 72 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 321 001(72) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNAE, 1, {IMM_NORMAL|BITS32|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55977, 205},
    /*   2 : JNAE imm64|short [i:        nw o64 72 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 001(72) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNAE, 1, {IMM_NORMAL|BITS64|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56089, 206},
    /*   3 : JNAE imm16|near [i:        jcc8 nw o16 72 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086,ND */
        /* 370 327 320 001(72) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNAE, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55864, 207},
    /*   4 : JNAE imm32|near [i:        jcc8 nw o32 72 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086,ND */
        /* 370 327 321 001(72) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNAE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55976, 207},
    /*   5 : JNAE imm64|near [i:        jcc8 nw o64 72 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64,ND */
        /* 370 327 324 001(72) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNAE, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56088, 208},
    /*   6 : JNAE imm32|near [i:        jcc8 nw o64 72 rel8             ] ND,AR0,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(72) 050 : AR0,NWSIZE,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNAE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56088, 209},
    /*   7 : JNAE imm16|near [i:        nw o16 0f 82 rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386,ND */
        /* 327 320 355 001(82) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JNAE, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56200, 210},
    /*   8 : JNAE imm32|near [i:        nw o32 0f 82 rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386,ND */
        /* 327 321 355 001(82) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JNAE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56312, 210},
    /*   9 : JNAE imm64|near [i:        nw o64 0f 82 rel                ] AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64,ND */
        /* 327 324 355 001(82) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNAE, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56424, 206},
    /*  10 : JNAE imm32|near [i:        nw o64 0f 82 rel                ] ND,AR0,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(82) 064 : AR0,NWSIZE,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNAE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56424, 211},
    /*  11 : JNAE imm [i:        73 jlen e9 rel                  ] ND,AR0,OSIZE,NOAPX,8086 */
        /* 001(73) 373 001(e9) 064 : AR0,OSIZE,NOAPX,8086 */
        {I_JNAE, 1, {IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56536, 212},
};

static const struct itemplate instrux_JNB[12] = {
    /*   0 : JNB imm16|short [i:        nw o16 73 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 320 001(73) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNB, 1, {IMM_NORMAL|BITS16|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55858, 205},
    /*   1 : JNB imm32|short [i:        nw o32 73 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 321 001(73) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNB, 1, {IMM_NORMAL|BITS32|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55970, 205},
    /*   2 : JNB imm64|short [i:        nw o64 73 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 001(73) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNB, 1, {IMM_NORMAL|BITS64|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56082, 206},
    /*   3 : JNB imm16|near [i:        jcc8 nw o16 73 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086,ND */
        /* 370 327 320 001(73) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNB, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55857, 207},
    /*   4 : JNB imm32|near [i:        jcc8 nw o32 73 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086,ND */
        /* 370 327 321 001(73) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNB, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55969, 207},
    /*   5 : JNB imm64|near [i:        jcc8 nw o64 73 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64,ND */
        /* 370 327 324 001(73) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNB, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56081, 208},
    /*   6 : JNB imm32|near [i:        jcc8 nw o64 73 rel8             ] ND,AR0,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(73) 050 : AR0,NWSIZE,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNB, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56081, 209},
    /*   7 : JNB imm16|near [i:        nw o16 0f 83 rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386,ND */
        /* 327 320 355 001(83) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JNB, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56193, 210},
    /*   8 : JNB imm32|near [i:        nw o32 0f 83 rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386,ND */
        /* 327 321 355 001(83) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JNB, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56305, 210},
    /*   9 : JNB imm64|near [i:        nw o64 0f 83 rel                ] AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64,ND */
        /* 327 324 355 001(83) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNB, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56417, 206},
    /*  10 : JNB imm32|near [i:        nw o64 0f 83 rel                ] ND,AR0,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(83) 064 : AR0,NWSIZE,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNB, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56417, 211},
    /*  11 : JNB imm [i:        72 jlen e9 rel                  ] ND,AR0,OSIZE,NOAPX,8086 */
        /* 001(72) 373 001(e9) 064 : AR0,OSIZE,NOAPX,8086 */
        {I_JNB, 1, {IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56529, 212},
};

static const struct itemplate instrux_JNBE[12] = {
    /*   0 : JNBE imm16|short [i:        nw o16 77 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 320 001(77) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNBE, 1, {IMM_NORMAL|BITS16|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55851, 205},
    /*   1 : JNBE imm32|short [i:        nw o32 77 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 321 001(77) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNBE, 1, {IMM_NORMAL|BITS32|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55963, 205},
    /*   2 : JNBE imm64|short [i:        nw o64 77 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 001(77) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNBE, 1, {IMM_NORMAL|BITS64|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56075, 206},
    /*   3 : JNBE imm16|near [i:        jcc8 nw o16 77 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086,ND */
        /* 370 327 320 001(77) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNBE, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55850, 207},
    /*   4 : JNBE imm32|near [i:        jcc8 nw o32 77 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086,ND */
        /* 370 327 321 001(77) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNBE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55962, 207},
    /*   5 : JNBE imm64|near [i:        jcc8 nw o64 77 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64,ND */
        /* 370 327 324 001(77) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNBE, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56074, 208},
    /*   6 : JNBE imm32|near [i:        jcc8 nw o64 77 rel8             ] ND,AR0,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(77) 050 : AR0,NWSIZE,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNBE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56074, 209},
    /*   7 : JNBE imm16|near [i:        nw o16 0f 87 rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386,ND */
        /* 327 320 355 001(87) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JNBE, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56186, 210},
    /*   8 : JNBE imm32|near [i:        nw o32 0f 87 rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386,ND */
        /* 327 321 355 001(87) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JNBE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56298, 210},
    /*   9 : JNBE imm64|near [i:        nw o64 0f 87 rel                ] AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64,ND */
        /* 327 324 355 001(87) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNBE, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56410, 206},
    /*  10 : JNBE imm32|near [i:        nw o64 0f 87 rel                ] ND,AR0,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(87) 064 : AR0,NWSIZE,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNBE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56410, 211},
    /*  11 : JNBE imm [i:        76 jlen e9 rel                  ] ND,AR0,OSIZE,NOAPX,8086 */
        /* 001(76) 373 001(e9) 064 : AR0,OSIZE,NOAPX,8086 */
        {I_JNBE, 1, {IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56522, 212},
};

static const struct itemplate instrux_JNC[12] = {
    /*   0 : JNC imm16|short [i:        nw o16 73 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 320 001(73) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNC, 1, {IMM_NORMAL|BITS16|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55858, 205},
    /*   1 : JNC imm32|short [i:        nw o32 73 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 321 001(73) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNC, 1, {IMM_NORMAL|BITS32|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55970, 205},
    /*   2 : JNC imm64|short [i:        nw o64 73 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 001(73) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNC, 1, {IMM_NORMAL|BITS64|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56082, 206},
    /*   3 : JNC imm16|near [i:        jcc8 nw o16 73 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 370 327 320 001(73) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNC, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55857, 207},
    /*   4 : JNC imm32|near [i:        jcc8 nw o32 73 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 370 327 321 001(73) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNC, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55969, 207},
    /*   5 : JNC imm64|near [i:        jcc8 nw o64 73 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(73) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNC, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56081, 208},
    /*   6 : JNC imm32|near [i:        jcc8 nw o64 73 rel8             ] ND,AR0,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(73) 050 : AR0,NWSIZE,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNC, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56081, 209},
    /*   7 : JNC imm16|near [i:        nw o16 0f 83 rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        /* 327 320 355 001(83) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JNC, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56193, 210},
    /*   8 : JNC imm32|near [i:        nw o32 0f 83 rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        /* 327 321 355 001(83) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JNC, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56305, 210},
    /*   9 : JNC imm64|near [i:        nw o64 0f 83 rel                ] AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(83) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNC, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56417, 206},
    /*  10 : JNC imm32|near [i:        nw o64 0f 83 rel                ] ND,AR0,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(83) 064 : AR0,NWSIZE,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNC, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56417, 211},
    /*  11 : JNC imm [i:        72 jlen e9 rel                  ] ND,AR0,OSIZE,NOAPX,8086 */
        /* 001(72) 373 001(e9) 064 : AR0,OSIZE,NOAPX,8086 */
        {I_JNC, 1, {IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56529, 212},
};

static const struct itemplate instrux_JNE[12] = {
    /*   0 : JNE imm16|short [i:        nw o16 75 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 320 001(75) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNE, 1, {IMM_NORMAL|BITS16|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55914, 205},
    /*   1 : JNE imm32|short [i:        nw o32 75 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 321 001(75) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNE, 1, {IMM_NORMAL|BITS32|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56026, 205},
    /*   2 : JNE imm64|short [i:        nw o64 75 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 001(75) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNE, 1, {IMM_NORMAL|BITS64|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56138, 206},
    /*   3 : JNE imm16|near [i:        jcc8 nw o16 75 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086,ND */
        /* 370 327 320 001(75) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNE, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55913, 207},
    /*   4 : JNE imm32|near [i:        jcc8 nw o32 75 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086,ND */
        /* 370 327 321 001(75) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56025, 207},
    /*   5 : JNE imm64|near [i:        jcc8 nw o64 75 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64,ND */
        /* 370 327 324 001(75) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNE, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56137, 208},
    /*   6 : JNE imm32|near [i:        jcc8 nw o64 75 rel8             ] ND,AR0,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(75) 050 : AR0,NWSIZE,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56137, 209},
    /*   7 : JNE imm16|near [i:        nw o16 0f 85 rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386,ND */
        /* 327 320 355 001(85) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JNE, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56249, 210},
    /*   8 : JNE imm32|near [i:        nw o32 0f 85 rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386,ND */
        /* 327 321 355 001(85) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JNE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56361, 210},
    /*   9 : JNE imm64|near [i:        nw o64 0f 85 rel                ] AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64,ND */
        /* 327 324 355 001(85) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNE, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56473, 206},
    /*  10 : JNE imm32|near [i:        nw o64 0f 85 rel                ] ND,AR0,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(85) 064 : AR0,NWSIZE,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56473, 211},
    /*  11 : JNE imm [i:        74 jlen e9 rel                  ] ND,AR0,OSIZE,NOAPX,8086 */
        /* 001(74) 373 001(e9) 064 : AR0,OSIZE,NOAPX,8086 */
        {I_JNE, 1, {IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56585, 212},
};

static const struct itemplate instrux_JNG[12] = {
    /*   0 : JNG imm16|short [i:        nw o16 7e rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 320 001(7e) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNG, 1, {IMM_NORMAL|BITS16|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55907, 205},
    /*   1 : JNG imm32|short [i:        nw o32 7e rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 321 001(7e) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNG, 1, {IMM_NORMAL|BITS32|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56019, 205},
    /*   2 : JNG imm64|short [i:        nw o64 7e rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 001(7e) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNG, 1, {IMM_NORMAL|BITS64|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56131, 206},
    /*   3 : JNG imm16|near [i:        jcc8 nw o16 7e rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 370 327 320 001(7e) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNG, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55906, 207},
    /*   4 : JNG imm32|near [i:        jcc8 nw o32 7e rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 370 327 321 001(7e) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNG, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56018, 207},
    /*   5 : JNG imm64|near [i:        jcc8 nw o64 7e rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(7e) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNG, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56130, 208},
    /*   6 : JNG imm32|near [i:        jcc8 nw o64 7e rel8             ] ND,AR0,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(7e) 050 : AR0,NWSIZE,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNG, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56130, 209},
    /*   7 : JNG imm16|near [i:        nw o16 0f 8e rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        /* 327 320 355 001(8e) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JNG, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56242, 210},
    /*   8 : JNG imm32|near [i:        nw o32 0f 8e rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        /* 327 321 355 001(8e) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JNG, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56354, 210},
    /*   9 : JNG imm64|near [i:        nw o64 0f 8e rel                ] AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(8e) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNG, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56466, 206},
    /*  10 : JNG imm32|near [i:        nw o64 0f 8e rel                ] ND,AR0,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(8e) 064 : AR0,NWSIZE,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNG, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56466, 211},
    /*  11 : JNG imm [i:        7f jlen e9 rel                  ] ND,AR0,OSIZE,NOAPX,8086 */
        /* 001(7f) 373 001(e9) 064 : AR0,OSIZE,NOAPX,8086 */
        {I_JNG, 1, {IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56578, 212},
};

static const struct itemplate instrux_JNGE[12] = {
    /*   0 : JNGE imm16|short [i:        nw o16 7c rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 320 001(7c) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNGE, 1, {IMM_NORMAL|BITS16|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55900, 205},
    /*   1 : JNGE imm32|short [i:        nw o32 7c rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 321 001(7c) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNGE, 1, {IMM_NORMAL|BITS32|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56012, 205},
    /*   2 : JNGE imm64|short [i:        nw o64 7c rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 001(7c) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNGE, 1, {IMM_NORMAL|BITS64|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56124, 206},
    /*   3 : JNGE imm16|near [i:        jcc8 nw o16 7c rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086,ND */
        /* 370 327 320 001(7c) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNGE, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55899, 207},
    /*   4 : JNGE imm32|near [i:        jcc8 nw o32 7c rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086,ND */
        /* 370 327 321 001(7c) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNGE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56011, 207},
    /*   5 : JNGE imm64|near [i:        jcc8 nw o64 7c rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64,ND */
        /* 370 327 324 001(7c) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNGE, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56123, 208},
    /*   6 : JNGE imm32|near [i:        jcc8 nw o64 7c rel8             ] ND,AR0,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(7c) 050 : AR0,NWSIZE,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNGE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56123, 209},
    /*   7 : JNGE imm16|near [i:        nw o16 0f 8c rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386,ND */
        /* 327 320 355 001(8c) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JNGE, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56235, 210},
    /*   8 : JNGE imm32|near [i:        nw o32 0f 8c rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386,ND */
        /* 327 321 355 001(8c) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JNGE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56347, 210},
    /*   9 : JNGE imm64|near [i:        nw o64 0f 8c rel                ] AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64,ND */
        /* 327 324 355 001(8c) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNGE, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56459, 206},
    /*  10 : JNGE imm32|near [i:        nw o64 0f 8c rel                ] ND,AR0,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(8c) 064 : AR0,NWSIZE,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNGE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56459, 211},
    /*  11 : JNGE imm [i:        7d jlen e9 rel                  ] ND,AR0,OSIZE,NOAPX,8086 */
        /* 001(7d) 373 001(e9) 064 : AR0,OSIZE,NOAPX,8086 */
        {I_JNGE, 1, {IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56571, 212},
};

static const struct itemplate instrux_JNL[12] = {
    /*   0 : JNL imm16|short [i:        nw o16 7d rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 320 001(7d) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNL, 1, {IMM_NORMAL|BITS16|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55893, 205},
    /*   1 : JNL imm32|short [i:        nw o32 7d rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 321 001(7d) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNL, 1, {IMM_NORMAL|BITS32|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56005, 205},
    /*   2 : JNL imm64|short [i:        nw o64 7d rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 001(7d) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNL, 1, {IMM_NORMAL|BITS64|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56117, 206},
    /*   3 : JNL imm16|near [i:        jcc8 nw o16 7d rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 370 327 320 001(7d) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNL, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55892, 207},
    /*   4 : JNL imm32|near [i:        jcc8 nw o32 7d rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 370 327 321 001(7d) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNL, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56004, 207},
    /*   5 : JNL imm64|near [i:        jcc8 nw o64 7d rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(7d) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNL, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56116, 208},
    /*   6 : JNL imm32|near [i:        jcc8 nw o64 7d rel8             ] ND,AR0,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(7d) 050 : AR0,NWSIZE,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNL, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56116, 209},
    /*   7 : JNL imm16|near [i:        nw o16 0f 8d rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        /* 327 320 355 001(8d) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JNL, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56228, 210},
    /*   8 : JNL imm32|near [i:        nw o32 0f 8d rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        /* 327 321 355 001(8d) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JNL, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56340, 210},
    /*   9 : JNL imm64|near [i:        nw o64 0f 8d rel                ] AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(8d) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNL, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56452, 206},
    /*  10 : JNL imm32|near [i:        nw o64 0f 8d rel                ] ND,AR0,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(8d) 064 : AR0,NWSIZE,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNL, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56452, 211},
    /*  11 : JNL imm [i:        7c jlen e9 rel                  ] ND,AR0,OSIZE,NOAPX,8086 */
        /* 001(7c) 373 001(e9) 064 : AR0,OSIZE,NOAPX,8086 */
        {I_JNL, 1, {IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56564, 212},
};

static const struct itemplate instrux_JNLE[12] = {
    /*   0 : JNLE imm16|short [i:        nw o16 7f rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 320 001(7f) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNLE, 1, {IMM_NORMAL|BITS16|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55886, 205},
    /*   1 : JNLE imm32|short [i:        nw o32 7f rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 321 001(7f) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNLE, 1, {IMM_NORMAL|BITS32|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55998, 205},
    /*   2 : JNLE imm64|short [i:        nw o64 7f rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 001(7f) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNLE, 1, {IMM_NORMAL|BITS64|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56110, 206},
    /*   3 : JNLE imm16|near [i:        jcc8 nw o16 7f rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086,ND */
        /* 370 327 320 001(7f) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNLE, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55885, 207},
    /*   4 : JNLE imm32|near [i:        jcc8 nw o32 7f rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086,ND */
        /* 370 327 321 001(7f) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNLE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55997, 207},
    /*   5 : JNLE imm64|near [i:        jcc8 nw o64 7f rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64,ND */
        /* 370 327 324 001(7f) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNLE, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56109, 208},
    /*   6 : JNLE imm32|near [i:        jcc8 nw o64 7f rel8             ] ND,AR0,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(7f) 050 : AR0,NWSIZE,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNLE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56109, 209},
    /*   7 : JNLE imm16|near [i:        nw o16 0f 8f rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386,ND */
        /* 327 320 355 001(8f) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JNLE, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56221, 210},
    /*   8 : JNLE imm32|near [i:        nw o32 0f 8f rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386,ND */
        /* 327 321 355 001(8f) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JNLE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56333, 210},
    /*   9 : JNLE imm64|near [i:        nw o64 0f 8f rel                ] AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64,ND */
        /* 327 324 355 001(8f) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNLE, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56445, 206},
    /*  10 : JNLE imm32|near [i:        nw o64 0f 8f rel                ] ND,AR0,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(8f) 064 : AR0,NWSIZE,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNLE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56445, 211},
    /*  11 : JNLE imm [i:        7e jlen e9 rel                  ] ND,AR0,OSIZE,NOAPX,8086 */
        /* 001(7e) 373 001(e9) 064 : AR0,OSIZE,NOAPX,8086 */
        {I_JNLE, 1, {IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56557, 212},
};

static const struct itemplate instrux_JNO[12] = {
    /*   0 : JNO imm16|short [i:        nw o16 71 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 320 001(71) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNO, 1, {IMM_NORMAL|BITS16|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55921, 205},
    /*   1 : JNO imm32|short [i:        nw o32 71 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 321 001(71) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNO, 1, {IMM_NORMAL|BITS32|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56033, 205},
    /*   2 : JNO imm64|short [i:        nw o64 71 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 001(71) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNO, 1, {IMM_NORMAL|BITS64|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56145, 206},
    /*   3 : JNO imm16|near [i:        jcc8 nw o16 71 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 370 327 320 001(71) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNO, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55920, 207},
    /*   4 : JNO imm32|near [i:        jcc8 nw o32 71 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 370 327 321 001(71) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNO, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56032, 207},
    /*   5 : JNO imm64|near [i:        jcc8 nw o64 71 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(71) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNO, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56144, 208},
    /*   6 : JNO imm32|near [i:        jcc8 nw o64 71 rel8             ] ND,AR0,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(71) 050 : AR0,NWSIZE,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNO, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56144, 209},
    /*   7 : JNO imm16|near [i:        nw o16 0f 81 rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        /* 327 320 355 001(81) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JNO, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56256, 210},
    /*   8 : JNO imm32|near [i:        nw o32 0f 81 rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        /* 327 321 355 001(81) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JNO, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56368, 210},
    /*   9 : JNO imm64|near [i:        nw o64 0f 81 rel                ] AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(81) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNO, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56480, 206},
    /*  10 : JNO imm32|near [i:        nw o64 0f 81 rel                ] ND,AR0,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(81) 064 : AR0,NWSIZE,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNO, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56480, 211},
    /*  11 : JNO imm [i:        70 jlen e9 rel                  ] ND,AR0,OSIZE,NOAPX,8086 */
        /* 001(70) 373 001(e9) 064 : AR0,OSIZE,NOAPX,8086 */
        {I_JNO, 1, {IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56592, 212},
};

static const struct itemplate instrux_JNP[12] = {
    /*   0 : JNP imm16|short [i:        nw o16 7b rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 320 001(7b) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNP, 1, {IMM_NORMAL|BITS16|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55928, 205},
    /*   1 : JNP imm32|short [i:        nw o32 7b rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 321 001(7b) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNP, 1, {IMM_NORMAL|BITS32|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56040, 205},
    /*   2 : JNP imm64|short [i:        nw o64 7b rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 001(7b) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNP, 1, {IMM_NORMAL|BITS64|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56152, 206},
    /*   3 : JNP imm16|near [i:        jcc8 nw o16 7b rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086,ND */
        /* 370 327 320 001(7b) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNP, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55927, 207},
    /*   4 : JNP imm32|near [i:        jcc8 nw o32 7b rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086,ND */
        /* 370 327 321 001(7b) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNP, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56039, 207},
    /*   5 : JNP imm64|near [i:        jcc8 nw o64 7b rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64,ND */
        /* 370 327 324 001(7b) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNP, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56151, 208},
    /*   6 : JNP imm32|near [i:        jcc8 nw o64 7b rel8             ] ND,AR0,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(7b) 050 : AR0,NWSIZE,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNP, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56151, 209},
    /*   7 : JNP imm16|near [i:        nw o16 0f 8b rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386,ND */
        /* 327 320 355 001(8b) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JNP, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56263, 210},
    /*   8 : JNP imm32|near [i:        nw o32 0f 8b rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386,ND */
        /* 327 321 355 001(8b) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JNP, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56375, 210},
    /*   9 : JNP imm64|near [i:        nw o64 0f 8b rel                ] AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64,ND */
        /* 327 324 355 001(8b) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNP, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56487, 206},
    /*  10 : JNP imm32|near [i:        nw o64 0f 8b rel                ] ND,AR0,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(8b) 064 : AR0,NWSIZE,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNP, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56487, 211},
    /*  11 : JNP imm [i:        7a jlen e9 rel                  ] ND,AR0,OSIZE,NOAPX,8086 */
        /* 001(7a) 373 001(e9) 064 : AR0,OSIZE,NOAPX,8086 */
        {I_JNP, 1, {IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56599, 212},
};

static const struct itemplate instrux_JNS[12] = {
    /*   0 : JNS imm16|short [i:        nw o16 79 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 320 001(79) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNS, 1, {IMM_NORMAL|BITS16|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55935, 205},
    /*   1 : JNS imm32|short [i:        nw o32 79 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 321 001(79) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNS, 1, {IMM_NORMAL|BITS32|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56047, 205},
    /*   2 : JNS imm64|short [i:        nw o64 79 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 001(79) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNS, 1, {IMM_NORMAL|BITS64|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56159, 206},
    /*   3 : JNS imm16|near [i:        jcc8 nw o16 79 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 370 327 320 001(79) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNS, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55934, 207},
    /*   4 : JNS imm32|near [i:        jcc8 nw o32 79 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 370 327 321 001(79) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNS, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56046, 207},
    /*   5 : JNS imm64|near [i:        jcc8 nw o64 79 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(79) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNS, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56158, 208},
    /*   6 : JNS imm32|near [i:        jcc8 nw o64 79 rel8             ] ND,AR0,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(79) 050 : AR0,NWSIZE,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNS, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56158, 209},
    /*   7 : JNS imm16|near [i:        nw o16 0f 89 rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        /* 327 320 355 001(89) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JNS, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56270, 210},
    /*   8 : JNS imm32|near [i:        nw o32 0f 89 rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        /* 327 321 355 001(89) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JNS, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56382, 210},
    /*   9 : JNS imm64|near [i:        nw o64 0f 89 rel                ] AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(89) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNS, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56494, 206},
    /*  10 : JNS imm32|near [i:        nw o64 0f 89 rel                ] ND,AR0,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(89) 064 : AR0,NWSIZE,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNS, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56494, 211},
    /*  11 : JNS imm [i:        78 jlen e9 rel                  ] ND,AR0,OSIZE,NOAPX,8086 */
        /* 001(78) 373 001(e9) 064 : AR0,OSIZE,NOAPX,8086 */
        {I_JNS, 1, {IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56606, 212},
};

static const struct itemplate instrux_JNZ[12] = {
    /*   0 : JNZ imm16|short [i:        nw o16 75 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 320 001(75) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNZ, 1, {IMM_NORMAL|BITS16|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55914, 205},
    /*   1 : JNZ imm32|short [i:        nw o32 75 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 321 001(75) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNZ, 1, {IMM_NORMAL|BITS32|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56026, 205},
    /*   2 : JNZ imm64|short [i:        nw o64 75 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 001(75) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNZ, 1, {IMM_NORMAL|BITS64|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56138, 206},
    /*   3 : JNZ imm16|near [i:        jcc8 nw o16 75 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 370 327 320 001(75) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNZ, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55913, 207},
    /*   4 : JNZ imm32|near [i:        jcc8 nw o32 75 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 370 327 321 001(75) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JNZ, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56025, 207},
    /*   5 : JNZ imm64|near [i:        jcc8 nw o64 75 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(75) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNZ, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56137, 208},
    /*   6 : JNZ imm32|near [i:        jcc8 nw o64 75 rel8             ] ND,AR0,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(75) 050 : AR0,NWSIZE,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNZ, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56137, 209},
    /*   7 : JNZ imm16|near [i:        nw o16 0f 85 rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        /* 327 320 355 001(85) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JNZ, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56249, 210},
    /*   8 : JNZ imm32|near [i:        nw o32 0f 85 rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        /* 327 321 355 001(85) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JNZ, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56361, 210},
    /*   9 : JNZ imm64|near [i:        nw o64 0f 85 rel                ] AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(85) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNZ, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56473, 206},
    /*  10 : JNZ imm32|near [i:        nw o64 0f 85 rel                ] ND,AR0,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(85) 064 : AR0,NWSIZE,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JNZ, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56473, 211},
    /*  11 : JNZ imm [i:        74 jlen e9 rel                  ] ND,AR0,OSIZE,NOAPX,8086 */
        /* 001(74) 373 001(e9) 064 : AR0,OSIZE,NOAPX,8086 */
        {I_JNZ, 1, {IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56585, 212},
};

static const struct itemplate instrux_JO[12] = {
    /*   0 : JO imm16|short [i:        nw o16 70 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 320 001(70) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JO, 1, {IMM_NORMAL|BITS16|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55942, 205},
    /*   1 : JO imm32|short [i:        nw o32 70 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 321 001(70) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JO, 1, {IMM_NORMAL|BITS32|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56054, 205},
    /*   2 : JO imm64|short [i:        nw o64 70 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 001(70) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JO, 1, {IMM_NORMAL|BITS64|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56166, 206},
    /*   3 : JO imm16|near [i:        jcc8 nw o16 70 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 370 327 320 001(70) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JO, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55941, 207},
    /*   4 : JO imm32|near [i:        jcc8 nw o32 70 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 370 327 321 001(70) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JO, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56053, 207},
    /*   5 : JO imm64|near [i:        jcc8 nw o64 70 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(70) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JO, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56165, 208},
    /*   6 : JO imm32|near [i:        jcc8 nw o64 70 rel8             ] ND,AR0,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(70) 050 : AR0,NWSIZE,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JO, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56165, 209},
    /*   7 : JO imm16|near [i:        nw o16 0f 80 rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        /* 327 320 355 001(80) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JO, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56277, 210},
    /*   8 : JO imm32|near [i:        nw o32 0f 80 rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        /* 327 321 355 001(80) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JO, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56389, 210},
    /*   9 : JO imm64|near [i:        nw o64 0f 80 rel                ] AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(80) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JO, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56501, 206},
    /*  10 : JO imm32|near [i:        nw o64 0f 80 rel                ] ND,AR0,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(80) 064 : AR0,NWSIZE,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JO, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56501, 211},
    /*  11 : JO imm [i:        71 jlen e9 rel                  ] ND,AR0,OSIZE,NOAPX,8086 */
        /* 001(71) 373 001(e9) 064 : AR0,OSIZE,NOAPX,8086 */
        {I_JO, 1, {IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56613, 212},
};

static const struct itemplate instrux_JP[12] = {
    /*   0 : JP imm16|short [i:        nw o16 7a rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 320 001(7a) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JP, 1, {IMM_NORMAL|BITS16|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55949, 205},
    /*   1 : JP imm32|short [i:        nw o32 7a rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 321 001(7a) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JP, 1, {IMM_NORMAL|BITS32|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56061, 205},
    /*   2 : JP imm64|short [i:        nw o64 7a rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 001(7a) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JP, 1, {IMM_NORMAL|BITS64|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56173, 206},
    /*   3 : JP imm16|near [i:        jcc8 nw o16 7a rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086,ND */
        /* 370 327 320 001(7a) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JP, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55948, 207},
    /*   4 : JP imm32|near [i:        jcc8 nw o32 7a rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086,ND */
        /* 370 327 321 001(7a) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JP, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56060, 207},
    /*   5 : JP imm64|near [i:        jcc8 nw o64 7a rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64,ND */
        /* 370 327 324 001(7a) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JP, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56172, 208},
    /*   6 : JP imm32|near [i:        jcc8 nw o64 7a rel8             ] ND,AR0,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(7a) 050 : AR0,NWSIZE,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JP, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56172, 209},
    /*   7 : JP imm16|near [i:        nw o16 0f 8a rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386,ND */
        /* 327 320 355 001(8a) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JP, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56284, 210},
    /*   8 : JP imm32|near [i:        nw o32 0f 8a rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386,ND */
        /* 327 321 355 001(8a) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JP, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56396, 210},
    /*   9 : JP imm64|near [i:        nw o64 0f 8a rel                ] AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64,ND */
        /* 327 324 355 001(8a) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JP, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56508, 206},
    /*  10 : JP imm32|near [i:        nw o64 0f 8a rel                ] ND,AR0,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(8a) 064 : AR0,NWSIZE,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JP, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56508, 211},
    /*  11 : JP imm [i:        7b jlen e9 rel                  ] ND,AR0,OSIZE,NOAPX,8086 */
        /* 001(7b) 373 001(e9) 064 : AR0,OSIZE,NOAPX,8086 */
        {I_JP, 1, {IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56620, 212},
};

static const struct itemplate instrux_JPE[12] = {
    /*   0 : JPE imm16|short [i:        nw o16 7a rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 320 001(7a) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JPE, 1, {IMM_NORMAL|BITS16|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55949, 205},
    /*   1 : JPE imm32|short [i:        nw o32 7a rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 321 001(7a) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JPE, 1, {IMM_NORMAL|BITS32|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56061, 205},
    /*   2 : JPE imm64|short [i:        nw o64 7a rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 001(7a) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JPE, 1, {IMM_NORMAL|BITS64|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56173, 206},
    /*   3 : JPE imm16|near [i:        jcc8 nw o16 7a rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 370 327 320 001(7a) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JPE, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55948, 207},
    /*   4 : JPE imm32|near [i:        jcc8 nw o32 7a rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 370 327 321 001(7a) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JPE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56060, 207},
    /*   5 : JPE imm64|near [i:        jcc8 nw o64 7a rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(7a) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JPE, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56172, 208},
    /*   6 : JPE imm32|near [i:        jcc8 nw o64 7a rel8             ] ND,AR0,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(7a) 050 : AR0,NWSIZE,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JPE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56172, 209},
    /*   7 : JPE imm16|near [i:        nw o16 0f 8a rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        /* 327 320 355 001(8a) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JPE, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56284, 210},
    /*   8 : JPE imm32|near [i:        nw o32 0f 8a rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        /* 327 321 355 001(8a) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JPE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56396, 210},
    /*   9 : JPE imm64|near [i:        nw o64 0f 8a rel                ] AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(8a) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JPE, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56508, 206},
    /*  10 : JPE imm32|near [i:        nw o64 0f 8a rel                ] ND,AR0,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(8a) 064 : AR0,NWSIZE,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JPE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56508, 211},
    /*  11 : JPE imm [i:        7b jlen e9 rel                  ] ND,AR0,OSIZE,NOAPX,8086 */
        /* 001(7b) 373 001(e9) 064 : AR0,OSIZE,NOAPX,8086 */
        {I_JPE, 1, {IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56620, 212},
};

static const struct itemplate instrux_JPO[12] = {
    /*   0 : JPO imm16|short [i:        nw o16 7b rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 320 001(7b) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JPO, 1, {IMM_NORMAL|BITS16|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55928, 205},
    /*   1 : JPO imm32|short [i:        nw o32 7b rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 321 001(7b) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JPO, 1, {IMM_NORMAL|BITS32|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56040, 205},
    /*   2 : JPO imm64|short [i:        nw o64 7b rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 001(7b) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JPO, 1, {IMM_NORMAL|BITS64|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56152, 206},
    /*   3 : JPO imm16|near [i:        jcc8 nw o16 7b rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 370 327 320 001(7b) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JPO, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55927, 207},
    /*   4 : JPO imm32|near [i:        jcc8 nw o32 7b rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 370 327 321 001(7b) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JPO, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56039, 207},
    /*   5 : JPO imm64|near [i:        jcc8 nw o64 7b rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(7b) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JPO, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56151, 208},
    /*   6 : JPO imm32|near [i:        jcc8 nw o64 7b rel8             ] ND,AR0,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(7b) 050 : AR0,NWSIZE,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JPO, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56151, 209},
    /*   7 : JPO imm16|near [i:        nw o16 0f 8b rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        /* 327 320 355 001(8b) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JPO, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56263, 210},
    /*   8 : JPO imm32|near [i:        nw o32 0f 8b rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        /* 327 321 355 001(8b) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JPO, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56375, 210},
    /*   9 : JPO imm64|near [i:        nw o64 0f 8b rel                ] AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(8b) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JPO, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56487, 206},
    /*  10 : JPO imm32|near [i:        nw o64 0f 8b rel                ] ND,AR0,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(8b) 064 : AR0,NWSIZE,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JPO, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56487, 211},
    /*  11 : JPO imm [i:        7a jlen e9 rel                  ] ND,AR0,OSIZE,NOAPX,8086 */
        /* 001(7a) 373 001(e9) 064 : AR0,OSIZE,NOAPX,8086 */
        {I_JPO, 1, {IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56599, 212},
};

static const struct itemplate instrux_JS[12] = {
    /*   0 : JS imm16|short [i:        nw o16 78 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 320 001(78) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JS, 1, {IMM_NORMAL|BITS16|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55956, 205},
    /*   1 : JS imm32|short [i:        nw o32 78 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 321 001(78) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JS, 1, {IMM_NORMAL|BITS32|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56068, 205},
    /*   2 : JS imm64|short [i:        nw o64 78 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 001(78) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JS, 1, {IMM_NORMAL|BITS64|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56180, 206},
    /*   3 : JS imm16|near [i:        jcc8 nw o16 78 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 370 327 320 001(78) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JS, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55955, 207},
    /*   4 : JS imm32|near [i:        jcc8 nw o32 78 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 370 327 321 001(78) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JS, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56067, 207},
    /*   5 : JS imm64|near [i:        jcc8 nw o64 78 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(78) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JS, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56179, 208},
    /*   6 : JS imm32|near [i:        jcc8 nw o64 78 rel8             ] ND,AR0,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(78) 050 : AR0,NWSIZE,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JS, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56179, 209},
    /*   7 : JS imm16|near [i:        nw o16 0f 88 rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        /* 327 320 355 001(88) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JS, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56291, 210},
    /*   8 : JS imm32|near [i:        nw o32 0f 88 rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        /* 327 321 355 001(88) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JS, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56403, 210},
    /*   9 : JS imm64|near [i:        nw o64 0f 88 rel                ] AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(88) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JS, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56515, 206},
    /*  10 : JS imm32|near [i:        nw o64 0f 88 rel                ] ND,AR0,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(88) 064 : AR0,NWSIZE,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JS, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56515, 211},
    /*  11 : JS imm [i:        79 jlen e9 rel                  ] ND,AR0,OSIZE,NOAPX,8086 */
        /* 001(79) 373 001(e9) 064 : AR0,OSIZE,NOAPX,8086 */
        {I_JS, 1, {IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56627, 212},
};

static const struct itemplate instrux_JZ[12] = {
    /*   0 : JZ imm16|short [i:        nw o16 74 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 320 001(74) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JZ, 1, {IMM_NORMAL|BITS16|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55879, 205},
    /*   1 : JZ imm32|short [i:        nw o32 74 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 321 001(74) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JZ, 1, {IMM_NORMAL|BITS32|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55991, 205},
    /*   2 : JZ imm64|short [i:        nw o64 74 rel8                  ] ND,AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 001(74) 050 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JZ, 1, {IMM_NORMAL|BITS64|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56103, 206},
    /*   3 : JZ imm16|near [i:        jcc8 nw o16 74 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 370 327 320 001(74) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JZ, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55878, 207},
    /*   4 : JZ imm32|near [i:        jcc8 nw o32 74 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 370 327 321 001(74) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_JZ, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+55990, 207},
    /*   5 : JZ imm64|near [i:        jcc8 nw o64 74 rel8             ] AR0,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(74) 050 : AR0,NWSIZE,OSIZE,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JZ, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56102, 208},
    /*   6 : JZ imm32|near [i:        jcc8 nw o64 74 rel8             ] ND,AR0,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 370 327 324 001(74) 050 : AR0,NWSIZE,SX,JMP_RELAX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JZ, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56102, 209},
    /*   7 : JZ imm16|near [i:        nw o16 0f 84 rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        /* 327 320 355 001(84) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JZ, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56214, 210},
    /*   8 : JZ imm32|near [i:        nw o32 0f 84 rel                ] AR0,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        /* 327 321 355 001(84) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOREX,NOAPX,NOLONG,BND,386 */
        {I_JZ, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56326, 210},
    /*   9 : JZ imm64|near [i:        nw o64 0f 84 rel                ] AR0,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(84) 064 : AR0,NWSIZE,OSIZE,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JZ, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56438, 206},
    /*  10 : JZ imm32|near [i:        nw o64 0f 84 rel                ] ND,AR0,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 355 001(84) 064 : AR0,NWSIZE,SX,JCC_HINT,NOAPX,LONG,BND,PROT,X86_64 */
        {I_JZ, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56438, 211},
    /*  11 : JZ imm [i:        75 jlen e9 rel                  ] ND,AR0,OSIZE,NOAPX,8086 */
        /* 001(75) 373 001(e9) 064 : AR0,OSIZE,NOAPX,8086 */
        {I_JZ, 1, {IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56550, 212},
};

static const struct itemplate instrux_JCXZ[8] = {
    /*   0 : JCXZ imm16|near|short [i:        a16 nw o16 e3 rel8                ] AR0,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 310 327 320 001(e3) 050 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_JCXZ, 1, {IMM_NORMAL|BITS16|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56634, 187},
    /*   1 : JCXZ imm32|near|short [i:        a16 nw o32 e3 rel8                ] AR0,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 310 327 321 001(e3) 050 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_JCXZ, 1, {IMM_NORMAL|BITS32|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56648, 187},
    /*   2 : JCXZ imm16|near|short,reg_cx [i:        a16 nw o16 e3 rel8                ] ND,AR0-1,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 310 327 320 001(e3) 050 : AR0,AR1,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_JCXZ, 2, {IMM_NORMAL|BITS16|NEAR|SHORT,REG_CX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56634, 214},
    /*   3 : JCXZ imm16|near|short,reg_ecx [i:        a32 nw o16 e3 rel8                ] ND,AR0-1,OSIZE,NOREX,NOAPX,NOLONG,386 */
        /* 311 327 320 001(e3) 050 : AR0,AR1,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,386 */
        {I_JCXZ, 2, {IMM_NORMAL|BITS16|NEAR|SHORT,REG_ECX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56641, 215},
    /*   4 : JCXZ imm32|near|short,reg_cx [i:        a16 nw o32 e3 rel8                ] ND,AR0-1,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 310 327 321 001(e3) 050 : AR0,AR1,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_JCXZ, 2, {IMM_NORMAL|BITS32|NEAR|SHORT,REG_CX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56648, 214},
    /*   5 : JCXZ imm32|near|short,reg_ecx [i:        a32 nw o32 e3 rel8                ] ND,AR0-1,OSIZE,NOREX,NOAPX,NOLONG,386 */
        /* 311 327 321 001(e3) 050 : AR0,AR1,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,386 */
        {I_JCXZ, 2, {IMM_NORMAL|BITS32|NEAR|SHORT,REG_ECX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56655, 215},
    /*   6 : JCXZ imm64|near|short,reg_ecx [i:        a32 nw o64 e3 rel8                ] ND,AR0-1,OSIZE,NOAPX,LONG,PROT,X86_64 */
        /* 311 327 324 001(e3) 050 : AR0,AR1,NWSIZE,OSIZE,NOAPX,LONG,PROT,X86_64 */
        {I_JCXZ, 2, {IMM_NORMAL|BITS64|NEAR|SHORT,REG_ECX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56662, 216},
    /*   7 : JCXZ imm64|near|short,reg_rcx [i:        a64 nw o64 e3 rel8                ] ND,AR0-1,OSIZE,NOAPX,LONG,PROT,X86_64 */
        /* 313 327 324 001(e3) 050 : AR0,AR1,NWSIZE,OSIZE,NOAPX,LONG,PROT,X86_64 */
        {I_JCXZ, 2, {IMM_NORMAL|BITS64|NEAR|SHORT,REG_RCX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56669, 216},
};

static const struct itemplate instrux_JECXZ[3] = {
    /*   0 : JECXZ imm16|near|short [i:        a32 nw o16 e3 rel8                ] AR0,OSIZE,NOREX,NOAPX,NOLONG,386 */
        /* 311 327 320 001(e3) 050 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,386 */
        {I_JECXZ, 1, {IMM_NORMAL|BITS16|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56641, 213},
    /*   1 : JECXZ imm32|near|short [i:        a32 nw o32 e3 rel8                ] AR0,OSIZE,NOREX,NOAPX,NOLONG,386 */
        /* 311 327 321 001(e3) 050 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,386 */
        {I_JECXZ, 1, {IMM_NORMAL|BITS32|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56655, 213},
    /*   2 : JECXZ imm64|near|short [i:        a32 nw o64 e3 rel8                ] AR0,OSIZE,NOAPX,LONG,PROT,X86_64 */
        /* 311 327 324 001(e3) 050 : AR0,NWSIZE,OSIZE,NOAPX,LONG,PROT,X86_64 */
        {I_JECXZ, 1, {IMM_NORMAL|BITS64|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56662, 188},
};

static const struct itemplate instrux_JRCXZ[1] = {
    /*   0 : JRCXZ imm64|near|short [i:        a64 nw o64 e3 rel8                ] AR0,OSIZE,NOAPX,LONG,PROT,X86_64 */
        /* 313 327 324 001(e3) 050 : AR0,NWSIZE,OSIZE,NOAPX,LONG,PROT,X86_64 */
        {I_JRCXZ, 1, {IMM_NORMAL|BITS64|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56669, 188},
};

static const struct itemplate instrux_LOOP[9] = {
    /*   0 : LOOP imm16|near|short [i:        asm nw o16 e2 rel8                ] AR0,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 312 327 320 001(e2) 050 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_LOOP, 1, {IMM_NORMAL|BITS16|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56676, 187},
    /*   1 : LOOP imm32|near|short [i:        asm nw o32 e2 rel8                ] AR0,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 312 327 321 001(e2) 050 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_LOOP, 1, {IMM_NORMAL|BITS32|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56697, 187},
    /*   2 : LOOP imm64|near|short [i:        asm nw o64 e2 rel8                ] AR0,OSIZE,NOAPX,LONG,PROT,X86_64 */
        /* 312 327 324 001(e2) 050 : AR0,NWSIZE,OSIZE,NOAPX,LONG,PROT,X86_64 */
        {I_LOOP, 1, {IMM_NORMAL|BITS64|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56718, 188},
    /*   3 : LOOP imm16|near|short,reg_cx [i-:       a16 nw o16 e2 rel8                ] AR0-1,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 310 327 320 001(e2) 050 : AR0,AR1,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_LOOP, 2, {IMM_NORMAL|BITS16|NEAR|SHORT,REG_CX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56683, 214},
    /*   4 : LOOP imm16|near|short,reg_ecx [i-:       a32 nw o16 e2 rel8                ] AR0-1,OSIZE,NOREX,NOAPX,NOLONG,386 */
        /* 311 327 320 001(e2) 050 : AR0,AR1,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,386 */
        {I_LOOP, 2, {IMM_NORMAL|BITS16|NEAR|SHORT,REG_ECX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56690, 215},
    /*   5 : LOOP imm32|near|short,reg_cx [i-:       a16 nw o32 e2 rel8                ] AR0-1,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 310 327 321 001(e2) 050 : AR0,AR1,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_LOOP, 2, {IMM_NORMAL|BITS32|NEAR|SHORT,REG_CX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56704, 214},
    /*   6 : LOOP imm32|near|short,reg_ecx [i-:       a32 nw o32 e2 rel8                ] AR0-1,OSIZE,NOREX,NOAPX,NOLONG,386 */
        /* 311 327 321 001(e2) 050 : AR0,AR1,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,386 */
        {I_LOOP, 2, {IMM_NORMAL|BITS32|NEAR|SHORT,REG_ECX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56711, 215},
    /*   7 : LOOP imm64|near|short,reg_ecx [i-:       a32 nw o64 e2 rel8                ] AR0-1,OSIZE,NOAPX,LONG,PROT,X86_64 */
        /* 311 327 324 001(e2) 050 : AR0,AR1,NWSIZE,OSIZE,NOAPX,LONG,PROT,X86_64 */
        {I_LOOP, 2, {IMM_NORMAL|BITS64|NEAR|SHORT,REG_ECX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56725, 216},
    /*   8 : LOOP imm64|near|short,reg_rcx [i-:       a64 nw o64 e2 rel8                ] AR0-1,OSIZE,NOAPX,LONG,PROT,X86_64 */
        /* 313 327 324 001(e2) 050 : AR0,AR1,NWSIZE,OSIZE,NOAPX,LONG,PROT,X86_64 */
        {I_LOOP, 2, {IMM_NORMAL|BITS64|NEAR|SHORT,REG_RCX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56732, 216},
};

static const struct itemplate instrux_LOOPW[2] = {
    /*   0 : LOOPW imm16|near|short [i:        a16 nw o16 e2 rel8                ] ND,AR0,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 310 327 320 001(e2) 050 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_LOOPW, 1, {IMM_NORMAL|BITS16|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56683, 187},
    /*   1 : LOOPW imm32|near|short [i:        a16 nw o32 e2 rel8                ] ND,AR0,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 310 327 321 001(e2) 050 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_LOOPW, 1, {IMM_NORMAL|BITS32|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56704, 187},
};

static const struct itemplate instrux_LOOPD[3] = {
    /*   0 : LOOPD imm16|near|short [i:        a32 nw o16 e2 rel8                ] ND,AR0,OSIZE,NOREX,NOAPX,NOLONG,386 */
        /* 311 327 320 001(e2) 050 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,386 */
        {I_LOOPD, 1, {IMM_NORMAL|BITS16|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56690, 213},
    /*   1 : LOOPD imm32|near|short [i:        a32 nw o32 e2 rel8                ] ND,AR0,OSIZE,NOREX,NOAPX,NOLONG,386 */
        /* 311 327 321 001(e2) 050 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,386 */
        {I_LOOPD, 1, {IMM_NORMAL|BITS32|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56711, 213},
    /*   2 : LOOPD imm64|near|short [i:        a32 nw o64 e2 rel8                ] ND,AR0,OSIZE,NOAPX,LONG,PROT,X86_64 */
        /* 311 327 324 001(e2) 050 : AR0,NWSIZE,OSIZE,NOAPX,LONG,PROT,X86_64 */
        {I_LOOPD, 1, {IMM_NORMAL|BITS64|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56725, 188},
};

static const struct itemplate instrux_LOOPQ[1] = {
    /*   0 : LOOPQ imm64|near|short [i:        a64 nw o64 e2 rel8                ] ND,AR0,OSIZE,NOAPX,LONG,PROT,X86_64 */
        /* 313 327 324 001(e2) 050 : AR0,NWSIZE,OSIZE,NOAPX,LONG,PROT,X86_64 */
        {I_LOOPQ, 1, {IMM_NORMAL|BITS64|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56732, 188},
};

static const struct itemplate instrux_LOOPE[9] = {
    /*   0 : LOOPE imm16|near|short [i:        asm nw o16 e1 rel8                ] AR0,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 312 327 320 001(e1) 050 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_LOOPE, 1, {IMM_NORMAL|BITS16|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56739, 187},
    /*   1 : LOOPE imm32|near|short [i:        asm nw o32 e1 rel8                ] AR0,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 312 327 321 001(e1) 050 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_LOOPE, 1, {IMM_NORMAL|BITS32|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56760, 187},
    /*   2 : LOOPE imm64|near|short [i:        asm nw o64 e1 rel8                ] AR0,OSIZE,NOAPX,LONG,PROT,X86_64 */
        /* 312 327 324 001(e1) 050 : AR0,NWSIZE,OSIZE,NOAPX,LONG,PROT,X86_64 */
        {I_LOOPE, 1, {IMM_NORMAL|BITS64|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56781, 188},
    /*   3 : LOOPE imm16|near|short,reg_cx [i-:       a16 nw o16 e1 rel8                ] AR0-1,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 310 327 320 001(e1) 050 : AR0,AR1,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_LOOPE, 2, {IMM_NORMAL|BITS16|NEAR|SHORT,REG_CX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56746, 214},
    /*   4 : LOOPE imm16|near|short,reg_ecx [i-:       a32 nw o16 e1 rel8                ] AR0-1,OSIZE,NOREX,NOAPX,NOLONG,386 */
        /* 311 327 320 001(e1) 050 : AR0,AR1,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,386 */
        {I_LOOPE, 2, {IMM_NORMAL|BITS16|NEAR|SHORT,REG_ECX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56753, 215},
    /*   5 : LOOPE imm32|near|short,reg_cx [i-:       a16 nw o32 e1 rel8                ] AR0-1,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 310 327 321 001(e1) 050 : AR0,AR1,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_LOOPE, 2, {IMM_NORMAL|BITS32|NEAR|SHORT,REG_CX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56767, 214},
    /*   6 : LOOPE imm32|near|short,reg_ecx [i-:       a32 nw o32 e1 rel8                ] AR0-1,OSIZE,NOREX,NOAPX,NOLONG,386 */
        /* 311 327 321 001(e1) 050 : AR0,AR1,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,386 */
        {I_LOOPE, 2, {IMM_NORMAL|BITS32|NEAR|SHORT,REG_ECX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56774, 215},
    /*   7 : LOOPE imm64|near|short,reg_ecx [i-:       a32 nw o64 e1 rel8                ] AR0-1,OSIZE,NOAPX,LONG,PROT,X86_64 */
        /* 311 327 324 001(e1) 050 : AR0,AR1,NWSIZE,OSIZE,NOAPX,LONG,PROT,X86_64 */
        {I_LOOPE, 2, {IMM_NORMAL|BITS64|NEAR|SHORT,REG_ECX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56788, 216},
    /*   8 : LOOPE imm64|near|short,reg_rcx [i-:       a64 nw o64 e1 rel8                ] AR0-1,OSIZE,NOAPX,LONG,PROT,X86_64 */
        /* 313 327 324 001(e1) 050 : AR0,AR1,NWSIZE,OSIZE,NOAPX,LONG,PROT,X86_64 */
        {I_LOOPE, 2, {IMM_NORMAL|BITS64|NEAR|SHORT,REG_RCX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56795, 216},
};

static const struct itemplate instrux_LOOPEW[2] = {
    /*   0 : LOOPEW imm16|near|short [i:        a16 nw o16 e1 rel8                ] ND,AR0,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 310 327 320 001(e1) 050 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_LOOPEW, 1, {IMM_NORMAL|BITS16|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56746, 187},
    /*   1 : LOOPEW imm32|near|short [i:        a16 nw o32 e1 rel8                ] ND,AR0,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 310 327 321 001(e1) 050 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_LOOPEW, 1, {IMM_NORMAL|BITS32|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56767, 187},
};

static const struct itemplate instrux_LOOPED[3] = {
    /*   0 : LOOPED imm16|near|short [i:        a32 nw o16 e1 rel8                ] ND,AR0,OSIZE,NOREX,NOAPX,NOLONG,386 */
        /* 311 327 320 001(e1) 050 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,386 */
        {I_LOOPED, 1, {IMM_NORMAL|BITS16|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56753, 213},
    /*   1 : LOOPED imm32|near|short [i:        a32 nw o32 e1 rel8                ] ND,AR0,OSIZE,NOREX,NOAPX,NOLONG,386 */
        /* 311 327 321 001(e1) 050 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,386 */
        {I_LOOPED, 1, {IMM_NORMAL|BITS32|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56774, 213},
    /*   2 : LOOPED imm64|near|short [i:        a32 nw o64 e1 rel8                ] ND,AR0,OSIZE,NOAPX,LONG,PROT,X86_64 */
        /* 311 327 324 001(e1) 050 : AR0,NWSIZE,OSIZE,NOAPX,LONG,PROT,X86_64 */
        {I_LOOPED, 1, {IMM_NORMAL|BITS64|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56788, 188},
};

static const struct itemplate instrux_LOOPEQ[1] = {
    /*   0 : LOOPEQ imm64|near|short [i:        a64 nw o64 e1 rel8                ] ND,AR0,OSIZE,NOAPX,LONG,PROT,X86_64 */
        /* 313 327 324 001(e1) 050 : AR0,NWSIZE,OSIZE,NOAPX,LONG,PROT,X86_64 */
        {I_LOOPEQ, 1, {IMM_NORMAL|BITS64|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56795, 188},
};

static const struct itemplate instrux_LOOPNE[9] = {
    /*   0 : LOOPNE imm16|near|short [i:        asm nw o16 e0 rel8                ] AR0,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 312 327 320 001(e0) 050 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_LOOPNE, 1, {IMM_NORMAL|BITS16|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56802, 187},
    /*   1 : LOOPNE imm32|near|short [i:        asm nw o32 e0 rel8                ] AR0,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 312 327 321 001(e0) 050 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_LOOPNE, 1, {IMM_NORMAL|BITS32|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56823, 187},
    /*   2 : LOOPNE imm64|near|short [i:        asm nw o64 e0 rel8                ] AR0,OSIZE,NOAPX,LONG,PROT,X86_64 */
        /* 312 327 324 001(e0) 050 : AR0,NWSIZE,OSIZE,NOAPX,LONG,PROT,X86_64 */
        {I_LOOPNE, 1, {IMM_NORMAL|BITS64|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56844, 188},
    /*   3 : LOOPNE imm16|near|short,reg_cx [i-:       a16 nw o16 e0 rel8                ] AR0-1,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 310 327 320 001(e0) 050 : AR0,AR1,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_LOOPNE, 2, {IMM_NORMAL|BITS16|NEAR|SHORT,REG_CX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56809, 214},
    /*   4 : LOOPNE imm16|near|short,reg_ecx [i-:       a32 nw o16 e0 rel8                ] AR0-1,OSIZE,NOREX,NOAPX,NOLONG,386 */
        /* 311 327 320 001(e0) 050 : AR0,AR1,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,386 */
        {I_LOOPNE, 2, {IMM_NORMAL|BITS16|NEAR|SHORT,REG_ECX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56816, 215},
    /*   5 : LOOPNE imm32|near|short,reg_cx [i-:       a16 nw o32 e0 rel8                ] AR0-1,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 310 327 321 001(e0) 050 : AR0,AR1,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_LOOPNE, 2, {IMM_NORMAL|BITS32|NEAR|SHORT,REG_CX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56830, 214},
    /*   6 : LOOPNE imm32|near|short,reg_ecx [i-:       a32 nw o32 e0 rel8                ] AR0-1,OSIZE,NOREX,NOAPX,NOLONG,386 */
        /* 311 327 321 001(e0) 050 : AR0,AR1,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,386 */
        {I_LOOPNE, 2, {IMM_NORMAL|BITS32|NEAR|SHORT,REG_ECX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56837, 215},
    /*   7 : LOOPNE imm64|near|short,reg_ecx [i-:       a32 nw o64 e0 rel8                ] AR0-1,OSIZE,NOAPX,LONG,PROT,X86_64 */
        /* 311 327 324 001(e0) 050 : AR0,AR1,NWSIZE,OSIZE,NOAPX,LONG,PROT,X86_64 */
        {I_LOOPNE, 2, {IMM_NORMAL|BITS64|NEAR|SHORT,REG_ECX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56851, 216},
    /*   8 : LOOPNE imm64|near|short,reg_rcx [i-:       a64 nw o64 e0 rel8                ] AR0-1,OSIZE,NOAPX,LONG,PROT,X86_64 */
        /* 313 327 324 001(e0) 050 : AR0,AR1,NWSIZE,OSIZE,NOAPX,LONG,PROT,X86_64 */
        {I_LOOPNE, 2, {IMM_NORMAL|BITS64|NEAR|SHORT,REG_RCX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56858, 216},
};

static const struct itemplate instrux_LOOPNEW[2] = {
    /*   0 : LOOPNEW imm16|near|short [i:        a16 nw o16 e0 rel8                ] ND,AR0,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 310 327 320 001(e0) 050 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_LOOPNEW, 1, {IMM_NORMAL|BITS16|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56809, 187},
    /*   1 : LOOPNEW imm32|near|short [i:        a16 nw o32 e0 rel8                ] ND,AR0,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 310 327 321 001(e0) 050 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_LOOPNEW, 1, {IMM_NORMAL|BITS32|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56830, 187},
};

static const struct itemplate instrux_LOOPNED[3] = {
    /*   0 : LOOPNED imm16|near|short [i:        a32 nw o16 e0 rel8                ] ND,AR0,OSIZE,NOREX,NOAPX,NOLONG,386 */
        /* 311 327 320 001(e0) 050 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,386 */
        {I_LOOPNED, 1, {IMM_NORMAL|BITS16|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56816, 213},
    /*   1 : LOOPNED imm32|near|short [i:        a32 nw o32 e0 rel8                ] ND,AR0,OSIZE,NOREX,NOAPX,NOLONG,386 */
        /* 311 327 321 001(e0) 050 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,386 */
        {I_LOOPNED, 1, {IMM_NORMAL|BITS32|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56837, 213},
    /*   2 : LOOPNED imm64|near|short [i:        a32 nw o64 e0 rel8                ] ND,AR0,OSIZE,NOAPX,LONG,PROT,X86_64 */
        /* 311 327 324 001(e0) 050 : AR0,NWSIZE,OSIZE,NOAPX,LONG,PROT,X86_64 */
        {I_LOOPNED, 1, {IMM_NORMAL|BITS64|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56851, 188},
};

static const struct itemplate instrux_LOOPNEQ[1] = {
    /*   0 : LOOPNEQ imm64|near|short [i:        a64 nw o64 e0 rel8                ] ND,AR0,OSIZE,NOAPX,LONG,PROT,X86_64 */
        /* 313 327 324 001(e0) 050 : AR0,NWSIZE,OSIZE,NOAPX,LONG,PROT,X86_64 */
        {I_LOOPNEQ, 1, {IMM_NORMAL|BITS64|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56858, 188},
};

static const struct itemplate instrux_LOOPZ[9] = {
    /*   0 : LOOPZ imm16|near|short [i:        asm nw o16 e1 rel8                ] ND,AR0,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 312 327 320 001(e1) 050 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_LOOPZ, 1, {IMM_NORMAL|BITS16|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56739, 187},
    /*   1 : LOOPZ imm32|near|short [i:        asm nw o32 e1 rel8                ] ND,AR0,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 312 327 321 001(e1) 050 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_LOOPZ, 1, {IMM_NORMAL|BITS32|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56760, 187},
    /*   2 : LOOPZ imm64|near|short [i:        asm nw o64 e1 rel8                ] ND,AR0,OSIZE,NOAPX,LONG,PROT,X86_64 */
        /* 312 327 324 001(e1) 050 : AR0,NWSIZE,OSIZE,NOAPX,LONG,PROT,X86_64 */
        {I_LOOPZ, 1, {IMM_NORMAL|BITS64|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56781, 188},
    /*   3 : LOOPZ imm16|near|short,reg_cx [i-:       a16 nw o16 e1 rel8                ] AR0-1,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 310 327 320 001(e1) 050 : AR0,AR1,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_LOOPZ, 2, {IMM_NORMAL|BITS16|NEAR|SHORT,REG_CX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56746, 214},
    /*   4 : LOOPZ imm16|near|short,reg_ecx [i-:       a32 nw o16 e1 rel8                ] AR0-1,OSIZE,NOREX,NOAPX,NOLONG,386 */
        /* 311 327 320 001(e1) 050 : AR0,AR1,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,386 */
        {I_LOOPZ, 2, {IMM_NORMAL|BITS16|NEAR|SHORT,REG_ECX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56753, 215},
    /*   5 : LOOPZ imm32|near|short,reg_cx [i-:       a16 nw o32 e1 rel8                ] AR0-1,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 310 327 321 001(e1) 050 : AR0,AR1,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_LOOPZ, 2, {IMM_NORMAL|BITS32|NEAR|SHORT,REG_CX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56767, 214},
    /*   6 : LOOPZ imm32|near|short,reg_ecx [i-:       a32 nw o32 e1 rel8                ] AR0-1,OSIZE,NOREX,NOAPX,NOLONG,386 */
        /* 311 327 321 001(e1) 050 : AR0,AR1,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,386 */
        {I_LOOPZ, 2, {IMM_NORMAL|BITS32|NEAR|SHORT,REG_ECX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56774, 215},
    /*   7 : LOOPZ imm64|near|short,reg_ecx [i-:       a32 nw o64 e1 rel8                ] AR0-1,OSIZE,NOAPX,LONG,PROT,X86_64 */
        /* 311 327 324 001(e1) 050 : AR0,AR1,NWSIZE,OSIZE,NOAPX,LONG,PROT,X86_64 */
        {I_LOOPZ, 2, {IMM_NORMAL|BITS64|NEAR|SHORT,REG_ECX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56788, 216},
    /*   8 : LOOPZ imm64|near|short,reg_rcx [i-:       a64 nw o64 e1 rel8                ] AR0-1,OSIZE,NOAPX,LONG,PROT,X86_64 */
        /* 313 327 324 001(e1) 050 : AR0,AR1,NWSIZE,OSIZE,NOAPX,LONG,PROT,X86_64 */
        {I_LOOPZ, 2, {IMM_NORMAL|BITS64|NEAR|SHORT,REG_RCX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56795, 216},
};

static const struct itemplate instrux_LOOPZW[2] = {
    /*   0 : LOOPZW imm16|near|short [i:        a16 nw o16 e1 rel8                ] ND,AR0,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 310 327 320 001(e1) 050 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_LOOPZW, 1, {IMM_NORMAL|BITS16|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56746, 187},
    /*   1 : LOOPZW imm32|near|short [i:        a16 nw o32 e1 rel8                ] ND,AR0,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 310 327 321 001(e1) 050 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_LOOPZW, 1, {IMM_NORMAL|BITS32|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56767, 187},
};

static const struct itemplate instrux_LOOPZD[3] = {
    /*   0 : LOOPZD imm16|near|short [i:        a32 nw o16 e1 rel8                ] ND,AR0,OSIZE,NOREX,NOAPX,NOLONG,386 */
        /* 311 327 320 001(e1) 050 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,386 */
        {I_LOOPZD, 1, {IMM_NORMAL|BITS16|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56753, 213},
    /*   1 : LOOPZD imm32|near|short [i:        a32 nw o32 e1 rel8                ] ND,AR0,OSIZE,NOREX,NOAPX,NOLONG,386 */
        /* 311 327 321 001(e1) 050 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,386 */
        {I_LOOPZD, 1, {IMM_NORMAL|BITS32|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56774, 213},
    /*   2 : LOOPZD imm64|near|short [i:        a32 nw o64 e1 rel8                ] ND,AR0,OSIZE,NOAPX,LONG,PROT,X86_64 */
        /* 311 327 324 001(e1) 050 : AR0,NWSIZE,OSIZE,NOAPX,LONG,PROT,X86_64 */
        {I_LOOPZD, 1, {IMM_NORMAL|BITS64|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56788, 188},
};

static const struct itemplate instrux_LOOPZQ[1] = {
    /*   0 : LOOPZQ imm64|near|short [i:        a64 nw o64 e1 rel8                ] ND,AR0,OSIZE,NOAPX,LONG,PROT,X86_64 */
        /* 313 327 324 001(e1) 050 : AR0,NWSIZE,OSIZE,NOAPX,LONG,PROT,X86_64 */
        {I_LOOPZQ, 1, {IMM_NORMAL|BITS64|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56795, 188},
};

static const struct itemplate instrux_LOOPNZ[9] = {
    /*   0 : LOOPNZ imm16|near|short [i:        asm nw o16 e0 rel8                ] ND,AR0,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 312 327 320 001(e0) 050 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_LOOPNZ, 1, {IMM_NORMAL|BITS16|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56802, 187},
    /*   1 : LOOPNZ imm32|near|short [i:        asm nw o32 e0 rel8                ] ND,AR0,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 312 327 321 001(e0) 050 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_LOOPNZ, 1, {IMM_NORMAL|BITS32|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56823, 187},
    /*   2 : LOOPNZ imm64|near|short [i:        asm nw o64 e0 rel8                ] ND,AR0,OSIZE,NOAPX,LONG,PROT,X86_64 */
        /* 312 327 324 001(e0) 050 : AR0,NWSIZE,OSIZE,NOAPX,LONG,PROT,X86_64 */
        {I_LOOPNZ, 1, {IMM_NORMAL|BITS64|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56844, 188},
    /*   3 : LOOPNZ imm16|near|short,reg_cx [i-:       a16 nw o16 e0 rel8                ] AR0-1,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 310 327 320 001(e0) 050 : AR0,AR1,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_LOOPNZ, 2, {IMM_NORMAL|BITS16|NEAR|SHORT,REG_CX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56809, 214},
    /*   4 : LOOPNZ imm16|near|short,reg_ecx [i-:       a32 nw o16 e0 rel8                ] AR0-1,OSIZE,NOREX,NOAPX,NOLONG,386 */
        /* 311 327 320 001(e0) 050 : AR0,AR1,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,386 */
        {I_LOOPNZ, 2, {IMM_NORMAL|BITS16|NEAR|SHORT,REG_ECX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56816, 215},
    /*   5 : LOOPNZ imm32|near|short,reg_cx [i-:       a16 nw o32 e0 rel8                ] AR0-1,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 310 327 321 001(e0) 050 : AR0,AR1,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_LOOPNZ, 2, {IMM_NORMAL|BITS32|NEAR|SHORT,REG_CX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56830, 214},
    /*   6 : LOOPNZ imm32|near|short,reg_ecx [i-:       a32 nw o32 e0 rel8                ] AR0-1,OSIZE,NOREX,NOAPX,NOLONG,386 */
        /* 311 327 321 001(e0) 050 : AR0,AR1,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,386 */
        {I_LOOPNZ, 2, {IMM_NORMAL|BITS32|NEAR|SHORT,REG_ECX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56837, 215},
    /*   7 : LOOPNZ imm64|near|short,reg_ecx [i-:       a32 nw o64 e0 rel8                ] AR0-1,OSIZE,NOAPX,LONG,PROT,X86_64 */
        /* 311 327 324 001(e0) 050 : AR0,AR1,NWSIZE,OSIZE,NOAPX,LONG,PROT,X86_64 */
        {I_LOOPNZ, 2, {IMM_NORMAL|BITS64|NEAR|SHORT,REG_ECX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56851, 216},
    /*   8 : LOOPNZ imm64|near|short,reg_rcx [i-:       a64 nw o64 e0 rel8                ] AR0-1,OSIZE,NOAPX,LONG,PROT,X86_64 */
        /* 313 327 324 001(e0) 050 : AR0,AR1,NWSIZE,OSIZE,NOAPX,LONG,PROT,X86_64 */
        {I_LOOPNZ, 2, {IMM_NORMAL|BITS64|NEAR|SHORT,REG_RCX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56858, 216},
};

static const struct itemplate instrux_LOOPNZW[2] = {
    /*   0 : LOOPNZW imm16|near|short [i:        a16 nw o16 e0 rel8                ] ND,AR0,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 310 327 320 001(e0) 050 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_LOOPNZW, 1, {IMM_NORMAL|BITS16|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56809, 187},
    /*   1 : LOOPNZW imm32|near|short [i:        a16 nw o32 e0 rel8                ] ND,AR0,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 310 327 321 001(e0) 050 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_LOOPNZW, 1, {IMM_NORMAL|BITS32|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56830, 187},
};

static const struct itemplate instrux_LOOPNZD[3] = {
    /*   0 : LOOPNZD imm16|near|short [i:        a32 nw o16 e0 rel8                ] ND,AR0,OSIZE,NOREX,NOAPX,NOLONG,386 */
        /* 311 327 320 001(e0) 050 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,386 */
        {I_LOOPNZD, 1, {IMM_NORMAL|BITS16|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56816, 213},
    /*   1 : LOOPNZD imm32|near|short [i:        a32 nw o32 e0 rel8                ] ND,AR0,OSIZE,NOREX,NOAPX,NOLONG,386 */
        /* 311 327 321 001(e0) 050 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,386 */
        {I_LOOPNZD, 1, {IMM_NORMAL|BITS32|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56837, 213},
    /*   2 : LOOPNZD imm64|near|short [i:        a32 nw o64 e0 rel8                ] ND,AR0,OSIZE,NOAPX,LONG,PROT,X86_64 */
        /* 311 327 324 001(e0) 050 : AR0,NWSIZE,OSIZE,NOAPX,LONG,PROT,X86_64 */
        {I_LOOPNZD, 1, {IMM_NORMAL|BITS64|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56851, 188},
};

static const struct itemplate instrux_LOOPNZQ[1] = {
    /*   0 : LOOPNZQ imm64|near|short [i:        a64 nw o64 e0 rel8                ] ND,AR0,OSIZE,NOAPX,LONG,PROT,X86_64 */
        /* 313 327 324 001(e0) 050 : AR0,NWSIZE,OSIZE,NOAPX,LONG,PROT,X86_64 */
        {I_LOOPNZQ, 1, {IMM_NORMAL|BITS64|NEAR|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56858, 188},
};

static const struct itemplate instrux_JMPE[9] = {
    /*   0 : JMPE imm16|near [i:        nw o16 0f b8 rel                  ] AR0,OSIZE,NOREX,NOAPX,NOLONG,IA64 */
        /* 327 320 355 001(b8) 064 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,IA64 */
        {I_JMPE, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56865, 217},
    /*   1 : JMPE imm32|near [i:        nw o32 0f b8 rel                  ] AR0,OSIZE,NOREX,NOAPX,NOLONG,IA64 */
        /* 327 321 355 001(b8) 064 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,IA64 */
        {I_JMPE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56872, 217},
    /*   2 : JMPE imm64|near [i:        nw o64 0f b8 rel                  ] AR0,OSIZE,LONG,PROT,X86_64 */
        /* 327 324 355 001(b8) 064 : AR0,NWSIZE,OSIZE,LONG,PROT,X86_64 */
        {I_JMPE, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56879, 204},
    /*   3 : JMPE imm32|near [i:        nw o64 0f b8 rel                  ] ND,AR0,SX,LONG,PROT,X86_64 */
        /* 327 324 355 001(b8) 064 : AR0,NWSIZE,SX,LONG,PROT,X86_64 */
        {I_JMPE, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56879, 218},
    /*   4 : JMPE rm16|near [m:        nw o16 np 0f 00 /6                ] AR0,OSIZE,IA64 */
        /* 327 320 360 355 001(00) 206 : AR0,NWSIZE,OSIZE,IA64 */
        {I_JMPE, 1, {RM_GPR|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+51157, 219},
    /*   5 : JMPE rm32|near [m:        nw o32 np 0f 00 /6                ] AR0,OSIZE,IA64 */
        /* 327 321 360 355 001(00) 206 : AR0,NWSIZE,OSIZE,IA64 */
        {I_JMPE, 1, {RM_GPR|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+51165, 219},
    /*   6 : JMPE rm64|near [m:        nw o64 np 0f 00 /6                ] AR0,OSIZE,LONG,PROT,X86_64 */
        /* 327 324 360 355 001(00) 206 : AR0,NWSIZE,OSIZE,LONG,PROT,X86_64 */
        {I_JMPE, 1, {RM_GPR|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+51173, 204},
    /*   7 : JMPE rm16|near [m:        o16 0f 00 /6                      ] AR0,OSIZE,NOREX,NOAPX,NOLONG,IA64 */
        /* 320 355 001(00) 206 : AR0,OSIZE,NOREX,NOAPX,NOLONG,IA64 */
        {I_JMPE, 1, {RM_GPR|BITS16|RN_L16|NEAR|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66956, 220},
    /*   8 : JMPE rm32|near [m:        o32 0f 00 /6                      ] AR0,OSIZE,NOREX,NOAPX,NOLONG,IA64 */
        /* 321 355 001(00) 206 : AR0,OSIZE,NOREX,NOAPX,NOLONG,IA64 */
        {I_JMPE, 1, {RM_GPR|BITS32|RN_L16|NEAR|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66962, 220},
};

static const struct itemplate instrux_CALL[20] = {
    /*   0 : CALL imm16|near [i:        nw o16 e8 rel                     ] AR0,OSIZE,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 320 001(e8) 064 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_CALL, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66968, 192},
    /*   1 : CALL imm32|near [i:        nw o32 e8 rel                     ] AR0,OSIZE,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 321 001(e8) 064 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_CALL, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66974, 192},
    /*   2 : CALL imm64|near [i:        nw o64 e8 rel                     ] AR0,OSIZE,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 001(e8) 064 : AR0,NWSIZE,OSIZE,NOAPX,LONG,BND,PROT,X86_64 */
        {I_CALL, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66980, 221},
    /*   3 : CALL imm32|near [i:        nw o64 e8 rel                     ] ND,AR0,SX,NOAPX,LONG,BND,PROT,X86_64 */
        /* 327 324 001(e8) 064 : AR0,NWSIZE,SX,NOAPX,LONG,BND,PROT,X86_64 */
        {I_CALL, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66980, 222},
    /*   4 : CALL rm16|near [m:        nw o16 ff /2                      ] AR0,OSIZE,NOREX,NOAPX,NOLONG,BND,8086 */
        /* 327 320 001(ff) 202 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,BND,8086 */
        {I_CALL, 1, {RM_GPR|BITS16|RN_L16|NEAR|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66986, 192},
    /*   5 : CALL rm32|near [m:        nw o32 ff /2                      ] AR0,OSIZE,NOREX,NOAPX,NOLONG,BND,386 */
        /* 327 321 001(ff) 202 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,BND,386 */
        {I_CALL, 1, {RM_GPR|BITS32|RN_L16|NEAR|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66992, 223},
    /*   6 : CALL rm64|near [m:        nw o64 ff /2                      ] LONG,BND,PROT,X86_64 */
        /* 327 324 001(ff) 202 : NWSIZE,LONG,BND,PROT,X86_64 */
        {I_CALL, 1, {RM_GPR|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66998, 224},
    /*   7 : CALL imm16|far [i:        o16 9a iwd seg                    ] ND,AR0,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 320 001(9a) 034 074 : AR0,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_CALL, 1, {IMM_NORMAL|BITS16|FAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67004, 197},
    /*   8 : CALL imm32|far [i:        o32 9a iwd seg                    ] ND,AR0,OSIZE,NOREX,NOAPX,NOLONG,386 */
        /* 321 001(9a) 034 074 : AR0,OSIZE,NOREX,NOAPX,NOLONG,386 */
        {I_CALL, 1, {IMM_NORMAL|BITS32|FAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67010, 198},
    /*   9 : CALL imm16:imm16 [ji:       o16 9a iw iw                      ] ND,SM0-1,AR0,SX,NOREX,NOAPX,NOLONG,8086 */
        /* 320 001(9a) 031 030 : SM0,SM1,AR0,SX,NOREX,NOAPX,NOLONG,8086 */
        {I_CALL, 2, {IMM_NORMAL|BITS16|COLON,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67016, 199},
    /*  10 : CALL imm32:imm32 [ji:       o32 9a id iw                      ] ND,SM0-1,AR0,SX,NOREX,NOAPX,NOLONG,386 */
        /* 321 001(9a) 041 030 : SM0,SM1,AR0,SX,NOREX,NOAPX,NOLONG,386 */
        {I_CALL, 2, {IMM_NORMAL|BITS32|COLON,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+67022, 200},
    /*  11 : CALL imm16:imm16|far [ji:       o16 9a iw iw                      ] ND,SM0-1,AR0,SX,NOREX,NOAPX,NOLONG,8086 */
        /* 320 001(9a) 031 030 : SM0,SM1,AR0,SX,NOREX,NOAPX,NOLONG,8086 */
        {I_CALL, 2, {IMM_NORMAL|BITS16|COLON,IMM_NORMAL|BITS16|FAR,0,0,0}, NO_DECORATOR, nasm_bytecodes+67016, 199},
    /*  12 : CALL imm32:imm32|far [ji:       o32 9a id iw                      ] ND,SM0-1,AR0,SX,NOREX,NOAPX,NOLONG,386 */
        /* 321 001(9a) 041 030 : SM0,SM1,AR0,SX,NOREX,NOAPX,NOLONG,386 */
        {I_CALL, 2, {IMM_NORMAL|BITS32|COLON,IMM_NORMAL|BITS32|FAR,0,0,0}, NO_DECORATOR, nasm_bytecodes+67022, 200},
    /*  13 : CALL imm16:imm16 [ji:       o16 9a iw iw                      ] AR1,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 320 001(9a) 031 030 : AR1,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_CALL, 2, {IMM_NORMAL|BITS16|COLON,IMM_NORMAL|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67016, 201},
    /*  14 : CALL imm16:imm32 [ji:       o32 9a id iw                      ] AR1,OSIZE,NOREX,NOAPX,NOLONG,386 */
        /* 321 001(9a) 041 030 : AR1,OSIZE,NOREX,NOAPX,NOLONG,386 */
        {I_CALL, 2, {IMM_NORMAL|BITS16|COLON,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+67022, 202},
    /*  15 : CALL imm16:imm16|far [ji:       o16 9a iw iw                      ] ND,AR1,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 320 001(9a) 031 030 : AR1,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_CALL, 2, {IMM_NORMAL|BITS16|COLON,IMM_NORMAL|BITS16|FAR,0,0,0}, NO_DECORATOR, nasm_bytecodes+67016, 201},
    /*  16 : CALL imm16:imm32|far [ji:       o32 9a id iw                      ] ND,AR1,OSIZE,NOREX,NOAPX,NOLONG,386 */
        /* 321 001(9a) 041 030 : AR1,OSIZE,NOREX,NOAPX,NOLONG,386 */
        {I_CALL, 2, {IMM_NORMAL|BITS16|COLON,IMM_NORMAL|BITS32|FAR,0,0,0}, NO_DECORATOR, nasm_bytecodes+67022, 202},
    /*  17 : CALL mem16|far [m:        o16 ff /3                         ] AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        /* 320 001(ff) 203 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,8086 */
        {I_CALL, 1, {MEMORY|BITS16|RN_L16|FAR|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71533, 187},
    /*  18 : CALL mem32|far [m:        o32 ff /3                         ] AR0,NWSIZE,OSIZE,386 */
        /* 321 001(ff) 203 : AR0,NWSIZE,OSIZE,386 */
        {I_CALL, 1, {MEMORY|BITS32|FAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71538, 203},
    /*  19 : CALL mem64|far [m:        o64 ff /3                         ] AR0,NWSIZE,OSIZE,LONG,386,X86_64 */
        /* 324 001(ff) 203 : AR0,NWSIZE,OSIZE,LONG,PROT,X86_64 */
        {I_CALL, 1, {MEMORY|BITS64|FAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71543, 204},
};

static const struct itemplate instrux_RET[2] = {
    /*   0 : RET void [          nw osm c3                         ] BND,8086 */
        /* 327 342 001(c3) : NWSIZE,BND,8086 */
        {I_RET, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71548, 225},
    /*   1 : RET imm16 [i:        nw osm c2 iw                      ] BND,8086 */
        /* 327 342 001(c2) 030 : NWSIZE,BND,8086 */
        {I_RET, 1, {IMM_NORMAL|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67028, 225},
};

static const struct itemplate instrux_RETW[2] = {
    /*   0 : RETW void [          nw o16 c3                         ] BND,8086 */
        /* 327 320 001(c3) : NWSIZE,BND,8086 */
        {I_RETW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71553, 225},
    /*   1 : RETW imm16 [i:        nw o16 c2 iw                      ] BND,8086 */
        /* 327 320 001(c2) 030 : NWSIZE,BND,8086 */
        {I_RETW, 1, {IMM_NORMAL|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67034, 225},
};

static const struct itemplate instrux_RETD[2] = {
    /*   0 : RETD void [          nw o32 c3                         ] NOREX,NOAPX,NOLONG,BND,386 */
        /* 327 321 001(c3) : NWSIZE,NOREX,NOAPX,NOLONG,BND,386 */
        {I_RETD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71558, 226},
    /*   1 : RETD imm16 [i:        nw o32 c2 iw                      ] NOREX,NOAPX,NOLONG,BND,386 */
        /* 327 321 001(c2) 030 : NWSIZE,NOREX,NOAPX,NOLONG,BND,386 */
        {I_RETD, 1, {IMM_NORMAL|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67040, 226},
};

static const struct itemplate instrux_RETQ[2] = {
    /*   0 : RETQ void [          nw o64 c3                         ] LONG,BND,386,X86_64 */
        /* 327 324 001(c3) : NWSIZE,LONG,BND,PROT,X86_64 */
        {I_RETQ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71563, 224},
    /*   1 : RETQ imm16 [i:        nw o64 c2 iw                      ] LONG,BND,386,X86_64 */
        /* 327 324 001(c2) 030 : NWSIZE,LONG,BND,PROT,X86_64 */
        {I_RETQ, 1, {IMM_NORMAL|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67046, 224},
};

static const struct itemplate instrux_RETF[2] = {
    /*   0 : RETF void [          odf cb                            ] 8086 */
        /* 322 001(cb) : 8086 */
        {I_RETF, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72589, 23},
    /*   1 : RETF imm16 [i:        odf ca iw                         ] 8086 */
        /* 322 001(ca) 030 : 8086 */
        {I_RETF, 1, {IMM_NORMAL|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71568, 23},
};

static const struct itemplate instrux_RETFW[2] = {
    /*   0 : RETFW void [          o16 cb                            ] 8086 */
        /* 320 001(cb) : 8086 */
        {I_RETFW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72593, 23},
    /*   1 : RETFW imm16 [i:        o16 ca iw                         ] 8086 */
        /* 320 001(ca) 030 : 8086 */
        {I_RETFW, 1, {IMM_NORMAL|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71573, 23},
};

static const struct itemplate instrux_RETFD[2] = {
    /*   0 : RETFD void [          o32 cb                            ] 386 */
        /* 321 001(cb) : 386 */
        {I_RETFD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72597, 3},
    /*   1 : RETFD imm16 [i:        o32 ca iw                         ] 386 */
        /* 321 001(ca) 030 : 386 */
        {I_RETFD, 1, {IMM_NORMAL|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71578, 3},
};

static const struct itemplate instrux_RETFQ[2] = {
    /*   0 : RETFQ void [          o64 cb                            ] LONG,386,X86_64 */
        /* 324 001(cb) : LONG,PROT,X86_64 */
        {I_RETFQ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72601, 24},
    /*   1 : RETFQ imm16 [i:        o64 ca iw                         ] LONG,386,X86_64 */
        /* 324 001(ca) 030 : LONG,PROT,X86_64 */
        {I_RETFQ, 1, {IMM_NORMAL|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71583, 24},
};

static const struct itemplate instrux_RETN[2] = {
    /*   0 : RETN void [          nw osm c3                         ] ND,BND,8086 */
        /* 327 342 001(c3) : NWSIZE,BND,8086 */
        {I_RETN, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71548, 225},
    /*   1 : RETN imm16 [i:        nw osm c2 iw                      ] ND,BND,8086 */
        /* 327 342 001(c2) 030 : NWSIZE,BND,8086 */
        {I_RETN, 1, {IMM_NORMAL|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67028, 225},
};

static const struct itemplate instrux_RETNW[2] = {
    /*   0 : RETNW void [          nw o16 c3                         ] ND,BND,8086 */
        /* 327 320 001(c3) : NWSIZE,BND,8086 */
        {I_RETNW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71553, 225},
    /*   1 : RETNW imm16 [i:        nw o16 c2 iw                      ] ND,BND,8086 */
        /* 327 320 001(c2) 030 : NWSIZE,BND,8086 */
        {I_RETNW, 1, {IMM_NORMAL|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67034, 225},
};

static const struct itemplate instrux_RETND[2] = {
    /*   0 : RETND void [          nw o32 c3                         ] ND,NOREX,NOAPX,NOLONG,BND,386 */
        /* 327 321 001(c3) : NWSIZE,NOREX,NOAPX,NOLONG,BND,386 */
        {I_RETND, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71558, 226},
    /*   1 : RETND imm16 [i:        nw o32 c2 iw                      ] ND,NOREX,NOAPX,NOLONG,BND,386 */
        /* 327 321 001(c2) 030 : NWSIZE,NOREX,NOAPX,NOLONG,BND,386 */
        {I_RETND, 1, {IMM_NORMAL|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67040, 226},
};

static const struct itemplate instrux_RETNQ[2] = {
    /*   0 : RETNQ void [          nw o64 c3                         ] ND,LONG,BND,386,X86_64 */
        /* 327 324 001(c3) : NWSIZE,LONG,BND,PROT,X86_64 */
        {I_RETNQ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71563, 224},
    /*   1 : RETNQ imm16 [i:        nw o64 c2 iw                      ] ND,LONG,BND,386,X86_64 */
        /* 327 324 001(c2) 030 : NWSIZE,LONG,BND,PROT,X86_64 */
        {I_RETNQ, 1, {IMM_NORMAL|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67046, 224},
};

static const struct itemplate instrux_INT[1] = {
    /*   0 : INT imm8 [i:        cd ib,u                           ] 8086 */
        /* 001(cd) 024 : 8086 */
        {I_INT, 1, {IMM_NORMAL|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72605, 23},
};

static const struct itemplate instrux_INT1[1] = {
    /*   0 : INT1 void [          f1                                ] 386 */
        /* 001(f1) : 386 */
        {I_INT1, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73302, 3},
};

static const struct itemplate instrux_INT01[1] = {
    /*   0 : INT01 void [          f1                                ] ND,386 */
        /* 001(f1) : 386 */
        {I_INT01, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73302, 3},
};

static const struct itemplate instrux_ICEBP[1] = {
    /*   0 : ICEBP void [          f1                                ] ND,386 */
        /* 001(f1) : 386 */
        {I_ICEBP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73302, 3},
};

static const struct itemplate instrux_INT3[1] = {
    /*   0 : INT3 void [          cc                                ] 8086 */
        /* 001(cc) : 8086 */
        {I_INT3, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73305, 23},
};

static const struct itemplate instrux_INT03[1] = {
    /*   0 : INT03 void [          cc                                ] ND,8086 */
        /* 001(cc) : 8086 */
        {I_INT03, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73305, 23},
};

static const struct itemplate instrux_BRKPT[1] = {
    /*   0 : BRKPT void [          cc                                ] ND,8086 */
        /* 001(cc) : 8086 */
        {I_BRKPT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73305, 23},
};

static const struct itemplate instrux_INTO[1] = {
    /*   0 : INTO void [          ce                                ] NOREX,NOAPX,NOLONG,8086 */
        /* 001(ce) : NOREX,NOAPX,NOLONG,8086 */
        {I_INTO, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73308, 227},
};

static const struct itemplate instrux_SYSCALL[1] = {
    /*   0 : SYSCALL void [          0f 05                             ] P6,AMD */
        /* 355 001(05) : P6,AMD */
        {I_SYSCALL, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72609, 228},
};

static const struct itemplate instrux_SYSENTER[1] = {
    /*   0 : SYSENTER void [          0f 34                             ] NOAPX,P6 */
        /* 355 001(34) : NOAPX,P6 */
        {I_SYSENTER, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72613, 229},
};

static const struct itemplate instrux_SYSEXIT[1] = {
    /*   0 : SYSEXIT void [          0f 35                             ] NOAPX,PRIV,P6 */
        /* 355 001(35) : NOAPX,PRIV,P6 */
        {I_SYSEXIT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72617, 230},
};

static const struct itemplate instrux_SYSRET[1] = {
    /*   0 : SYSRET void [          0f 07                             ] PRIV,P6,AMD */
        /* 355 001(07) : PRIV,P6,AMD */
        {I_SYSRET, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72621, 231},
};

static const struct itemplate instrux_IRET[1] = {
    /*   0 : IRET void [          osm cf                            ] FL,8086 */
        /* 342 001(cf) : FL,8086 */
        {I_IRET, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72625, 54},
};

static const struct itemplate instrux_IRETW[1] = {
    /*   0 : IRETW void [          o16 cf                            ] FL,8086 */
        /* 320 001(cf) : FL,8086 */
        {I_IRETW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72629, 54},
};

static const struct itemplate instrux_IRETD[1] = {
    /*   0 : IRETD void [          o32 cf                            ] FL,386 */
        /* 321 001(cf) : FL,386 */
        {I_IRETD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72633, 55},
};

static const struct itemplate instrux_IRETQ[1] = {
    /*   0 : IRETQ void [          o64 cf                            ] LONG,FL,386,X86_64 */
        /* 324 001(cf) : LONG,FL,PROT,X86_64 */
        {I_IRETQ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72637, 56},
};

static const struct itemplate instrux_ERETS[1] = {
    /*   0 : ERETS void [          f2 0f 01 ca                       ] LONG,PRIV,PROT,FRED,X86_64 */
        /* 332 355 002(01 ca) : LONG,PRIV,PROT,FRED,X86_64 */
        {I_ERETS, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67052, 232},
};

static const struct itemplate instrux_ERETU[1] = {
    /*   0 : ERETU void [          f3 0f 01 ca                       ] LONG,PRIV,PROT,FRED,X86_64 */
        /* 333 355 002(01 ca) : LONG,PRIV,PROT,FRED,X86_64 */
        {I_ERETU, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67058, 232},
};

static const struct itemplate instrux_CLC[1] = {
    /*   0 : CLC void [          f8                                ] FL,8086 */
        /* 001(f8) : FL,8086 */
        {I_CLC, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71785, 54},
};

static const struct itemplate instrux_CLD[1] = {
    /*   0 : CLD void [          fc                                ] FL,8086 */
        /* 001(fc) : FL,8086 */
        {I_CLD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67139, 54},
};

static const struct itemplate instrux_CLI[1] = {
    /*   0 : CLI void [          fa                                ] FL,8086 */
        /* 001(fa) : FL,8086 */
        {I_CLI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67349, 54},
};

static const struct itemplate instrux_CLAC[1] = {
    /*   0 : CLAC void [          np 0f 01 ca                       ] FL,PRIV,SMAP,FUTURE */
        /* 360 355 002(01 ca) : FL,PRIV,SMAP,FUTURE */
        {I_CLAC, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67064, 233},
};

static const struct itemplate instrux_STC[1] = {
    /*   0 : STC void [          f9                                ] FL,8086 */
        /* 001(f9) : FL,8086 */
        {I_STC, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71675, 54},
};

static const struct itemplate instrux_STD[1] = {
    /*   0 : STD void [          fd                                ] FL,8086 */
        /* 001(fd) : FL,8086 */
        {I_STD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73311, 54},
};

static const struct itemplate instrux_STI[1] = {
    /*   0 : STI void [          fb                                ] FL,8086 */
        /* 001(fb) : FL,8086 */
        {I_STI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71725, 54},
};

static const struct itemplate instrux_STAC[1] = {
    /*   0 : STAC void [          np 0f 01 cb                       ] FL,PRIV,SMAP,FUTURE */
        /* 360 355 002(01 cb) : FL,PRIV,SMAP,FUTURE */
        {I_STAC, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67070, 233},
};

static const struct itemplate instrux_CMC[1] = {
    /*   0 : CMC void [          f5                                ] FL,8086 */
        /* 001(f5) : FL,8086 */
        {I_CMC, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73314, 54},
};

static const struct itemplate instrux_LAHF[1] = {
    /*   0 : LAHF void [          9f                                ] 8086 */
        /* 001(9f) : 8086 */
        {I_LAHF, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73317, 23},
};

static const struct itemplate instrux_SAHF[1] = {
    /*   0 : SAHF void [          9e                                ] FL,8086 */
        /* 001(9e) : FL,8086 */
        {I_SAHF, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57226, 54},
};

static const struct itemplate instrux_SALC[1] = {
    /*   0 : SALC void [          d6                                ] NOREX,NOAPX,NOLONG,UNDOC,8086 */
        /* 001(d6) : NOREX,NOAPX,NOLONG,UNDOC,8086 */
        {I_SALC, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72380, 234},
};

static const struct itemplate instrux_PUSHF[1] = {
    /*   0 : PUSHF void [          nw osm 9c                         ] 8086 */
        /* 327 342 001(9c) : NWSIZE,8086 */
        {I_PUSHF, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71588, 235},
};

static const struct itemplate instrux_PUSHFW[1] = {
    /*   0 : PUSHFW void [          nw o16 9c                         ] 8086 */
        /* 327 320 001(9c) : NWSIZE,8086 */
        {I_PUSHFW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71593, 235},
};

static const struct itemplate instrux_PUSHFD[1] = {
    /*   0 : PUSHFD void [          nw o32 9c                         ] 386 */
        /* 327 321 001(9c) : NWSIZE,386 */
        {I_PUSHFD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71598, 236},
};

static const struct itemplate instrux_PUSHFQ[1] = {
    /*   0 : PUSHFQ void [          nw o64 9c                         ] LONG,386,X86_64 */
        /* 327 324 001(9c) : NWSIZE,LONG,PROT,X86_64 */
        {I_PUSHFQ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71603, 237},
};

static const struct itemplate instrux_POPF[1] = {
    /*   0 : POPF void [          nw osm 9d                         ] FL,8086 */
        /* 327 342 001(9d) : NWSIZE,FL,8086 */
        {I_POPF, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71608, 238},
};

static const struct itemplate instrux_POPFW[1] = {
    /*   0 : POPFW void [          nw o16 9d                         ] FL,8086 */
        /* 327 320 001(9d) : NWSIZE,FL,8086 */
        {I_POPFW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71613, 238},
};

static const struct itemplate instrux_POPFD[1] = {
    /*   0 : POPFD void [          nw o32 9d                         ] FL,386 */
        /* 327 321 001(9d) : NWSIZE,FL,386 */
        {I_POPFD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71618, 239},
};

static const struct itemplate instrux_POPFQ[1] = {
    /*   0 : POPFQ void [          nw o64 9d                         ] LONG,FL,386,X86_64 */
        /* 327 324 001(9d) : NWSIZE,LONG,FL,PROT,X86_64 */
        {I_POPFQ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71623, 240},
};

static const struct itemplate instrux_CMPSB[1] = {
    /*   0 : CMPSB void [          repe o8 a6                        ] NOAPX,FL,8086 */
        /* 335 001(a6) : NOAPX,FL,8086 */
        {I_CMPSB, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72641, 241},
};

static const struct itemplate instrux_CMPSW[1] = {
    /*   0 : CMPSW void [          repe o16 a7                       ] NOAPX,FL,8086 */
        /* 335 320 001(a7) : NOAPX,FL,8086 */
        {I_CMPSW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71628, 241},
};

static const struct itemplate instrux_CMPSD[2] = {
    /*   0 : CMPSD void [          repe o32 a7                       ] NOAPX,FL,386 */
        /* 335 321 001(a7) : NOAPX,FL,386 */
        {I_CMPSD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71633, 242},
    /*   1 : CMPSD xmmreg,xmmrm128,imm8 [rmi:      f2 0f c2 /r ib,u                  ] FL,SSE2,WILLAMETTE */
        /* 332 355 001(c2) 110 026 : FL,SSE2,WILLAMETTE */
        {I_CMPSD, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+57950, 392},
};

static const struct itemplate instrux_CMPSQ[1] = {
    /*   0 : CMPSQ void [          repe o64 a7                       ] NOAPX,LONG,FL,386,X86_64 */
        /* 335 324 001(a7) : NOAPX,LONG,FL,PROT,X86_64 */
        {I_CMPSQ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71638, 243},
};

static const struct itemplate instrux_LODSB[1] = {
    /*   0 : LODSB void [          o8 ac                             ] NOAPX,8086 */
        /* 001(ac) : NOAPX,8086 */
        {I_LODSB, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73320, 244},
};

static const struct itemplate instrux_LODSW[1] = {
    /*   0 : LODSW void [          o16 ad                            ] NOAPX,8086 */
        /* 320 001(ad) : NOAPX,8086 */
        {I_LODSW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72645, 244},
};

static const struct itemplate instrux_LODSD[1] = {
    /*   0 : LODSD void [          o32 ad                            ] NOAPX,386 */
        /* 321 001(ad) : NOAPX,386 */
        {I_LODSD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72649, 245},
};

static const struct itemplate instrux_LODSQ[1] = {
    /*   0 : LODSQ void [          o64 ad                            ] NOAPX,LONG,386,X86_64 */
        /* 324 001(ad) : NOAPX,LONG,PROT,X86_64 */
        {I_LODSQ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72653, 246},
};

static const struct itemplate instrux_MOVSB[1] = {
    /*   0 : MOVSB void [          o8 a4                             ] NOAPX,8086 */
        /* 001(a4) : NOAPX,8086 */
        {I_MOVSB, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57254, 244},
};

static const struct itemplate instrux_MOVSW[1] = {
    /*   0 : MOVSW void [          o16 a5                            ] NOAPX,8086 */
        /* 320 001(a5) : NOAPX,8086 */
        {I_MOVSW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72657, 244},
};

static const struct itemplate instrux_MOVSD[3] = {
    /*   0 : MOVSD void [          o32 a5                            ] NOAPX,386 */
        /* 321 001(a5) : NOAPX,386 */
        {I_MOVSD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72661, 245},
    /*   1 : MOVSD xmmreg,xmmrm64 [rm:       f2 0f 10 /r                       ] SSE2,WILLAMETTE */
        /* 332 355 001(10) 110 : SSE2,WILLAMETTE */
        {I_MOVSD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+69140, 250},
    /*   2 : MOVSD xmmrm64,xmmreg [mr:       f2 0f 11 /r                       ] SSE2,WILLAMETTE */
        /* 332 355 001(11) 101 : SSE2,WILLAMETTE */
        {I_MOVSD, 2, {RM_XMM|BITS64,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+69146, 250},
};

static const struct itemplate instrux_MOVSQ[1] = {
    /*   0 : MOVSQ void [          o64 a5                            ] NOAPX,LONG,386,X86_64 */
        /* 324 001(a5) : NOAPX,LONG,PROT,X86_64 */
        {I_MOVSQ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72665, 246},
};

static const struct itemplate instrux_STOSB[1] = {
    /*   0 : STOSB void [          o8 aa                             ] NOAPX,8086 */
        /* 001(aa) : NOAPX,8086 */
        {I_STOSB, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72758, 244},
};

static const struct itemplate instrux_STOSW[1] = {
    /*   0 : STOSW void [          o16 ab                            ] NOAPX,8086 */
        /* 320 001(ab) : NOAPX,8086 */
        {I_STOSW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72669, 244},
};

static const struct itemplate instrux_STOSD[1] = {
    /*   0 : STOSD void [          o32 ab                            ] NOAPX,386 */
        /* 321 001(ab) : NOAPX,386 */
        {I_STOSD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72673, 245},
};

static const struct itemplate instrux_STOSQ[1] = {
    /*   0 : STOSQ void [          o64 ab                            ] NOAPX,LONG,386,X86_64 */
        /* 324 001(ab) : NOAPX,LONG,PROT,X86_64 */
        {I_STOSQ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72677, 246},
};

static const struct itemplate instrux_SCASB[1] = {
    /*   0 : SCASB void [          repe o8 ae                        ] NOAPX,FL,8086 */
        /* 335 001(ae) : NOAPX,FL,8086 */
        {I_SCASB, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72681, 241},
};

static const struct itemplate instrux_SCASW[1] = {
    /*   0 : SCASW void [          repe o16 af                       ] NOAPX,FL,8086 */
        /* 335 320 001(af) : NOAPX,FL,8086 */
        {I_SCASW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71643, 241},
};

static const struct itemplate instrux_SCASD[1] = {
    /*   0 : SCASD void [          repe o32 af                       ] NOAPX,FL,386 */
        /* 335 321 001(af) : NOAPX,FL,386 */
        {I_SCASD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71648, 242},
};

static const struct itemplate instrux_SCASQ[1] = {
    /*   0 : SCASQ void [          repe o64 af                       ] NOAPX,LONG,FL,386,X86_64 */
        /* 335 324 001(af) : NOAPX,LONG,FL,PROT,X86_64 */
        {I_SCASQ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71653, 243},
};

static const struct itemplate instrux_INSB[1] = {
    /*   0 : INSB void [          o8 6c                             ] 186 */
        /* 001(6c) : 186 */
        {I_INSB, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73323, 247},
};

static const struct itemplate instrux_INSW[1] = {
    /*   0 : INSW void [          o16 6d                            ] 186 */
        /* 320 001(6d) : 186 */
        {I_INSW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72685, 247},
};

static const struct itemplate instrux_INSD[1] = {
    /*   0 : INSD void [          o32 6d                            ] 386 */
        /* 321 001(6d) : 386 */
        {I_INSD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72689, 3},
};

static const struct itemplate instrux_OUTSB[1] = {
    /*   0 : OUTSB void [          o8 6e                             ] 186 */
        /* 001(6e) : 186 */
        {I_OUTSB, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73326, 247},
};

static const struct itemplate instrux_OUTSW[1] = {
    /*   0 : OUTSW void [          o16 6f                            ] 186 */
        /* 320 001(6f) : 186 */
        {I_OUTSW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72693, 247},
};

static const struct itemplate instrux_OUTSD[1] = {
    /*   0 : OUTSD void [          o32 6f                            ] 386 */
        /* 321 001(6f) : 386 */
        {I_OUTSD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72697, 3},
};

static const struct itemplate instrux_LFENCE[2] = {
    /*   0 : LFENCE void [          np 0f ae e8                       ] LONG,PROT,X86_64,AMD */
        /* 360 355 002(ae e8) : LONG,PROT,X86_64,AMD */
        {I_LFENCE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67076, 248},
    /*   1 : LFENCE void [          np 0f ae e8                       ] SSE2,WILLAMETTE */
        /* 360 355 002(ae e8) : SSE2,WILLAMETTE */
        {I_LFENCE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67076, 250},
};

static const struct itemplate instrux_MFENCE[2] = {
    /*   0 : MFENCE void [          np 0f ae f0                       ] LONG,PROT,X86_64,AMD */
        /* 360 355 002(ae f0) : LONG,PROT,X86_64,AMD */
        {I_MFENCE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67082, 248},
    /*   1 : MFENCE void [          np 0f ae f0                       ] SSE2,WILLAMETTE */
        /* 360 355 002(ae f0) : SSE2,WILLAMETTE */
        {I_MFENCE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67082, 250},
};

static const struct itemplate instrux_SFENCE[2] = {
    /*   0 : SFENCE void [          np 0f ae f8                       ] LONG,PROT,X86_64,AMD */
        /* 360 355 002(ae f8) : LONG,PROT,X86_64,AMD */
        {I_SFENCE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67088, 248},
    /*   1 : SFENCE void [          np 0f ae f8                       ] KATMAI */
        /* 360 355 002(ae f8) : KATMAI */
        {I_SFENCE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67088, 378},
};

static const struct itemplate instrux_SERIALIZE[1] = {
    /*   0 : SERIALIZE void [          np 0f 01 e8                       ] SERIALIZE,FUTURE */
        /* 360 355 002(01 e8) : SERIALIZE,FUTURE */
        {I_SERIALIZE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67094, 249},
};

static const struct itemplate instrux_CLFLUSH[1] = {
    /*   0 : CLFLUSH mem [m:        np 0f ae /7                       ] SSE2,WILLAMETTE */
        /* 360 355 001(ae) 207 : SSE2,WILLAMETTE */
        {I_CLFLUSH, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67100, 250},
};

static const struct itemplate instrux_CLFLUSHOPT[1] = {
    /*   0 : CLFLUSHOPT mem [m:        66 0f ae /7                       ] CLFLUSHOPT,FUTURE */
        /* 361 355 001(ae) 207 : CLFLUSHOPT,FUTURE */
        {I_CLFLUSHOPT, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67106, 251},
};

static const struct itemplate instrux_CLWB[1] = {
    /*   0 : CLWB mem [m:        66 0f ae /6                       ] CLWB,FUTURE */
        /* 361 355 001(ae) 206 : CLWB,FUTURE */
        {I_CLWB, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67112, 252},
};

static const struct itemplate instrux_PCOMMIT[1] = {
    /*   0 : PCOMMIT void [          66 0f ae f8                       ] OBSOLETE,NEVER,NOP,FUTURE */
        /* 361 355 002(ae f8) : OBSOLETE,NEVER,NOP,FUTURE */
        {I_PCOMMIT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67118, 253},
};

static const struct itemplate instrux_CLZERO[4] = {
    /*   0 : CLZERO reg_ax [-:        a16 0f 01 fc                      ] NOLONG,CLZERO,FUTURE,AMD */
        /* 310 355 002(01 fc) : NOREX,NOAPX,NOLONG,CLZERO,FUTURE,AMD */
        {I_CLZERO, 1, {REG_AX|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67124, 254},
    /*   1 : CLZERO reg_eax [-:        a32 0f 01 fc                      ] CLZERO,FUTURE,AMD */
        /* 311 355 002(01 fc) : CLZERO,FUTURE,AMD */
        {I_CLZERO, 1, {REG_EAX,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67130, 255},
    /*   2 : CLZERO reg_rax [-:        a64 0f 01 fc                      ] LONG,PROT,CLZERO,X86_64,AMD */
        /* 313 355 002(01 fc) : LONG,PROT,CLZERO,X86_64,AMD */
        {I_CLZERO, 1, {REG_RAX,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67136, 256},
    /*   3 : CLZERO void [          0f 01 fc                          ] ND,CLZERO,FUTURE,AMD */
        /* 355 002(01 fc) : CLZERO,FUTURE,AMD */
        {I_CLZERO, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67137, 255},
};

static const struct itemplate instrux_INVD[1] = {
    /*   0 : INVD void [          0f 08                             ] PRIV,486 */
        /* 355 001(08) : PRIV,486 */
        {I_INVD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72701, 257},
};

static const struct itemplate instrux_WBINVD[1] = {
    /*   0 : WBINVD void [          np 0f 09                          ] PRIV,486 */
        /* 360 355 001(09) : PRIV,486 */
        {I_WBINVD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71658, 257},
};

static const struct itemplate instrux_WBNOINVD[1] = {
    /*   0 : WBNOINVD void [          f3 0f 09                          ] PRIV,WBNOINVD,FUTURE */
        /* 333 355 001(09) : PRIV,WBNOINVD,FUTURE */
        {I_WBNOINVD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71663, 258},
};

static const struct itemplate instrux_INVPCID[3] = {
    /*   0 : INVPCID reg32,mem128 [rm:       66 0f38 82 /r                     ] NOREX,NOAPX,NOLONG,PRIV,INVPCID,FUTURE */
        /* 361 356 001(82) 110 : NOREX,NOAPX,NOLONG,PRIV,INVPCID,FUTURE */
        {I_INVPCID, 2, {REG_GPR|BITS32|RN_L16,MEMORY|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67142, 259},
    /*   1 : INVPCID reg64,mem128 [rm:       66 0f38 82 /r                     ] LONG,PRIV,PROT,INVPCID,X86_64 */
        /* 361 356 001(82) 110 : NOAPX,LONG,PRIV,PROT,INVPCID,X86_64 */
        {I_INVPCID, 2, {REG_GPR|BITS64|RN_L16,MEMORY|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67142, 260},
    /*   2 : INVPCID reg64,mem128 [rm:       evex.nf0.nd0.l0.f3.m4.w1 f2 /r    ] LONG,PRIV,PROT,APX,INVPCID,X86_64 */
        /* 250(f4 fe 08) 300 001(f2) 110 : LONG,EVEX,PRIV,PROT,APX,INVPCID,X86_64 */
        {I_INVPCID, 2, {REG_GPR|BITS64,MEMORY|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+24732, 261},
};

static const struct itemplate instrux_INVLPG[1] = {
    /*   0 : INVLPG mem [m:        0f 01 /7                          ] PRIV,486 */
        /* 355 001(01) 207 : PRIV,486 */
        {I_INVLPG, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71668, 257},
};

static const struct itemplate instrux_INVLPGA[4] = {
    /*   0 : INVLPGA reg_ax,reg_ecx [--:       a16 0f 01 df                      ] NOLONG,X86_64,AMD */
        /* 310 355 002(01 df) : NOREX,NOAPX,NOLONG,X86_64,AMD */
        {I_INVLPGA, 2, {REG_AX|RN_L16,REG_ECX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67148, 262},
    /*   1 : INVLPGA reg_eax,reg_ecx [--:       a32 0f 01 df                      ] X86_64,AMD */
        /* 311 355 002(01 df) : X86_64,AMD */
        {I_INVLPGA, 2, {REG_EAX,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67154, 263},
    /*   2 : INVLPGA reg_rax,reg_ecx [--:       a64 0f 01 df                      ] LONG,PROT,X86_64,AMD */
        /* 313 355 002(01 df) : LONG,PROT,X86_64,AMD */
        {I_INVLPGA, 2, {REG_RAX,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67160, 248},
    /*   3 : INVLPGA void [          adf 0f 01 df                      ] ND,X86_64,AMD */
        /* 312 355 002(01 df) : X86_64,AMD */
        {I_INVLPGA, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67166, 263},
};

static const struct itemplate instrux_RDPMC[1] = {
    /*   0 : RDPMC void [          0f 33                             ] NOAPX,P6 */
        /* 355 001(33) : NOAPX,P6 */
        {I_RDPMC, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72705, 229},
};

static const struct itemplate instrux_RDTSC[1] = {
    /*   0 : RDTSC void [          0f 31                             ] NOAPX,PENT */
        /* 355 001(31) : NOAPX,PENT */
        {I_RDTSC, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72709, 264},
};

static const struct itemplate instrux_RDTSCP[1] = {
    /*   0 : RDTSCP void [          0f 01 f9                          ] X86_64 */
        /* 355 002(01 f9) : X86_64 */
        {I_RDTSCP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71673, 265},
};

static const struct itemplate instrux_RDRAND[3] = {
    /*   0 : RDRAND reg16 [m:        o16 0f c7 /6                      ] FL,RDRAND,FUTURE */
        /* 320 355 001(c7) 206 : FL,RDRAND,FUTURE */
        {I_RDRAND, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67172, 266},
    /*   1 : RDRAND reg32 [m:        o32 0f c7 /6                      ] FL,RDRAND,FUTURE */
        /* 321 355 001(c7) 206 : FL,RDRAND,FUTURE */
        {I_RDRAND, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67178, 266},
    /*   2 : RDRAND reg64 [m:        o64 0f c7 /6                      ] LONG,FL,PROT,RDRAND,X86_64 */
        /* 324 355 001(c7) 206 : LONG,FL,PROT,RDRAND,X86_64 */
        {I_RDRAND, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67184, 267},
};

static const struct itemplate instrux_RDSEED[3] = {
    /*   0 : RDSEED reg16 [m:        o16 0f c7 /7                      ] FL,RDSEED,FUTURE */
        /* 320 355 001(c7) 207 : FL,RDSEED,FUTURE */
        {I_RDSEED, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67190, 268},
    /*   1 : RDSEED reg32 [m:        o32 0f c7 /7                      ] FL,RDSEED,FUTURE */
        /* 321 355 001(c7) 207 : FL,RDSEED,FUTURE */
        {I_RDSEED, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+51183, 268},
    /*   2 : RDSEED reg64 [m:        o64 0f c7 /7                      ] LONG,FL,PROT,RDSEED,X86_64 */
        /* 324 355 001(c7) 207 : LONG,FL,PROT,RDSEED,X86_64 */
        {I_RDSEED, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+51191, 269},
};

static const struct itemplate instrux_RDPID[3] = {
    /*   0 : RDPID reg64 [m:        f3 0f c7 /7                       ] ND,OPT,LONG,PROT,RDPID,X86_64 */
        /* 333 355 001(c7) 207 : OPT,LONG,PROT,RDPID,X86_64 */
        {I_RDPID, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67196, 270},
    /*   1 : RDPID reg32 [m:        f3 !osp o32 0f c7 /7              ] RDPID,FUTURE */
        /* 333 364 321 355 001(c7) 207 : RDPID,FUTURE */
        {I_RDPID, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+51181, 271},
    /*   2 : RDPID reg64 [m:        f3 !osp o64 0f c7 /7              ] LONG,PROT,RDPID,X86_64 */
        /* 333 364 324 355 001(c7) 207 : LONG,PROT,RDPID,X86_64 */
        {I_RDPID, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+51189, 272},
};

static const struct itemplate instrux_CLTS[1] = {
    /*   0 : CLTS void [          0f 06                             ] PRIV,286 */
        /* 355 001(06) : PRIV,286 */
        {I_CLTS, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72713, 273},
};

static const struct itemplate instrux_CPUID[1] = {
    /*   0 : CPUID void [          0f a2                             ] PENT */
        /* 355 001(a2) : PENT */
        {I_CPUID, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72717, 274},
};

static const struct itemplate instrux_LMSW[1] = {
    /*   0 : LMSW rm16 [m:        0f 01 /6                          ] PRIV,286 */
        /* 355 001(01) 206 : PRIV,286 */
        {I_LMSW, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71678, 273},
};

static const struct itemplate instrux_SMSW[5] = {
    /*   0 : SMSW rm16 [m:        0f 01 /4                          ] 286 */
        /* 355 001(01) 204 : 286 */
        {I_SMSW, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67221, 275},
    /*   1 : SMSW reg64 [m:        o64nw 0f 01 /4                    ] ND,LONG,PROT,X86_64 */
        /* 323 355 001(01) 204 : NWSIZE,LONG,PROT,X86_64 */
        {I_SMSW, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67202, 237},
    /*   2 : SMSW reg16 [m:        o16 0f 01 /4                      ] 286 */
        /* 320 355 001(01) 204 : 286 */
        {I_SMSW, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67208, 275},
    /*   3 : SMSW reg32 [m:        o32 0f 01 /4                      ] 386 */
        /* 321 355 001(01) 204 : 386 */
        {I_SMSW, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67214, 3},
    /*   4 : SMSW reg64 [m:        o64 0f 01 /4                      ] LONG,PROT,X86_64 */
        /* 324 355 001(01) 204 : LONG,PROT,X86_64 */
        {I_SMSW, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67220, 24},
};

static const struct itemplate instrux_WRMSR[1] = {
    /*   0 : WRMSR void [          0f 30                             ] NOAPX,PRIV,PENT */
        /* 355 001(30) : NOAPX,PRIV,PENT */
        {I_WRMSR, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72721, 279},
};

static const struct itemplate instrux_RDMSR[3] = {
    /*   0 : RDMSR void [          0f 32                             ] NOAPX,PRIV,PENT */
        /* 355 001(32) : NOAPX,PRIV,PENT */
        {I_RDMSR, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72725, 279},
    /*   1 : RDMSR reg64,imm32 [mi:       vex.128.f2.m7.w0 f6 /0 id        ] LONG,PRIV,PROT,APX,MSR_IMM,X86_64,FUTURE */
        /* 270(007 003) 001(f6) 200 041 : NOAPX,LONG,VEX,PRIV,PROT,APX,MSR_IMM,FUTURE */
        {I_RDMSR, 2, {REG_GPR|BITS64|RN_L16,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+51197, 280},
    /*   2 : RDMSR reg64,imm32 [mi:       evex.128.f2.m7.w0 f6 /0 id        ] LONG,PRIV,PROT,APX,MSR_IMM,X86_64,FUTURE,APX */
        /* 250(f7 7f 08) 300 001(f6) 200 041 : LONG,EVEX,PRIV,PROT,APX,MSR_IMM,FUTURE */
        {I_RDMSR, 2, {REG_GPR|BITS64,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+13023, 281},
};

static const struct itemplate instrux_WRMSRNS[3] = {
    /*   0 : WRMSRNS void [          np 0f 01 c6                       ] PRIV,WRMSRNS,FUTURE */
        /* 360 355 002(01 c6) : PRIV,WRMSRNS,FUTURE */
        {I_WRMSRNS, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67262, 282},
    /*   1 : WRMSRNS imm32,reg64 [im:       vex.128.f3.m7.w0 f6 /0 id        ] LONG,PRIV,PROT,APX,MSR_IMM,X86_64,FUTURE */
        /* 270(007 002) 001(f6) 210 040 : NOAPX,LONG,VEX,PRIV,PROT,APX,MSR_IMM,FUTURE */
        {I_WRMSRNS, 2, {IMM_NORMAL|BITS32,REG_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+51205, 280},
    /*   2 : WRMSRNS imm32,reg64 [im:       evex.128.f3.m7.w0 f6 /0 id        ] LONG,PRIV,PROT,APX,MSR_IMM,X86_64,FUTURE,APX */
        /* 250(f7 7e 08) 300 001(f6) 210 040 : LONG,EVEX,PRIV,PROT,APX,MSR_IMM,FUTURE */
        {I_WRMSRNS, 2, {IMM_NORMAL|BITS32,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+13033, 281},
};

static const struct itemplate instrux_RDMSRLIST[1] = {
    /*   0 : RDMSRLIST void [          f2 0f 01 c6                       ] LONG,PRIV,PROT,MSRLIST,X86_64 */
        /* 332 355 002(01 c6) : LONG,PRIV,PROT,MSRLIST,X86_64 */
        {I_RDMSRLIST, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67268, 283},
};

static const struct itemplate instrux_WRMSRLIST[1] = {
    /*   0 : WRMSRLIST void [          f3 0f 01 c6                       ] LONG,PRIV,PROT,MSRLIST,X86_64 */
        /* 333 355 002(01 c6) : LONG,PRIV,PROT,MSRLIST,X86_64 */
        {I_WRMSRLIST, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67274, 283},
};

static const struct itemplate instrux_URDMSR[4] = {
    /*   0 : URDMSR reg64,reg64 [mr:       f2 0f 38 f8 /r                    ] NOAPX,FUTURE */
        /* 332 355 002(38 f8) 101 : NOAPX,FUTURE */
        {I_URDMSR, 2, {REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56886, 284},
    /*   1 : URDMSR reg64,reg64 [mr:       evex.nf0.nd0.l0.f2.m4.w0 f8 /r    ] LONG,PROT,APX,X86_64,FUTURE */
        /* 250(f4 7f 08) 300 001(f8) 101 : LONG,EVEX,PROT,APX,FUTURE */
        {I_URDMSR, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+24741, 285},
    /*   2 : URDMSR reg64,imm32 [mi:       vex.128.f2.m7.w0 f8 /0 id        ] FUTURE */
        /* 270(007 003) 001(f8) 200 041 : NOAPX,VEX,FUTURE */
        {I_URDMSR, 2, {REG_GPR|BITS64|RN_L16,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+51213, 286},
    /*   3 : URDMSR reg64,imm32 [mi:       evex.128.f2.m7.w0 f8 /0 id        ] FUTURE,APX */
        /* 250(f7 7f 08) 300 001(f8) 200 041 : LONG,EVEX,PROT,APX,FUTURE */
        {I_URDMSR, 2, {REG_GPR|BITS64,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+13043, 285},
};

static const struct itemplate instrux_UWRMSR[4] = {
    /*   0 : UWRMSR reg64,reg64 [mr:       f3 0f 38 f8 /r                    ] NOAPX,FUTURE */
        /* 333 355 002(38 f8) 101 : NOAPX,FUTURE */
        {I_UWRMSR, 2, {REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56893, 284},
    /*   1 : UWRMSR reg64,reg64 [mr:       evex.nf0.nd0.l0.f3.m4.w0 f8 /r    ] LONG,PROT,APX,X86_64,FUTURE */
        /* 250(f4 7e 08) 300 001(f8) 101 : LONG,EVEX,PROT,APX,FUTURE */
        {I_UWRMSR, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+24750, 285},
    /*   2 : UWRMSR reg64,imm32 [mi:       vex.128.f3.m7.w0 f8 /0 id        ] FUTURE */
        /* 270(007 002) 001(f8) 200 041 : NOAPX,VEX,FUTURE */
        {I_UWRMSR, 2, {REG_GPR|BITS64|RN_L16,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+51221, 286},
    /*   3 : UWRMSR reg64,imm32 [mi:       evex.128.f3.m7.w0 f8 /0 id        ] FUTURE,APX */
        /* 250(f7 7e 08) 300 001(f8) 200 041 : LONG,EVEX,PROT,APX,FUTURE */
        {I_UWRMSR, 2, {REG_GPR|BITS64,IMM_NORMAL|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+13053, 285},
};

static const struct itemplate instrux_UMOV[6] = {
    /*   0 : UMOV rm8,reg8 [mr:       np o8 0f 10 /r                    ] ND,SM0-1,NOREX,NOAPX,NOLONG,UNDOC,OBSOLETE,386 */
        /* 360 355 001(10) 101 : SM0,SM1,NOREX,NOAPX,NOLONG,UNDOC,OBSOLETE,386 */
        {I_UMOV, 2, {RM_GPR|BITS8|RN_L16,REG_GPR|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67280, 287},
    /*   1 : UMOV rm16,reg16 [mr:       np o16 0f 11 /r                   ] ND,SM0-1,NOREX,NOAPX,NOLONG,UNDOC,OBSOLETE,386 */
        /* 360 320 355 001(11) 101 : SM0,SM1,NOREX,NOAPX,NOLONG,UNDOC,OBSOLETE,386 */
        {I_UMOV, 2, {RM_GPR|BITS16|RN_L16,REG_GPR|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56900, 287},
    /*   2 : UMOV rm32,reg32 [mr:       np o32 0f 11 /r                   ] ND,SM0-1,NOREX,NOAPX,NOLONG,UNDOC,OBSOLETE,386 */
        /* 360 321 355 001(11) 101 : SM0,SM1,NOREX,NOAPX,NOLONG,UNDOC,OBSOLETE,386 */
        {I_UMOV, 2, {RM_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56907, 287},
    /*   3 : UMOV reg8,rm8 [rm:       np o8 0f 12 /r                    ] ND,SM0-1,NOREX,NOAPX,NOLONG,UNDOC,OBSOLETE,386 */
        /* 360 355 001(12) 110 : SM0,SM1,NOREX,NOAPX,NOLONG,UNDOC,OBSOLETE,386 */
        {I_UMOV, 2, {REG_GPR|BITS8|RN_L16,RM_GPR|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67286, 287},
    /*   4 : UMOV reg16,rm16 [rm:       np o16 0f 13 /r                   ] ND,SM0-1,NOREX,NOAPX,NOLONG,UNDOC,OBSOLETE,386 */
        /* 360 320 355 001(13) 110 : SM0,SM1,NOREX,NOAPX,NOLONG,UNDOC,OBSOLETE,386 */
        {I_UMOV, 2, {REG_GPR|BITS16|RN_L16,RM_GPR|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56914, 287},
    /*   5 : UMOV reg32,rm32 [rm:       np o32 0f 13 /r                   ] ND,SM0-1,NOREX,NOAPX,NOLONG,UNDOC,OBSOLETE,386 */
        /* 360 321 355 001(13) 110 : SM0,SM1,NOREX,NOAPX,NOLONG,UNDOC,OBSOLETE,386 */
        {I_UMOV, 2, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+56921, 287},
};

static const struct itemplate instrux_BB0_RESET[1] = {
    /*   0 : BB0_RESET void [          m1 3a                             ] ND,NOREX,NOAPX,NOLONG,OBSOLETE,PENT,CYRIX */
        /* 355 001(3a) : NOREX,NOAPX,NOLONG,OBSOLETE,PENT,CYRIX */
        {I_BB0_RESET, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72729, 288},
};

static const struct itemplate instrux_BB1_RESET[1] = {
    /*   0 : BB1_RESET void [          m1 3b                             ] ND,NOREX,NOAPX,NOLONG,OBSOLETE,PENT,CYRIX */
        /* 355 001(3b) : NOREX,NOAPX,NOLONG,OBSOLETE,PENT,CYRIX */
        {I_BB1_RESET, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72733, 288},
};

static const struct itemplate instrux_CPU_READ[1] = {
    /*   0 : CPU_READ void [          m1 3d                             ] ND,NOREX,NOAPX,NOLONG,OBSOLETE,PENT,CYRIX */
        /* 355 001(3d) : NOREX,NOAPX,NOLONG,OBSOLETE,PENT,CYRIX */
        {I_CPU_READ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72737, 288},
};

static const struct itemplate instrux_CPU_WRITE[1] = {
    /*   0 : CPU_WRITE void [          m1 3c                             ] ND,NOREX,NOAPX,NOLONG,OBSOLETE,PENT,CYRIX */
        /* 355 001(3c) : NOREX,NOAPX,NOLONG,OBSOLETE,PENT,CYRIX */
        {I_CPU_WRITE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72741, 288},
};

static const struct itemplate instrux_DMINT[1] = {
    /*   0 : DMINT void [          m1 39                             ] ND,NOREX,NOAPX,NOLONG,OBSOLETE,P6,CYRIX */
        /* 355 001(39) : NOREX,NOAPX,NOLONG,OBSOLETE,P6,CYRIX */
        {I_DMINT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72745, 289},
};

static const struct itemplate instrux_RDM[1] = {
    /*   0 : RDM void [          0f 3a                             ] ND,NOREX,NOAPX,NOLONG,OBSOLETE,P6,CYRIX */
        /* 355 001(3a) : NOREX,NOAPX,NOLONG,OBSOLETE,P6,CYRIX */
        {I_RDM, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72729, 289},
};

static const struct itemplate instrux_SMINT[1] = {
    /*   0 : SMINT void [          m1 38                             ] ND,NOREX,NOAPX,NOLONG,OBSOLETE,P6,CYRIX */
        /* 355 001(38) : NOREX,NOAPX,NOLONG,OBSOLETE,P6,CYRIX */
        {I_SMINT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72749, 289},
};

static const struct itemplate instrux_SMINTOLD[1] = {
    /*   0 : SMINTOLD void [          m1 7e                             ] ND,NOREX,NOAPX,NOLONG,OBSOLETE,486,CYRIX */
        /* 355 001(7e) : NOREX,NOAPX,NOLONG,OBSOLETE,486,CYRIX */
        {I_SMINTOLD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72753, 290},
};

static const struct itemplate instrux_RSM[1] = {
    /*   0 : RSM void [          0f aa                             ] FL,SMM,PENT */
        /* 355 001(aa) : FL,SMM,PENT */
        {I_RSM, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72757, 291},
};

static const struct itemplate instrux_WRSHR[1] = {
    /*   0 : WRSHR rm32 [m:        o32 0f 37 /0                      ] ND,NOREX,NOAPX,NOLONG,SMM,OBSOLETE,P6,CYRIX */
        /* 321 355 001(37) 200 : NOREX,NOAPX,NOLONG,SMM,OBSOLETE,P6,CYRIX */
        {I_WRSHR, 1, {RM_GPR|BITS32|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67292, 292},
};

static const struct itemplate instrux_RDSHR[1] = {
    /*   0 : RDSHR rm32 [m:        o32 0f 36 /0                      ] ND,NOREX,NOAPX,NOLONG,SMM,OBSOLETE,P6,CYRIX */
        /* 321 355 001(36) 200 : NOREX,NOAPX,NOLONG,SMM,OBSOLETE,P6,CYRIX */
        {I_RDSHR, 1, {RM_GPR|BITS32|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67298, 292},
};

static const struct itemplate instrux_RSDC[1] = {
    /*   0 : RSDC reg_sreg,mem80 [rm:       0f 79 /r                          ] ND,NOREX,NOAPX,NOLONG,SMM,OBSOLETE,486,CYRIX */
        /* 355 001(79) 110 : NOREX,NOAPX,NOLONG,SMM,OBSOLETE,486,CYRIX */
        {I_RSDC, 2, {REG_SREG|RN_L16,MEMORY|BITS80|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69519, 293},
};

static const struct itemplate instrux_RSLDT[1] = {
    /*   0 : RSLDT mem80 [m:        0f 7b /0                          ] ND,NOREX,NOAPX,NOLONG,SMM,OBSOLETE,486,CYRIX */
        /* 355 001(7b) 200 : NOREX,NOAPX,NOLONG,SMM,OBSOLETE,486,CYRIX */
        {I_RSLDT, 1, {MEMORY|BITS80|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71693, 293},
};

static const struct itemplate instrux_RSTS[1] = {
    /*   0 : RSTS mem80 [m:        0f 7d /0                          ] ND,NOREX,NOAPX,NOLONG,SMM,OBSOLETE,486,CYRIX */
        /* 355 001(7d) 200 : NOREX,NOAPX,NOLONG,SMM,OBSOLETE,486,CYRIX */
        {I_RSTS, 1, {MEMORY|BITS80|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71698, 293},
};

static const struct itemplate instrux_SVDC[1] = {
    /*   0 : SVDC mem80,reg_sreg [mr:       m1 78 /r                          ] ND,NOREX,NOAPX,NOLONG,SMM,OBSOLETE,486,CYRIX */
        /* 355 001(78) 101 : NOREX,NOAPX,NOLONG,SMM,OBSOLETE,486,CYRIX */
        {I_SVDC, 2, {MEMORY|BITS80|RN_L16,REG_SREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58015, 293},
};

static const struct itemplate instrux_SVLDT[1] = {
    /*   0 : SVLDT mem80 [m:        m1 7a /0                          ] ND,NOREX,NOAPX,NOLONG,SMM,OBSOLETE,486,CYRIX */
        /* 355 001(7a) 200 : NOREX,NOAPX,NOLONG,SMM,OBSOLETE,486,CYRIX */
        {I_SVLDT, 1, {MEMORY|BITS80|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71703, 293},
};

static const struct itemplate instrux_SVTS[1] = {
    /*   0 : SVTS mem80 [m:        m1 7c /0                          ] ND,NOREX,NOAPX,NOLONG,SMM,OBSOLETE,486,CYRIX */
        /* 355 001(7c) 200 : NOREX,NOAPX,NOLONG,SMM,OBSOLETE,486,CYRIX */
        {I_SVTS, 1, {MEMORY|BITS80|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71708, 293},
};

static const struct itemplate instrux_HLT[1] = {
    /*   0 : HLT void [          f4                                ] PRIV,8086 */
        /* 001(f4) : PRIV,8086 */
        {I_HLT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73329, 294},
};

static const struct itemplate instrux_PAUSE[1] = {
    /*   0 : PAUSE void [          osz f3i 90                        ] 8086 */
        /* 330 333 001(90) : 8086 */
        {I_PAUSE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71713, 23},
};

static const struct itemplate instrux_MONITOR[4] = {
    /*   0 : MONITOR void [          asm 0f 01 c8                      ] MONITOR,PRESCOTT */
        /* 312 355 002(01 c8) : MONITOR,PRESCOTT */
        {I_MONITOR, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67304, 295},
    /*   1 : MONITOR reg_ax,reg_ecx,reg_edx [---:      a16 0f 01 c8                      ] ND,NOLONG,MONITOR,PRESCOTT */
        /* 310 355 002(01 c8) : NOREX,NOAPX,NOLONG,MONITOR,PRESCOTT */
        {I_MONITOR, 3, {REG_AX|RN_L16,REG_ECX|RN_L16,REG_EDX|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+67310, 296},
    /*   2 : MONITOR reg_eax,reg_ecx,reg_edx [---:      a32 0f 01 c8                      ] ND,MONITOR,PRESCOTT */
        /* 311 355 002(01 c8) : MONITOR,PRESCOTT */
        {I_MONITOR, 3, {REG_EAX,REG_ECX,REG_EDX,0,0}, NO_DECORATOR, nasm_bytecodes+67316, 295},
    /*   3 : MONITOR reg_rax,reg_ecx,reg_edx [---:      a64 0f 01 c8                      ] ND,LONG,PROT,MONITOR,X86_64 */
        /* 313 355 002(01 c8) : LONG,PROT,MONITOR,X86_64 */
        {I_MONITOR, 3, {REG_RAX,REG_ECX,REG_EDX,0,0}, NO_DECORATOR, nasm_bytecodes+67322, 297},
};

static const struct itemplate instrux_MONITORW[1] = {
    /*   0 : MONITORW void [          a16 0f 01 c8                      ] NOLONG,MONITOR,PRESCOTT */
        /* 310 355 002(01 c8) : NOREX,NOAPX,NOLONG,MONITOR,PRESCOTT */
        {I_MONITORW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67310, 296},
};

static const struct itemplate instrux_MONITORD[1] = {
    /*   0 : MONITORD void [          a32 0f 01 c8                      ] MONITOR,PRESCOTT */
        /* 311 355 002(01 c8) : MONITOR,PRESCOTT */
        {I_MONITORD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67316, 295},
};

static const struct itemplate instrux_MONITORQ[1] = {
    /*   0 : MONITORQ void [          a64 0f 01 c8                      ] LONG,MONITOR,PRESCOTT,X86_64 */
        /* 313 355 002(01 c8) : LONG,PROT,MONITOR,X86_64 */
        {I_MONITORQ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67322, 297},
};

static const struct itemplate instrux_MWAIT[2] = {
    /*   0 : MWAIT void [          0f 01 c9                          ] MONITOR,PRESCOTT */
        /* 355 002(01 c9) : MONITOR,PRESCOTT */
        {I_MWAIT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71718, 295},
    /*   1 : MWAIT reg_eax,reg_ecx [--:       0f 01 c9                          ] ND,MONITOR,PRESCOTT */
        /* 355 002(01 c9) : MONITOR,PRESCOTT */
        {I_MWAIT, 2, {REG_EAX,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+71718, 295},
};

static const struct itemplate instrux_MONITORX[7] = {
    /*   0 : MONITORX void [          asm 0f 01 fa                      ] MONITORX,FUTURE,AMD */
        /* 312 355 002(01 fa) : MONITORX,FUTURE,AMD */
        {I_MONITORX, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67328, 298},
    /*   1 : MONITORX void [          a16 0f 01 fa                      ] NOLONG,MONITORX,FUTURE,AMD */
        /* 310 355 002(01 fa) : NOREX,NOAPX,NOLONG,MONITORX,FUTURE,AMD */
        {I_MONITORX, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67334, 299},
    /*   2 : MONITORX void [          a32 0f 01 fa                      ] MONITORX,FUTURE,AMD */
        /* 311 355 002(01 fa) : MONITORX,FUTURE,AMD */
        {I_MONITORX, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67340, 298},
    /*   3 : MONITORX void [          a64 0f 01 fa                      ] LONG,MONITORX,X86_64,FUTURE,AMD */
        /* 313 355 002(01 fa) : LONG,PROT,MONITORX,FUTURE,AMD */
        {I_MONITORX, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67346, 300},
    /*   4 : MONITORX reg_ax,reg_ecx,reg_edx [---:      a16 0f 01 fa                      ] ND,NOLONG,MONITORX,FUTURE,AMD */
        /* 310 355 002(01 fa) : NOREX,NOAPX,NOLONG,MONITORX,FUTURE,AMD */
        {I_MONITORX, 3, {REG_AX|RN_L16,REG_ECX|RN_L16,REG_EDX|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+67334, 299},
    /*   5 : MONITORX reg_eax,reg_ecx,reg_edx [---:      a32 0f 01 fa                      ] ND,MONITORX,FUTURE,AMD */
        /* 311 355 002(01 fa) : MONITORX,FUTURE,AMD */
        {I_MONITORX, 3, {REG_EAX,REG_ECX,REG_EDX,0,0}, NO_DECORATOR, nasm_bytecodes+67340, 298},
    /*   6 : MONITORX reg_rax,reg_ecx,reg_edx [---:      a64 0f 01 fa                      ] ND,LONG,PROT,MONITORX,X86_64,AMD */
        /* 313 355 002(01 fa) : LONG,PROT,MONITORX,X86_64,AMD */
        {I_MONITORX, 3, {REG_RAX,REG_ECX,REG_EDX,0,0}, NO_DECORATOR, nasm_bytecodes+67346, 301},
};

static const struct itemplate instrux_MWAITX[2] = {
    /*   0 : MWAITX void [          0f 01 fb                          ] MONITORX,FUTURE,AMD */
        /* 355 002(01 fb) : MONITORX,FUTURE,AMD */
        {I_MWAITX, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71723, 298},
    /*   1 : MWAITX reg_eax,reg_ecx [--:       0f 01 fb                          ] ND,MONITORX,FUTURE,AMD */
        /* 355 002(01 fb) : MONITORX,FUTURE,AMD */
        {I_MWAITX, 2, {REG_EAX,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+71723, 298},
};

static const struct itemplate instrux_TPAUSE[2] = {
    /*   0 : TPAUSE reg32 [m:        66 0f ae /6                       ] FL,WAITPKG,FUTURE */
        /* 361 355 001(ae) 206 : FL,WAITPKG,FUTURE */
        {I_TPAUSE, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67112, 302},
    /*   1 : TPAUSE reg32,reg_edx,reg_eax [m--:      66 0f ae /6                       ] ND,FL,WAITPKG,FUTURE */
        /* 361 355 001(ae) 206 : FL,WAITPKG,FUTURE */
        {I_TPAUSE, 3, {REG_GPR|BITS32,REG_EDX,REG_EAX,0,0}, NO_DECORATOR, nasm_bytecodes+67112, 302},
};

static const struct itemplate instrux_UMONITOR[3] = {
    /*   0 : UMONITOR reg16 [m:        a16 f3 0f ae /6                   ] NOLONG,WAITPKG,FUTURE */
        /* 310 333 355 001(ae) 206 : NOREX,NOAPX,NOLONG,WAITPKG,FUTURE */
        {I_UMONITOR, 1, {REG_GPR|BITS16|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56928, 303},
    /*   1 : UMONITOR reg32 [m:        a32 f3 0f ae /6                   ] WAITPKG,FUTURE */
        /* 311 333 355 001(ae) 206 : WAITPKG,FUTURE */
        {I_UMONITOR, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56935, 304},
    /*   2 : UMONITOR reg64 [m:        a64 f3 0f ae /6                   ] LONG,PROT,WAITPKG,X86_64 */
        /* 313 333 355 001(ae) 206 : LONG,PROT,WAITPKG,X86_64 */
        {I_UMONITOR, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56942, 305},
};

static const struct itemplate instrux_UMWAIT[2] = {
    /*   0 : UMWAIT reg32 [m:        f2 0f ae /6                       ] WAITPKG,FUTURE */
        /* 332 355 001(ae) 206 : WAITPKG,FUTURE */
        {I_UMWAIT, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67352, 304},
    /*   1 : UMWAIT reg32,reg_edx,reg_eax [m--:      f2 0f ae /6                       ] ND,WAITPKG,FUTURE */
        /* 332 355 001(ae) 206 : WAITPKG,FUTURE */
        {I_UMWAIT, 3, {REG_GPR|BITS32,REG_EDX,REG_EAX,0,0}, NO_DECORATOR, nasm_bytecodes+67352, 304},
};

static const struct itemplate instrux_IN[6] = {
    /*   0 : IN reg_al,imm8 [-i:       o8 e4 ib,u                        ] NOAPX,8086 */
        /* 001(e4) 025 : NOAPX,8086 */
        {I_IN, 2, {REG_AL|RN_L16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+72761, 244},
    /*   1 : IN reg_ax,imm8 [-i:       o16 e5 ib,u                       ] NOAPX,8086 */
        /* 320 001(e5) 025 : NOAPX,8086 */
        {I_IN, 2, {REG_AX|RN_L16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+71728, 244},
    /*   2 : IN reg_eax,imm8 [-i:       o32 e5 ib,u                       ] NOAPX,ZU,386 */
        /* 321 001(e5) 025 : NOAPX,ZU,386 */
        {I_IN, 2, {REG_EAX|RN_L16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+71733, 306},
    /*   3 : IN reg_al,reg_dx [--:       o8 ec                             ] NOAPX,8086 */
        /* 001(ec) : NOAPX,8086 */
        {I_IN, 2, {REG_AL|RN_L16,REG_DX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+70031, 244},
    /*   4 : IN reg_ax,reg_dx [--:       o16 ed                            ] NOAPX,8086 */
        /* 320 001(ed) : NOAPX,8086 */
        {I_IN, 2, {REG_AX|RN_L16,REG_DX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+72765, 244},
    /*   5 : IN reg_eax,reg_dx [--:       o32 ed                            ] NOAPX,ZU,386 */
        /* 321 001(ed) : NOAPX,ZU,386 */
        {I_IN, 2, {REG_EAX|RN_L16,REG_DX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+72769, 306},
};

static const struct itemplate instrux_OUT[6] = {
    /*   0 : OUT imm8,reg_al [i-:       o8 e6 ib,u                        ] NOAPX,8086 */
        /* 001(e6) 024 : NOAPX,8086 */
        {I_OUT, 2, {IMM_NORMAL|BITS8,REG_AL|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+72773, 244},
    /*   1 : OUT imm8,reg_ax [i-:       o16 e7 ib,u                       ] NOAPX,8086 */
        /* 320 001(e7) 024 : NOAPX,8086 */
        {I_OUT, 2, {IMM_NORMAL|BITS8,REG_AX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+71738, 244},
    /*   2 : OUT imm8,reg_eax [i-:       o32 e7 ib,u                       ] NOAPX,386 */
        /* 321 001(e7) 024 : NOAPX,386 */
        {I_OUT, 2, {IMM_NORMAL|BITS8,REG_EAX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+71743, 245},
    /*   3 : OUT reg_dx,reg_al [--:       o8 ee                             ] NOAPX,8086 */
        /* 001(ee) : NOAPX,8086 */
        {I_OUT, 2, {REG_DX|RN_L16,REG_AL|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+70013, 244},
    /*   4 : OUT reg_dx,reg_ax [--:       o16 ef                            ] NOAPX,8086 */
        /* 320 001(ef) : NOAPX,8086 */
        {I_OUT, 2, {REG_DX|RN_L16,REG_AX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+72777, 244},
    /*   5 : OUT reg_dx,reg_eax [--:       o32 ef                            ] NOAPX,386 */
        /* 321 001(ef) : NOAPX,386 */
        {I_OUT, 2, {REG_DX|RN_L16,REG_EAX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+72781, 245},
};

static const struct itemplate instrux_LDS[2] = {
    /*   0 : LDS reg16,mem16 [rm:       o16 c5 /r                         ] NOREX,NOAPX,NOLONG,8086 */
        /* 320 001(c5) 110 : NOREX,NOAPX,NOLONG,8086 */
        {I_LDS, 2, {REG_GPR|BITS16|RN_L16,MEMORY|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+71753, 227},
    /*   1 : LDS reg32,mem32 [rm:       o32 c5 /r                         ] NOREX,NOAPX,NOLONG,386 */
        /* 321 001(c5) 110 : NOREX,NOAPX,NOLONG,386 */
        {I_LDS, 2, {REG_GPR|BITS32|RN_L16,MEMORY|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+71758, 307},
};

static const struct itemplate instrux_LES[2] = {
    /*   0 : LES reg16,mem16 [rm:       o16 c4 /r                         ] NOREX,NOAPX,NOLONG,8086 */
        /* 320 001(c4) 110 : NOREX,NOAPX,NOLONG,8086 */
        {I_LES, 2, {REG_GPR|BITS16|RN_L16,MEMORY|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+71763, 227},
    /*   1 : LES reg32,mem32 [rm:       o32 c4 /r                         ] NOREX,NOAPX,NOLONG,386 */
        /* 321 001(c4) 110 : NOREX,NOAPX,NOLONG,386 */
        {I_LES, 2, {REG_GPR|BITS32|RN_L16,MEMORY|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+71768, 307},
};

static const struct itemplate instrux_LFS[3] = {
    /*   0 : LFS reg16,mem16 [rm:       o16 0f b4 /r                      ] SM0-1,386 */
        /* 320 355 001(b4) 110 : SM0,SM1,386 */
        {I_LFS, 2, {REG_GPR|BITS16,MEMORY|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67388, 13},
    /*   1 : LFS reg32,mem32 [rm:       o32 0f b4 /r                      ] SM0-1,386 */
        /* 321 355 001(b4) 110 : SM0,SM1,386 */
        {I_LFS, 2, {REG_GPR|BITS32,MEMORY|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+67394, 13},
    /*   2 : LFS reg64,mem64 [rm:       o64 0f b4 /r                      ] SM0-1,LONG,PROT,X86_64 */
        /* 324 355 001(b4) 110 : SM0,SM1,LONG,PROT,X86_64 */
        {I_LFS, 2, {REG_GPR|BITS64,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+67400, 14},
};

static const struct itemplate instrux_LGS[3] = {
    /*   0 : LGS reg16,mem16 [rm:       o16 0f b5 /r                      ] SM0-1,386 */
        /* 320 355 001(b5) 110 : SM0,SM1,386 */
        {I_LGS, 2, {REG_GPR|BITS16,MEMORY|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67406, 13},
    /*   1 : LGS reg32,mem32 [rm:       o32 0f b5 /r                      ] SM0-1,386 */
        /* 321 355 001(b5) 110 : SM0,SM1,386 */
        {I_LGS, 2, {REG_GPR|BITS32,MEMORY|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+67412, 13},
    /*   2 : LGS reg64,mem64 [rm:       o64 0f b5 /r                      ] SM0-1,LONG,PROT,X86_64 */
        /* 324 355 001(b5) 110 : SM0,SM1,LONG,PROT,X86_64 */
        {I_LGS, 2, {REG_GPR|BITS64,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+67418, 14},
};

static const struct itemplate instrux_LSS[3] = {
    /*   0 : LSS reg16,mem16 [rm:       o16 0f b2 /r                      ] SM0-1,386 */
        /* 320 355 001(b2) 110 : SM0,SM1,386 */
        {I_LSS, 2, {REG_GPR|BITS16,MEMORY|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67424, 13},
    /*   1 : LSS reg32,mem32 [rm:       o32 0f b2 /r                      ] SM0-1,386 */
        /* 321 355 001(b2) 110 : SM0,SM1,386 */
        {I_LSS, 2, {REG_GPR|BITS32,MEMORY|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+67430, 13},
    /*   2 : LSS reg64,mem64 [rm:       o64 0f b2 /r                      ] SM0-1,LONG,PROT,X86_64 */
        /* 324 355 001(b2) 110 : SM0,SM1,LONG,PROT,X86_64 */
        {I_LSS, 2, {REG_GPR|BITS64,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+67436, 14},
};

static const struct itemplate instrux_PUSH[21] = {
    /*   0 : PUSH reg_es [-:        06                                ] NOREX,NOAPX,NOLONG,8086 */
        /* 001(06) : NOREX,NOAPX,NOLONG,8086 */
        {I_PUSH, 1, {REG_ES|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72714, 227},
    /*   1 : PUSH reg_cs [-:        0e                                ] NOREX,NOAPX,NOLONG,8086 */
        /* 001(0e) : NOREX,NOAPX,NOLONG,8086 */
        {I_PUSH, 1, {REG_CS|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72922, 227},
    /*   2 : PUSH reg_ss [-:        16                                ] NOREX,NOAPX,NOLONG,8086 */
        /* 001(16) : NOREX,NOAPX,NOLONG,8086 */
        {I_PUSH, 1, {REG_SS|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+29301, 227},
    /*   3 : PUSH reg_ds [-:        1e                                ] NOREX,NOAPX,NOLONG,8086 */
        /* 001(1e) : NOREX,NOAPX,NOLONG,8086 */
        {I_PUSH, 1, {REG_DS|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+29445, 227},
    /*   4 : PUSH reg_fs [-:        0f a0                             ] 386 */
        /* 355 001(a0) : 386 */
        {I_PUSH, 1, {REG_FS,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72785, 3},
    /*   5 : PUSH reg_gs [-:        0f a8                             ] 386 */
        /* 355 001(a8) : 386 */
        {I_PUSH, 1, {REG_GS,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72789, 3},
    /*   6 : PUSH reg16 [r:        nw o16 50+r                       ] 8086 */
        /* 327 320 010 120 : NWSIZE,8086 */
        {I_PUSH, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72158, 235},
    /*   7 : PUSH reg32 [r:        nw o32 50+r                       ] 386 */
        /* 327 321 010 120 : NWSIZE,386 */
        {I_PUSH, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72163, 236},
    /*   8 : PUSH reg64 [r:        nw o64 50+r                       ] LONG,PROT,X86_64 */
        /* 327 324 010 120 : NWSIZE,LONG,PROT,X86_64 */
        {I_PUSH, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72168, 237},
    /*   9 : PUSH rm16 [m:        nw o16 ff /6                      ] AR0,OSIZE,8086 */
        /* 327 320 001(ff) 206 : AR0,NWSIZE,OSIZE,8086 */
        {I_PUSH, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67766, 340},
    /*  10 : PUSH rm32 [m:        nw o32 ff /6                      ] AR0,OSIZE,386 */
        /* 327 321 001(ff) 206 : AR0,NWSIZE,OSIZE,386 */
        {I_PUSH, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67772, 203},
    /*  11 : PUSH rm64 [m:        nw o64 ff /6                      ] AR0,OSIZE,LONG,PROT,X86_64 */
        /* 327 324 001(ff) 206 : AR0,NWSIZE,OSIZE,LONG,PROT,X86_64 */
        {I_PUSH, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67778, 204},
    /*  12 : PUSH imm8 [i:        nw osz 6a ib,s                    ] ND,AR0,SX,186 */
        /* 327 330 001(6a) 274 : AR0,NWSIZE,SX,186 */
        {I_PUSH, 1, {IMM_NORMAL|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67784, 341},
    /*  13 : PUSH sbyteword16 [i:        nw o16 6a ib,s                    ] AR0,OSIZE,186 */
        /* 327 320 001(6a) 274 : AR0,NWSIZE,OSIZE,186 */
        {I_PUSH, 1, {SBYTEWORD|BITS16|IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67790, 342},
    /*  14 : PUSH sbytedword32 [i:        nw o32 6a ib,s                    ] AR0,OSIZE,386 */
        /* 327 321 001(6a) 274 : AR0,NWSIZE,OSIZE,386 */
        {I_PUSH, 1, {SBYTEDWORD|BITS32|IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67796, 203},
    /*  15 : PUSH sbytedword64 [i:        nw o64 6a ib,s                    ] AR0,OSIZE,LONG,386,X86_64 */
        /* 327 324 001(6a) 274 : AR0,NWSIZE,OSIZE,LONG,PROT,X86_64 */
        {I_PUSH, 1, {SBYTEDWORD|BITS64|IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67802, 204},
    /*  16 : PUSH imm16 [i:        nw o16 68 iw                      ] AR0,OSIZE,186 */
        /* 327 320 001(68) 030 : AR0,NWSIZE,OSIZE,186 */
        {I_PUSH, 1, {IMM_NORMAL|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67808, 342},
    /*  17 : PUSH imm32 [i:        nw o32 68 id                      ] AR0,OSIZE,386 */
        /* 327 321 001(68) 040 : AR0,NWSIZE,OSIZE,386 */
        {I_PUSH, 1, {IMM_NORMAL|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67814, 203},
    /*  18 : PUSH sdword64 [i:        nw o64 68 id,s                    ] AR0,OSIZE,LONG,386,X86_64 */
        /* 327 324 001(68) 254 : AR0,NWSIZE,OSIZE,LONG,PROT,X86_64 */
        {I_PUSH, 1, {SDWORD|BITS64|IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67820, 204},
    /*  19 : PUSH reg64,reg64 [vm:       o64nw evex.nd1.l0.np.m4.w0 ff /6  ] ND,LONG,PROT,APX,X86_64 */
        /* 323 240(f4 7c 18) 300 001(ff) 216 : NWSIZE,LONG,EVEX,PROT,APX,X86_64 */
        {I_PUSH, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+13063, 346},
    /*  20 : PUSH reg64:reg64 [vm:       o64nw evex.nd1.l0.np.m4.w0 ff /6  ] ND,LONG,PROT,APX,X86_64 */
        /* 323 240(f4 7c 18) 300 001(ff) 216 : NWSIZE,LONG,EVEX,PROT,APX,X86_64 */
        {I_PUSH, 2, {REG_GPR|BITS64|COLON,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+13063, 346},
};

static const struct itemplate instrux_POP[14] = {
    /*   0 : POP reg_es [-:        07                                ] NOREX,NOAPX,NOLONG,8086 */
        /* 001(07) : NOREX,NOAPX,NOLONG,8086 */
        {I_POP, 1, {REG_ES|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72622, 227},
    /*   1 : POP reg_cs [-:        m0 0f                             ] ND,NOREX,NOAPX,NOLONG,UNDOC,OBSOLETE,8086 */
        /* 001(0f) : NOREX,NOAPX,NOLONG,UNDOC,OBSOLETE,8086 */
        {I_POP, 1, {REG_CS|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+29193, 308},
    /*   2 : POP reg_ss [-:        17                                ] NOREX,NOAPX,NOLONG,8086 */
        /* 001(17) : NOREX,NOAPX,NOLONG,8086 */
        {I_POP, 1, {REG_SS|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+29319, 227},
    /*   3 : POP reg_ds [-:        1f                                ] NOREX,NOAPX,NOLONG,8086 */
        /* 001(1f) : NOREX,NOAPX,NOLONG,8086 */
        {I_POP, 1, {REG_DS|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+29463, 227},
    /*   4 : POP reg_fs [-:        0f a1                             ] 386 */
        /* 355 001(a1) : 386 */
        {I_POP, 1, {REG_FS,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72793, 3},
    /*   5 : POP reg_gs [-:        0f a9                             ] 386 */
        /* 355 001(a9) : 386 */
        {I_POP, 1, {REG_GS,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72797, 3},
    /*   6 : POP reg16 [r:        nw o16 58+r                       ] 8086 */
        /* 327 320 010 130 : NWSIZE,8086 */
        {I_POP, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72173, 235},
    /*   7 : POP reg32 [r:        nw o32 58+r                       ] 386 */
        /* 327 321 010 130 : NWSIZE,386 */
        {I_POP, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72178, 236},
    /*   8 : POP reg64 [r:        nw o64 58+r                       ] LONG,PROT,X86_64 */
        /* 327 324 010 130 : NWSIZE,LONG,PROT,X86_64 */
        {I_POP, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72183, 237},
    /*   9 : POP rm16 [m:        nw o16 8f /0                      ] 8086 */
        /* 327 320 001(8f) 200 : NWSIZE,8086 */
        {I_POP, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67826, 235},
    /*  10 : POP rm32 [m:        nw o32 8f /0                      ] 386 */
        /* 327 321 001(8f) 200 : NWSIZE,386 */
        {I_POP, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67832, 236},
    /*  11 : POP rm64 [m:        nw o64 8f /0                      ] LONG,PROT,X86_64 */
        /* 327 324 001(8f) 200 : NWSIZE,LONG,PROT,X86_64 */
        {I_POP, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67838, 237},
    /*  12 : POP reg64,reg64 [vm:       o64nw evex.nd1.l0.np.m4.w0 8f /0  ] ND,LONG,PROT,APX,X86_64 */
        /* 323 240(f4 7c 18) 300 001(8f) 210 : NWSIZE,LONG,EVEX,PROT,APX,X86_64 */
        {I_POP, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+13083, 346},
    /*  13 : POP reg64:reg64 [mv:       o64nw evex.nd1.l0.np.m4.w0 8f /0  ] ND,LONG,PROT,APX,X86_64 */
        /* 323 241(f4 7c 18) 300 001(8f) 200 : NWSIZE,LONG,EVEX,PROT,APX,X86_64 */
        {I_POP, 2, {REG_GPR|BITS64|COLON,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+13093, 346},
};

static const struct itemplate instrux_RDFSBASE[2] = {
    /*   0 : RDFSBASE reg32 [m:        w0 f3 0f ae /0                    ] LONG,PROT,X86_64 */
        /* 317 333 355 001(ae) 200 : LONG,PROT,X86_64 */
        {I_RDFSBASE, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56949, 24},
    /*   1 : RDFSBASE reg64 [m:        w1 f3 0f ae /0                    ] LONG,PROT,X86_64 */
        /* 324 333 355 001(ae) 200 : LONG,PROT,X86_64 */
        {I_RDFSBASE, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56956, 24},
};

static const struct itemplate instrux_RDGSBASE[2] = {
    /*   0 : RDGSBASE reg32 [m:        w0 f3 0f ae /1                    ] LONG,PROT,X86_64 */
        /* 317 333 355 001(ae) 201 : LONG,PROT,X86_64 */
        {I_RDGSBASE, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56963, 24},
    /*   1 : RDGSBASE reg64 [m:        w1 f3 0f ae /1                    ] LONG,PROT,X86_64 */
        /* 324 333 355 001(ae) 201 : LONG,PROT,X86_64 */
        {I_RDGSBASE, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56970, 24},
};

static const struct itemplate instrux_WRFSBASE[2] = {
    /*   0 : WRFSBASE reg32 [m:        w0 f3 0f ae /2                    ] LONG,PROT,X86_64 */
        /* 317 333 355 001(ae) 202 : LONG,PROT,X86_64 */
        {I_WRFSBASE, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56977, 24},
    /*   1 : WRFSBASE reg64 [m:        w1 f3 0f ae /2                    ] LONG,PROT,X86_64 */
        /* 324 333 355 001(ae) 202 : LONG,PROT,X86_64 */
        {I_WRFSBASE, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56984, 24},
};

static const struct itemplate instrux_WRGSBASE[2] = {
    /*   0 : WRGSBASE reg32 [m:        w0 f3 0f ae /3                    ] LONG,PROT,X86_64 */
        /* 317 333 355 001(ae) 203 : LONG,PROT,X86_64 */
        {I_WRGSBASE, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56991, 24},
    /*   1 : WRGSBASE reg64 [m:        w1 f3 0f ae /3                    ] LONG,PROT,X86_64 */
        /* 324 333 355 001(ae) 203 : LONG,PROT,X86_64 */
        {I_WRGSBASE, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56998, 24},
};

static const struct itemplate instrux_ARPL[2] = {
    /*   0 : ARPL rm16,reg16 [mr:       optw o16 63 /r                    ] SM0-1,NOREX,NOAPX,NOLONG,FL,PROT,286 */
        /* 336 320 001(63) 101 : SM0,SM1,NOREX,NOAPX,NOLONG,FL,PROT,286 */
        {I_ARPL, 2, {RM_GPR|BITS16|RN_L16,REG_GPR|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67442, 309},
    /*   1 : ARPL rm16,reg32 [mr:       optw o32 63 /r                    ] SM0-1,NOREX,NOAPX,NOLONG,FL,PROT,386 */
        /* 336 321 001(63) 101 : SM0,SM1,NOREX,NOAPX,NOLONG,FL,PROT,386 */
        {I_ARPL, 2, {RM_GPR|BITS16|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67448, 310},
};

static const struct itemplate instrux_LAR[3] = {
    /*   0 : LAR reg16,rm_sel [rm:       o16 0f 02 /r                      ] FL,PROT,286 */
        /* 320 355 001(02) 110 : FL,PROT,286 */
        {I_LAR, 2, {REG_GPR|BITS16,RM_SEL,0,0,0}, NO_DECORATOR, nasm_bytecodes+67454, 311},
    /*   1 : LAR reg32,rm_sel [rm:       optd o32 0f 02 /r                 ] FL,PROT,386 */
        /* 337 321 355 001(02) 110 : FL,PROT,386 */
        {I_LAR, 2, {REG_GPR|BITS32,RM_SEL,0,0,0}, NO_DECORATOR, nasm_bytecodes+57005, 312},
    /*   2 : LAR reg64,rm_sel [rm:       optd o64 0f 02 /r                 ] LONG,FL,PROT,X86_64 */
        /* 337 324 355 001(02) 110 : LONG,FL,PROT,X86_64 */
        {I_LAR, 2, {REG_GPR|BITS64,RM_SEL,0,0,0}, NO_DECORATOR, nasm_bytecodes+57012, 56},
};

static const struct itemplate instrux_LSL[3] = {
    /*   0 : LSL reg16,rm_sel [rm:       o16 0f 03 /r                      ] PROT,286 */
        /* 320 355 001(03) 110 : PROT,286 */
        {I_LSL, 2, {REG_GPR|BITS16,RM_SEL,0,0,0}, NO_DECORATOR, nasm_bytecodes+67460, 313},
    /*   1 : LSL reg32,rm_sel [rm:       optd o32 0f 03 /r                 ] PROT,386 */
        /* 337 321 355 001(03) 110 : PROT,386 */
        {I_LSL, 2, {REG_GPR|BITS32,RM_SEL,0,0,0}, NO_DECORATOR, nasm_bytecodes+57019, 314},
    /*   2 : LSL reg64,rm_sel [rm:       optd o64 0f 03 /r                 ] LONG,PROT,X86_64 */
        /* 337 324 355 001(03) 110 : LONG,PROT,X86_64 */
        {I_LSL, 2, {REG_GPR|BITS64,RM_SEL,0,0,0}, NO_DECORATOR, nasm_bytecodes+57026, 24},
};

static const struct itemplate instrux_VERR[1] = {
    /*   0 : VERR rm_sel [m:        0f 00 /4                          ] FL,PROT,286 */
        /* 355 001(00) 204 : FL,PROT,286 */
        {I_VERR, 1, {RM_SEL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71773, 311},
};

static const struct itemplate instrux_VERW[1] = {
    /*   0 : VERW rm_sel [m:        0f 00 /5                          ] FL,PROT,286 */
        /* 355 001(00) 205 : FL,PROT,286 */
        {I_VERW, 1, {RM_SEL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71778, 311},
};

static const struct itemplate instrux_SWAPGS[1] = {
    /*   0 : SWAPGS void [          0f 01 f8                          ] LONG,PROT,X86_64 */
        /* 355 002(01 f8) : LONG,PROT,X86_64 */
        {I_SWAPGS, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71783, 24},
};

static const struct itemplate instrux_LKGS[1] = {
    /*   0 : LKGS rm_sel [m:        f2 0f 00 /6                       ] LONG,PRIV,PROT,LKGS,X86_64 */
        /* 332 355 001(00) 206 : LONG,PRIV,PROT,LKGS,X86_64 */
        {I_LKGS, 1, {RM_SEL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67466, 315},
};

static const struct itemplate instrux_LGDT[3] = {
    /*   0 : LGDT mem16 [m:        nw o16 0f 01 /2                   ] AR0,OSIZE,PRIV,286 */
        /* 327 320 355 001(01) 202 : AR0,NWSIZE,OSIZE,PRIV,286 */
        {I_LGDT, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57033, 316},
    /*   1 : LGDT mem32 [m:        nw o32 0f 01 /2                   ] AR0,OSIZE,PRIV,386 */
        /* 327 321 355 001(01) 202 : AR0,NWSIZE,OSIZE,PRIV,386 */
        {I_LGDT, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57040, 317},
    /*   2 : LGDT mem64 [m:        nw o64 0f 01 /2                   ] AR0,OSIZE,LONG,PRIV,386,X86_64 */
        /* 327 324 355 001(01) 202 : AR0,NWSIZE,OSIZE,LONG,PRIV,PROT,X86_64 */
        {I_LGDT, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57047, 318},
};

static const struct itemplate instrux_LIDT[3] = {
    /*   0 : LIDT mem16 [m:        nw o16 0f 01 /3                   ] AR0,OSIZE,PRIV,286 */
        /* 327 320 355 001(01) 203 : AR0,NWSIZE,OSIZE,PRIV,286 */
        {I_LIDT, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57054, 316},
    /*   1 : LIDT mem32 [m:        nw o32 0f 01 /3                   ] AR0,OSIZE,PRIV,386 */
        /* 327 321 355 001(01) 203 : AR0,NWSIZE,OSIZE,PRIV,386 */
        {I_LIDT, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57061, 317},
    /*   2 : LIDT mem64 [m:        nw o64 0f 01 /3                   ] AR0,OSIZE,LONG,PRIV,386,X86_64 */
        /* 327 324 355 001(01) 203 : AR0,NWSIZE,OSIZE,LONG,PRIV,PROT,X86_64 */
        {I_LIDT, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57068, 318},
};

static const struct itemplate instrux_LLDT[4] = {
    /*   0 : LLDT mem16 [m:        0f 00 /2                          ] PRIV,PROT,286 */
        /* 355 001(00) 202 : PRIV,PROT,286 */
        {I_LLDT, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57091, 319},
    /*   1 : LLDT reg16 [m:        optw o16 0f 00 /2                 ] PRIV,PROT,286 */
        /* 336 320 355 001(00) 202 : PRIV,PROT,286 */
        {I_LLDT, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57075, 319},
    /*   2 : LLDT reg32 [m:        optw o32 0f 00 /2                 ] PRIV,PROT,386 */
        /* 336 321 355 001(00) 202 : PRIV,PROT,386 */
        {I_LLDT, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57082, 320},
    /*   3 : LLDT reg64 [m:        optw o64 0f 00 /2                 ] LONG,PRIV,PROT,386,X86_64 */
        /* 336 324 355 001(00) 202 : LONG,PRIV,PROT,X86_64 */
        {I_LLDT, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57089, 321},
};

static const struct itemplate instrux_LTR[4] = {
    /*   0 : LTR mem16 [m:        0f 00 /3                          ] PRIV,PROT,286 */
        /* 355 001(00) 203 : PRIV,PROT,286 */
        {I_LTR, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57112, 319},
    /*   1 : LTR reg16 [m:        optw o16 0f 00 /3                 ] PRIV,PROT,286 */
        /* 336 320 355 001(00) 203 : PRIV,PROT,286 */
        {I_LTR, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57096, 319},
    /*   2 : LTR reg32 [m:        optw o32 0f 00 /3                 ] PRIV,PROT,386 */
        /* 336 321 355 001(00) 203 : PRIV,PROT,386 */
        {I_LTR, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57103, 320},
    /*   3 : LTR reg64 [m:        optw o64 0f 00 /3                 ] LONG,PRIV,PROT,386,X86_64 */
        /* 336 324 355 001(00) 203 : LONG,PRIV,PROT,X86_64 */
        {I_LTR, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57110, 321},
};

static const struct itemplate instrux_SGDT[3] = {
    /*   0 : SGDT mem16 [m:        nw o16 0f 01 /0                   ] AR0,OSIZE,286 */
        /* 327 320 355 001(01) 200 : AR0,NWSIZE,OSIZE,286 */
        {I_SGDT, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57117, 322},
    /*   1 : SGDT mem32 [m:        nw o32 0f 01 /0                   ] AR0,OSIZE,386 */
        /* 327 321 355 001(01) 200 : AR0,NWSIZE,OSIZE,386 */
        {I_SGDT, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57124, 203},
    /*   2 : SGDT mem64 [m:        nw o64 0f 01 /0                   ] AR0,OSIZE,LONG,386,X86_64 */
        /* 327 324 355 001(01) 200 : AR0,NWSIZE,OSIZE,LONG,PROT,X86_64 */
        {I_SGDT, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57131, 204},
};

static const struct itemplate instrux_SIDT[3] = {
    /*   0 : SIDT mem16 [m:        nw o16 0f 01 /1                   ] AR0,OSIZE,286 */
        /* 327 320 355 001(01) 201 : AR0,NWSIZE,OSIZE,286 */
        {I_SIDT, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57138, 322},
    /*   1 : SIDT mem32 [m:        nw o32 0f 01 /1                   ] AR0,OSIZE,386 */
        /* 327 321 355 001(01) 201 : AR0,NWSIZE,OSIZE,386 */
        {I_SIDT, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57145, 203},
    /*   2 : SIDT mem64 [m:        nw o64 0f 01 /1                   ] AR0,OSIZE,LONG,386,X86_64 */
        /* 327 324 355 001(01) 201 : AR0,NWSIZE,OSIZE,LONG,PROT,X86_64 */
        {I_SIDT, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57152, 204},
};

static const struct itemplate instrux_SLDT[4] = {
    /*   0 : SLDT mem16 [m:        0f 00 /0                          ] PROT,286 */
        /* 355 001(00) 200 : PROT,286 */
        {I_SLDT, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67473, 313},
    /*   1 : SLDT reg16 [m:        o16 0f 00 /0                      ] PROT,286 */
        /* 320 355 001(00) 200 : PROT,286 */
        {I_SLDT, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67472, 313},
    /*   2 : SLDT reg32 [m:        optd o32 0f 00 /0                 ] PROT,386 */
        /* 337 321 355 001(00) 200 : PROT,386 */
        {I_SLDT, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57159, 314},
    /*   3 : SLDT reg64 [m:        optd o64 0f 00 /0                 ] LONG,PROT,386,X86_64 */
        /* 337 324 355 001(00) 200 : LONG,PROT,X86_64 */
        {I_SLDT, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57166, 24},
};

static const struct itemplate instrux_STR[4] = {
    /*   0 : STR mem16 [m:        0f 00 /1                          ] PROT,286 */
        /* 355 001(00) 201 : PROT,286 */
        {I_STR, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67479, 313},
    /*   1 : STR reg16 [m:        o16 0f 00 /1                      ] PROT,286 */
        /* 320 355 001(00) 201 : PROT,286 */
        {I_STR, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67478, 313},
    /*   2 : STR reg32 [m:        optd o32 0f 00 /1                 ] PROT,386 */
        /* 337 321 355 001(00) 201 : PROT,386 */
        {I_STR, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57173, 314},
    /*   3 : STR reg64 [m:        optd o64 0f 00 /1                 ] LONG,PROT,386,X86_64 */
        /* 337 324 355 001(00) 201 : LONG,PROT,X86_64 */
        {I_STR, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57180, 24},
};

static const struct itemplate instrux_LOADALL[1] = {
    /*   0 : LOADALL void [          0f 07                             ] ND,UNDOC,OBSOLETE,386 */
        /* 355 001(07) : UNDOC,OBSOLETE,386 */
        {I_LOADALL, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72621, 323},
};

static const struct itemplate instrux_LOADALL286[1] = {
    /*   0 : LOADALL286 void [          0f 05                             ] ND,UNDOC,OBSOLETE,286 */
        /* 355 001(05) : UNDOC,OBSOLETE,286 */
        {I_LOADALL286, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72609, 324},
};

static const struct itemplate instrux_F2XM1[1] = {
    /*   0 : F2XM1 void [          d9 f0                             ] FPU,8086 */
        /* 002(d9 f0) : FPU,8086 */
        {I_F2XM1, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72801, 325},
};

static const struct itemplate instrux_FABS[1] = {
    /*   0 : FABS void [          d9 e1                             ] FPU,8086 */
        /* 002(d9 e1) : FPU,8086 */
        {I_FABS, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72805, 325},
};

static const struct itemplate instrux_FADD[7] = {
    /*   0 : FADD mem32 [m:        d8 /0                             ] FPU,8086 */
        /* 001(d8) 200 : FPU,8086 */
        {I_FADD, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+69802, 325},
    /*   1 : FADD mem64 [m:        dc /0                             ] FPU,8086 */
        /* 001(dc) 200 : FPU,8086 */
        {I_FADD, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72809, 325},
    /*   2 : FADD fpureg|to [r:        dc c0+r                           ] FPU,8086 */
        /* 001(dc) 010 300 : FPU,8086 */
        {I_FADD, 1, {FPUREG|TO,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71788, 325},
    /*   3 : FADD fpureg [r:        d8 c0+r                           ] FPU,8086 */
        /* 001(d8) 010 300 : FPU,8086 */
        {I_FADD, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71793, 325},
    /*   4 : FADD fpureg,fpu0 [r-:       dc c0+r                           ] FPU,8086 */
        /* 001(dc) 010 300 : FPU,8086 */
        {I_FADD, 2, {FPUREG,FPUREG|RN_ZERO,0,0,0}, NO_DECORATOR, nasm_bytecodes+71788, 325},
    /*   5 : FADD fpu0,fpureg [-r:       d8 c0+r                           ] FPU,8086 */
        /* 001(d8) 011 300 : FPU,8086 */
        {I_FADD, 2, {FPUREG|RN_ZERO,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+71798, 325},
    /*   6 : FADD void [          de c1                             ] ND,FPU,8086 */
        /* 002(de c1) : FPU,8086 */
        {I_FADD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72813, 325},
};

static const struct itemplate instrux_FADDP[3] = {
    /*   0 : FADDP fpureg [r:        de c0+r                           ] FPU,8086 */
        /* 001(de) 010 300 : FPU,8086 */
        {I_FADDP, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71803, 325},
    /*   1 : FADDP fpureg,fpu0 [r-:       de c0+r                           ] FPU,8086 */
        /* 001(de) 010 300 : FPU,8086 */
        {I_FADDP, 2, {FPUREG,FPUREG|RN_ZERO,0,0,0}, NO_DECORATOR, nasm_bytecodes+71803, 325},
    /*   2 : FADDP void [          de c1                             ] ND,FPU,8086 */
        /* 002(de c1) : FPU,8086 */
        {I_FADDP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72813, 325},
};

static const struct itemplate instrux_FBLD[2] = {
    /*   0 : FBLD mem80 [m:        df /4                             ] FPU,8086 */
        /* 001(df) 204 : FPU,8086 */
        {I_FBLD, 1, {MEMORY|BITS80,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72817, 325},
    /*   1 : FBLD mem [m:        df /4                             ] FPU,8086 */
        /* 001(df) 204 : FPU,8086 */
        {I_FBLD, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72817, 325},
};

static const struct itemplate instrux_FBSTP[2] = {
    /*   0 : FBSTP mem80 [m:        df /6                             ] FPU,8086 */
        /* 001(df) 206 : FPU,8086 */
        {I_FBSTP, 1, {MEMORY|BITS80,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72821, 325},
    /*   1 : FBSTP mem [m:        df /6                             ] FPU,8086 */
        /* 001(df) 206 : FPU,8086 */
        {I_FBSTP, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72821, 325},
};

static const struct itemplate instrux_FCHS[1] = {
    /*   0 : FCHS void [          d9 e0                             ] FPU,8086 */
        /* 002(d9 e0) : FPU,8086 */
        {I_FCHS, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72825, 325},
};

static const struct itemplate instrux_FCLEX[1] = {
    /*   0 : FCLEX void [          wait db e2                        ] FPU,8086 */
        /* 341 002(db e2) : FPU,8086 */
        {I_FCLEX, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71808, 325},
};

static const struct itemplate instrux_FCMOVB[3] = {
    /*   0 : FCMOVB fpureg [r:        da c0+r                           ] FPU,P6 */
        /* 001(da) 010 300 : FPU,P6 */
        {I_FCMOVB, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71813, 326},
    /*   1 : FCMOVB fpu0,fpureg [-r:       da c0+r                           ] FPU,P6 */
        /* 001(da) 011 300 : FPU,P6 */
        {I_FCMOVB, 2, {FPUREG|RN_ZERO,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+71818, 326},
    /*   2 : FCMOVB void [          da c1                             ] ND,FPU,P6 */
        /* 002(da c1) : FPU,P6 */
        {I_FCMOVB, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72829, 326},
};

static const struct itemplate instrux_FCMOVBE[3] = {
    /*   0 : FCMOVBE fpureg [r:        da d0+r                           ] FPU,P6 */
        /* 001(da) 010 320 : FPU,P6 */
        {I_FCMOVBE, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71823, 326},
    /*   1 : FCMOVBE fpu0,fpureg [-r:       da d0+r                           ] FPU,P6 */
        /* 001(da) 011 320 : FPU,P6 */
        {I_FCMOVBE, 2, {FPUREG|RN_ZERO,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+71828, 326},
    /*   2 : FCMOVBE void [          da d1                             ] ND,FPU,P6 */
        /* 002(da d1) : FPU,P6 */
        {I_FCMOVBE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72833, 326},
};

static const struct itemplate instrux_FCMOVE[3] = {
    /*   0 : FCMOVE fpureg [r:        da c8+r                           ] FPU,P6 */
        /* 001(da) 010 310 : FPU,P6 */
        {I_FCMOVE, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71833, 326},
    /*   1 : FCMOVE fpu0,fpureg [-r:       da c8+r                           ] FPU,P6 */
        /* 001(da) 011 310 : FPU,P6 */
        {I_FCMOVE, 2, {FPUREG|RN_ZERO,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+71838, 326},
    /*   2 : FCMOVE void [          da c9                             ] ND,FPU,P6 */
        /* 002(da c9) : FPU,P6 */
        {I_FCMOVE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72837, 326},
};

static const struct itemplate instrux_FCMOVNB[3] = {
    /*   0 : FCMOVNB fpureg [r:        db c0+r                           ] FPU,P6 */
        /* 001(db) 010 300 : FPU,P6 */
        {I_FCMOVNB, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71843, 326},
    /*   1 : FCMOVNB fpu0,fpureg [-r:       db c0+r                           ] FPU,P6 */
        /* 001(db) 011 300 : FPU,P6 */
        {I_FCMOVNB, 2, {FPUREG|RN_ZERO,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+71848, 326},
    /*   2 : FCMOVNB void [          db c1                             ] ND,FPU,P6 */
        /* 002(db c1) : FPU,P6 */
        {I_FCMOVNB, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72841, 326},
};

static const struct itemplate instrux_FCMOVNBE[3] = {
    /*   0 : FCMOVNBE fpureg [r:        db d0+r                           ] FPU,P6 */
        /* 001(db) 010 320 : FPU,P6 */
        {I_FCMOVNBE, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71853, 326},
    /*   1 : FCMOVNBE fpu0,fpureg [-r:       db d0+r                           ] FPU,P6 */
        /* 001(db) 011 320 : FPU,P6 */
        {I_FCMOVNBE, 2, {FPUREG|RN_ZERO,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+71858, 326},
    /*   2 : FCMOVNBE void [          db d1                             ] ND,FPU,P6 */
        /* 002(db d1) : FPU,P6 */
        {I_FCMOVNBE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72845, 326},
};

static const struct itemplate instrux_FCMOVNE[3] = {
    /*   0 : FCMOVNE fpureg [r:        db c8+r                           ] FPU,P6 */
        /* 001(db) 010 310 : FPU,P6 */
        {I_FCMOVNE, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71863, 326},
    /*   1 : FCMOVNE fpu0,fpureg [-r:       db c8+r                           ] FPU,P6 */
        /* 001(db) 011 310 : FPU,P6 */
        {I_FCMOVNE, 2, {FPUREG|RN_ZERO,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+71868, 326},
    /*   2 : FCMOVNE void [          db c9                             ] ND,FPU,P6 */
        /* 002(db c9) : FPU,P6 */
        {I_FCMOVNE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72849, 326},
};

static const struct itemplate instrux_FCMOVNU[3] = {
    /*   0 : FCMOVNU fpureg [r:        db d8+r                           ] FPU,P6 */
        /* 001(db) 010 330 : FPU,P6 */
        {I_FCMOVNU, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71873, 326},
    /*   1 : FCMOVNU fpu0,fpureg [-r:       db d8+r                           ] FPU,P6 */
        /* 001(db) 011 330 : FPU,P6 */
        {I_FCMOVNU, 2, {FPUREG|RN_ZERO,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+71878, 326},
    /*   2 : FCMOVNU void [          db d9                             ] ND,FPU,P6 */
        /* 002(db d9) : FPU,P6 */
        {I_FCMOVNU, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72853, 326},
};

static const struct itemplate instrux_FCMOVU[3] = {
    /*   0 : FCMOVU fpureg [r:        da d8+r                           ] FPU,P6 */
        /* 001(da) 010 330 : FPU,P6 */
        {I_FCMOVU, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71883, 326},
    /*   1 : FCMOVU fpu0,fpureg [-r:       da d8+r                           ] FPU,P6 */
        /* 001(da) 011 330 : FPU,P6 */
        {I_FCMOVU, 2, {FPUREG|RN_ZERO,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+71888, 326},
    /*   2 : FCMOVU void [          da d9                             ] ND,FPU,P6 */
        /* 002(da d9) : FPU,P6 */
        {I_FCMOVU, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72857, 326},
};

static const struct itemplate instrux_FCOM[5] = {
    /*   0 : FCOM mem32 [m:        d8 /2                             ] FPU,8086 */
        /* 001(d8) 202 : FPU,8086 */
        {I_FCOM, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+69808, 325},
    /*   1 : FCOM mem64 [m:        dc /2                             ] FPU,8086 */
        /* 001(dc) 202 : FPU,8086 */
        {I_FCOM, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72861, 325},
    /*   2 : FCOM fpureg [r:        d8 d0+r                           ] FPU,8086 */
        /* 001(d8) 010 320 : FPU,8086 */
        {I_FCOM, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71893, 325},
    /*   3 : FCOM fpu0,fpureg [-r:       d8 d0+r                           ] FPU,8086 */
        /* 001(d8) 011 320 : FPU,8086 */
        {I_FCOM, 2, {FPUREG|RN_ZERO,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+71898, 325},
    /*   4 : FCOM void [          d8 d1                             ] ND,FPU,8086 */
        /* 002(d8 d1) : FPU,8086 */
        {I_FCOM, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72865, 325},
};

static const struct itemplate instrux_FCOMI[3] = {
    /*   0 : FCOMI fpureg [r:        db f0+r                           ] FL,FPU,P6 */
        /* 001(db) 010 360 : FL,FPU,P6 */
        {I_FCOMI, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71903, 327},
    /*   1 : FCOMI fpu0,fpureg [-r:       db f0+r                           ] FL,FPU,P6 */
        /* 001(db) 011 360 : FL,FPU,P6 */
        {I_FCOMI, 2, {FPUREG|RN_ZERO,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+71908, 327},
    /*   2 : FCOMI void [          db f1                             ] ND,FL,FPU,P6 */
        /* 002(db f1) : FL,FPU,P6 */
        {I_FCOMI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72869, 327},
};

static const struct itemplate instrux_FCOMIP[3] = {
    /*   0 : FCOMIP fpureg [r:        df f0+r                           ] FL,FPU,P6 */
        /* 001(df) 010 360 : FL,FPU,P6 */
        {I_FCOMIP, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71913, 327},
    /*   1 : FCOMIP fpu0,fpureg [-r:       df f0+r                           ] FL,FPU,P6 */
        /* 001(df) 011 360 : FL,FPU,P6 */
        {I_FCOMIP, 2, {FPUREG|RN_ZERO,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+71918, 327},
    /*   2 : FCOMIP void [          df f1                             ] ND,FL,FPU,P6 */
        /* 002(df f1) : FL,FPU,P6 */
        {I_FCOMIP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72873, 327},
};

static const struct itemplate instrux_FCOMP[5] = {
    /*   0 : FCOMP mem32 [m:        d8 /3                             ] FPU,8086 */
        /* 001(d8) 203 : FPU,8086 */
        {I_FCOMP, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+69796, 325},
    /*   1 : FCOMP mem64 [m:        dc /3                             ] FPU,8086 */
        /* 001(dc) 203 : FPU,8086 */
        {I_FCOMP, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72877, 325},
    /*   2 : FCOMP fpureg [r:        d8 d8+r                           ] FPU,8086 */
        /* 001(d8) 010 330 : FPU,8086 */
        {I_FCOMP, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71923, 325},
    /*   3 : FCOMP fpu0,fpureg [-r:       d8 d8+r                           ] FPU,8086 */
        /* 001(d8) 011 330 : FPU,8086 */
        {I_FCOMP, 2, {FPUREG|RN_ZERO,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+71928, 325},
    /*   4 : FCOMP void [          d8 d9                             ] ND,FPU,8086 */
        /* 002(d8 d9) : FPU,8086 */
        {I_FCOMP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72881, 325},
};

static const struct itemplate instrux_FCOMPP[1] = {
    /*   0 : FCOMPP void [          de d9                             ] FPU,8086 */
        /* 002(de d9) : FPU,8086 */
        {I_FCOMPP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72885, 325},
};

static const struct itemplate instrux_FCOS[1] = {
    /*   0 : FCOS void [          d9 ff                             ] FPU,386 */
        /* 002(d9 ff) : FPU,386 */
        {I_FCOS, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72889, 328},
};

static const struct itemplate instrux_FDECSTP[1] = {
    /*   0 : FDECSTP void [          d9 f6                             ] FPU,8086 */
        /* 002(d9 f6) : FPU,8086 */
        {I_FDECSTP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72893, 325},
};

static const struct itemplate instrux_FDISI[1] = {
    /*   0 : FDISI void [          wait db e1                        ] FPU,8086 */
        /* 341 002(db e1) : FPU,8086 */
        {I_FDISI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71933, 325},
};

static const struct itemplate instrux_FDIV[7] = {
    /*   0 : FDIV mem32 [m:        d8 /6                             ] FPU,8086 */
        /* 001(d8) 206 : FPU,8086 */
        {I_FDIV, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72897, 325},
    /*   1 : FDIV mem64 [m:        dc /6                             ] FPU,8086 */
        /* 001(dc) 206 : FPU,8086 */
        {I_FDIV, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72901, 325},
    /*   2 : FDIV fpureg|to [r:        dc f8+r                           ] FPU,8086 */
        /* 001(dc) 010 370 : FPU,8086 */
        {I_FDIV, 1, {FPUREG|TO,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71938, 325},
    /*   3 : FDIV fpureg [r:        d8 f0+r                           ] FPU,8086 */
        /* 001(d8) 010 360 : FPU,8086 */
        {I_FDIV, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71943, 325},
    /*   4 : FDIV fpureg,fpu0 [r-:       dc f8+r                           ] FPU,8086 */
        /* 001(dc) 010 370 : FPU,8086 */
        {I_FDIV, 2, {FPUREG,FPUREG|RN_ZERO,0,0,0}, NO_DECORATOR, nasm_bytecodes+71938, 325},
    /*   5 : FDIV fpu0,fpureg [-r:       d8 f0+r                           ] FPU,8086 */
        /* 001(d8) 011 360 : FPU,8086 */
        {I_FDIV, 2, {FPUREG|RN_ZERO,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+71948, 325},
    /*   6 : FDIV void [          de f9                             ] ND,FPU,8086 */
        /* 002(de f9) : FPU,8086 */
        {I_FDIV, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72905, 325},
};

static const struct itemplate instrux_FDIVP[3] = {
    /*   0 : FDIVP fpureg [r:        de f8+r                           ] FPU,8086 */
        /* 001(de) 010 370 : FPU,8086 */
        {I_FDIVP, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71953, 325},
    /*   1 : FDIVP fpureg,fpu0 [r-:       de f8+r                           ] FPU,8086 */
        /* 001(de) 010 370 : FPU,8086 */
        {I_FDIVP, 2, {FPUREG,FPUREG|RN_ZERO,0,0,0}, NO_DECORATOR, nasm_bytecodes+71953, 325},
    /*   2 : FDIVP void [          de f9                             ] ND,FPU,8086 */
        /* 002(de f9) : FPU,8086 */
        {I_FDIVP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72905, 325},
};

static const struct itemplate instrux_FDIVR[7] = {
    /*   0 : FDIVR mem32 [m:        d8 /7                             ] FPU,8086 */
        /* 001(d8) 207 : FPU,8086 */
        {I_FDIVR, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72909, 325},
    /*   1 : FDIVR mem64 [m:        dc /7                             ] FPU,8086 */
        /* 001(dc) 207 : FPU,8086 */
        {I_FDIVR, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72913, 325},
    /*   2 : FDIVR fpureg|to [r:        dc f0+r                           ] FPU,8086 */
        /* 001(dc) 010 360 : FPU,8086 */
        {I_FDIVR, 1, {FPUREG|TO,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71958, 325},
    /*   3 : FDIVR fpureg,fpu0 [r-:       dc f0+r                           ] FPU,8086 */
        /* 001(dc) 010 360 : FPU,8086 */
        {I_FDIVR, 2, {FPUREG,FPUREG|RN_ZERO,0,0,0}, NO_DECORATOR, nasm_bytecodes+71958, 325},
    /*   4 : FDIVR fpureg [r:        d8 f8+r                           ] FPU,8086 */
        /* 001(d8) 010 370 : FPU,8086 */
        {I_FDIVR, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71963, 325},
    /*   5 : FDIVR fpu0,fpureg [-r:       d8 f8+r                           ] FPU,8086 */
        /* 001(d8) 011 370 : FPU,8086 */
        {I_FDIVR, 2, {FPUREG|RN_ZERO,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+71968, 325},
    /*   6 : FDIVR void [          de f1                             ] ND,FPU,8086 */
        /* 002(de f1) : FPU,8086 */
        {I_FDIVR, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72917, 325},
};

static const struct itemplate instrux_FDIVRP[3] = {
    /*   0 : FDIVRP fpureg [r:        de f0+r                           ] FPU,8086 */
        /* 001(de) 010 360 : FPU,8086 */
        {I_FDIVRP, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71973, 325},
    /*   1 : FDIVRP fpureg,fpu0 [r-:       de f0+r                           ] FPU,8086 */
        /* 001(de) 010 360 : FPU,8086 */
        {I_FDIVRP, 2, {FPUREG,FPUREG|RN_ZERO,0,0,0}, NO_DECORATOR, nasm_bytecodes+71973, 325},
    /*   2 : FDIVRP void [          de f1                             ] ND,FPU,8086 */
        /* 002(de f1) : FPU,8086 */
        {I_FDIVRP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72917, 325},
};

static const struct itemplate instrux_FEMMS[1] = {
    /*   0 : FEMMS void [          0f 0e                             ] 3DNOW,PENT */
        /* 355 001(0e) : 3DNOW,PENT */
        {I_FEMMS, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72921, 329},
};

static const struct itemplate instrux_FENI[1] = {
    /*   0 : FENI void [          wait db e0                        ] FPU,8086 */
        /* 341 002(db e0) : FPU,8086 */
        {I_FENI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71978, 325},
};

static const struct itemplate instrux_FFREE[2] = {
    /*   0 : FFREE fpureg [r:        dd c0+r                           ] FPU,8086 */
        /* 001(dd) 010 300 : FPU,8086 */
        {I_FFREE, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71983, 325},
    /*   1 : FFREE void [          dd c1                             ] FPU,8086 */
        /* 002(dd c1) : FPU,8086 */
        {I_FFREE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72925, 325},
};

static const struct itemplate instrux_FFREEP[2] = {
    /*   0 : FFREEP fpureg [r:        df c0+r                           ] UNDOC,FPU,286 */
        /* 001(df) 010 300 : UNDOC,FPU,286 */
        {I_FFREEP, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71988, 330},
    /*   1 : FFREEP void [          df c1                             ] UNDOC,FPU,286 */
        /* 002(df c1) : UNDOC,FPU,286 */
        {I_FFREEP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72929, 330},
};

static const struct itemplate instrux_FIADD[2] = {
    /*   0 : FIADD mem32 [m:        da /0                             ] FPU,8086 */
        /* 001(da) 200 : FPU,8086 */
        {I_FIADD, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72933, 325},
    /*   1 : FIADD mem16 [m:        de /0                             ] FPU,8086 */
        /* 001(de) 200 : FPU,8086 */
        {I_FIADD, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72937, 325},
};

static const struct itemplate instrux_FICOM[2] = {
    /*   0 : FICOM mem32 [m:        da /2                             ] FPU,8086 */
        /* 001(da) 202 : FPU,8086 */
        {I_FICOM, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72941, 325},
    /*   1 : FICOM mem16 [m:        de /2                             ] FPU,8086 */
        /* 001(de) 202 : FPU,8086 */
        {I_FICOM, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72945, 325},
};

static const struct itemplate instrux_FICOMP[2] = {
    /*   0 : FICOMP mem32 [m:        da /3                             ] FPU,8086 */
        /* 001(da) 203 : FPU,8086 */
        {I_FICOMP, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72949, 325},
    /*   1 : FICOMP mem16 [m:        de /3                             ] FPU,8086 */
        /* 001(de) 203 : FPU,8086 */
        {I_FICOMP, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72953, 325},
};

static const struct itemplate instrux_FIDIV[2] = {
    /*   0 : FIDIV mem32 [m:        da /6                             ] FPU,8086 */
        /* 001(da) 206 : FPU,8086 */
        {I_FIDIV, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72957, 325},
    /*   1 : FIDIV mem16 [m:        de /6                             ] FPU,8086 */
        /* 001(de) 206 : FPU,8086 */
        {I_FIDIV, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72961, 325},
};

static const struct itemplate instrux_FIDIVR[2] = {
    /*   0 : FIDIVR mem32 [m:        da /7                             ] FPU,8086 */
        /* 001(da) 207 : FPU,8086 */
        {I_FIDIVR, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72965, 325},
    /*   1 : FIDIVR mem16 [m:        de /7                             ] FPU,8086 */
        /* 001(de) 207 : FPU,8086 */
        {I_FIDIVR, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72969, 325},
};

static const struct itemplate instrux_FILD[3] = {
    /*   0 : FILD mem32 [m:        db /0                             ] FPU,8086 */
        /* 001(db) 200 : FPU,8086 */
        {I_FILD, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72973, 325},
    /*   1 : FILD mem16 [m:        df /0                             ] FPU,8086 */
        /* 001(df) 200 : FPU,8086 */
        {I_FILD, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72977, 325},
    /*   2 : FILD mem64 [m:        df /5                             ] FPU,8086 */
        /* 001(df) 205 : FPU,8086 */
        {I_FILD, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72981, 325},
};

static const struct itemplate instrux_FIMUL[2] = {
    /*   0 : FIMUL mem32 [m:        da /1                             ] FPU,8086 */
        /* 001(da) 201 : FPU,8086 */
        {I_FIMUL, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72985, 325},
    /*   1 : FIMUL mem16 [m:        de /1                             ] FPU,8086 */
        /* 001(de) 201 : FPU,8086 */
        {I_FIMUL, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72989, 325},
};

static const struct itemplate instrux_FINCSTP[1] = {
    /*   0 : FINCSTP void [          d9 f7                             ] FPU,8086 */
        /* 002(d9 f7) : FPU,8086 */
        {I_FINCSTP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72993, 325},
};

static const struct itemplate instrux_FINIT[1] = {
    /*   0 : FINIT void [          wait db e3                        ] FPU,8086 */
        /* 341 002(db e3) : FPU,8086 */
        {I_FINIT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71993, 325},
};

static const struct itemplate instrux_FIST[2] = {
    /*   0 : FIST mem32 [m:        db /2                             ] FPU,8086 */
        /* 001(db) 202 : FPU,8086 */
        {I_FIST, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72997, 325},
    /*   1 : FIST mem16 [m:        df /2                             ] FPU,8086 */
        /* 001(df) 202 : FPU,8086 */
        {I_FIST, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73001, 325},
};

static const struct itemplate instrux_FISTP[3] = {
    /*   0 : FISTP mem32 [m:        db /3                             ] FPU,8086 */
        /* 001(db) 203 : FPU,8086 */
        {I_FISTP, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73005, 325},
    /*   1 : FISTP mem16 [m:        df /3                             ] FPU,8086 */
        /* 001(df) 203 : FPU,8086 */
        {I_FISTP, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73009, 325},
    /*   2 : FISTP mem64 [m:        df /7                             ] FPU,8086 */
        /* 001(df) 207 : FPU,8086 */
        {I_FISTP, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73013, 325},
};

static const struct itemplate instrux_FISTTP[3] = {
    /*   0 : FISTTP mem16 [m:        df /1                             ] FPU,PRESCOTT */
        /* 001(df) 201 : FPU,PRESCOTT */
        {I_FISTTP, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73017, 331},
    /*   1 : FISTTP mem32 [m:        db /1                             ] FPU,PRESCOTT */
        /* 001(db) 201 : FPU,PRESCOTT */
        {I_FISTTP, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73021, 331},
    /*   2 : FISTTP mem64 [m:        dd /1                             ] FPU,PRESCOTT */
        /* 001(dd) 201 : FPU,PRESCOTT */
        {I_FISTTP, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73025, 331},
};

static const struct itemplate instrux_FISUB[2] = {
    /*   0 : FISUB mem32 [m:        da /4                             ] FPU,8086 */
        /* 001(da) 204 : FPU,8086 */
        {I_FISUB, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73029, 325},
    /*   1 : FISUB mem16 [m:        de /4                             ] FPU,8086 */
        /* 001(de) 204 : FPU,8086 */
        {I_FISUB, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73033, 325},
};

static const struct itemplate instrux_FISUBR[2] = {
    /*   0 : FISUBR mem32 [m:        da /5                             ] FPU,8086 */
        /* 001(da) 205 : FPU,8086 */
        {I_FISUBR, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73037, 325},
    /*   1 : FISUBR mem16 [m:        de /5                             ] FPU,8086 */
        /* 001(de) 205 : FPU,8086 */
        {I_FISUBR, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73041, 325},
};

static const struct itemplate instrux_FLD[5] = {
    /*   0 : FLD mem32 [m:        d9 /0                             ] FPU,8086 */
        /* 001(d9) 200 : FPU,8086 */
        {I_FLD, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73045, 325},
    /*   1 : FLD mem64 [m:        dd /0                             ] FPU,8086 */
        /* 001(dd) 200 : FPU,8086 */
        {I_FLD, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73049, 325},
    /*   2 : FLD mem80 [m:        db /5                             ] FPU,8086 */
        /* 001(db) 205 : FPU,8086 */
        {I_FLD, 1, {MEMORY|BITS80,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73053, 325},
    /*   3 : FLD fpureg [r:        d9 c0+r                           ] FPU,8086 */
        /* 001(d9) 010 300 : FPU,8086 */
        {I_FLD, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71998, 325},
    /*   4 : FLD void [          d9 c1                             ] ND,FPU,8086 */
        /* 002(d9 c1) : FPU,8086 */
        {I_FLD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73057, 325},
};

static const struct itemplate instrux_FLD1[1] = {
    /*   0 : FLD1 void [          d9 e8                             ] FPU,8086 */
        /* 002(d9 e8) : FPU,8086 */
        {I_FLD1, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73061, 325},
};

static const struct itemplate instrux_FLDCW[1] = {
    /*   0 : FLDCW mem [m:        d9 /5                             ] AR0,SW,FPU,8086 */
        /* 001(d9) 205 : AR0,SW,FPU,8086 */
        {I_FLDCW, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73065, 332},
};

static const struct itemplate instrux_FLDENV[1] = {
    /*   0 : FLDENV mem [m:        d9 /4                             ] FPU,8086 */
        /* 001(d9) 204 : FPU,8086 */
        {I_FLDENV, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73069, 325},
};

static const struct itemplate instrux_FLDL2E[1] = {
    /*   0 : FLDL2E void [          d9 ea                             ] FPU,8086 */
        /* 002(d9 ea) : FPU,8086 */
        {I_FLDL2E, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73073, 325},
};

static const struct itemplate instrux_FLDL2T[1] = {
    /*   0 : FLDL2T void [          d9 e9                             ] FPU,8086 */
        /* 002(d9 e9) : FPU,8086 */
        {I_FLDL2T, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73077, 325},
};

static const struct itemplate instrux_FLDLG2[1] = {
    /*   0 : FLDLG2 void [          d9 ec                             ] FPU,8086 */
        /* 002(d9 ec) : FPU,8086 */
        {I_FLDLG2, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73081, 325},
};

static const struct itemplate instrux_FLDLN2[1] = {
    /*   0 : FLDLN2 void [          d9 ed                             ] FPU,8086 */
        /* 002(d9 ed) : FPU,8086 */
        {I_FLDLN2, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73085, 325},
};

static const struct itemplate instrux_FLDPI[1] = {
    /*   0 : FLDPI void [          d9 eb                             ] FPU,8086 */
        /* 002(d9 eb) : FPU,8086 */
        {I_FLDPI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73089, 325},
};

static const struct itemplate instrux_FLDZ[1] = {
    /*   0 : FLDZ void [          d9 ee                             ] FPU,8086 */
        /* 002(d9 ee) : FPU,8086 */
        {I_FLDZ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73093, 325},
};

static const struct itemplate instrux_FMUL[7] = {
    /*   0 : FMUL mem32 [m:        d8 /1                             ] FPU,8086 */
        /* 001(d8) 201 : FPU,8086 */
        {I_FMUL, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+69790, 325},
    /*   1 : FMUL mem64 [m:        dc /1                             ] FPU,8086 */
        /* 001(dc) 201 : FPU,8086 */
        {I_FMUL, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73097, 325},
    /*   2 : FMUL fpureg|to [r:        dc c8+r                           ] FPU,8086 */
        /* 001(dc) 010 310 : FPU,8086 */
        {I_FMUL, 1, {FPUREG|TO,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72003, 325},
    /*   3 : FMUL fpureg,fpu0 [r-:       dc c8+r                           ] FPU,8086 */
        /* 001(dc) 010 310 : FPU,8086 */
        {I_FMUL, 2, {FPUREG,FPUREG|RN_ZERO,0,0,0}, NO_DECORATOR, nasm_bytecodes+72003, 325},
    /*   4 : FMUL fpureg [r:        d8 c8+r                           ] FPU,8086 */
        /* 001(d8) 010 310 : FPU,8086 */
        {I_FMUL, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72008, 325},
    /*   5 : FMUL fpu0,fpureg [-r:       d8 c8+r                           ] FPU,8086 */
        /* 001(d8) 011 310 : FPU,8086 */
        {I_FMUL, 2, {FPUREG|RN_ZERO,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+72013, 325},
    /*   6 : FMUL void [          de c9                             ] ND,FPU,8086 */
        /* 002(de c9) : FPU,8086 */
        {I_FMUL, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73101, 325},
};

static const struct itemplate instrux_FMULP[3] = {
    /*   0 : FMULP fpureg [r:        de c8+r                           ] FPU,8086 */
        /* 001(de) 010 310 : FPU,8086 */
        {I_FMULP, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72018, 325},
    /*   1 : FMULP fpureg,fpu0 [r-:       de c8+r                           ] FPU,8086 */
        /* 001(de) 010 310 : FPU,8086 */
        {I_FMULP, 2, {FPUREG,FPUREG|RN_ZERO,0,0,0}, NO_DECORATOR, nasm_bytecodes+72018, 325},
    /*   2 : FMULP void [          de c9                             ] ND,FPU,8086 */
        /* 002(de c9) : FPU,8086 */
        {I_FMULP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73101, 325},
};

static const struct itemplate instrux_FNCLEX[1] = {
    /*   0 : FNCLEX void [          db e2                             ] FPU,8086 */
        /* 002(db e2) : FPU,8086 */
        {I_FNCLEX, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71809, 325},
};

static const struct itemplate instrux_FNDISI[1] = {
    /*   0 : FNDISI void [          db e1                             ] FPU,8086 */
        /* 002(db e1) : FPU,8086 */
        {I_FNDISI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71934, 325},
};

static const struct itemplate instrux_FNENI[1] = {
    /*   0 : FNENI void [          db e0                             ] FPU,8086 */
        /* 002(db e0) : FPU,8086 */
        {I_FNENI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71979, 325},
};

static const struct itemplate instrux_FNINIT[1] = {
    /*   0 : FNINIT void [          db e3                             ] FPU,8086 */
        /* 002(db e3) : FPU,8086 */
        {I_FNINIT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71994, 325},
};

static const struct itemplate instrux_FNOP[1] = {
    /*   0 : FNOP void [          d9 d0                             ] FPU,8086 */
        /* 002(d9 d0) : FPU,8086 */
        {I_FNOP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73105, 325},
};

static const struct itemplate instrux_FNSAVE[1] = {
    /*   0 : FNSAVE mem [m:        dd /6                             ] FPU,8086 */
        /* 001(dd) 206 : FPU,8086 */
        {I_FNSAVE, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72024, 325},
};

static const struct itemplate instrux_FNSTCW[1] = {
    /*   0 : FNSTCW mem [m:        d9 /7                             ] AR0,SW,FPU,8086 */
        /* 001(d9) 207 : AR0,SW,FPU,8086 */
        {I_FNSTCW, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72034, 332},
};

static const struct itemplate instrux_FNSTENV[1] = {
    /*   0 : FNSTENV mem [m:        d9 /6                             ] FPU,8086 */
        /* 001(d9) 206 : FPU,8086 */
        {I_FNSTENV, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72039, 325},
};

static const struct itemplate instrux_FNSTSW[2] = {
    /*   0 : FNSTSW mem [m:        dd /7                             ] AR0,SW,FPU,8086 */
        /* 001(dd) 207 : AR0,SW,FPU,8086 */
        {I_FNSTSW, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72049, 332},
    /*   1 : FNSTSW reg_ax [-:        df e0                             ] FPU,286 */
        /* 002(df e0) : FPU,286 */
        {I_FNSTSW, 1, {REG_AX,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72054, 333},
};

static const struct itemplate instrux_FPATAN[1] = {
    /*   0 : FPATAN void [          d9 f3                             ] FPU,8086 */
        /* 002(d9 f3) : FPU,8086 */
        {I_FPATAN, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73109, 325},
};

static const struct itemplate instrux_FPREM[1] = {
    /*   0 : FPREM void [          d9 f8                             ] FPU,8086 */
        /* 002(d9 f8) : FPU,8086 */
        {I_FPREM, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73113, 325},
};

static const struct itemplate instrux_FPREM1[1] = {
    /*   0 : FPREM1 void [          d9 f5                             ] FPU,386 */
        /* 002(d9 f5) : FPU,386 */
        {I_FPREM1, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73117, 328},
};

static const struct itemplate instrux_FPTAN[1] = {
    /*   0 : FPTAN void [          d9 f2                             ] FPU,8086 */
        /* 002(d9 f2) : FPU,8086 */
        {I_FPTAN, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73121, 325},
};

static const struct itemplate instrux_FRNDINT[1] = {
    /*   0 : FRNDINT void [          d9 fc                             ] FPU,8086 */
        /* 002(d9 fc) : FPU,8086 */
        {I_FRNDINT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73125, 325},
};

static const struct itemplate instrux_FRSTOR[1] = {
    /*   0 : FRSTOR mem [m:        dd /4                             ] FPU,8086 */
        /* 001(dd) 204 : FPU,8086 */
        {I_FRSTOR, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73129, 325},
};

static const struct itemplate instrux_FSAVE[1] = {
    /*   0 : FSAVE mem [m:        wait dd /6                        ] FPU,8086 */
        /* 341 001(dd) 206 : FPU,8086 */
        {I_FSAVE, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72023, 325},
};

static const struct itemplate instrux_FSCALE[1] = {
    /*   0 : FSCALE void [          d9 fd                             ] FPU,8086 */
        /* 002(d9 fd) : FPU,8086 */
        {I_FSCALE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73133, 325},
};

static const struct itemplate instrux_FSETPM[1] = {
    /*   0 : FSETPM void [          db e4                             ] FPU,286 */
        /* 002(db e4) : FPU,286 */
        {I_FSETPM, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73137, 333},
};

static const struct itemplate instrux_FSIN[1] = {
    /*   0 : FSIN void [          d9 fe                             ] FPU,386 */
        /* 002(d9 fe) : FPU,386 */
        {I_FSIN, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73141, 328},
};

static const struct itemplate instrux_FSINCOS[1] = {
    /*   0 : FSINCOS void [          d9 fb                             ] FPU,386 */
        /* 002(d9 fb) : FPU,386 */
        {I_FSINCOS, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73145, 328},
};

static const struct itemplate instrux_FSQRT[1] = {
    /*   0 : FSQRT void [          d9 fa                             ] FPU,8086 */
        /* 002(d9 fa) : FPU,8086 */
        {I_FSQRT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73149, 325},
};

static const struct itemplate instrux_FST[4] = {
    /*   0 : FST mem32 [m:        d9 /2                             ] FPU,8086 */
        /* 001(d9) 202 : FPU,8086 */
        {I_FST, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73153, 325},
    /*   1 : FST mem64 [m:        dd /2                             ] FPU,8086 */
        /* 001(dd) 202 : FPU,8086 */
        {I_FST, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73157, 325},
    /*   2 : FST fpureg [r:        dd d0+r                           ] FPU,8086 */
        /* 001(dd) 010 320 : FPU,8086 */
        {I_FST, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72028, 325},
    /*   3 : FST void [          dd d1                             ] ND,FPU,8086 */
        /* 002(dd d1) : FPU,8086 */
        {I_FST, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73161, 325},
};

static const struct itemplate instrux_FSTCW[1] = {
    /*   0 : FSTCW mem [m:        wait d9 /7                        ] AR0,SW,FPU,8086 */
        /* 341 001(d9) 207 : AR0,SW,FPU,8086 */
        {I_FSTCW, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72033, 332},
};

static const struct itemplate instrux_FSTENV[1] = {
    /*   0 : FSTENV mem [m:        wait d9 /6                        ] FPU,8086 */
        /* 341 001(d9) 206 : FPU,8086 */
        {I_FSTENV, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72038, 325},
};

static const struct itemplate instrux_FSTP[5] = {
    /*   0 : FSTP mem32 [m:        d9 /3                             ] FPU,8086 */
        /* 001(d9) 203 : FPU,8086 */
        {I_FSTP, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73165, 325},
    /*   1 : FSTP mem64 [m:        dd /3                             ] FPU,8086 */
        /* 001(dd) 203 : FPU,8086 */
        {I_FSTP, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73169, 325},
    /*   2 : FSTP mem80 [m:        db /7                             ] FPU,8086 */
        /* 001(db) 207 : FPU,8086 */
        {I_FSTP, 1, {MEMORY|BITS80,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73173, 325},
    /*   3 : FSTP fpureg [r:        dd d8+r                           ] FPU,8086 */
        /* 001(dd) 010 330 : FPU,8086 */
        {I_FSTP, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72043, 325},
    /*   4 : FSTP void [          dd d9                             ] ND,FPU,8086 */
        /* 002(dd d9) : FPU,8086 */
        {I_FSTP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73177, 325},
};

static const struct itemplate instrux_FSTSW[2] = {
    /*   0 : FSTSW mem [m:        wait dd /7                        ] AR0,SW,FPU,8086 */
        /* 341 001(dd) 207 : AR0,SW,FPU,8086 */
        {I_FSTSW, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72048, 332},
    /*   1 : FSTSW reg_ax [-:        wait df e0                        ] FPU,286 */
        /* 341 002(df e0) : FPU,286 */
        {I_FSTSW, 1, {REG_AX,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72053, 333},
};

static const struct itemplate instrux_FSUB[7] = {
    /*   0 : FSUB mem32 [m:        d8 /4                             ] FPU,8086 */
        /* 001(d8) 204 : FPU,8086 */
        {I_FSUB, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73181, 325},
    /*   1 : FSUB mem64 [m:        dc /4                             ] FPU,8086 */
        /* 001(dc) 204 : FPU,8086 */
        {I_FSUB, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73185, 325},
    /*   2 : FSUB fpureg|to [r:        dc e8+r                           ] FPU,8086 */
        /* 001(dc) 010 350 : FPU,8086 */
        {I_FSUB, 1, {FPUREG|TO,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72058, 325},
    /*   3 : FSUB fpureg,fpu0 [r-:       dc e8+r                           ] FPU,8086 */
        /* 001(dc) 010 350 : FPU,8086 */
        {I_FSUB, 2, {FPUREG,FPUREG|RN_ZERO,0,0,0}, NO_DECORATOR, nasm_bytecodes+72058, 325},
    /*   4 : FSUB fpureg [r:        d8 e0+r                           ] FPU,8086 */
        /* 001(d8) 010 340 : FPU,8086 */
        {I_FSUB, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72063, 325},
    /*   5 : FSUB fpu0,fpureg [-r:       d8 e0+r                           ] FPU,8086 */
        /* 001(d8) 011 340 : FPU,8086 */
        {I_FSUB, 2, {FPUREG|RN_ZERO,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+72068, 325},
    /*   6 : FSUB void [          de e9                             ] ND,FPU,8086 */
        /* 002(de e9) : FPU,8086 */
        {I_FSUB, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73189, 325},
};

static const struct itemplate instrux_FSUBP[3] = {
    /*   0 : FSUBP fpureg [r:        de e8+r                           ] FPU,8086 */
        /* 001(de) 010 350 : FPU,8086 */
        {I_FSUBP, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72073, 325},
    /*   1 : FSUBP fpureg,fpu0 [r-:       de e8+r                           ] FPU,8086 */
        /* 001(de) 010 350 : FPU,8086 */
        {I_FSUBP, 2, {FPUREG,FPUREG|RN_ZERO,0,0,0}, NO_DECORATOR, nasm_bytecodes+72073, 325},
    /*   2 : FSUBP void [          de e9                             ] ND,FPU,8086 */
        /* 002(de e9) : FPU,8086 */
        {I_FSUBP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73189, 325},
};

static const struct itemplate instrux_FSUBR[7] = {
    /*   0 : FSUBR mem32 [m:        d8 /5                             ] FPU,8086 */
        /* 001(d8) 205 : FPU,8086 */
        {I_FSUBR, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73193, 325},
    /*   1 : FSUBR mem64 [m:        dc /5                             ] FPU,8086 */
        /* 001(dc) 205 : FPU,8086 */
        {I_FSUBR, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73197, 325},
    /*   2 : FSUBR fpureg|to [r:        dc e0+r                           ] FPU,8086 */
        /* 001(dc) 010 340 : FPU,8086 */
        {I_FSUBR, 1, {FPUREG|TO,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72078, 325},
    /*   3 : FSUBR fpureg,fpu0 [r-:       dc e0+r                           ] FPU,8086 */
        /* 001(dc) 010 340 : FPU,8086 */
        {I_FSUBR, 2, {FPUREG,FPUREG|RN_ZERO,0,0,0}, NO_DECORATOR, nasm_bytecodes+72078, 325},
    /*   4 : FSUBR fpureg [r:        d8 e8+r                           ] FPU,8086 */
        /* 001(d8) 010 350 : FPU,8086 */
        {I_FSUBR, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72083, 325},
    /*   5 : FSUBR fpu0,fpureg [-r:       d8 e8+r                           ] FPU,8086 */
        /* 001(d8) 011 350 : FPU,8086 */
        {I_FSUBR, 2, {FPUREG|RN_ZERO,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+72088, 325},
    /*   6 : FSUBR void [          de e1                             ] ND,FPU,8086 */
        /* 002(de e1) : FPU,8086 */
        {I_FSUBR, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73201, 325},
};

static const struct itemplate instrux_FSUBRP[3] = {
    /*   0 : FSUBRP fpureg [r:        de e0+r                           ] FPU,8086 */
        /* 001(de) 010 340 : FPU,8086 */
        {I_FSUBRP, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72093, 325},
    /*   1 : FSUBRP fpureg,fpu0 [r-:       de e0+r                           ] FPU,8086 */
        /* 001(de) 010 340 : FPU,8086 */
        {I_FSUBRP, 2, {FPUREG,FPUREG|RN_ZERO,0,0,0}, NO_DECORATOR, nasm_bytecodes+72093, 325},
    /*   2 : FSUBRP void [          de e1                             ] ND,FPU,8086 */
        /* 002(de e1) : FPU,8086 */
        {I_FSUBRP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73201, 325},
};

static const struct itemplate instrux_FTST[1] = {
    /*   0 : FTST void [          d9 e4                             ] FPU,8086 */
        /* 002(d9 e4) : FPU,8086 */
        {I_FTST, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73205, 325},
};

static const struct itemplate instrux_FUCOM[3] = {
    /*   0 : FUCOM fpureg [r:        dd e0+r                           ] FPU,386 */
        /* 001(dd) 010 340 : FPU,386 */
        {I_FUCOM, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72098, 328},
    /*   1 : FUCOM fpu0,fpureg [-r:       dd e0+r                           ] FPU,386 */
        /* 001(dd) 011 340 : FPU,386 */
        {I_FUCOM, 2, {FPUREG|RN_ZERO,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+72103, 328},
    /*   2 : FUCOM void [          dd e1                             ] ND,FPU,386 */
        /* 002(dd e1) : FPU,386 */
        {I_FUCOM, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73209, 328},
};

static const struct itemplate instrux_FUCOMI[3] = {
    /*   0 : FUCOMI fpureg [r:        db e8+r                           ] FL,FPU,P6 */
        /* 001(db) 010 350 : FL,FPU,P6 */
        {I_FUCOMI, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72108, 327},
    /*   1 : FUCOMI fpu0,fpureg [-r:       db e8+r                           ] FL,FPU,P6 */
        /* 001(db) 011 350 : FL,FPU,P6 */
        {I_FUCOMI, 2, {FPUREG|RN_ZERO,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+72113, 327},
    /*   2 : FUCOMI void [          db e9                             ] ND,FL,FPU,P6 */
        /* 002(db e9) : FL,FPU,P6 */
        {I_FUCOMI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73213, 327},
};

static const struct itemplate instrux_FUCOMIP[3] = {
    /*   0 : FUCOMIP fpureg [r:        df e8+r                           ] FL,FPU,P6 */
        /* 001(df) 010 350 : FL,FPU,P6 */
        {I_FUCOMIP, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72118, 327},
    /*   1 : FUCOMIP fpu0,fpureg [-r:       df e8+r                           ] FL,FPU,P6 */
        /* 001(df) 011 350 : FL,FPU,P6 */
        {I_FUCOMIP, 2, {FPUREG|RN_ZERO,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+72123, 327},
    /*   2 : FUCOMIP void [          df e9                             ] ND,FL,FPU,P6 */
        /* 002(df e9) : FL,FPU,P6 */
        {I_FUCOMIP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73217, 327},
};

static const struct itemplate instrux_FUCOMP[3] = {
    /*   0 : FUCOMP fpureg [r:        dd e8+r                           ] FPU,386 */
        /* 001(dd) 010 350 : FPU,386 */
        {I_FUCOMP, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72128, 328},
    /*   1 : FUCOMP fpu0,fpureg [-r:       dd e8+r                           ] FPU,386 */
        /* 001(dd) 011 350 : FPU,386 */
        {I_FUCOMP, 2, {FPUREG|RN_ZERO,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+72133, 328},
    /*   2 : FUCOMP void [          dd e9                             ] ND,FPU,386 */
        /* 002(dd e9) : FPU,386 */
        {I_FUCOMP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73221, 328},
};

static const struct itemplate instrux_FUCOMPP[1] = {
    /*   0 : FUCOMPP void [          da e9                             ] FPU,386 */
        /* 002(da e9) : FPU,386 */
        {I_FUCOMPP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73225, 328},
};

static const struct itemplate instrux_FXAM[1] = {
    /*   0 : FXAM void [          d9 e5                             ] FPU,8086 */
        /* 002(d9 e5) : FPU,8086 */
        {I_FXAM, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73229, 325},
};

static const struct itemplate instrux_FXCH[4] = {
    /*   0 : FXCH fpureg [r:        d9 c8+r                           ] FPU,8086 */
        /* 001(d9) 010 310 : FPU,8086 */
        {I_FXCH, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72138, 325},
    /*   1 : FXCH fpureg,fpu0 [r-:       d9 c8+r                           ] FPU,8086 */
        /* 001(d9) 010 310 : FPU,8086 */
        {I_FXCH, 2, {FPUREG,FPUREG|RN_ZERO,0,0,0}, NO_DECORATOR, nasm_bytecodes+72138, 325},
    /*   2 : FXCH fpu0,fpureg [-r:       d9 c8+r                           ] FPU,8086 */
        /* 001(d9) 011 310 : FPU,8086 */
        {I_FXCH, 2, {FPUREG|RN_ZERO,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+72143, 325},
    /*   3 : FXCH void [          d9 c9                             ] ND,FPU,8086 */
        /* 002(d9 c9) : FPU,8086 */
        {I_FXCH, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73233, 325},
};

static const struct itemplate instrux_FXTRACT[1] = {
    /*   0 : FXTRACT void [          d9 f4                             ] FPU,8086 */
        /* 002(d9 f4) : FPU,8086 */
        {I_FXTRACT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73237, 325},
};

static const struct itemplate instrux_FYL2X[1] = {
    /*   0 : FYL2X void [          d9 f1                             ] FPU,8086 */
        /* 002(d9 f1) : FPU,8086 */
        {I_FYL2X, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73241, 325},
};

static const struct itemplate instrux_FYL2XP1[1] = {
    /*   0 : FYL2XP1 void [          d9 f9                             ] FPU,8086 */
        /* 002(d9 f9) : FPU,8086 */
        {I_FYL2XP1, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73245, 325},
};

static const struct itemplate instrux_EMMS[1] = {
    /*   0 : EMMS void [          0f 77                             ] MMX,PENT */
        /* 355 001(77) : MMX,PENT */
        {I_EMMS, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73249, 334},
};

static const struct itemplate instrux_MOVD[16] = {
    /*   0 : MOVD mmxreg,rm32 [rm:       np 0f 6e /r                       ] MMX,PENT */
        /* 360 355 001(6e) 110 : MMX,PENT */
        {I_MOVD, 2, {MMXREG,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+67484, 334},
    /*   1 : MOVD rm32,mmxreg [mr:       np 0f 7e /r                       ] MMX,PENT */
        /* 360 355 001(7e) 101 : MMX,PENT */
        {I_MOVD, 2, {RM_GPR|BITS32,MMXREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+67490, 334},
    /*   2 : MOVD mmxreg,rm64 [rm:       np o64 0f 6e /r                   ] ND,LONG,PROT,MMX,X86_64 */
        /* 360 324 355 001(6e) 110 : LONG,PROT,MMX,X86_64 */
        {I_MOVD, 2, {MMXREG,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+57187, 335},
    /*   3 : MOVD rm64,mmxreg [mr:       np o64 0f 7e /r                   ] ND,LONG,PROT,MMX,X86_64 */
        /* 360 324 355 001(7e) 101 : LONG,PROT,MMX,X86_64 */
        {I_MOVD, 2, {RM_GPR|BITS64,MMXREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+57194, 335},
    /*   4 : MOVD mem,xmmreg [mr:       66 norexw 0f 7e /r                ] AR0-1,SD,SSE2,WILLAMETTE */
        /* 361 317 355 001(7e) 101 : AR0,AR1,SD,SSE2,WILLAMETTE */
        {I_MOVD, 2, {MEMORY,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+57810, 385},
    /*   5 : MOVD xmmreg,mem [rm:       66 norexw 0f 6e /r                ] AR0-1,SD,SSE2,WILLAMETTE */
        /* 361 317 355 001(6e) 110 : AR0,AR1,SD,SSE2,WILLAMETTE */
        {I_MOVD, 2, {XMMREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+57817, 385},
    /*   6 : MOVD xmmreg,rm32 [rm:       66 norexw 0f 6e /r                ] SSE2,WILLAMETTE */
        /* 361 317 355 001(6e) 110 : SSE2,WILLAMETTE */
        {I_MOVD, 2, {XMMREG,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+57817, 250},
    /*   7 : MOVD rm32,xmmreg [mr:       66 norexw 0f 7e /r                ] SSE2,WILLAMETTE */
        /* 361 317 355 001(7e) 101 : SSE2,WILLAMETTE */
        {I_MOVD, 2, {RM_GPR|BITS32,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+57810, 250},
    /*   8 : MOVD kreg32,krm32 [rm:       vex.l0.0f.ko32 90 /r             ] ND,ZU,AVX512BW,FUTURE */
        /* 270(001 201) 001(90) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_MOVD, 2, {OPMASKREG|BITS32|RN_L16,RM_OPMASK|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65132, 504},
    /*   9 : MOVD kreg32,krm32 [rm:       evex.l0.0f.ko32 90 /r             ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 250(f1 fd 08) 300 001(90) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_MOVD, 2, {OPMASKREG|BITS32,RM_OPMASK|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+29682, 505},
    /*  10 : MOVD mem32,kreg32 [mr:       vex.l0.0f.ko32 91 /r             ] ND,ZU,AVX512BW,FUTURE */
        /* 270(001 201) 001(91) 101 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_MOVD, 2, {MEMORY|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65160, 504},
    /*  11 : MOVD mem32,kreg32 [mr:       evex.l0.0f.ko32 91 /r             ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 250(f1 fd 08) 300 001(91) 101 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_MOVD, 2, {MEMORY|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+29718, 505},
    /*  12 : MOVD kreg32,reg32 [rm:       vex.l0.0f.f2.w0 92 /r            ] ND,ZU,AVX512BW,FUTURE */
        /* 270(001 003) 001(92) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_MOVD, 2, {OPMASKREG|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65174, 504},
    /*  13 : MOVD kreg32,reg32 [rm:       evex.l0.0f.f2.w0 92 /r            ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 250(f1 7f 08) 300 001(92) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_MOVD, 2, {OPMASKREG|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+29736, 505},
    /*  14 : MOVD reg32,kreg32 [rm:       vex.l0.0f.f2.w0 93 /r            ] ND,ZU,AVX512BW,FUTURE */
        /* 270(001 003) 001(93) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_MOVD, 2, {REG_GPR|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65188, 504},
    /*  15 : MOVD reg32,kreg32 [rm:       evex.l0.0f.f2.w0 93 /r            ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 250(f1 7f 08) 300 001(93) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_MOVD, 2, {REG_GPR|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+29754, 505},
};

static const struct itemplate instrux_MOVQ[18] = {
    /*   0 : MOVQ mmxreg,mmxrm64 [rm:       np 0f 6f /r                       ] MMX,PENT */
        /* 360 355 001(6f) 110 : MMX,PENT */
        {I_MOVQ, 2, {MMXREG,RM_MMX|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+67496, 334},
    /*   1 : MOVQ mmxrm64,mmxreg [mr:       np 0f 7f /r                       ] MMX,PENT */
        /* 360 355 001(7f) 101 : MMX,PENT */
        {I_MOVQ, 2, {RM_MMX|BITS64,MMXREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+67502, 334},
    /*   2 : MOVQ mmxreg,rm64 [rm:       np o64 0f 6e /r                   ] LONG,PROT,MMX,X86_64 */
        /* 360 324 355 001(6e) 110 : LONG,PROT,MMX,X86_64 */
        {I_MOVQ, 2, {MMXREG,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+57187, 335},
    /*   3 : MOVQ rm64,mmxreg [mr:       np o64 0f 7e /r                   ] LONG,PROT,MMX,X86_64 */
        /* 360 324 355 001(7e) 101 : LONG,PROT,MMX,X86_64 */
        {I_MOVQ, 2, {RM_GPR|BITS64,MMXREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+57194, 335},
    /*   4 : MOVQ xmmreg,xmmreg [rm:       f3 0f 7e /r                       ] SSE2,WILLAMETTE */
        /* 333 355 001(7e) 110 : SSE2,WILLAMETTE */
        {I_MOVQ, 2, {XMMREG,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+68570, 250},
    /*   5 : MOVQ xmmreg,xmmreg [mr:       66 0f d6 /r                       ] SSE2,WILLAMETTE */
        /* 361 355 001(d6) 101 : SSE2,WILLAMETTE */
        {I_MOVQ, 2, {XMMREG,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+68576, 250},
    /*   6 : MOVQ mem,xmmreg [mr:       66 0f d6 /r                       ] AR0-1,SQ,SSE2,WILLAMETTE */
        /* 361 355 001(d6) 101 : AR0,AR1,SQ,SSE2,WILLAMETTE */
        {I_MOVQ, 2, {MEMORY,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+68576, 386},
    /*   7 : MOVQ xmmreg,mem [rm:       f3 0f 7e /r                       ] AR0-1,SQ,SSE2,WILLAMETTE */
        /* 333 355 001(7e) 110 : AR0,AR1,SQ,SSE2,WILLAMETTE */
        {I_MOVQ, 2, {XMMREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+68570, 386},
    /*   8 : MOVQ xmmreg,rm64 [rm:       66 o64 0f 6e /r                   ] LONG,PROT,SSE2,X86_64 */
        /* 361 324 355 001(6e) 110 : LONG,PROT,SSE2,X86_64 */
        {I_MOVQ, 2, {XMMREG,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+57824, 387},
    /*   9 : MOVQ rm64,xmmreg [mr:       66 o64 0f 7e /r                   ] LONG,PROT,SSE2,X86_64 */
        /* 361 324 355 001(7e) 101 : LONG,PROT,SSE2,X86_64 */
        {I_MOVQ, 2, {RM_GPR|BITS64,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+57831, 387},
    /*  10 : MOVQ kreg64,krm64 [rm:       vex.l0.0f.ko64 90 /r             ] ND,ZU,AVX512BW,FUTURE */
        /* 270(001 200) 001(90) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_MOVQ, 2, {OPMASKREG|BITS64|RN_L16,RM_OPMASK|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65139, 504},
    /*  11 : MOVQ kreg64,krm64 [rm:       evex.l0.0f.ko64 90 /r             ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 250(f1 fc 08) 300 001(90) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_MOVQ, 2, {OPMASKREG|BITS64,RM_OPMASK|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+29691, 505},
    /*  12 : MOVQ mem64,kreg64 [mr:       vex.l0.0f.ko64 91 /r             ] ND,ZU,AVX512BW,FUTURE */
        /* 270(001 200) 001(91) 101 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_MOVQ, 2, {MEMORY|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65167, 504},
    /*  13 : MOVQ mem64,kreg64 [mr:       evex.l0.0f.ko64 91 /r             ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 250(f1 fc 08) 300 001(91) 101 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_MOVQ, 2, {MEMORY|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+29727, 505},
    /*  14 : MOVQ kreg64,reg64 [rm:       vex.l0.0f.f2.w1 92 /r            ] ND,ZU,LONG,PROT,AVX512BW,X86_64 */
        /* 270(001 203) 001(92) 110 : NOAPX,ZU,LONG,VEX,PROT,AVX512BW,X86_64 */
        {I_MOVQ, 2, {OPMASKREG|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65181, 506},
    /*  15 : MOVQ kreg64,reg64 [rm:       evex.l0.0f.f2.w1 92 /r            ] ND,ZU,LONG,PROT,AVX512BW,X86_64,APX */
        /* 250(f1 ff 08) 300 001(92) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,X86_64 */
        {I_MOVQ, 2, {OPMASKREG|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+29745, 507},
    /*  16 : MOVQ reg64,kreg64 [rm:       vex.l0.0f.f2.w1 93 /r            ] ND,ZU,LONG,PROT,AVX512BW,X86_64 */
        /* 270(001 203) 001(93) 110 : NOAPX,ZU,LONG,VEX,PROT,AVX512BW,X86_64 */
        {I_MOVQ, 2, {REG_GPR|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65195, 506},
    /*  17 : MOVQ reg64,kreg64 [rm:       evex.l0.0f.f2.w1 93 /r            ] ND,ZU,LONG,PROT,AVX512BW,X86_64,APX */
        /* 250(f1 ff 08) 300 001(93) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,X86_64 */
        {I_MOVQ, 2, {REG_GPR|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+29763, 507},
};

static const struct itemplate instrux_PACKSSDW[2] = {
    /*   0 : PACKSSDW mmxreg,mmxrm [rm:       np 0f 6b /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(6b) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PACKSSDW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67508, 336},
    /*   1 : PACKSSDW xmmreg,xmmrm [rm:       66 0f 6b /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(6b) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PACKSSDW, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68594, 382},
};

static const struct itemplate instrux_PACKSSWB[2] = {
    /*   0 : PACKSSWB mmxreg,mmxrm [rm:       np 0f 63 /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(63) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PACKSSWB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67514, 336},
    /*   1 : PACKSSWB xmmreg,xmmrm [rm:       66 0f 63 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(63) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PACKSSWB, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68588, 382},
};

static const struct itemplate instrux_PACKUSWB[2] = {
    /*   0 : PACKUSWB mmxreg,mmxrm [rm:       np 0f 67 /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(67) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PACKUSWB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67520, 336},
    /*   1 : PACKUSWB xmmreg,xmmrm [rm:       66 0f 67 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(67) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PACKUSWB, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68600, 382},
};

static const struct itemplate instrux_PADDB[2] = {
    /*   0 : PADDB mmxreg,mmxrm [rm:       np 0f fc /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(fc) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PADDB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67526, 336},
    /*   1 : PADDB xmmreg,xmmrm [rm:       66 0f fc /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(fc) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PADDB, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68606, 382},
};

static const struct itemplate instrux_PADDD[2] = {
    /*   0 : PADDD mmxreg,mmxrm [rm:       np 0f fe /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(fe) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PADDD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67532, 336},
    /*   1 : PADDD xmmreg,xmmrm [rm:       66 0f fe /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(fe) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PADDD, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68618, 382},
};

static const struct itemplate instrux_PADDSB[2] = {
    /*   0 : PADDSB mmxreg,mmxrm [rm:       np 0f ec /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(ec) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PADDSB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67538, 336},
    /*   1 : PADDSB xmmreg,xmmrm [rm:       66 0f ec /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(ec) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PADDSB, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68636, 382},
};

static const struct itemplate instrux_PADDSIW[1] = {
    /*   0 : PADDSIW mmxreg,mmxrm [rm:       0f 51 /r                          ] AR0-1,SQ,MMX,PENT,CYRIX */
        /* 355 001(51) 110 : AR0,AR1,SQ,MMX,PENT,CYRIX */
        {I_PADDSIW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+69189, 337},
};

static const struct itemplate instrux_PADDSW[2] = {
    /*   0 : PADDSW mmxreg,mmxrm [rm:       np 0f ed /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(ed) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PADDSW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67544, 336},
    /*   1 : PADDSW xmmreg,xmmrm [rm:       66 0f ed /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(ed) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PADDSW, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68642, 382},
};

static const struct itemplate instrux_PADDUSB[2] = {
    /*   0 : PADDUSB mmxreg,mmxrm [rm:       np 0f dc /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(dc) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PADDUSB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67550, 336},
    /*   1 : PADDUSB xmmreg,xmmrm [rm:       66 0f dc /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(dc) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PADDUSB, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68648, 382},
};

static const struct itemplate instrux_PADDUSW[2] = {
    /*   0 : PADDUSW mmxreg,mmxrm [rm:       np 0f dd /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(dd) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PADDUSW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67556, 336},
    /*   1 : PADDUSW xmmreg,xmmrm [rm:       66 0f dd /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(dd) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PADDUSW, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68654, 382},
};

static const struct itemplate instrux_PADDW[2] = {
    /*   0 : PADDW mmxreg,mmxrm [rm:       np 0f fd /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(fd) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PADDW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67562, 336},
    /*   1 : PADDW xmmreg,xmmrm [rm:       66 0f fd /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(fd) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PADDW, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68612, 382},
};

static const struct itemplate instrux_PAND[2] = {
    /*   0 : PAND mmxreg,mmxrm [rm:       np 0f db /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(db) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PAND, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67568, 336},
    /*   1 : PAND xmmreg,xmmrm [rm:       66 0f db /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(db) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PAND, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68660, 382},
};

static const struct itemplate instrux_PANDN[2] = {
    /*   0 : PANDN mmxreg,mmxrm [rm:       np 0f df /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(df) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PANDN, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67574, 336},
    /*   1 : PANDN xmmreg,xmmrm [rm:       66 0f df /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(df) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PANDN, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68666, 382},
};

static const struct itemplate instrux_PAVEB[1] = {
    /*   0 : PAVEB mmxreg,mmxrm [rm:       0f 50 /r                          ] AR0-1,SQ,MMX,PENT,CYRIX */
        /* 355 001(50) 110 : AR0,AR1,SQ,MMX,PENT,CYRIX */
        {I_PAVEB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+69135, 337},
};

static const struct itemplate instrux_PAVGUSB[1] = {
    /*   0 : PAVGUSB mmxreg,mmxrm [rm:       0f 0f /r bf                       ] AR0-1,SQ,3DNOW,PENT */
        /* 355 001(0f) 110 001(bf) : AR0,AR1,SQ,3DNOW,PENT */
        {I_PAVGUSB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+57201, 338},
};

static const struct itemplate instrux_PCMPEQB[2] = {
    /*   0 : PCMPEQB mmxreg,mmxrm [rm:       np 0f 74 /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(74) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PCMPEQB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67580, 336},
    /*   1 : PCMPEQB xmmreg,xmmrm [rm:       66 0f 74 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(74) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PCMPEQB, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68684, 382},
};

static const struct itemplate instrux_PCMPEQD[2] = {
    /*   0 : PCMPEQD mmxreg,mmxrm [rm:       np 0f 76 /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(76) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PCMPEQD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67586, 336},
    /*   1 : PCMPEQD xmmreg,xmmrm [rm:       66 0f 76 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(76) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PCMPEQD, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68696, 382},
};

static const struct itemplate instrux_PCMPEQW[2] = {
    /*   0 : PCMPEQW mmxreg,mmxrm [rm:       np 0f 75 /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(75) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PCMPEQW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67592, 336},
    /*   1 : PCMPEQW xmmreg,xmmrm [rm:       66 0f 75 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(75) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PCMPEQW, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68690, 382},
};

static const struct itemplate instrux_PCMPGTB[2] = {
    /*   0 : PCMPGTB mmxreg,mmxrm [rm:       np 0f 64 /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(64) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PCMPGTB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67598, 336},
    /*   1 : PCMPGTB xmmreg,xmmrm [rm:       66 0f 64 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(64) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PCMPGTB, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68702, 382},
};

static const struct itemplate instrux_PCMPGTD[2] = {
    /*   0 : PCMPGTD mmxreg,mmxrm [rm:       np 0f 66 /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(66) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PCMPGTD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67604, 336},
    /*   1 : PCMPGTD xmmreg,xmmrm [rm:       66 0f 66 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(66) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PCMPGTD, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68714, 382},
};

static const struct itemplate instrux_PCMPGTW[2] = {
    /*   0 : PCMPGTW mmxreg,mmxrm [rm:       np 0f 65 /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(65) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PCMPGTW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67610, 336},
    /*   1 : PCMPGTW xmmreg,xmmrm [rm:       66 0f 65 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(65) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PCMPGTW, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68708, 382},
};

static const struct itemplate instrux_PDISTIB[1] = {
    /*   0 : PDISTIB mmxreg,mem [rm:       0f 54 /r                          ] AR0-1,SQ,MMX,PENT,CYRIX */
        /* 355 001(54) 110 : AR0,AR1,SQ,MMX,PENT,CYRIX */
        {I_PDISTIB, 2, {MMXREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+68973, 337},
};

static const struct itemplate instrux_PF2ID[1] = {
    /*   0 : PF2ID mmxreg,mmxrm [rm:       0f 0f /r 1d                       ] AR0-1,SQ,3DNOW,PENT */
        /* 355 001(0f) 110 001(1d) : AR0,AR1,SQ,3DNOW,PENT */
        {I_PF2ID, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+57208, 338},
};

static const struct itemplate instrux_PFACC[1] = {
    /*   0 : PFACC mmxreg,mmxrm [rm:       0f 0f /r ae                       ] AR0-1,SQ,3DNOW,PENT */
        /* 355 001(0f) 110 001(ae) : AR0,AR1,SQ,3DNOW,PENT */
        {I_PFACC, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+57215, 338},
};

static const struct itemplate instrux_PFADD[1] = {
    /*   0 : PFADD mmxreg,mmxrm [rm:       0f 0f /r 9e                       ] AR0-1,SQ,3DNOW,PENT */
        /* 355 001(0f) 110 001(9e) : AR0,AR1,SQ,3DNOW,PENT */
        {I_PFADD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+57222, 338},
};

static const struct itemplate instrux_PFCMPEQ[1] = {
    /*   0 : PFCMPEQ mmxreg,mmxrm [rm:       0f 0f /r b0                       ] AR0-1,SQ,3DNOW,PENT */
        /* 355 001(0f) 110 001(b0) : AR0,AR1,SQ,3DNOW,PENT */
        {I_PFCMPEQ, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+57229, 338},
};

static const struct itemplate instrux_PFCMPGE[1] = {
    /*   0 : PFCMPGE mmxreg,mmxrm [rm:       0f 0f /r 90                       ] AR0-1,SQ,3DNOW,PENT */
        /* 355 001(0f) 110 001(90) : AR0,AR1,SQ,3DNOW,PENT */
        {I_PFCMPGE, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+57236, 338},
};

static const struct itemplate instrux_PFCMPGT[1] = {
    /*   0 : PFCMPGT mmxreg,mmxrm [rm:       0f 0f /r a0                       ] AR0-1,SQ,3DNOW,PENT */
        /* 355 001(0f) 110 001(a0) : AR0,AR1,SQ,3DNOW,PENT */
        {I_PFCMPGT, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+57243, 338},
};

static const struct itemplate instrux_PFMAX[1] = {
    /*   0 : PFMAX mmxreg,mmxrm [rm:       0f 0f /r a4                       ] AR0-1,SQ,3DNOW,PENT */
        /* 355 001(0f) 110 001(a4) : AR0,AR1,SQ,3DNOW,PENT */
        {I_PFMAX, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+57250, 338},
};

static const struct itemplate instrux_PFMIN[1] = {
    /*   0 : PFMIN mmxreg,mmxrm [rm:       0f 0f /r 94                       ] AR0-1,SQ,3DNOW,PENT */
        /* 355 001(0f) 110 001(94) : AR0,AR1,SQ,3DNOW,PENT */
        {I_PFMIN, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+57257, 338},
};

static const struct itemplate instrux_PFMUL[1] = {
    /*   0 : PFMUL mmxreg,mmxrm [rm:       0f 0f /r b4                       ] AR0-1,SQ,3DNOW,PENT */
        /* 355 001(0f) 110 001(b4) : AR0,AR1,SQ,3DNOW,PENT */
        {I_PFMUL, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+57264, 338},
};

static const struct itemplate instrux_PFRCP[1] = {
    /*   0 : PFRCP mmxreg,mmxrm [rm:       0f 0f /r 96                       ] AR0-1,SQ,3DNOW,PENT */
        /* 355 001(0f) 110 001(96) : AR0,AR1,SQ,3DNOW,PENT */
        {I_PFRCP, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+57271, 338},
};

static const struct itemplate instrux_PFRCPIT1[1] = {
    /*   0 : PFRCPIT1 mmxreg,mmxrm [rm:       0f 0f /r a6                       ] AR0-1,SQ,3DNOW,PENT */
        /* 355 001(0f) 110 001(a6) : AR0,AR1,SQ,3DNOW,PENT */
        {I_PFRCPIT1, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+57278, 338},
};

static const struct itemplate instrux_PFRCPIT2[1] = {
    /*   0 : PFRCPIT2 mmxreg,mmxrm [rm:       0f 0f /r b6                       ] AR0-1,SQ,3DNOW,PENT */
        /* 355 001(0f) 110 001(b6) : AR0,AR1,SQ,3DNOW,PENT */
        {I_PFRCPIT2, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+57285, 338},
};

static const struct itemplate instrux_PFRSQIT1[1] = {
    /*   0 : PFRSQIT1 mmxreg,mmxrm [rm:       0f 0f /r a7                       ] AR0-1,SQ,3DNOW,PENT */
        /* 355 001(0f) 110 001(a7) : AR0,AR1,SQ,3DNOW,PENT */
        {I_PFRSQIT1, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+57292, 338},
};

static const struct itemplate instrux_PFRSQRT[1] = {
    /*   0 : PFRSQRT mmxreg,mmxrm [rm:       0f 0f /r 97                       ] AR0-1,SQ,3DNOW,PENT */
        /* 355 001(0f) 110 001(97) : AR0,AR1,SQ,3DNOW,PENT */
        {I_PFRSQRT, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+57299, 338},
};

static const struct itemplate instrux_PFSUB[1] = {
    /*   0 : PFSUB mmxreg,mmxrm [rm:       0f 0f /r 9a                       ] AR0-1,SQ,3DNOW,PENT */
        /* 355 001(0f) 110 001(9a) : AR0,AR1,SQ,3DNOW,PENT */
        {I_PFSUB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+57306, 338},
};

static const struct itemplate instrux_PFSUBR[1] = {
    /*   0 : PFSUBR mmxreg,mmxrm [rm:       0f 0f /r aa                       ] AR0-1,SQ,3DNOW,PENT */
        /* 355 001(0f) 110 001(aa) : AR0,AR1,SQ,3DNOW,PENT */
        {I_PFSUBR, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+57313, 338},
};

static const struct itemplate instrux_PI2FD[1] = {
    /*   0 : PI2FD mmxreg,mmxrm [rm:       0f 0f /r 0d                       ] AR0-1,SQ,3DNOW,PENT */
        /* 355 001(0f) 110 001(0d) : AR0,AR1,SQ,3DNOW,PENT */
        {I_PI2FD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+57320, 338},
};

static const struct itemplate instrux_PMACHRIW[1] = {
    /*   0 : PMACHRIW mmxreg,mem [rm:       0f 5e /r                          ] AR0-1,SQ,MMX,PENT,CYRIX */
        /* 355 001(5e) 110 : AR0,AR1,SQ,MMX,PENT,CYRIX */
        {I_PMACHRIW, 2, {MMXREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+69069, 337},
};

static const struct itemplate instrux_PMADDWD[2] = {
    /*   0 : PMADDWD mmxreg,mmxrm [rm:       np 0f f5 /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(f5) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PMADDWD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67616, 336},
    /*   1 : PMADDWD xmmreg,xmmrm [rm:       66 0f f5 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(f5) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PMADDWD, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68720, 382},
};

static const struct itemplate instrux_PMAGW[1] = {
    /*   0 : PMAGW mmxreg,mmxrm [rm:       0f 52 /r                          ] AR0-1,SQ,MMX,PENT,CYRIX */
        /* 355 001(52) 110 : AR0,AR1,SQ,MMX,PENT,CYRIX */
        {I_PMAGW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+68397, 337},
};

static const struct itemplate instrux_PMULHRIW[1] = {
    /*   0 : PMULHRIW mmxreg,mmxrm [rm:       0f 5d /r                          ] AR0-1,SQ,MMX,PENT,CYRIX */
        /* 355 001(5d) 110 : AR0,AR1,SQ,MMX,PENT,CYRIX */
        {I_PMULHRIW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+69093, 337},
};

static const struct itemplate instrux_PMULHRWA[1] = {
    /*   0 : PMULHRWA mmxreg,mmxrm [rm:       0f 0f /r b7                       ] AR0-1,SQ,3DNOW,PENT */
        /* 355 001(0f) 110 001(b7) : AR0,AR1,SQ,3DNOW,PENT */
        {I_PMULHRWA, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+57327, 338},
};

static const struct itemplate instrux_PMULHRWC[1] = {
    /*   0 : PMULHRWC mmxreg,mmxrm [rm:       0f 59 /r                          ] AR0-1,SQ,MMX,PENT,CYRIX */
        /* 355 001(59) 110 : AR0,AR1,SQ,MMX,PENT,CYRIX */
        {I_PMULHRWC, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+69171, 337},
};

static const struct itemplate instrux_PMULHW[2] = {
    /*   0 : PMULHW mmxreg,mmxrm [rm:       np 0f e5 /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(e5) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PMULHW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67622, 336},
    /*   1 : PMULHW xmmreg,xmmrm [rm:       66 0f e5 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(e5) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PMULHW, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68762, 382},
};

static const struct itemplate instrux_PMULLW[2] = {
    /*   0 : PMULLW mmxreg,mmxrm [rm:       np 0f d5 /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(d5) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PMULLW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67628, 336},
    /*   1 : PMULLW xmmreg,xmmrm [rm:       66 0f d5 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(d5) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PMULLW, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68768, 382},
};

static const struct itemplate instrux_PMVGEZB[1] = {
    /*   0 : PMVGEZB mmxreg,mem [rm:       0f 5c /r                          ] AR0-1,SQ,MMX,PENT,CYRIX */
        /* 355 001(5c) 110 : AR0,AR1,SQ,MMX,PENT,CYRIX */
        {I_PMVGEZB, 2, {MMXREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+69201, 337},
};

static const struct itemplate instrux_PMVLZB[1] = {
    /*   0 : PMVLZB mmxreg,mem [rm:       0f 5b /r                          ] AR0-1,SQ,MMX,PENT,CYRIX */
        /* 355 001(5b) 110 : AR0,AR1,SQ,MMX,PENT,CYRIX */
        {I_PMVLZB, 2, {MMXREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+69057, 337},
};

static const struct itemplate instrux_PMVNZB[1] = {
    /*   0 : PMVNZB mmxreg,mem [rm:       0f 5a /r                          ] AR0-1,SQ,MMX,PENT,CYRIX */
        /* 355 001(5a) 110 : AR0,AR1,SQ,MMX,PENT,CYRIX */
        {I_PMVNZB, 2, {MMXREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+69039, 337},
};

static const struct itemplate instrux_PMVZB[1] = {
    /*   0 : PMVZB mmxreg,mem [rm:       0f 58 /r                          ] AR0-1,SQ,MMX,PENT,CYRIX */
        /* 355 001(58) 110 : AR0,AR1,SQ,MMX,PENT,CYRIX */
        {I_PMVZB, 2, {MMXREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+68961, 337},
};

static const struct itemplate instrux_POR[2] = {
    /*   0 : POR mmxreg,mmxrm [rm:       np 0f eb /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(eb) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_POR, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67634, 336},
    /*   1 : POR xmmreg,xmmrm [rm:       66 0f eb /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(eb) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_POR, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68786, 382},
};

static const struct itemplate instrux_PREFETCH[1] = {
    /*   0 : PREFETCH mem [m:        0f 0d /0                          ] AR0,SQ,3DNOW,PENT */
        /* 355 001(0d) 200 : AR0,SQ,3DNOW,PENT */
        {I_PREFETCH, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72148, 339},
};

static const struct itemplate instrux_PREFETCHW[1] = {
    /*   0 : PREFETCHW mem [m:        0f 0d /1                          ] AR0,SQ,3DNOW,PENT */
        /* 355 001(0d) 201 : AR0,SQ,3DNOW,PENT */
        {I_PREFETCHW, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72153, 339},
};

static const struct itemplate instrux_PSLLD[4] = {
    /*   0 : PSLLD mmxreg,mmxrm [rm:       np 0f f2 /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(f2) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PSLLD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67640, 336},
    /*   1 : PSLLD mmxreg,imm [mi:       np 0f 72 /6 ib,u                  ] MMX,PENT */
        /* 360 355 001(72) 206 025 : MMX,PENT */
        {I_PSLLD, 2, {MMXREG,IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+57334, 334},
    /*   2 : PSLLD xmmreg,xmmrm [rm:       66 0f f2 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(f2) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PSLLD, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68804, 382},
    /*   3 : PSLLD xmmreg,imm [mi:       66 0f 72 /6 ib,u                  ] AR1,SB,SSE2,WILLAMETTE */
        /* 361 355 001(72) 206 025 : AR1,SB,SSE2,WILLAMETTE */
        {I_PSLLD, 2, {XMMREG,IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+57887, 391},
};

static const struct itemplate instrux_PSLLQ[4] = {
    /*   0 : PSLLQ mmxreg,mmxrm [rm:       np 0f f3 /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(f3) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PSLLQ, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67646, 336},
    /*   1 : PSLLQ mmxreg,imm [mi:       np 0f 73 /6 ib,u                  ] MMX,PENT */
        /* 360 355 001(73) 206 025 : MMX,PENT */
        {I_PSLLQ, 2, {MMXREG,IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+57341, 334},
    /*   2 : PSLLQ xmmreg,xmmrm [rm:       66 0f f3 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(f3) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PSLLQ, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68810, 382},
    /*   3 : PSLLQ xmmreg,imm [mi:       66 0f 73 /6 ib,u                  ] AR1,SB,SSE2,WILLAMETTE */
        /* 361 355 001(73) 206 025 : AR1,SB,SSE2,WILLAMETTE */
        {I_PSLLQ, 2, {XMMREG,IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+57894, 391},
};

static const struct itemplate instrux_PSLLW[4] = {
    /*   0 : PSLLW mmxreg,mmxrm [rm:       np 0f f1 /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(f1) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PSLLW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67652, 336},
    /*   1 : PSLLW mmxreg,imm [mi:       np 0f 71 /6 ib,u                  ] MMX,PENT */
        /* 360 355 001(71) 206 025 : MMX,PENT */
        {I_PSLLW, 2, {MMXREG,IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+57348, 334},
    /*   2 : PSLLW xmmreg,xmmrm [rm:       66 0f f1 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(f1) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PSLLW, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68798, 382},
    /*   3 : PSLLW xmmreg,imm [mi:       66 0f 71 /6 ib,u                  ] AR1,SB,SSE2,WILLAMETTE */
        /* 361 355 001(71) 206 025 : AR1,SB,SSE2,WILLAMETTE */
        {I_PSLLW, 2, {XMMREG,IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+57880, 391},
};

static const struct itemplate instrux_PSRAD[4] = {
    /*   0 : PSRAD mmxreg,mmxrm [rm:       np 0f e2 /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(e2) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PSRAD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67658, 336},
    /*   1 : PSRAD mmxreg,imm [mi:       np 0f 72 /4 ib,u                  ] MMX,PENT */
        /* 360 355 001(72) 204 025 : MMX,PENT */
        {I_PSRAD, 2, {MMXREG,IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+57355, 334},
    /*   2 : PSRAD xmmreg,xmmrm [rm:       66 0f e2 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(e2) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PSRAD, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68822, 382},
    /*   3 : PSRAD xmmreg,imm [mi:       66 0f 72 /4 ib,u                  ] AR1,SB,SSE2,WILLAMETTE */
        /* 361 355 001(72) 204 025 : AR1,SB,SSE2,WILLAMETTE */
        {I_PSRAD, 2, {XMMREG,IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+57908, 391},
};

static const struct itemplate instrux_PSRAW[4] = {
    /*   0 : PSRAW mmxreg,mmxrm [rm:       np 0f e1 /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(e1) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PSRAW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67664, 336},
    /*   1 : PSRAW mmxreg,imm [mi:       np 0f 71 /4 ib,u                  ] MMX,PENT */
        /* 360 355 001(71) 204 025 : MMX,PENT */
        {I_PSRAW, 2, {MMXREG,IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+57362, 334},
    /*   2 : PSRAW xmmreg,xmmrm [rm:       66 0f e1 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(e1) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PSRAW, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68816, 382},
    /*   3 : PSRAW xmmreg,imm [mi:       66 0f 71 /4 ib,u                  ] AR1,SB,SSE2,WILLAMETTE */
        /* 361 355 001(71) 204 025 : AR1,SB,SSE2,WILLAMETTE */
        {I_PSRAW, 2, {XMMREG,IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+57901, 391},
};

static const struct itemplate instrux_PSRLD[4] = {
    /*   0 : PSRLD mmxreg,mmxrm [rm:       np 0f d2 /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(d2) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PSRLD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67670, 336},
    /*   1 : PSRLD mmxreg,imm [mi:       np 0f 72 /2 ib,u                  ] MMX,PENT */
        /* 360 355 001(72) 202 025 : MMX,PENT */
        {I_PSRLD, 2, {MMXREG,IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+57369, 334},
    /*   2 : PSRLD xmmreg,xmmrm [rm:       66 0f d2 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(d2) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PSRLD, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68834, 382},
    /*   3 : PSRLD xmmreg,imm [mi:       66 0f 72 /2 ib,u                  ] AR1,SB,SSE2,WILLAMETTE */
        /* 361 355 001(72) 202 025 : AR1,SB,SSE2,WILLAMETTE */
        {I_PSRLD, 2, {XMMREG,IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+57929, 391},
};

static const struct itemplate instrux_PSRLQ[4] = {
    /*   0 : PSRLQ mmxreg,mmxrm [rm:       np 0f d3 /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(d3) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PSRLQ, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67676, 336},
    /*   1 : PSRLQ mmxreg,imm [mi:       np 0f 73 /2 ib,u                  ] MMX,PENT */
        /* 360 355 001(73) 202 025 : MMX,PENT */
        {I_PSRLQ, 2, {MMXREG,IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+57376, 334},
    /*   2 : PSRLQ xmmreg,xmmrm [rm:       66 0f d3 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(d3) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PSRLQ, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68840, 382},
    /*   3 : PSRLQ xmmreg,imm [mi:       66 0f 73 /2 ib,u                  ] AR1,SB,SSE2,WILLAMETTE */
        /* 361 355 001(73) 202 025 : AR1,SB,SSE2,WILLAMETTE */
        {I_PSRLQ, 2, {XMMREG,IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+57936, 391},
};

static const struct itemplate instrux_PSRLW[4] = {
    /*   0 : PSRLW mmxreg,mmxrm [rm:       np 0f d1 /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(d1) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PSRLW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67682, 336},
    /*   1 : PSRLW mmxreg,imm [mi:       np 0f 71 /2 ib,u                  ] MMX,PENT */
        /* 360 355 001(71) 202 025 : MMX,PENT */
        {I_PSRLW, 2, {MMXREG,IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+57383, 334},
    /*   2 : PSRLW xmmreg,xmmrm [rm:       66 0f d1 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(d1) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PSRLW, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68828, 382},
    /*   3 : PSRLW xmmreg,imm [mi:       66 0f 71 /2 ib,u                  ] AR1,SB,SSE2,WILLAMETTE */
        /* 361 355 001(71) 202 025 : AR1,SB,SSE2,WILLAMETTE */
        {I_PSRLW, 2, {XMMREG,IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+57922, 391},
};

static const struct itemplate instrux_PSUBB[2] = {
    /*   0 : PSUBB mmxreg,mmxrm [rm:       np 0f f8 /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(f8) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PSUBB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67688, 336},
    /*   1 : PSUBB xmmreg,xmmrm [rm:       66 0f f8 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(f8) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PSUBB, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68846, 382},
};

static const struct itemplate instrux_PSUBD[2] = {
    /*   0 : PSUBD mmxreg,mmxrm [rm:       np 0f fa /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(fa) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PSUBD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67694, 336},
    /*   1 : PSUBD xmmreg,xmmrm [rm:       66 0f fa /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(fa) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PSUBD, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68858, 382},
};

static const struct itemplate instrux_PSUBSB[2] = {
    /*   0 : PSUBSB mmxreg,mmxrm [rm:       np 0f e8 /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(e8) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PSUBSB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67700, 336},
    /*   1 : PSUBSB xmmreg,xmmrm [rm:       66 0f e8 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(e8) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PSUBSB, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68876, 382},
};

static const struct itemplate instrux_PSUBSIW[1] = {
    /*   0 : PSUBSIW mmxreg,mmxrm [rm:       0f 55 /r                          ] AR0-1,SQ,MMX,PENT,CYRIX */
        /* 355 001(55) 110 : AR0,AR1,SQ,MMX,PENT,CYRIX */
        {I_PSUBSIW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+68967, 337},
};

static const struct itemplate instrux_PSUBSW[2] = {
    /*   0 : PSUBSW mmxreg,mmxrm [rm:       np 0f e9 /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(e9) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PSUBSW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67706, 336},
    /*   1 : PSUBSW xmmreg,xmmrm [rm:       66 0f e9 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(e9) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PSUBSW, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68882, 382},
};

static const struct itemplate instrux_PSUBUSB[2] = {
    /*   0 : PSUBUSB mmxreg,mmxrm [rm:       np 0f d8 /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(d8) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PSUBUSB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67712, 336},
    /*   1 : PSUBUSB xmmreg,xmmrm [rm:       66 0f d8 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(d8) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PSUBUSB, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68888, 382},
};

static const struct itemplate instrux_PSUBUSW[2] = {
    /*   0 : PSUBUSW mmxreg,mmxrm [rm:       np 0f d9 /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(d9) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PSUBUSW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67718, 336},
    /*   1 : PSUBUSW xmmreg,xmmrm [rm:       66 0f d9 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(d9) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PSUBUSW, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68894, 382},
};

static const struct itemplate instrux_PSUBW[2] = {
    /*   0 : PSUBW mmxreg,mmxrm [rm:       np 0f f9 /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(f9) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PSUBW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67724, 336},
    /*   1 : PSUBW xmmreg,xmmrm [rm:       66 0f f9 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(f9) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PSUBW, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68852, 382},
};

static const struct itemplate instrux_PUNPCKHBW[2] = {
    /*   0 : PUNPCKHBW mmxreg,mmxrm [rm:       np 0f 68 /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(68) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PUNPCKHBW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67730, 336},
    /*   1 : PUNPCKHBW xmmreg,xmmrm [rm:       66 0f 68 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(68) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PUNPCKHBW, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68900, 382},
};

static const struct itemplate instrux_PUNPCKHDQ[2] = {
    /*   0 : PUNPCKHDQ mmxreg,mmxrm [rm:       np 0f 6a /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(6a) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PUNPCKHDQ, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67736, 336},
    /*   1 : PUNPCKHDQ xmmreg,xmmrm [rm:       66 0f 6a /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(6a) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PUNPCKHDQ, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68912, 382},
};

static const struct itemplate instrux_PUNPCKHWD[2] = {
    /*   0 : PUNPCKHWD mmxreg,mmxrm [rm:       np 0f 69 /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(69) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PUNPCKHWD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67742, 336},
    /*   1 : PUNPCKHWD xmmreg,xmmrm [rm:       66 0f 69 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(69) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PUNPCKHWD, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68906, 382},
};

static const struct itemplate instrux_PUNPCKLBW[2] = {
    /*   0 : PUNPCKLBW mmxreg,mmxrm [rm:       np 0f 60 /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(60) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PUNPCKLBW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67748, 336},
    /*   1 : PUNPCKLBW xmmreg,xmmrm [rm:       66 0f 60 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(60) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PUNPCKLBW, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68924, 382},
};

static const struct itemplate instrux_PUNPCKLDQ[2] = {
    /*   0 : PUNPCKLDQ mmxreg,mmxrm [rm:       np 0f 62 /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(62) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PUNPCKLDQ, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67754, 336},
    /*   1 : PUNPCKLDQ xmmreg,xmmrm [rm:       66 0f 62 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(62) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PUNPCKLDQ, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68936, 382},
};

static const struct itemplate instrux_PUNPCKLWD[2] = {
    /*   0 : PUNPCKLWD mmxreg,mmxrm [rm:       np 0f 61 /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(61) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PUNPCKLWD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67760, 336},
    /*   1 : PUNPCKLWD xmmreg,xmmrm [rm:       66 0f 61 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(61) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PUNPCKLWD, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68930, 382},
};

static const struct itemplate instrux_PUSHA[1] = {
    /*   0 : PUSHA void [          osm 60                            ] NOREX,NOAPX,NOLONG,186 */
        /* 342 001(60) : NOREX,NOAPX,NOLONG,186 */
        {I_PUSHA, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73253, 343},
};

static const struct itemplate instrux_PUSHAW[1] = {
    /*   0 : PUSHAW void [          o16 60                            ] NOREX,NOAPX,NOLONG,186 */
        /* 320 001(60) : NOREX,NOAPX,NOLONG,186 */
        {I_PUSHAW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73257, 343},
};

static const struct itemplate instrux_PUSHAD[1] = {
    /*   0 : PUSHAD void [          o32 60                            ] NOREX,NOAPX,NOLONG,386 */
        /* 321 001(60) : NOREX,NOAPX,NOLONG,386 */
        {I_PUSHAD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73261, 307},
};

static const struct itemplate instrux_POPA[1] = {
    /*   0 : POPA void [          osm 61                            ] NOREX,NOAPX,NOLONG,186 */
        /* 342 001(61) : NOREX,NOAPX,NOLONG,186 */
        {I_POPA, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73265, 343},
};

static const struct itemplate instrux_POPAW[1] = {
    /*   0 : POPAW void [          o16 61                            ] NOREX,NOAPX,NOLONG,186 */
        /* 320 001(61) : NOREX,NOAPX,NOLONG,186 */
        {I_POPAW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73269, 343},
};

static const struct itemplate instrux_POPAD[1] = {
    /*   0 : POPAD void [          o32 61                            ] NOREX,NOAPX,NOLONG,386 */
        /* 321 001(61) : NOREX,NOAPX,NOLONG,386 */
        {I_POPAD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73273, 307},
};

static const struct itemplate instrux_ENTER[2] = {
    /*   0 : ENTER imm16,imm8 [ij:       nw osm c8 iw ib,u                 ] 186 */
        /* 327 342 001(c8) 030 025 : NWSIZE,186 */
        {I_ENTER, 2, {IMM_NORMAL|BITS16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+57390, 344},
    /*   1 : ENTER imm16 [i:        nw osm c8 iw 00                   ] ND,186 */
        /* 327 342 001(c8) 030 001(00) : NWSIZE,186 */
        {I_ENTER, 1, {IMM_NORMAL|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+51229, 344},
};

static const struct itemplate instrux_ENTERW[2] = {
    /*   0 : ENTERW imm16,imm8 [ij:       nw o16 c8 iw ib,u                 ] 186 */
        /* 327 320 001(c8) 030 025 : NWSIZE,186 */
        {I_ENTERW, 2, {IMM_NORMAL|BITS16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+57397, 344},
    /*   1 : ENTERW imm16 [i:        nw o16 c8 iw 00                   ] ND,186 */
        /* 327 320 001(c8) 030 001(00) : NWSIZE,186 */
        {I_ENTERW, 1, {IMM_NORMAL|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+51237, 344},
};

static const struct itemplate instrux_ENTERD[2] = {
    /*   0 : ENTERD imm16,imm8 [ij:       nw o32 c8 iw ib,u                 ] 386 */
        /* 327 321 001(c8) 030 025 : NWSIZE,386 */
        {I_ENTERD, 2, {IMM_NORMAL|BITS16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+57404, 236},
    /*   1 : ENTERD imm16 [i:        nw o32 c8 iw 00                   ] ND,386 */
        /* 327 321 001(c8) 030 001(00) : NWSIZE,386 */
        {I_ENTERD, 1, {IMM_NORMAL|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+51245, 236},
};

static const struct itemplate instrux_ENTERQ[2] = {
    /*   0 : ENTERQ imm16,imm8 [ij:       nw o64 c8 iw ib,u                 ] LONG,386,X86_64 */
        /* 327 324 001(c8) 030 025 : NWSIZE,LONG,PROT,X86_64 */
        {I_ENTERQ, 2, {IMM_NORMAL|BITS16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+57411, 237},
    /*   1 : ENTERQ imm16 [i:        nw o64 c8 iw 00                   ] ND,LONG,386,X86_64 */
        /* 327 324 001(c8) 030 001(00) : NWSIZE,LONG,PROT,X86_64 */
        {I_ENTERQ, 1, {IMM_NORMAL|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+51253, 237},
};

static const struct itemplate instrux_LEAVE[1] = {
    /*   0 : LEAVE void [          nw osm c9                         ] 186 */
        /* 327 342 001(c9) : NWSIZE,186 */
        {I_LEAVE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72188, 344},
};

static const struct itemplate instrux_LEAVEW[1] = {
    /*   0 : LEAVEW void [          nw o16 c9                         ] 186 */
        /* 327 320 001(c9) : NWSIZE,186 */
        {I_LEAVEW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72193, 344},
};

static const struct itemplate instrux_LEAVED[1] = {
    /*   0 : LEAVED void [          nw o32 c9                         ] 386 */
        /* 327 321 001(c9) : NWSIZE,386 */
        {I_LEAVED, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72198, 236},
};

static const struct itemplate instrux_LEAVEQ[1] = {
    /*   0 : LEAVEQ void [          nw o64 c9                         ] LONG,386,X86_64 */
        /* 327 324 001(c9) : NWSIZE,LONG,PROT,X86_64 */
        {I_LEAVEQ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72203, 237},
};

static const struct itemplate instrux_BOUND[2] = {
    /*   0 : BOUND reg16,mem [rm:       o16 62 /r                         ] NOREX,NOAPX,NOLONG,186 */
        /* 320 001(62) 110 : NOREX,NOAPX,NOLONG,186 */
        {I_BOUND, 2, {REG_GPR|BITS16|RN_L16,MEMORY|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+72208, 343},
    /*   1 : BOUND reg32,mem [rm:       o32 62 /r                         ] NOREX,NOAPX,NOLONG,386 */
        /* 321 001(62) 110 : NOREX,NOAPX,NOLONG,386 */
        {I_BOUND, 2, {REG_GPR|BITS32|RN_L16,MEMORY|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+72213, 307},
};

static const struct itemplate instrux_PUSHP[3] = {
    /*   0 : PUSHP reg64 [r:        o64nw rex.w rex2 50+r             ] LONG,PROT,APX,X86_64 */
        /* 323 347 350 010 120 : NWSIZE,LONG,REX2,PROT,APX,X86_64 */
        {I_PUSHP, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67844, 345},
    /*   1 : PUSHP reg64,reg64 [vm:       o64nw evex.nd1.l0.np.m4.w1 ff /6  ] ND,LONG,PROT,APX,X86_64 */
        /* 323 240(f4 fc 18) 300 001(ff) 216 : NWSIZE,LONG,EVEX,PROT,APX,X86_64 */
        {I_PUSHP, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+13073, 346},
    /*   2 : PUSHP reg64:reg64 [vm:       o64nw evex.nd1.l0.np.m4.w1 ff /6  ] ND,LONG,PROT,APX,X86_64 */
        /* 323 240(f4 fc 18) 300 001(ff) 216 : NWSIZE,LONG,EVEX,PROT,APX,X86_64 */
        {I_PUSHP, 2, {REG_GPR|BITS64|COLON,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+13073, 346},
};

static const struct itemplate instrux_POPP[3] = {
    /*   0 : POPP reg64 [r:        o64nw rex.w rex2 58+r             ] LONG,PROT,APX,X86_64 */
        /* 323 347 350 010 130 : NWSIZE,LONG,REX2,PROT,APX,X86_64 */
        {I_POPP, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+67850, 345},
    /*   1 : POPP reg64,reg64 [vm:       o64nw evex.nd1.l0.np.m4.w1 8f /0  ] ND,LONG,PROT,APX,X86_64 */
        /* 323 240(f4 fc 18) 300 001(8f) 210 : NWSIZE,LONG,EVEX,PROT,APX,X86_64 */
        {I_POPP, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+13103, 346},
    /*   2 : POPP reg64:reg64 [mv:       o64nw evex.nd1.l0.np.m4.w1 8f /0  ] ND,LONG,PROT,APX,X86_64 */
        /* 323 241(f4 fc 18) 300 001(8f) 200 : NWSIZE,LONG,EVEX,PROT,APX,X86_64 */
        {I_POPP, 2, {REG_GPR|BITS64|COLON,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+13113, 346},
};

static const struct itemplate instrux_PUSH2[2] = {
    /*   0 : PUSH2 reg64,reg64 [vm:       o64nw evex.nd1.l0.np.m4.w0 ff /6  ] LONG,PROT,APX,X86_64 */
        /* 323 240(f4 7c 18) 300 001(ff) 216 : NWSIZE,LONG,EVEX,PROT,APX,X86_64 */
        {I_PUSH2, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+13063, 346},
    /*   1 : PUSH2 reg64:reg64 [vm:       o64nw evex.nd1.l0.np.m4.w0 ff /6  ] ND,LONG,PROT,APX,X86_64 */
        /* 323 240(f4 7c 18) 300 001(ff) 216 : NWSIZE,LONG,EVEX,PROT,APX,X86_64 */
        {I_PUSH2, 2, {REG_GPR|BITS64|COLON,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+13063, 346},
};

static const struct itemplate instrux_PUSH2P[2] = {
    /*   0 : PUSH2P reg64,reg64 [vm:       o64nw evex.nd1.l0.np.m4.w1 ff /6  ] LONG,PROT,APX,X86_64 */
        /* 323 240(f4 fc 18) 300 001(ff) 216 : NWSIZE,LONG,EVEX,PROT,APX,X86_64 */
        {I_PUSH2P, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+13073, 346},
    /*   1 : PUSH2P reg64:reg64 [vm:       o64nw evex.nd1.l0.np.m4.w1 ff /6  ] ND,LONG,PROT,APX,X86_64 */
        /* 323 240(f4 fc 18) 300 001(ff) 216 : NWSIZE,LONG,EVEX,PROT,APX,X86_64 */
        {I_PUSH2P, 2, {REG_GPR|BITS64|COLON,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+13073, 346},
};

static const struct itemplate instrux_POP2[2] = {
    /*   0 : POP2 reg64,reg64 [vm:       o64nw evex.nd1.l0.np.m4.w0 8f /0  ] LONG,PROT,APX,X86_64 */
        /* 323 240(f4 7c 18) 300 001(8f) 210 : NWSIZE,LONG,EVEX,PROT,APX,X86_64 */
        {I_POP2, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+13083, 346},
    /*   1 : POP2 reg64:reg64 [mv:       o64nw evex.nd1.l0.np.m4.w0 8f /0  ] ND,LONG,PROT,APX,X86_64 */
        /* 323 241(f4 7c 18) 300 001(8f) 200 : NWSIZE,LONG,EVEX,PROT,APX,X86_64 */
        {I_POP2, 2, {REG_GPR|BITS64|COLON,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+13093, 346},
};

static const struct itemplate instrux_POP2P[2] = {
    /*   0 : POP2P reg64,reg64 [vm:       o64nw evex.nd1.l0.np.m4.w1 8f /0  ] LONG,PROT,APX,X86_64 */
        /* 323 240(f4 fc 18) 300 001(8f) 210 : NWSIZE,LONG,EVEX,PROT,APX,X86_64 */
        {I_POP2P, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+13103, 346},
    /*   1 : POP2P reg64:reg64 [mv:       o64nw evex.nd1.l0.np.m4.w1 8f /0  ] ND,LONG,PROT,APX,X86_64 */
        /* 323 241(f4 fc 18) 300 001(8f) 200 : NWSIZE,LONG,EVEX,PROT,APX,X86_64 */
        {I_POP2P, 2, {REG_GPR|BITS64|COLON,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+13113, 346},
};

static const struct itemplate instrux_PXOR[2] = {
    /*   0 : PXOR mmxreg,mmxrm [rm:       np 0f ef /r                       ] AR0-1,SQ,MMX,PENT */
        /* 360 355 001(ef) 110 : AR0,AR1,SQ,MMX,PENT */
        {I_PXOR, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+67856, 336},
    /*   1 : PXOR xmmreg,xmmrm [rm:       66 0f ef /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(ef) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PXOR, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68948, 382},
};

static const struct itemplate instrux_SKINIT[1] = {
    /*   0 : SKINIT void [          0f 01 de                          ] LONG,PROT,X86_64 */
        /* 355 002(01 de) : LONG,PROT,X86_64 */
        {I_SKINIT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72218, 24},
};

static const struct itemplate instrux_UD0[4] = {
    /*   0 : UD0 reg16,rm16 [rm:       o16 0f ff /r                      ] SM0-1,186 */
        /* 320 355 001(ff) 110 : SM0,SM1,186 */
        {I_UD0, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67862, 347},
    /*   1 : UD0 reg32,rm32 [rm:       o32 0f ff /r                      ] SM0-1,386 */
        /* 321 355 001(ff) 110 : SM0,SM1,386 */
        {I_UD0, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+67868, 13},
    /*   2 : UD0 reg64,rm64 [rm:       o64 0f ff /r                      ] SM0-1,LONG,PROT,X86_64 */
        /* 324 355 001(ff) 110 : SM0,SM1,LONG,PROT,X86_64 */
        {I_UD0, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+67874, 14},
    /*   3 : UD0 void [          0f ff                             ] 186 */
        /* 355 001(ff) : 186 */
        {I_UD0, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73277, 247},
};

static const struct itemplate instrux_UD1[4] = {
    /*   0 : UD1 reg16,rm16 [rm:       o16 0f b9 /r                      ] SM0-1,186 */
        /* 320 355 001(b9) 110 : SM0,SM1,186 */
        {I_UD1, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67880, 347},
    /*   1 : UD1 reg32,rm32 [rm:       o32 0f b9 /r                      ] SM0-1,386 */
        /* 321 355 001(b9) 110 : SM0,SM1,386 */
        {I_UD1, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+67886, 13},
    /*   2 : UD1 reg64,rm64 [rm:       o64 0f b9 /r                      ] SM0-1,LONG,PROT,X86_64 */
        /* 324 355 001(b9) 110 : SM0,SM1,LONG,PROT,X86_64 */
        {I_UD1, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+67892, 14},
    /*   3 : UD1 void [          0f b9                             ] 186 */
        /* 355 001(b9) : 186 */
        {I_UD1, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73281, 247},
};

static const struct itemplate instrux_UD2B[4] = {
    /*   0 : UD2B reg16,rm16 [rm:       o16 0f b9 /r                      ] ND,SM0-1,186 */
        /* 320 355 001(b9) 110 : SM0,SM1,186 */
        {I_UD2B, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67880, 347},
    /*   1 : UD2B reg32,rm32 [rm:       o32 0f b9 /r                      ] ND,SM0-1,386 */
        /* 321 355 001(b9) 110 : SM0,SM1,386 */
        {I_UD2B, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+67886, 13},
    /*   2 : UD2B reg64,rm64 [rm:       o64 0f b9 /r                      ] ND,SM0-1,LONG,PROT,X86_64 */
        /* 324 355 001(b9) 110 : SM0,SM1,LONG,PROT,X86_64 */
        {I_UD2B, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+67892, 14},
    /*   3 : UD2B void [          0f b9                             ] ND,186 */
        /* 355 001(b9) : 186 */
        {I_UD2B, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73281, 247},
};

static const struct itemplate instrux_UD2[4] = {
    /*   0 : UD2 void [          0f 0b                             ] 186 */
        /* 355 001(0b) : 186 */
        {I_UD2, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73285, 247},
    /*   1 : UD2 reg16,rm16 [rm:       o16 0f 0b /r                      ] ND,SM0-1,186 */
        /* 320 355 001(0b) 110 : SM0,SM1,186 */
        {I_UD2, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67898, 347},
    /*   2 : UD2 reg32,rm32 [rm:       o32 0f 0b /r                      ] ND,SM0-1,386 */
        /* 321 355 001(0b) 110 : SM0,SM1,386 */
        {I_UD2, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+67904, 13},
    /*   3 : UD2 reg64,rm64 [rm:       o64 0f 0b /r                      ] ND,SM0-1,LONG,PROT,X86_64 */
        /* 324 355 001(0b) 110 : SM0,SM1,LONG,PROT,X86_64 */
        {I_UD2, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+67910, 14},
};

static const struct itemplate instrux_UD2A[4] = {
    /*   0 : UD2A void [          0f 0b                             ] ND,186 */
        /* 355 001(0b) : 186 */
        {I_UD2A, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73285, 247},
    /*   1 : UD2A reg16,rm16 [rm:       o16 0f 0b /r                      ] ND,186 */
        /* 320 355 001(0b) 110 : 186 */
        {I_UD2A, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67898, 247},
    /*   2 : UD2A reg32,rm32 [rm:       o32 0f 0b /r                      ] ND,386 */
        /* 321 355 001(0b) 110 : 386 */
        {I_UD2A, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+67904, 3},
    /*   3 : UD2A reg64,rm64 [rm:       o64 0f 0b /r                      ] ND,LONG,PROT,X86_64 */
        /* 324 355 001(0b) 110 : LONG,PROT,X86_64 */
        {I_UD2A, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+67910, 24},
};

static const struct itemplate instrux_UDB[1] = {
    /*   0 : UDB void [          d6                                ] LONG,PROT,X86_64 */
        /* 001(d6) : LONG,PROT,X86_64 */
        {I_UDB, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72380, 24},
};

static const struct itemplate instrux_FWAIT[1] = {
    /*   0 : FWAIT void [          wait                              ] 8086 */
        /* 341 : 8086 */
        {I_FWAIT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73211, 23},
};

static const struct itemplate instrux_XLATB[1] = {
    /*   0 : XLATB void [          d7                                ] 8086 */
        /* 001(d7) : 8086 */
        {I_XLATB, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+69947, 23},
};

static const struct itemplate instrux_XLAT[1] = {
    /*   0 : XLAT void [          d7                                ] ND,8086 */
        /* 001(d7) : 8086 */
        {I_XLAT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+69947, 23},
};

static const struct itemplate instrux_CCMP[15] = {
    /*   0 : CCMP spec4,rm8,reg8 [wmr:      evex.scc11.dfv.l0.m4.o8 38 /r       ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0b) 300 001(38) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMP, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24759, 348},
    /*   1 : CCMP spec4,rm16,reg16 [wmr:      evex.scc11.dfv.l0.m4.o16 39 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 0b) 300 320 001(39) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMP, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13123, 349},
    /*   2 : CCMP spec4,rm32,reg32 [wmr:      evex.scc11.dfv.l0.m4.o32 39 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0b) 300 321 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMP, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13283, 350},
    /*   3 : CCMP spec4,rm64,reg64 [wmr:      evex.scc11.dfv.l0.m4.o64 39 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 0b) 300 324 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMP, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13443, 350},
    /*   4 : CCMP spec4,reg8,rm8 [wrm:      evex.scc11.dfv.l0.m4.o8 3a /r       ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0b) 300 001(3a) 121 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMP, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS8,RM_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24903, 348},
    /*   5 : CCMP spec4,reg16,rm16 [wrm:      evex.scc11.dfv.l0.m4.o16 3b /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 0b) 300 320 001(3b) 121 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMP, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13603, 349},
    /*   6 : CCMP spec4,reg32,rm32 [wrm:      evex.scc11.dfv.l0.m4.o32 3b /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0b) 300 321 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMP, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13763, 350},
    /*   7 : CCMP spec4,reg64,rm64 [wrm:      evex.scc11.dfv.l0.m4.o64 3b /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 0b) 300 324 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMP, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13923, 350},
    /*   8 : CCMP spec4,rm16,sbyteword16 [wmi:      evex.scc11.dfv.l0.m4.o16 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 0b) 300 320 001(83) 217 276 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMP, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2367, 349},
    /*   9 : CCMP spec4,rm32,sbytedword32 [wmi:      evex.scc11.dfv.l0.m4.o32 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0b) 300 321 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMP, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2543, 350},
    /*  10 : CCMP spec4,rm64,sbytedword64 [wmi:      evex.scc11.dfv.l0.m4.o64 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 0b) 300 324 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMP, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2719, 350},
    /*  11 : CCMP spec4,rm8,imm8 [wmi:      evex.scc11.dfv.l0.m4.o8 80 /7 ib    ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0b) 300 001(80) 217 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMP, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14083, 348},
    /*  12 : CCMP spec4,rm16,imm16 [wmi:      evex.scc11.dfv.l0.m4.o16 81 /7 iw   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 0b) 300 320 001(81) 217 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMP, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+2895, 349},
    /*  13 : CCMP spec4,rm32,imm32 [wmi:      evex.scc11.dfv.l0.m4.o32 81 /7 id   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0b) 300 321 001(81) 217 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMP, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3071, 350},
    /*  14 : CCMP spec4,rm64,sdword64 [wmi:      evex.scc11.dfv.l0.m4.o64 81 /7 id,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 0b) 300 324 001(81) 217 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMP, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3247, 350},
};

static const struct itemplate instrux_CCMPA[15] = {
    /*   0 : CCMPA spec4,rm8,reg8 [wmr:      evex.scc7.dfv.l0.m4.o8 38 /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 07) 300 001(38) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24768, 348},
    /*   1 : CCMPA spec4,rm16,reg16 [wmr:      evex.scc7.dfv.l0.m4.o16 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 07) 300 320 001(39) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13133, 349},
    /*   2 : CCMPA spec4,rm32,reg32 [wmr:      evex.scc7.dfv.l0.m4.o32 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 07) 300 321 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13293, 350},
    /*   3 : CCMPA spec4,rm64,reg64 [wmr:      evex.scc7.dfv.l0.m4.o64 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 07) 300 324 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13453, 350},
    /*   4 : CCMPA spec4,reg8,rm8 [wrm:      evex.scc7.dfv.l0.m4.o8 3a /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 07) 300 001(3a) 121 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPA, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS8,RM_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24912, 348},
    /*   5 : CCMPA spec4,reg16,rm16 [wrm:      evex.scc7.dfv.l0.m4.o16 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 07) 300 320 001(3b) 121 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPA, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13613, 349},
    /*   6 : CCMPA spec4,reg32,rm32 [wrm:      evex.scc7.dfv.l0.m4.o32 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 07) 300 321 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPA, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13773, 350},
    /*   7 : CCMPA spec4,reg64,rm64 [wrm:      evex.scc7.dfv.l0.m4.o64 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 07) 300 324 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPA, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13933, 350},
    /*   8 : CCMPA spec4,rm16,sbyteword16 [wmi:      evex.scc7.dfv.l0.m4.o16 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 07) 300 320 001(83) 217 276 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2378, 349},
    /*   9 : CCMPA spec4,rm32,sbytedword32 [wmi:      evex.scc7.dfv.l0.m4.o32 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 07) 300 321 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2554, 350},
    /*  10 : CCMPA spec4,rm64,sbytedword64 [wmi:      evex.scc7.dfv.l0.m4.o64 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 07) 300 324 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2730, 350},
    /*  11 : CCMPA spec4,rm8,imm8 [wmi:      evex.scc7.dfv.l0.m4.o8 80 /7 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 07) 300 001(80) 217 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14093, 348},
    /*  12 : CCMPA spec4,rm16,imm16 [wmi:      evex.scc7.dfv.l0.m4.o16 81 /7 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 07) 300 320 001(81) 217 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+2906, 349},
    /*  13 : CCMPA spec4,rm32,imm32 [wmi:      evex.scc7.dfv.l0.m4.o32 81 /7 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 07) 300 321 001(81) 217 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3082, 350},
    /*  14 : CCMPA spec4,rm64,sdword64 [wmi:      evex.scc7.dfv.l0.m4.o64 81 /7 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 07) 300 324 001(81) 217 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3258, 350},
};

static const struct itemplate instrux_CCMPAE[15] = {
    /*   0 : CCMPAE spec4,rm8,reg8 [wmr:      evex.scc3.dfv.l0.m4.o8 38 /r       ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 03) 300 001(38) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24777, 348},
    /*   1 : CCMPAE spec4,rm16,reg16 [wmr:      evex.scc3.dfv.l0.m4.o16 39 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 03) 300 320 001(39) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13143, 349},
    /*   2 : CCMPAE spec4,rm32,reg32 [wmr:      evex.scc3.dfv.l0.m4.o32 39 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 03) 300 321 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13303, 350},
    /*   3 : CCMPAE spec4,rm64,reg64 [wmr:      evex.scc3.dfv.l0.m4.o64 39 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 03) 300 324 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13463, 350},
    /*   4 : CCMPAE spec4,reg8,rm8 [wrm:      evex.scc3.dfv.l0.m4.o8 3a /r       ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 03) 300 001(3a) 121 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPAE, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS8,RM_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24921, 348},
    /*   5 : CCMPAE spec4,reg16,rm16 [wrm:      evex.scc3.dfv.l0.m4.o16 3b /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 03) 300 320 001(3b) 121 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPAE, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13623, 349},
    /*   6 : CCMPAE spec4,reg32,rm32 [wrm:      evex.scc3.dfv.l0.m4.o32 3b /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 03) 300 321 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPAE, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13783, 350},
    /*   7 : CCMPAE spec4,reg64,rm64 [wrm:      evex.scc3.dfv.l0.m4.o64 3b /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 03) 300 324 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPAE, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13943, 350},
    /*   8 : CCMPAE spec4,rm16,sbyteword16 [wmi:      evex.scc3.dfv.l0.m4.o16 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 03) 300 320 001(83) 217 276 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2389, 349},
    /*   9 : CCMPAE spec4,rm32,sbytedword32 [wmi:      evex.scc3.dfv.l0.m4.o32 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 03) 300 321 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2565, 350},
    /*  10 : CCMPAE spec4,rm64,sbytedword64 [wmi:      evex.scc3.dfv.l0.m4.o64 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 03) 300 324 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2741, 350},
    /*  11 : CCMPAE spec4,rm8,imm8 [wmi:      evex.scc3.dfv.l0.m4.o8 80 /7 ib    ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 03) 300 001(80) 217 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14103, 348},
    /*  12 : CCMPAE spec4,rm16,imm16 [wmi:      evex.scc3.dfv.l0.m4.o16 81 /7 iw   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 03) 300 320 001(81) 217 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+2917, 349},
    /*  13 : CCMPAE spec4,rm32,imm32 [wmi:      evex.scc3.dfv.l0.m4.o32 81 /7 id   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 03) 300 321 001(81) 217 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3093, 350},
    /*  14 : CCMPAE spec4,rm64,sdword64 [wmi:      evex.scc3.dfv.l0.m4.o64 81 /7 id,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 03) 300 324 001(81) 217 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3269, 350},
};

static const struct itemplate instrux_CCMPB[15] = {
    /*   0 : CCMPB spec4,rm8,reg8 [wmr:      evex.scc2.dfv.l0.m4.o8 38 /r       ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 02) 300 001(38) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24786, 348},
    /*   1 : CCMPB spec4,rm16,reg16 [wmr:      evex.scc2.dfv.l0.m4.o16 39 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 02) 300 320 001(39) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13153, 349},
    /*   2 : CCMPB spec4,rm32,reg32 [wmr:      evex.scc2.dfv.l0.m4.o32 39 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 02) 300 321 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13313, 350},
    /*   3 : CCMPB spec4,rm64,reg64 [wmr:      evex.scc2.dfv.l0.m4.o64 39 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 02) 300 324 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13473, 350},
    /*   4 : CCMPB spec4,reg8,rm8 [wrm:      evex.scc2.dfv.l0.m4.o8 3a /r       ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 02) 300 001(3a) 121 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPB, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS8,RM_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24930, 348},
    /*   5 : CCMPB spec4,reg16,rm16 [wrm:      evex.scc2.dfv.l0.m4.o16 3b /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 02) 300 320 001(3b) 121 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPB, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13633, 349},
    /*   6 : CCMPB spec4,reg32,rm32 [wrm:      evex.scc2.dfv.l0.m4.o32 3b /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 02) 300 321 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPB, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13793, 350},
    /*   7 : CCMPB spec4,reg64,rm64 [wrm:      evex.scc2.dfv.l0.m4.o64 3b /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 02) 300 324 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPB, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13953, 350},
    /*   8 : CCMPB spec4,rm16,sbyteword16 [wmi:      evex.scc2.dfv.l0.m4.o16 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 02) 300 320 001(83) 217 276 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2400, 349},
    /*   9 : CCMPB spec4,rm32,sbytedword32 [wmi:      evex.scc2.dfv.l0.m4.o32 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 02) 300 321 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2576, 350},
    /*  10 : CCMPB spec4,rm64,sbytedword64 [wmi:      evex.scc2.dfv.l0.m4.o64 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 02) 300 324 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2752, 350},
    /*  11 : CCMPB spec4,rm8,imm8 [wmi:      evex.scc2.dfv.l0.m4.o8 80 /7 ib    ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 02) 300 001(80) 217 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14113, 348},
    /*  12 : CCMPB spec4,rm16,imm16 [wmi:      evex.scc2.dfv.l0.m4.o16 81 /7 iw   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 02) 300 320 001(81) 217 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+2928, 349},
    /*  13 : CCMPB spec4,rm32,imm32 [wmi:      evex.scc2.dfv.l0.m4.o32 81 /7 id   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 02) 300 321 001(81) 217 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3104, 350},
    /*  14 : CCMPB spec4,rm64,sdword64 [wmi:      evex.scc2.dfv.l0.m4.o64 81 /7 id,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 02) 300 324 001(81) 217 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3280, 350},
};

static const struct itemplate instrux_CCMPBE[15] = {
    /*   0 : CCMPBE spec4,rm8,reg8 [wmr:      evex.scc6.dfv.l0.m4.o8 38 /r       ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 06) 300 001(38) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24795, 348},
    /*   1 : CCMPBE spec4,rm16,reg16 [wmr:      evex.scc6.dfv.l0.m4.o16 39 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 06) 300 320 001(39) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13163, 349},
    /*   2 : CCMPBE spec4,rm32,reg32 [wmr:      evex.scc6.dfv.l0.m4.o32 39 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 06) 300 321 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13323, 350},
    /*   3 : CCMPBE spec4,rm64,reg64 [wmr:      evex.scc6.dfv.l0.m4.o64 39 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 06) 300 324 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13483, 350},
    /*   4 : CCMPBE spec4,reg8,rm8 [wrm:      evex.scc6.dfv.l0.m4.o8 3a /r       ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 06) 300 001(3a) 121 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPBE, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS8,RM_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24939, 348},
    /*   5 : CCMPBE spec4,reg16,rm16 [wrm:      evex.scc6.dfv.l0.m4.o16 3b /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 06) 300 320 001(3b) 121 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPBE, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13643, 349},
    /*   6 : CCMPBE spec4,reg32,rm32 [wrm:      evex.scc6.dfv.l0.m4.o32 3b /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 06) 300 321 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPBE, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13803, 350},
    /*   7 : CCMPBE spec4,reg64,rm64 [wrm:      evex.scc6.dfv.l0.m4.o64 3b /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 06) 300 324 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPBE, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13963, 350},
    /*   8 : CCMPBE spec4,rm16,sbyteword16 [wmi:      evex.scc6.dfv.l0.m4.o16 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 06) 300 320 001(83) 217 276 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2411, 349},
    /*   9 : CCMPBE spec4,rm32,sbytedword32 [wmi:      evex.scc6.dfv.l0.m4.o32 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 06) 300 321 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2587, 350},
    /*  10 : CCMPBE spec4,rm64,sbytedword64 [wmi:      evex.scc6.dfv.l0.m4.o64 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 06) 300 324 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2763, 350},
    /*  11 : CCMPBE spec4,rm8,imm8 [wmi:      evex.scc6.dfv.l0.m4.o8 80 /7 ib    ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 06) 300 001(80) 217 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14123, 348},
    /*  12 : CCMPBE spec4,rm16,imm16 [wmi:      evex.scc6.dfv.l0.m4.o16 81 /7 iw   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 06) 300 320 001(81) 217 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+2939, 349},
    /*  13 : CCMPBE spec4,rm32,imm32 [wmi:      evex.scc6.dfv.l0.m4.o32 81 /7 id   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 06) 300 321 001(81) 217 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3115, 350},
    /*  14 : CCMPBE spec4,rm64,sdword64 [wmi:      evex.scc6.dfv.l0.m4.o64 81 /7 id,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 06) 300 324 001(81) 217 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3291, 350},
};

static const struct itemplate instrux_CCMPC[15] = {
    /*   0 : CCMPC spec4,rm8,reg8 [wmr:      evex.scc2.dfv.l0.m4.o8 38 /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 02) 300 001(38) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24786, 348},
    /*   1 : CCMPC spec4,rm16,reg16 [wmr:      evex.scc2.dfv.l0.m4.o16 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 02) 300 320 001(39) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13153, 349},
    /*   2 : CCMPC spec4,rm32,reg32 [wmr:      evex.scc2.dfv.l0.m4.o32 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 02) 300 321 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13313, 350},
    /*   3 : CCMPC spec4,rm64,reg64 [wmr:      evex.scc2.dfv.l0.m4.o64 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 02) 300 324 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13473, 350},
    /*   4 : CCMPC spec4,reg8,rm8 [wrm:      evex.scc2.dfv.l0.m4.o8 3a /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 02) 300 001(3a) 121 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPC, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS8,RM_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24930, 348},
    /*   5 : CCMPC spec4,reg16,rm16 [wrm:      evex.scc2.dfv.l0.m4.o16 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 02) 300 320 001(3b) 121 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPC, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13633, 349},
    /*   6 : CCMPC spec4,reg32,rm32 [wrm:      evex.scc2.dfv.l0.m4.o32 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 02) 300 321 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPC, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13793, 350},
    /*   7 : CCMPC spec4,reg64,rm64 [wrm:      evex.scc2.dfv.l0.m4.o64 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 02) 300 324 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPC, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13953, 350},
    /*   8 : CCMPC spec4,rm16,sbyteword16 [wmi:      evex.scc2.dfv.l0.m4.o16 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 02) 300 320 001(83) 217 276 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2400, 349},
    /*   9 : CCMPC spec4,rm32,sbytedword32 [wmi:      evex.scc2.dfv.l0.m4.o32 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 02) 300 321 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2576, 350},
    /*  10 : CCMPC spec4,rm64,sbytedword64 [wmi:      evex.scc2.dfv.l0.m4.o64 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 02) 300 324 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2752, 350},
    /*  11 : CCMPC spec4,rm8,imm8 [wmi:      evex.scc2.dfv.l0.m4.o8 80 /7 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 02) 300 001(80) 217 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14113, 348},
    /*  12 : CCMPC spec4,rm16,imm16 [wmi:      evex.scc2.dfv.l0.m4.o16 81 /7 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 02) 300 320 001(81) 217 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+2928, 349},
    /*  13 : CCMPC spec4,rm32,imm32 [wmi:      evex.scc2.dfv.l0.m4.o32 81 /7 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 02) 300 321 001(81) 217 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3104, 350},
    /*  14 : CCMPC spec4,rm64,sdword64 [wmi:      evex.scc2.dfv.l0.m4.o64 81 /7 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 02) 300 324 001(81) 217 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3280, 350},
};

static const struct itemplate instrux_CCMPE[15] = {
    /*   0 : CCMPE spec4,rm8,reg8 [wmr:      evex.scc4.dfv.l0.m4.o8 38 /r       ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 04) 300 001(38) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24804, 348},
    /*   1 : CCMPE spec4,rm16,reg16 [wmr:      evex.scc4.dfv.l0.m4.o16 39 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 04) 300 320 001(39) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13173, 349},
    /*   2 : CCMPE spec4,rm32,reg32 [wmr:      evex.scc4.dfv.l0.m4.o32 39 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 04) 300 321 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13333, 350},
    /*   3 : CCMPE spec4,rm64,reg64 [wmr:      evex.scc4.dfv.l0.m4.o64 39 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 04) 300 324 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13493, 350},
    /*   4 : CCMPE spec4,reg8,rm8 [wrm:      evex.scc4.dfv.l0.m4.o8 3a /r       ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 04) 300 001(3a) 121 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPE, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS8,RM_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24948, 348},
    /*   5 : CCMPE spec4,reg16,rm16 [wrm:      evex.scc4.dfv.l0.m4.o16 3b /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 04) 300 320 001(3b) 121 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPE, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13653, 349},
    /*   6 : CCMPE spec4,reg32,rm32 [wrm:      evex.scc4.dfv.l0.m4.o32 3b /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 04) 300 321 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPE, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13813, 350},
    /*   7 : CCMPE spec4,reg64,rm64 [wrm:      evex.scc4.dfv.l0.m4.o64 3b /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 04) 300 324 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPE, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13973, 350},
    /*   8 : CCMPE spec4,rm16,sbyteword16 [wmi:      evex.scc4.dfv.l0.m4.o16 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 04) 300 320 001(83) 217 276 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2422, 349},
    /*   9 : CCMPE spec4,rm32,sbytedword32 [wmi:      evex.scc4.dfv.l0.m4.o32 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 04) 300 321 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2598, 350},
    /*  10 : CCMPE spec4,rm64,sbytedword64 [wmi:      evex.scc4.dfv.l0.m4.o64 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 04) 300 324 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2774, 350},
    /*  11 : CCMPE spec4,rm8,imm8 [wmi:      evex.scc4.dfv.l0.m4.o8 80 /7 ib    ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 04) 300 001(80) 217 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14133, 348},
    /*  12 : CCMPE spec4,rm16,imm16 [wmi:      evex.scc4.dfv.l0.m4.o16 81 /7 iw   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 04) 300 320 001(81) 217 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+2950, 349},
    /*  13 : CCMPE spec4,rm32,imm32 [wmi:      evex.scc4.dfv.l0.m4.o32 81 /7 id   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 04) 300 321 001(81) 217 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3126, 350},
    /*  14 : CCMPE spec4,rm64,sdword64 [wmi:      evex.scc4.dfv.l0.m4.o64 81 /7 id,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 04) 300 324 001(81) 217 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3302, 350},
};

static const struct itemplate instrux_CCMPF[15] = {
    /*   0 : CCMPF spec4,rm8,reg8 [wmr:      evex.scc11.dfv.l0.m4.o8 38 /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0b) 300 001(38) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPF, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24759, 348},
    /*   1 : CCMPF spec4,rm16,reg16 [wmr:      evex.scc11.dfv.l0.m4.o16 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0b) 300 320 001(39) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPF, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13123, 349},
    /*   2 : CCMPF spec4,rm32,reg32 [wmr:      evex.scc11.dfv.l0.m4.o32 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0b) 300 321 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPF, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13283, 350},
    /*   3 : CCMPF spec4,rm64,reg64 [wmr:      evex.scc11.dfv.l0.m4.o64 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0b) 300 324 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPF, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13443, 350},
    /*   4 : CCMPF spec4,reg8,rm8 [wrm:      evex.scc11.dfv.l0.m4.o8 3a /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0b) 300 001(3a) 121 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPF, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS8,RM_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24903, 348},
    /*   5 : CCMPF spec4,reg16,rm16 [wrm:      evex.scc11.dfv.l0.m4.o16 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0b) 300 320 001(3b) 121 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPF, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13603, 349},
    /*   6 : CCMPF spec4,reg32,rm32 [wrm:      evex.scc11.dfv.l0.m4.o32 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0b) 300 321 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPF, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13763, 350},
    /*   7 : CCMPF spec4,reg64,rm64 [wrm:      evex.scc11.dfv.l0.m4.o64 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0b) 300 324 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPF, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13923, 350},
    /*   8 : CCMPF spec4,rm16,sbyteword16 [wmi:      evex.scc11.dfv.l0.m4.o16 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0b) 300 320 001(83) 217 276 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPF, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2367, 349},
    /*   9 : CCMPF spec4,rm32,sbytedword32 [wmi:      evex.scc11.dfv.l0.m4.o32 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0b) 300 321 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPF, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2543, 350},
    /*  10 : CCMPF spec4,rm64,sbytedword64 [wmi:      evex.scc11.dfv.l0.m4.o64 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0b) 300 324 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPF, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2719, 350},
    /*  11 : CCMPF spec4,rm8,imm8 [wmi:      evex.scc11.dfv.l0.m4.o8 80 /7 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0b) 300 001(80) 217 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPF, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14083, 348},
    /*  12 : CCMPF spec4,rm16,imm16 [wmi:      evex.scc11.dfv.l0.m4.o16 81 /7 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0b) 300 320 001(81) 217 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPF, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+2895, 349},
    /*  13 : CCMPF spec4,rm32,imm32 [wmi:      evex.scc11.dfv.l0.m4.o32 81 /7 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0b) 300 321 001(81) 217 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPF, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3071, 350},
    /*  14 : CCMPF spec4,rm64,sdword64 [wmi:      evex.scc11.dfv.l0.m4.o64 81 /7 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0b) 300 324 001(81) 217 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPF, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3247, 350},
};

static const struct itemplate instrux_CCMPG[15] = {
    /*   0 : CCMPG spec4,rm8,reg8 [wmr:      evex.scc15.dfv.l0.m4.o8 38 /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0f) 300 001(38) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24813, 348},
    /*   1 : CCMPG spec4,rm16,reg16 [wmr:      evex.scc15.dfv.l0.m4.o16 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0f) 300 320 001(39) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13183, 349},
    /*   2 : CCMPG spec4,rm32,reg32 [wmr:      evex.scc15.dfv.l0.m4.o32 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0f) 300 321 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13343, 350},
    /*   3 : CCMPG spec4,rm64,reg64 [wmr:      evex.scc15.dfv.l0.m4.o64 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0f) 300 324 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13503, 350},
    /*   4 : CCMPG spec4,reg8,rm8 [wrm:      evex.scc15.dfv.l0.m4.o8 3a /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0f) 300 001(3a) 121 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPG, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS8,RM_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24957, 348},
    /*   5 : CCMPG spec4,reg16,rm16 [wrm:      evex.scc15.dfv.l0.m4.o16 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0f) 300 320 001(3b) 121 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPG, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13663, 349},
    /*   6 : CCMPG spec4,reg32,rm32 [wrm:      evex.scc15.dfv.l0.m4.o32 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0f) 300 321 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPG, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13823, 350},
    /*   7 : CCMPG spec4,reg64,rm64 [wrm:      evex.scc15.dfv.l0.m4.o64 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0f) 300 324 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPG, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13983, 350},
    /*   8 : CCMPG spec4,rm16,sbyteword16 [wmi:      evex.scc15.dfv.l0.m4.o16 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0f) 300 320 001(83) 217 276 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2433, 349},
    /*   9 : CCMPG spec4,rm32,sbytedword32 [wmi:      evex.scc15.dfv.l0.m4.o32 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0f) 300 321 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2609, 350},
    /*  10 : CCMPG spec4,rm64,sbytedword64 [wmi:      evex.scc15.dfv.l0.m4.o64 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0f) 300 324 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2785, 350},
    /*  11 : CCMPG spec4,rm8,imm8 [wmi:      evex.scc15.dfv.l0.m4.o8 80 /7 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0f) 300 001(80) 217 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14143, 348},
    /*  12 : CCMPG spec4,rm16,imm16 [wmi:      evex.scc15.dfv.l0.m4.o16 81 /7 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0f) 300 320 001(81) 217 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+2961, 349},
    /*  13 : CCMPG spec4,rm32,imm32 [wmi:      evex.scc15.dfv.l0.m4.o32 81 /7 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0f) 300 321 001(81) 217 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3137, 350},
    /*  14 : CCMPG spec4,rm64,sdword64 [wmi:      evex.scc15.dfv.l0.m4.o64 81 /7 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0f) 300 324 001(81) 217 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3313, 350},
};

static const struct itemplate instrux_CCMPGE[15] = {
    /*   0 : CCMPGE spec4,rm8,reg8 [wmr:      evex.scc13.dfv.l0.m4.o8 38 /r       ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0d) 300 001(38) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24822, 348},
    /*   1 : CCMPGE spec4,rm16,reg16 [wmr:      evex.scc13.dfv.l0.m4.o16 39 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 0d) 300 320 001(39) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13193, 349},
    /*   2 : CCMPGE spec4,rm32,reg32 [wmr:      evex.scc13.dfv.l0.m4.o32 39 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0d) 300 321 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13353, 350},
    /*   3 : CCMPGE spec4,rm64,reg64 [wmr:      evex.scc13.dfv.l0.m4.o64 39 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 0d) 300 324 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13513, 350},
    /*   4 : CCMPGE spec4,reg8,rm8 [wrm:      evex.scc13.dfv.l0.m4.o8 3a /r       ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0d) 300 001(3a) 121 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPGE, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS8,RM_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24966, 348},
    /*   5 : CCMPGE spec4,reg16,rm16 [wrm:      evex.scc13.dfv.l0.m4.o16 3b /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 0d) 300 320 001(3b) 121 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPGE, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13673, 349},
    /*   6 : CCMPGE spec4,reg32,rm32 [wrm:      evex.scc13.dfv.l0.m4.o32 3b /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0d) 300 321 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPGE, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13833, 350},
    /*   7 : CCMPGE spec4,reg64,rm64 [wrm:      evex.scc13.dfv.l0.m4.o64 3b /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 0d) 300 324 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPGE, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13993, 350},
    /*   8 : CCMPGE spec4,rm16,sbyteword16 [wmi:      evex.scc13.dfv.l0.m4.o16 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 0d) 300 320 001(83) 217 276 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2444, 349},
    /*   9 : CCMPGE spec4,rm32,sbytedword32 [wmi:      evex.scc13.dfv.l0.m4.o32 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0d) 300 321 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2620, 350},
    /*  10 : CCMPGE spec4,rm64,sbytedword64 [wmi:      evex.scc13.dfv.l0.m4.o64 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 0d) 300 324 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2796, 350},
    /*  11 : CCMPGE spec4,rm8,imm8 [wmi:      evex.scc13.dfv.l0.m4.o8 80 /7 ib    ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0d) 300 001(80) 217 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14153, 348},
    /*  12 : CCMPGE spec4,rm16,imm16 [wmi:      evex.scc13.dfv.l0.m4.o16 81 /7 iw   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 0d) 300 320 001(81) 217 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+2972, 349},
    /*  13 : CCMPGE spec4,rm32,imm32 [wmi:      evex.scc13.dfv.l0.m4.o32 81 /7 id   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0d) 300 321 001(81) 217 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3148, 350},
    /*  14 : CCMPGE spec4,rm64,sdword64 [wmi:      evex.scc13.dfv.l0.m4.o64 81 /7 id,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 0d) 300 324 001(81) 217 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3324, 350},
};

static const struct itemplate instrux_CCMPL[15] = {
    /*   0 : CCMPL spec4,rm8,reg8 [wmr:      evex.scc12.dfv.l0.m4.o8 38 /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0c) 300 001(38) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24831, 348},
    /*   1 : CCMPL spec4,rm16,reg16 [wmr:      evex.scc12.dfv.l0.m4.o16 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0c) 300 320 001(39) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13203, 349},
    /*   2 : CCMPL spec4,rm32,reg32 [wmr:      evex.scc12.dfv.l0.m4.o32 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0c) 300 321 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13363, 350},
    /*   3 : CCMPL spec4,rm64,reg64 [wmr:      evex.scc12.dfv.l0.m4.o64 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0c) 300 324 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13523, 350},
    /*   4 : CCMPL spec4,reg8,rm8 [wrm:      evex.scc12.dfv.l0.m4.o8 3a /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0c) 300 001(3a) 121 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPL, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS8,RM_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24975, 348},
    /*   5 : CCMPL spec4,reg16,rm16 [wrm:      evex.scc12.dfv.l0.m4.o16 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0c) 300 320 001(3b) 121 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPL, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13683, 349},
    /*   6 : CCMPL spec4,reg32,rm32 [wrm:      evex.scc12.dfv.l0.m4.o32 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0c) 300 321 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPL, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13843, 350},
    /*   7 : CCMPL spec4,reg64,rm64 [wrm:      evex.scc12.dfv.l0.m4.o64 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0c) 300 324 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPL, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14003, 350},
    /*   8 : CCMPL spec4,rm16,sbyteword16 [wmi:      evex.scc12.dfv.l0.m4.o16 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0c) 300 320 001(83) 217 276 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2455, 349},
    /*   9 : CCMPL spec4,rm32,sbytedword32 [wmi:      evex.scc12.dfv.l0.m4.o32 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0c) 300 321 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2631, 350},
    /*  10 : CCMPL spec4,rm64,sbytedword64 [wmi:      evex.scc12.dfv.l0.m4.o64 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0c) 300 324 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2807, 350},
    /*  11 : CCMPL spec4,rm8,imm8 [wmi:      evex.scc12.dfv.l0.m4.o8 80 /7 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0c) 300 001(80) 217 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14163, 348},
    /*  12 : CCMPL spec4,rm16,imm16 [wmi:      evex.scc12.dfv.l0.m4.o16 81 /7 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0c) 300 320 001(81) 217 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+2983, 349},
    /*  13 : CCMPL spec4,rm32,imm32 [wmi:      evex.scc12.dfv.l0.m4.o32 81 /7 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0c) 300 321 001(81) 217 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3159, 350},
    /*  14 : CCMPL spec4,rm64,sdword64 [wmi:      evex.scc12.dfv.l0.m4.o64 81 /7 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0c) 300 324 001(81) 217 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3335, 350},
};

static const struct itemplate instrux_CCMPLE[15] = {
    /*   0 : CCMPLE spec4,rm8,reg8 [wmr:      evex.scc14.dfv.l0.m4.o8 38 /r       ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0e) 300 001(38) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24840, 348},
    /*   1 : CCMPLE spec4,rm16,reg16 [wmr:      evex.scc14.dfv.l0.m4.o16 39 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 0e) 300 320 001(39) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13213, 349},
    /*   2 : CCMPLE spec4,rm32,reg32 [wmr:      evex.scc14.dfv.l0.m4.o32 39 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0e) 300 321 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13373, 350},
    /*   3 : CCMPLE spec4,rm64,reg64 [wmr:      evex.scc14.dfv.l0.m4.o64 39 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 0e) 300 324 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13533, 350},
    /*   4 : CCMPLE spec4,reg8,rm8 [wrm:      evex.scc14.dfv.l0.m4.o8 3a /r       ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0e) 300 001(3a) 121 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPLE, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS8,RM_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24984, 348},
    /*   5 : CCMPLE spec4,reg16,rm16 [wrm:      evex.scc14.dfv.l0.m4.o16 3b /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 0e) 300 320 001(3b) 121 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPLE, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13693, 349},
    /*   6 : CCMPLE spec4,reg32,rm32 [wrm:      evex.scc14.dfv.l0.m4.o32 3b /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0e) 300 321 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPLE, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13853, 350},
    /*   7 : CCMPLE spec4,reg64,rm64 [wrm:      evex.scc14.dfv.l0.m4.o64 3b /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 0e) 300 324 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPLE, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14013, 350},
    /*   8 : CCMPLE spec4,rm16,sbyteword16 [wmi:      evex.scc14.dfv.l0.m4.o16 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 0e) 300 320 001(83) 217 276 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2466, 349},
    /*   9 : CCMPLE spec4,rm32,sbytedword32 [wmi:      evex.scc14.dfv.l0.m4.o32 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0e) 300 321 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2642, 350},
    /*  10 : CCMPLE spec4,rm64,sbytedword64 [wmi:      evex.scc14.dfv.l0.m4.o64 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 0e) 300 324 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2818, 350},
    /*  11 : CCMPLE spec4,rm8,imm8 [wmi:      evex.scc14.dfv.l0.m4.o8 80 /7 ib    ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0e) 300 001(80) 217 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14173, 348},
    /*  12 : CCMPLE spec4,rm16,imm16 [wmi:      evex.scc14.dfv.l0.m4.o16 81 /7 iw   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 0e) 300 320 001(81) 217 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+2994, 349},
    /*  13 : CCMPLE spec4,rm32,imm32 [wmi:      evex.scc14.dfv.l0.m4.o32 81 /7 id   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0e) 300 321 001(81) 217 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3170, 350},
    /*  14 : CCMPLE spec4,rm64,sdword64 [wmi:      evex.scc14.dfv.l0.m4.o64 81 /7 id,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 0e) 300 324 001(81) 217 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3346, 350},
};

static const struct itemplate instrux_CCMPNA[15] = {
    /*   0 : CCMPNA spec4,rm8,reg8 [wmr:      evex.scc6.dfv.l0.m4.o8 38 /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 06) 300 001(38) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24795, 348},
    /*   1 : CCMPNA spec4,rm16,reg16 [wmr:      evex.scc6.dfv.l0.m4.o16 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 06) 300 320 001(39) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13163, 349},
    /*   2 : CCMPNA spec4,rm32,reg32 [wmr:      evex.scc6.dfv.l0.m4.o32 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 06) 300 321 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13323, 350},
    /*   3 : CCMPNA spec4,rm64,reg64 [wmr:      evex.scc6.dfv.l0.m4.o64 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 06) 300 324 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13483, 350},
    /*   4 : CCMPNA spec4,reg8,rm8 [wrm:      evex.scc6.dfv.l0.m4.o8 3a /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 06) 300 001(3a) 121 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNA, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS8,RM_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24939, 348},
    /*   5 : CCMPNA spec4,reg16,rm16 [wrm:      evex.scc6.dfv.l0.m4.o16 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 06) 300 320 001(3b) 121 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNA, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13643, 349},
    /*   6 : CCMPNA spec4,reg32,rm32 [wrm:      evex.scc6.dfv.l0.m4.o32 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 06) 300 321 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNA, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13803, 350},
    /*   7 : CCMPNA spec4,reg64,rm64 [wrm:      evex.scc6.dfv.l0.m4.o64 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 06) 300 324 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNA, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13963, 350},
    /*   8 : CCMPNA spec4,rm16,sbyteword16 [wmi:      evex.scc6.dfv.l0.m4.o16 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 06) 300 320 001(83) 217 276 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2411, 349},
    /*   9 : CCMPNA spec4,rm32,sbytedword32 [wmi:      evex.scc6.dfv.l0.m4.o32 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 06) 300 321 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2587, 350},
    /*  10 : CCMPNA spec4,rm64,sbytedword64 [wmi:      evex.scc6.dfv.l0.m4.o64 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 06) 300 324 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2763, 350},
    /*  11 : CCMPNA spec4,rm8,imm8 [wmi:      evex.scc6.dfv.l0.m4.o8 80 /7 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 06) 300 001(80) 217 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14123, 348},
    /*  12 : CCMPNA spec4,rm16,imm16 [wmi:      evex.scc6.dfv.l0.m4.o16 81 /7 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 06) 300 320 001(81) 217 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+2939, 349},
    /*  13 : CCMPNA spec4,rm32,imm32 [wmi:      evex.scc6.dfv.l0.m4.o32 81 /7 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 06) 300 321 001(81) 217 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3115, 350},
    /*  14 : CCMPNA spec4,rm64,sdword64 [wmi:      evex.scc6.dfv.l0.m4.o64 81 /7 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 06) 300 324 001(81) 217 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3291, 350},
};

static const struct itemplate instrux_CCMPNAE[15] = {
    /*   0 : CCMPNAE spec4,rm8,reg8 [wmr:      evex.scc2.dfv.l0.m4.o8 38 /r       ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 02) 300 001(38) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24786, 348},
    /*   1 : CCMPNAE spec4,rm16,reg16 [wmr:      evex.scc2.dfv.l0.m4.o16 39 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 02) 300 320 001(39) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13153, 349},
    /*   2 : CCMPNAE spec4,rm32,reg32 [wmr:      evex.scc2.dfv.l0.m4.o32 39 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 02) 300 321 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13313, 350},
    /*   3 : CCMPNAE spec4,rm64,reg64 [wmr:      evex.scc2.dfv.l0.m4.o64 39 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 02) 300 324 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13473, 350},
    /*   4 : CCMPNAE spec4,reg8,rm8 [wrm:      evex.scc2.dfv.l0.m4.o8 3a /r       ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 02) 300 001(3a) 121 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNAE, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS8,RM_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24930, 348},
    /*   5 : CCMPNAE spec4,reg16,rm16 [wrm:      evex.scc2.dfv.l0.m4.o16 3b /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 02) 300 320 001(3b) 121 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNAE, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13633, 349},
    /*   6 : CCMPNAE spec4,reg32,rm32 [wrm:      evex.scc2.dfv.l0.m4.o32 3b /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 02) 300 321 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNAE, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13793, 350},
    /*   7 : CCMPNAE spec4,reg64,rm64 [wrm:      evex.scc2.dfv.l0.m4.o64 3b /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 02) 300 324 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNAE, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13953, 350},
    /*   8 : CCMPNAE spec4,rm16,sbyteword16 [wmi:      evex.scc2.dfv.l0.m4.o16 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 02) 300 320 001(83) 217 276 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2400, 349},
    /*   9 : CCMPNAE spec4,rm32,sbytedword32 [wmi:      evex.scc2.dfv.l0.m4.o32 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 02) 300 321 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2576, 350},
    /*  10 : CCMPNAE spec4,rm64,sbytedword64 [wmi:      evex.scc2.dfv.l0.m4.o64 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 02) 300 324 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2752, 350},
    /*  11 : CCMPNAE spec4,rm8,imm8 [wmi:      evex.scc2.dfv.l0.m4.o8 80 /7 ib    ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 02) 300 001(80) 217 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14113, 348},
    /*  12 : CCMPNAE spec4,rm16,imm16 [wmi:      evex.scc2.dfv.l0.m4.o16 81 /7 iw   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 02) 300 320 001(81) 217 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+2928, 349},
    /*  13 : CCMPNAE spec4,rm32,imm32 [wmi:      evex.scc2.dfv.l0.m4.o32 81 /7 id   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 02) 300 321 001(81) 217 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3104, 350},
    /*  14 : CCMPNAE spec4,rm64,sdword64 [wmi:      evex.scc2.dfv.l0.m4.o64 81 /7 id,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 02) 300 324 001(81) 217 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3280, 350},
};

static const struct itemplate instrux_CCMPNB[15] = {
    /*   0 : CCMPNB spec4,rm8,reg8 [wmr:      evex.scc3.dfv.l0.m4.o8 38 /r       ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 03) 300 001(38) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24777, 348},
    /*   1 : CCMPNB spec4,rm16,reg16 [wmr:      evex.scc3.dfv.l0.m4.o16 39 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 03) 300 320 001(39) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13143, 349},
    /*   2 : CCMPNB spec4,rm32,reg32 [wmr:      evex.scc3.dfv.l0.m4.o32 39 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 03) 300 321 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13303, 350},
    /*   3 : CCMPNB spec4,rm64,reg64 [wmr:      evex.scc3.dfv.l0.m4.o64 39 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 03) 300 324 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13463, 350},
    /*   4 : CCMPNB spec4,reg8,rm8 [wrm:      evex.scc3.dfv.l0.m4.o8 3a /r       ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 03) 300 001(3a) 121 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNB, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS8,RM_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24921, 348},
    /*   5 : CCMPNB spec4,reg16,rm16 [wrm:      evex.scc3.dfv.l0.m4.o16 3b /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 03) 300 320 001(3b) 121 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNB, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13623, 349},
    /*   6 : CCMPNB spec4,reg32,rm32 [wrm:      evex.scc3.dfv.l0.m4.o32 3b /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 03) 300 321 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNB, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13783, 350},
    /*   7 : CCMPNB spec4,reg64,rm64 [wrm:      evex.scc3.dfv.l0.m4.o64 3b /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 03) 300 324 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNB, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13943, 350},
    /*   8 : CCMPNB spec4,rm16,sbyteword16 [wmi:      evex.scc3.dfv.l0.m4.o16 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 03) 300 320 001(83) 217 276 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2389, 349},
    /*   9 : CCMPNB spec4,rm32,sbytedword32 [wmi:      evex.scc3.dfv.l0.m4.o32 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 03) 300 321 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2565, 350},
    /*  10 : CCMPNB spec4,rm64,sbytedword64 [wmi:      evex.scc3.dfv.l0.m4.o64 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 03) 300 324 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2741, 350},
    /*  11 : CCMPNB spec4,rm8,imm8 [wmi:      evex.scc3.dfv.l0.m4.o8 80 /7 ib    ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 03) 300 001(80) 217 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14103, 348},
    /*  12 : CCMPNB spec4,rm16,imm16 [wmi:      evex.scc3.dfv.l0.m4.o16 81 /7 iw   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 03) 300 320 001(81) 217 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+2917, 349},
    /*  13 : CCMPNB spec4,rm32,imm32 [wmi:      evex.scc3.dfv.l0.m4.o32 81 /7 id   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 03) 300 321 001(81) 217 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3093, 350},
    /*  14 : CCMPNB spec4,rm64,sdword64 [wmi:      evex.scc3.dfv.l0.m4.o64 81 /7 id,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 03) 300 324 001(81) 217 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3269, 350},
};

static const struct itemplate instrux_CCMPNBE[15] = {
    /*   0 : CCMPNBE spec4,rm8,reg8 [wmr:      evex.scc7.dfv.l0.m4.o8 38 /r       ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 07) 300 001(38) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24768, 348},
    /*   1 : CCMPNBE spec4,rm16,reg16 [wmr:      evex.scc7.dfv.l0.m4.o16 39 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 07) 300 320 001(39) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13133, 349},
    /*   2 : CCMPNBE spec4,rm32,reg32 [wmr:      evex.scc7.dfv.l0.m4.o32 39 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 07) 300 321 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13293, 350},
    /*   3 : CCMPNBE spec4,rm64,reg64 [wmr:      evex.scc7.dfv.l0.m4.o64 39 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 07) 300 324 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13453, 350},
    /*   4 : CCMPNBE spec4,reg8,rm8 [wrm:      evex.scc7.dfv.l0.m4.o8 3a /r       ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 07) 300 001(3a) 121 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNBE, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS8,RM_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24912, 348},
    /*   5 : CCMPNBE spec4,reg16,rm16 [wrm:      evex.scc7.dfv.l0.m4.o16 3b /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 07) 300 320 001(3b) 121 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNBE, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13613, 349},
    /*   6 : CCMPNBE spec4,reg32,rm32 [wrm:      evex.scc7.dfv.l0.m4.o32 3b /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 07) 300 321 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNBE, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13773, 350},
    /*   7 : CCMPNBE spec4,reg64,rm64 [wrm:      evex.scc7.dfv.l0.m4.o64 3b /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 07) 300 324 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNBE, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13933, 350},
    /*   8 : CCMPNBE spec4,rm16,sbyteword16 [wmi:      evex.scc7.dfv.l0.m4.o16 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 07) 300 320 001(83) 217 276 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2378, 349},
    /*   9 : CCMPNBE spec4,rm32,sbytedword32 [wmi:      evex.scc7.dfv.l0.m4.o32 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 07) 300 321 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2554, 350},
    /*  10 : CCMPNBE spec4,rm64,sbytedword64 [wmi:      evex.scc7.dfv.l0.m4.o64 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 07) 300 324 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2730, 350},
    /*  11 : CCMPNBE spec4,rm8,imm8 [wmi:      evex.scc7.dfv.l0.m4.o8 80 /7 ib    ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 07) 300 001(80) 217 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14093, 348},
    /*  12 : CCMPNBE spec4,rm16,imm16 [wmi:      evex.scc7.dfv.l0.m4.o16 81 /7 iw   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 07) 300 320 001(81) 217 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+2906, 349},
    /*  13 : CCMPNBE spec4,rm32,imm32 [wmi:      evex.scc7.dfv.l0.m4.o32 81 /7 id   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 07) 300 321 001(81) 217 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3082, 350},
    /*  14 : CCMPNBE spec4,rm64,sdword64 [wmi:      evex.scc7.dfv.l0.m4.o64 81 /7 id,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 07) 300 324 001(81) 217 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3258, 350},
};

static const struct itemplate instrux_CCMPNC[15] = {
    /*   0 : CCMPNC spec4,rm8,reg8 [wmr:      evex.scc3.dfv.l0.m4.o8 38 /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 03) 300 001(38) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24777, 348},
    /*   1 : CCMPNC spec4,rm16,reg16 [wmr:      evex.scc3.dfv.l0.m4.o16 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 03) 300 320 001(39) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13143, 349},
    /*   2 : CCMPNC spec4,rm32,reg32 [wmr:      evex.scc3.dfv.l0.m4.o32 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 03) 300 321 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13303, 350},
    /*   3 : CCMPNC spec4,rm64,reg64 [wmr:      evex.scc3.dfv.l0.m4.o64 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 03) 300 324 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13463, 350},
    /*   4 : CCMPNC spec4,reg8,rm8 [wrm:      evex.scc3.dfv.l0.m4.o8 3a /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 03) 300 001(3a) 121 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNC, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS8,RM_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24921, 348},
    /*   5 : CCMPNC spec4,reg16,rm16 [wrm:      evex.scc3.dfv.l0.m4.o16 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 03) 300 320 001(3b) 121 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNC, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13623, 349},
    /*   6 : CCMPNC spec4,reg32,rm32 [wrm:      evex.scc3.dfv.l0.m4.o32 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 03) 300 321 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNC, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13783, 350},
    /*   7 : CCMPNC spec4,reg64,rm64 [wrm:      evex.scc3.dfv.l0.m4.o64 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 03) 300 324 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNC, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13943, 350},
    /*   8 : CCMPNC spec4,rm16,sbyteword16 [wmi:      evex.scc3.dfv.l0.m4.o16 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 03) 300 320 001(83) 217 276 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2389, 349},
    /*   9 : CCMPNC spec4,rm32,sbytedword32 [wmi:      evex.scc3.dfv.l0.m4.o32 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 03) 300 321 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2565, 350},
    /*  10 : CCMPNC spec4,rm64,sbytedword64 [wmi:      evex.scc3.dfv.l0.m4.o64 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 03) 300 324 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2741, 350},
    /*  11 : CCMPNC spec4,rm8,imm8 [wmi:      evex.scc3.dfv.l0.m4.o8 80 /7 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 03) 300 001(80) 217 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14103, 348},
    /*  12 : CCMPNC spec4,rm16,imm16 [wmi:      evex.scc3.dfv.l0.m4.o16 81 /7 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 03) 300 320 001(81) 217 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+2917, 349},
    /*  13 : CCMPNC spec4,rm32,imm32 [wmi:      evex.scc3.dfv.l0.m4.o32 81 /7 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 03) 300 321 001(81) 217 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3093, 350},
    /*  14 : CCMPNC spec4,rm64,sdword64 [wmi:      evex.scc3.dfv.l0.m4.o64 81 /7 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 03) 300 324 001(81) 217 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3269, 350},
};

static const struct itemplate instrux_CCMPNE[15] = {
    /*   0 : CCMPNE spec4,rm8,reg8 [wmr:      evex.scc5.dfv.l0.m4.o8 38 /r       ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 05) 300 001(38) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24849, 348},
    /*   1 : CCMPNE spec4,rm16,reg16 [wmr:      evex.scc5.dfv.l0.m4.o16 39 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 05) 300 320 001(39) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13223, 349},
    /*   2 : CCMPNE spec4,rm32,reg32 [wmr:      evex.scc5.dfv.l0.m4.o32 39 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 05) 300 321 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13383, 350},
    /*   3 : CCMPNE spec4,rm64,reg64 [wmr:      evex.scc5.dfv.l0.m4.o64 39 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 05) 300 324 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13543, 350},
    /*   4 : CCMPNE spec4,reg8,rm8 [wrm:      evex.scc5.dfv.l0.m4.o8 3a /r       ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 05) 300 001(3a) 121 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNE, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS8,RM_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24993, 348},
    /*   5 : CCMPNE spec4,reg16,rm16 [wrm:      evex.scc5.dfv.l0.m4.o16 3b /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 05) 300 320 001(3b) 121 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNE, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13703, 349},
    /*   6 : CCMPNE spec4,reg32,rm32 [wrm:      evex.scc5.dfv.l0.m4.o32 3b /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 05) 300 321 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNE, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13863, 350},
    /*   7 : CCMPNE spec4,reg64,rm64 [wrm:      evex.scc5.dfv.l0.m4.o64 3b /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 05) 300 324 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNE, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14023, 350},
    /*   8 : CCMPNE spec4,rm16,sbyteword16 [wmi:      evex.scc5.dfv.l0.m4.o16 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 05) 300 320 001(83) 217 276 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2477, 349},
    /*   9 : CCMPNE spec4,rm32,sbytedword32 [wmi:      evex.scc5.dfv.l0.m4.o32 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 05) 300 321 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2653, 350},
    /*  10 : CCMPNE spec4,rm64,sbytedword64 [wmi:      evex.scc5.dfv.l0.m4.o64 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 05) 300 324 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2829, 350},
    /*  11 : CCMPNE spec4,rm8,imm8 [wmi:      evex.scc5.dfv.l0.m4.o8 80 /7 ib    ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 05) 300 001(80) 217 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14183, 348},
    /*  12 : CCMPNE spec4,rm16,imm16 [wmi:      evex.scc5.dfv.l0.m4.o16 81 /7 iw   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 05) 300 320 001(81) 217 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3005, 349},
    /*  13 : CCMPNE spec4,rm32,imm32 [wmi:      evex.scc5.dfv.l0.m4.o32 81 /7 id   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 05) 300 321 001(81) 217 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3181, 350},
    /*  14 : CCMPNE spec4,rm64,sdword64 [wmi:      evex.scc5.dfv.l0.m4.o64 81 /7 id,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 05) 300 324 001(81) 217 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3357, 350},
};

static const struct itemplate instrux_CCMPNG[15] = {
    /*   0 : CCMPNG spec4,rm8,reg8 [wmr:      evex.scc14.dfv.l0.m4.o8 38 /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0e) 300 001(38) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24840, 348},
    /*   1 : CCMPNG spec4,rm16,reg16 [wmr:      evex.scc14.dfv.l0.m4.o16 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0e) 300 320 001(39) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13213, 349},
    /*   2 : CCMPNG spec4,rm32,reg32 [wmr:      evex.scc14.dfv.l0.m4.o32 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0e) 300 321 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13373, 350},
    /*   3 : CCMPNG spec4,rm64,reg64 [wmr:      evex.scc14.dfv.l0.m4.o64 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0e) 300 324 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13533, 350},
    /*   4 : CCMPNG spec4,reg8,rm8 [wrm:      evex.scc14.dfv.l0.m4.o8 3a /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0e) 300 001(3a) 121 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNG, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS8,RM_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24984, 348},
    /*   5 : CCMPNG spec4,reg16,rm16 [wrm:      evex.scc14.dfv.l0.m4.o16 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0e) 300 320 001(3b) 121 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNG, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13693, 349},
    /*   6 : CCMPNG spec4,reg32,rm32 [wrm:      evex.scc14.dfv.l0.m4.o32 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0e) 300 321 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNG, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13853, 350},
    /*   7 : CCMPNG spec4,reg64,rm64 [wrm:      evex.scc14.dfv.l0.m4.o64 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0e) 300 324 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNG, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14013, 350},
    /*   8 : CCMPNG spec4,rm16,sbyteword16 [wmi:      evex.scc14.dfv.l0.m4.o16 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0e) 300 320 001(83) 217 276 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2466, 349},
    /*   9 : CCMPNG spec4,rm32,sbytedword32 [wmi:      evex.scc14.dfv.l0.m4.o32 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0e) 300 321 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2642, 350},
    /*  10 : CCMPNG spec4,rm64,sbytedword64 [wmi:      evex.scc14.dfv.l0.m4.o64 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0e) 300 324 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2818, 350},
    /*  11 : CCMPNG spec4,rm8,imm8 [wmi:      evex.scc14.dfv.l0.m4.o8 80 /7 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0e) 300 001(80) 217 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14173, 348},
    /*  12 : CCMPNG spec4,rm16,imm16 [wmi:      evex.scc14.dfv.l0.m4.o16 81 /7 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0e) 300 320 001(81) 217 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+2994, 349},
    /*  13 : CCMPNG spec4,rm32,imm32 [wmi:      evex.scc14.dfv.l0.m4.o32 81 /7 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0e) 300 321 001(81) 217 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3170, 350},
    /*  14 : CCMPNG spec4,rm64,sdword64 [wmi:      evex.scc14.dfv.l0.m4.o64 81 /7 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0e) 300 324 001(81) 217 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3346, 350},
};

static const struct itemplate instrux_CCMPNGE[15] = {
    /*   0 : CCMPNGE spec4,rm8,reg8 [wmr:      evex.scc12.dfv.l0.m4.o8 38 /r       ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0c) 300 001(38) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24831, 348},
    /*   1 : CCMPNGE spec4,rm16,reg16 [wmr:      evex.scc12.dfv.l0.m4.o16 39 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 0c) 300 320 001(39) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13203, 349},
    /*   2 : CCMPNGE spec4,rm32,reg32 [wmr:      evex.scc12.dfv.l0.m4.o32 39 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0c) 300 321 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13363, 350},
    /*   3 : CCMPNGE spec4,rm64,reg64 [wmr:      evex.scc12.dfv.l0.m4.o64 39 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 0c) 300 324 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13523, 350},
    /*   4 : CCMPNGE spec4,reg8,rm8 [wrm:      evex.scc12.dfv.l0.m4.o8 3a /r       ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0c) 300 001(3a) 121 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNGE, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS8,RM_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24975, 348},
    /*   5 : CCMPNGE spec4,reg16,rm16 [wrm:      evex.scc12.dfv.l0.m4.o16 3b /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 0c) 300 320 001(3b) 121 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNGE, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13683, 349},
    /*   6 : CCMPNGE spec4,reg32,rm32 [wrm:      evex.scc12.dfv.l0.m4.o32 3b /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0c) 300 321 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNGE, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13843, 350},
    /*   7 : CCMPNGE spec4,reg64,rm64 [wrm:      evex.scc12.dfv.l0.m4.o64 3b /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 0c) 300 324 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNGE, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14003, 350},
    /*   8 : CCMPNGE spec4,rm16,sbyteword16 [wmi:      evex.scc12.dfv.l0.m4.o16 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 0c) 300 320 001(83) 217 276 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2455, 349},
    /*   9 : CCMPNGE spec4,rm32,sbytedword32 [wmi:      evex.scc12.dfv.l0.m4.o32 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0c) 300 321 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2631, 350},
    /*  10 : CCMPNGE spec4,rm64,sbytedword64 [wmi:      evex.scc12.dfv.l0.m4.o64 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 0c) 300 324 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2807, 350},
    /*  11 : CCMPNGE spec4,rm8,imm8 [wmi:      evex.scc12.dfv.l0.m4.o8 80 /7 ib    ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0c) 300 001(80) 217 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14163, 348},
    /*  12 : CCMPNGE spec4,rm16,imm16 [wmi:      evex.scc12.dfv.l0.m4.o16 81 /7 iw   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 0c) 300 320 001(81) 217 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+2983, 349},
    /*  13 : CCMPNGE spec4,rm32,imm32 [wmi:      evex.scc12.dfv.l0.m4.o32 81 /7 id   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0c) 300 321 001(81) 217 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3159, 350},
    /*  14 : CCMPNGE spec4,rm64,sdword64 [wmi:      evex.scc12.dfv.l0.m4.o64 81 /7 id,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 0c) 300 324 001(81) 217 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3335, 350},
};

static const struct itemplate instrux_CCMPNL[15] = {
    /*   0 : CCMPNL spec4,rm8,reg8 [wmr:      evex.scc13.dfv.l0.m4.o8 38 /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0d) 300 001(38) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24822, 348},
    /*   1 : CCMPNL spec4,rm16,reg16 [wmr:      evex.scc13.dfv.l0.m4.o16 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0d) 300 320 001(39) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13193, 349},
    /*   2 : CCMPNL spec4,rm32,reg32 [wmr:      evex.scc13.dfv.l0.m4.o32 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0d) 300 321 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13353, 350},
    /*   3 : CCMPNL spec4,rm64,reg64 [wmr:      evex.scc13.dfv.l0.m4.o64 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0d) 300 324 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13513, 350},
    /*   4 : CCMPNL spec4,reg8,rm8 [wrm:      evex.scc13.dfv.l0.m4.o8 3a /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0d) 300 001(3a) 121 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNL, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS8,RM_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24966, 348},
    /*   5 : CCMPNL spec4,reg16,rm16 [wrm:      evex.scc13.dfv.l0.m4.o16 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0d) 300 320 001(3b) 121 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNL, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13673, 349},
    /*   6 : CCMPNL spec4,reg32,rm32 [wrm:      evex.scc13.dfv.l0.m4.o32 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0d) 300 321 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNL, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13833, 350},
    /*   7 : CCMPNL spec4,reg64,rm64 [wrm:      evex.scc13.dfv.l0.m4.o64 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0d) 300 324 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNL, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13993, 350},
    /*   8 : CCMPNL spec4,rm16,sbyteword16 [wmi:      evex.scc13.dfv.l0.m4.o16 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0d) 300 320 001(83) 217 276 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2444, 349},
    /*   9 : CCMPNL spec4,rm32,sbytedword32 [wmi:      evex.scc13.dfv.l0.m4.o32 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0d) 300 321 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2620, 350},
    /*  10 : CCMPNL spec4,rm64,sbytedword64 [wmi:      evex.scc13.dfv.l0.m4.o64 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0d) 300 324 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2796, 350},
    /*  11 : CCMPNL spec4,rm8,imm8 [wmi:      evex.scc13.dfv.l0.m4.o8 80 /7 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0d) 300 001(80) 217 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14153, 348},
    /*  12 : CCMPNL spec4,rm16,imm16 [wmi:      evex.scc13.dfv.l0.m4.o16 81 /7 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0d) 300 320 001(81) 217 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+2972, 349},
    /*  13 : CCMPNL spec4,rm32,imm32 [wmi:      evex.scc13.dfv.l0.m4.o32 81 /7 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0d) 300 321 001(81) 217 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3148, 350},
    /*  14 : CCMPNL spec4,rm64,sdword64 [wmi:      evex.scc13.dfv.l0.m4.o64 81 /7 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0d) 300 324 001(81) 217 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3324, 350},
};

static const struct itemplate instrux_CCMPNLE[15] = {
    /*   0 : CCMPNLE spec4,rm8,reg8 [wmr:      evex.scc15.dfv.l0.m4.o8 38 /r       ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0f) 300 001(38) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24813, 348},
    /*   1 : CCMPNLE spec4,rm16,reg16 [wmr:      evex.scc15.dfv.l0.m4.o16 39 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 0f) 300 320 001(39) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13183, 349},
    /*   2 : CCMPNLE spec4,rm32,reg32 [wmr:      evex.scc15.dfv.l0.m4.o32 39 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0f) 300 321 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13343, 350},
    /*   3 : CCMPNLE spec4,rm64,reg64 [wmr:      evex.scc15.dfv.l0.m4.o64 39 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 0f) 300 324 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13503, 350},
    /*   4 : CCMPNLE spec4,reg8,rm8 [wrm:      evex.scc15.dfv.l0.m4.o8 3a /r       ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0f) 300 001(3a) 121 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNLE, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS8,RM_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24957, 348},
    /*   5 : CCMPNLE spec4,reg16,rm16 [wrm:      evex.scc15.dfv.l0.m4.o16 3b /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 0f) 300 320 001(3b) 121 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNLE, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13663, 349},
    /*   6 : CCMPNLE spec4,reg32,rm32 [wrm:      evex.scc15.dfv.l0.m4.o32 3b /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0f) 300 321 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNLE, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13823, 350},
    /*   7 : CCMPNLE spec4,reg64,rm64 [wrm:      evex.scc15.dfv.l0.m4.o64 3b /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 0f) 300 324 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNLE, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13983, 350},
    /*   8 : CCMPNLE spec4,rm16,sbyteword16 [wmi:      evex.scc15.dfv.l0.m4.o16 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 0f) 300 320 001(83) 217 276 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2433, 349},
    /*   9 : CCMPNLE spec4,rm32,sbytedword32 [wmi:      evex.scc15.dfv.l0.m4.o32 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0f) 300 321 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2609, 350},
    /*  10 : CCMPNLE spec4,rm64,sbytedword64 [wmi:      evex.scc15.dfv.l0.m4.o64 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 0f) 300 324 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2785, 350},
    /*  11 : CCMPNLE spec4,rm8,imm8 [wmi:      evex.scc15.dfv.l0.m4.o8 80 /7 ib    ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0f) 300 001(80) 217 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14143, 348},
    /*  12 : CCMPNLE spec4,rm16,imm16 [wmi:      evex.scc15.dfv.l0.m4.o16 81 /7 iw   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 0f) 300 320 001(81) 217 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+2961, 349},
    /*  13 : CCMPNLE spec4,rm32,imm32 [wmi:      evex.scc15.dfv.l0.m4.o32 81 /7 id   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0f) 300 321 001(81) 217 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3137, 350},
    /*  14 : CCMPNLE spec4,rm64,sdword64 [wmi:      evex.scc15.dfv.l0.m4.o64 81 /7 id,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 0f) 300 324 001(81) 217 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3313, 350},
};

static const struct itemplate instrux_CCMPNO[15] = {
    /*   0 : CCMPNO spec4,rm8,reg8 [wmr:      evex.scc1.dfv.l0.m4.o8 38 /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 01) 300 001(38) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24858, 348},
    /*   1 : CCMPNO spec4,rm16,reg16 [wmr:      evex.scc1.dfv.l0.m4.o16 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 01) 300 320 001(39) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13233, 349},
    /*   2 : CCMPNO spec4,rm32,reg32 [wmr:      evex.scc1.dfv.l0.m4.o32 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 01) 300 321 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13393, 350},
    /*   3 : CCMPNO spec4,rm64,reg64 [wmr:      evex.scc1.dfv.l0.m4.o64 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 01) 300 324 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13553, 350},
    /*   4 : CCMPNO spec4,reg8,rm8 [wrm:      evex.scc1.dfv.l0.m4.o8 3a /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 01) 300 001(3a) 121 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNO, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS8,RM_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+25002, 348},
    /*   5 : CCMPNO spec4,reg16,rm16 [wrm:      evex.scc1.dfv.l0.m4.o16 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 01) 300 320 001(3b) 121 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNO, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13713, 349},
    /*   6 : CCMPNO spec4,reg32,rm32 [wrm:      evex.scc1.dfv.l0.m4.o32 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 01) 300 321 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNO, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13873, 350},
    /*   7 : CCMPNO spec4,reg64,rm64 [wrm:      evex.scc1.dfv.l0.m4.o64 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 01) 300 324 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNO, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14033, 350},
    /*   8 : CCMPNO spec4,rm16,sbyteword16 [wmi:      evex.scc1.dfv.l0.m4.o16 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 01) 300 320 001(83) 217 276 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2488, 349},
    /*   9 : CCMPNO spec4,rm32,sbytedword32 [wmi:      evex.scc1.dfv.l0.m4.o32 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 01) 300 321 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2664, 350},
    /*  10 : CCMPNO spec4,rm64,sbytedword64 [wmi:      evex.scc1.dfv.l0.m4.o64 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 01) 300 324 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2840, 350},
    /*  11 : CCMPNO spec4,rm8,imm8 [wmi:      evex.scc1.dfv.l0.m4.o8 80 /7 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 01) 300 001(80) 217 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14193, 348},
    /*  12 : CCMPNO spec4,rm16,imm16 [wmi:      evex.scc1.dfv.l0.m4.o16 81 /7 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 01) 300 320 001(81) 217 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3016, 349},
    /*  13 : CCMPNO spec4,rm32,imm32 [wmi:      evex.scc1.dfv.l0.m4.o32 81 /7 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 01) 300 321 001(81) 217 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3192, 350},
    /*  14 : CCMPNO spec4,rm64,sdword64 [wmi:      evex.scc1.dfv.l0.m4.o64 81 /7 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 01) 300 324 001(81) 217 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3368, 350},
};

static const struct itemplate instrux_CCMPNS[15] = {
    /*   0 : CCMPNS spec4,rm8,reg8 [wmr:      evex.scc9.dfv.l0.m4.o8 38 /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 09) 300 001(38) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24867, 348},
    /*   1 : CCMPNS spec4,rm16,reg16 [wmr:      evex.scc9.dfv.l0.m4.o16 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 09) 300 320 001(39) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13243, 349},
    /*   2 : CCMPNS spec4,rm32,reg32 [wmr:      evex.scc9.dfv.l0.m4.o32 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 09) 300 321 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13403, 350},
    /*   3 : CCMPNS spec4,rm64,reg64 [wmr:      evex.scc9.dfv.l0.m4.o64 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 09) 300 324 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13563, 350},
    /*   4 : CCMPNS spec4,reg8,rm8 [wrm:      evex.scc9.dfv.l0.m4.o8 3a /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 09) 300 001(3a) 121 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNS, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS8,RM_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+25011, 348},
    /*   5 : CCMPNS spec4,reg16,rm16 [wrm:      evex.scc9.dfv.l0.m4.o16 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 09) 300 320 001(3b) 121 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNS, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13723, 349},
    /*   6 : CCMPNS spec4,reg32,rm32 [wrm:      evex.scc9.dfv.l0.m4.o32 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 09) 300 321 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNS, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13883, 350},
    /*   7 : CCMPNS spec4,reg64,rm64 [wrm:      evex.scc9.dfv.l0.m4.o64 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 09) 300 324 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNS, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14043, 350},
    /*   8 : CCMPNS spec4,rm16,sbyteword16 [wmi:      evex.scc9.dfv.l0.m4.o16 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 09) 300 320 001(83) 217 276 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2499, 349},
    /*   9 : CCMPNS spec4,rm32,sbytedword32 [wmi:      evex.scc9.dfv.l0.m4.o32 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 09) 300 321 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2675, 350},
    /*  10 : CCMPNS spec4,rm64,sbytedword64 [wmi:      evex.scc9.dfv.l0.m4.o64 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 09) 300 324 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2851, 350},
    /*  11 : CCMPNS spec4,rm8,imm8 [wmi:      evex.scc9.dfv.l0.m4.o8 80 /7 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 09) 300 001(80) 217 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14203, 348},
    /*  12 : CCMPNS spec4,rm16,imm16 [wmi:      evex.scc9.dfv.l0.m4.o16 81 /7 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 09) 300 320 001(81) 217 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3027, 349},
    /*  13 : CCMPNS spec4,rm32,imm32 [wmi:      evex.scc9.dfv.l0.m4.o32 81 /7 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 09) 300 321 001(81) 217 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3203, 350},
    /*  14 : CCMPNS spec4,rm64,sdword64 [wmi:      evex.scc9.dfv.l0.m4.o64 81 /7 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 09) 300 324 001(81) 217 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3379, 350},
};

static const struct itemplate instrux_CCMPNZ[15] = {
    /*   0 : CCMPNZ spec4,rm8,reg8 [wmr:      evex.scc5.dfv.l0.m4.o8 38 /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 05) 300 001(38) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24849, 348},
    /*   1 : CCMPNZ spec4,rm16,reg16 [wmr:      evex.scc5.dfv.l0.m4.o16 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 05) 300 320 001(39) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13223, 349},
    /*   2 : CCMPNZ spec4,rm32,reg32 [wmr:      evex.scc5.dfv.l0.m4.o32 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 05) 300 321 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13383, 350},
    /*   3 : CCMPNZ spec4,rm64,reg64 [wmr:      evex.scc5.dfv.l0.m4.o64 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 05) 300 324 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13543, 350},
    /*   4 : CCMPNZ spec4,reg8,rm8 [wrm:      evex.scc5.dfv.l0.m4.o8 3a /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 05) 300 001(3a) 121 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNZ, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS8,RM_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24993, 348},
    /*   5 : CCMPNZ spec4,reg16,rm16 [wrm:      evex.scc5.dfv.l0.m4.o16 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 05) 300 320 001(3b) 121 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNZ, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13703, 349},
    /*   6 : CCMPNZ spec4,reg32,rm32 [wrm:      evex.scc5.dfv.l0.m4.o32 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 05) 300 321 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNZ, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13863, 350},
    /*   7 : CCMPNZ spec4,reg64,rm64 [wrm:      evex.scc5.dfv.l0.m4.o64 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 05) 300 324 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNZ, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14023, 350},
    /*   8 : CCMPNZ spec4,rm16,sbyteword16 [wmi:      evex.scc5.dfv.l0.m4.o16 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 05) 300 320 001(83) 217 276 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2477, 349},
    /*   9 : CCMPNZ spec4,rm32,sbytedword32 [wmi:      evex.scc5.dfv.l0.m4.o32 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 05) 300 321 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2653, 350},
    /*  10 : CCMPNZ spec4,rm64,sbytedword64 [wmi:      evex.scc5.dfv.l0.m4.o64 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 05) 300 324 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2829, 350},
    /*  11 : CCMPNZ spec4,rm8,imm8 [wmi:      evex.scc5.dfv.l0.m4.o8 80 /7 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 05) 300 001(80) 217 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14183, 348},
    /*  12 : CCMPNZ spec4,rm16,imm16 [wmi:      evex.scc5.dfv.l0.m4.o16 81 /7 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 05) 300 320 001(81) 217 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3005, 349},
    /*  13 : CCMPNZ spec4,rm32,imm32 [wmi:      evex.scc5.dfv.l0.m4.o32 81 /7 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 05) 300 321 001(81) 217 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3181, 350},
    /*  14 : CCMPNZ spec4,rm64,sdword64 [wmi:      evex.scc5.dfv.l0.m4.o64 81 /7 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 05) 300 324 001(81) 217 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPNZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3357, 350},
};

static const struct itemplate instrux_CCMPO[15] = {
    /*   0 : CCMPO spec4,rm8,reg8 [wmr:      evex.scc0.dfv.l0.m4.o8 38 /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 00) 300 001(38) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24876, 348},
    /*   1 : CCMPO spec4,rm16,reg16 [wmr:      evex.scc0.dfv.l0.m4.o16 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 00) 300 320 001(39) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13253, 349},
    /*   2 : CCMPO spec4,rm32,reg32 [wmr:      evex.scc0.dfv.l0.m4.o32 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 00) 300 321 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13413, 350},
    /*   3 : CCMPO spec4,rm64,reg64 [wmr:      evex.scc0.dfv.l0.m4.o64 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 00) 300 324 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13573, 350},
    /*   4 : CCMPO spec4,reg8,rm8 [wrm:      evex.scc0.dfv.l0.m4.o8 3a /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 00) 300 001(3a) 121 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPO, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS8,RM_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+25020, 348},
    /*   5 : CCMPO spec4,reg16,rm16 [wrm:      evex.scc0.dfv.l0.m4.o16 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 00) 300 320 001(3b) 121 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPO, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13733, 349},
    /*   6 : CCMPO spec4,reg32,rm32 [wrm:      evex.scc0.dfv.l0.m4.o32 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 00) 300 321 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPO, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13893, 350},
    /*   7 : CCMPO spec4,reg64,rm64 [wrm:      evex.scc0.dfv.l0.m4.o64 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 00) 300 324 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPO, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14053, 350},
    /*   8 : CCMPO spec4,rm16,sbyteword16 [wmi:      evex.scc0.dfv.l0.m4.o16 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 00) 300 320 001(83) 217 276 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2510, 349},
    /*   9 : CCMPO spec4,rm32,sbytedword32 [wmi:      evex.scc0.dfv.l0.m4.o32 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 00) 300 321 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2686, 350},
    /*  10 : CCMPO spec4,rm64,sbytedword64 [wmi:      evex.scc0.dfv.l0.m4.o64 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 00) 300 324 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2862, 350},
    /*  11 : CCMPO spec4,rm8,imm8 [wmi:      evex.scc0.dfv.l0.m4.o8 80 /7 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 00) 300 001(80) 217 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14213, 348},
    /*  12 : CCMPO spec4,rm16,imm16 [wmi:      evex.scc0.dfv.l0.m4.o16 81 /7 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 00) 300 320 001(81) 217 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3038, 349},
    /*  13 : CCMPO spec4,rm32,imm32 [wmi:      evex.scc0.dfv.l0.m4.o32 81 /7 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 00) 300 321 001(81) 217 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3214, 350},
    /*  14 : CCMPO spec4,rm64,sdword64 [wmi:      evex.scc0.dfv.l0.m4.o64 81 /7 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 00) 300 324 001(81) 217 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3390, 350},
};

static const struct itemplate instrux_CCMPS[15] = {
    /*   0 : CCMPS spec4,rm8,reg8 [wmr:      evex.scc8.dfv.l0.m4.o8 38 /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 08) 300 001(38) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24885, 348},
    /*   1 : CCMPS spec4,rm16,reg16 [wmr:      evex.scc8.dfv.l0.m4.o16 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 08) 300 320 001(39) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13263, 349},
    /*   2 : CCMPS spec4,rm32,reg32 [wmr:      evex.scc8.dfv.l0.m4.o32 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 08) 300 321 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13423, 350},
    /*   3 : CCMPS spec4,rm64,reg64 [wmr:      evex.scc8.dfv.l0.m4.o64 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 08) 300 324 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13583, 350},
    /*   4 : CCMPS spec4,reg8,rm8 [wrm:      evex.scc8.dfv.l0.m4.o8 3a /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 08) 300 001(3a) 121 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPS, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS8,RM_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+25029, 348},
    /*   5 : CCMPS spec4,reg16,rm16 [wrm:      evex.scc8.dfv.l0.m4.o16 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 08) 300 320 001(3b) 121 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPS, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13743, 349},
    /*   6 : CCMPS spec4,reg32,rm32 [wrm:      evex.scc8.dfv.l0.m4.o32 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 08) 300 321 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPS, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13903, 350},
    /*   7 : CCMPS spec4,reg64,rm64 [wrm:      evex.scc8.dfv.l0.m4.o64 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 08) 300 324 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPS, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14063, 350},
    /*   8 : CCMPS spec4,rm16,sbyteword16 [wmi:      evex.scc8.dfv.l0.m4.o16 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 08) 300 320 001(83) 217 276 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2521, 349},
    /*   9 : CCMPS spec4,rm32,sbytedword32 [wmi:      evex.scc8.dfv.l0.m4.o32 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 08) 300 321 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2697, 350},
    /*  10 : CCMPS spec4,rm64,sbytedword64 [wmi:      evex.scc8.dfv.l0.m4.o64 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 08) 300 324 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2873, 350},
    /*  11 : CCMPS spec4,rm8,imm8 [wmi:      evex.scc8.dfv.l0.m4.o8 80 /7 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 08) 300 001(80) 217 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14223, 348},
    /*  12 : CCMPS spec4,rm16,imm16 [wmi:      evex.scc8.dfv.l0.m4.o16 81 /7 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 08) 300 320 001(81) 217 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3049, 349},
    /*  13 : CCMPS spec4,rm32,imm32 [wmi:      evex.scc8.dfv.l0.m4.o32 81 /7 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 08) 300 321 001(81) 217 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3225, 350},
    /*  14 : CCMPS spec4,rm64,sdword64 [wmi:      evex.scc8.dfv.l0.m4.o64 81 /7 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 08) 300 324 001(81) 217 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3401, 350},
};

static const struct itemplate instrux_CCMPT[15] = {
    /*   0 : CCMPT spec4,rm8,reg8 [wmr:      evex.scc10.dfv.l0.m4.o8 38 /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0a) 300 001(38) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPT, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24894, 348},
    /*   1 : CCMPT spec4,rm16,reg16 [wmr:      evex.scc10.dfv.l0.m4.o16 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0a) 300 320 001(39) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPT, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13273, 349},
    /*   2 : CCMPT spec4,rm32,reg32 [wmr:      evex.scc10.dfv.l0.m4.o32 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0a) 300 321 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPT, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13433, 350},
    /*   3 : CCMPT spec4,rm64,reg64 [wmr:      evex.scc10.dfv.l0.m4.o64 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0a) 300 324 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPT, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13593, 350},
    /*   4 : CCMPT spec4,reg8,rm8 [wrm:      evex.scc10.dfv.l0.m4.o8 3a /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0a) 300 001(3a) 121 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPT, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS8,RM_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+25038, 348},
    /*   5 : CCMPT spec4,reg16,rm16 [wrm:      evex.scc10.dfv.l0.m4.o16 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0a) 300 320 001(3b) 121 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPT, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13753, 349},
    /*   6 : CCMPT spec4,reg32,rm32 [wrm:      evex.scc10.dfv.l0.m4.o32 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0a) 300 321 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPT, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13913, 350},
    /*   7 : CCMPT spec4,reg64,rm64 [wrm:      evex.scc10.dfv.l0.m4.o64 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0a) 300 324 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPT, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14073, 350},
    /*   8 : CCMPT spec4,rm16,sbyteword16 [wmi:      evex.scc10.dfv.l0.m4.o16 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0a) 300 320 001(83) 217 276 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPT, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2532, 349},
    /*   9 : CCMPT spec4,rm32,sbytedword32 [wmi:      evex.scc10.dfv.l0.m4.o32 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0a) 300 321 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPT, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2708, 350},
    /*  10 : CCMPT spec4,rm64,sbytedword64 [wmi:      evex.scc10.dfv.l0.m4.o64 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0a) 300 324 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPT, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2884, 350},
    /*  11 : CCMPT spec4,rm8,imm8 [wmi:      evex.scc10.dfv.l0.m4.o8 80 /7 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0a) 300 001(80) 217 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPT, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14233, 348},
    /*  12 : CCMPT spec4,rm16,imm16 [wmi:      evex.scc10.dfv.l0.m4.o16 81 /7 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0a) 300 320 001(81) 217 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPT, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3060, 349},
    /*  13 : CCMPT spec4,rm32,imm32 [wmi:      evex.scc10.dfv.l0.m4.o32 81 /7 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0a) 300 321 001(81) 217 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPT, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3236, 350},
    /*  14 : CCMPT spec4,rm64,sdword64 [wmi:      evex.scc10.dfv.l0.m4.o64 81 /7 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0a) 300 324 001(81) 217 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPT, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3412, 350},
};

static const struct itemplate instrux_CCMPZ[15] = {
    /*   0 : CCMPZ spec4,rm8,reg8 [wmr:      evex.scc4.dfv.l0.m4.o8 38 /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 04) 300 001(38) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24804, 348},
    /*   1 : CCMPZ spec4,rm16,reg16 [wmr:      evex.scc4.dfv.l0.m4.o16 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 04) 300 320 001(39) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13173, 349},
    /*   2 : CCMPZ spec4,rm32,reg32 [wmr:      evex.scc4.dfv.l0.m4.o32 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 04) 300 321 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13333, 350},
    /*   3 : CCMPZ spec4,rm64,reg64 [wmr:      evex.scc4.dfv.l0.m4.o64 39 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 04) 300 324 001(39) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13493, 350},
    /*   4 : CCMPZ spec4,reg8,rm8 [wrm:      evex.scc4.dfv.l0.m4.o8 3a /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 04) 300 001(3a) 121 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPZ, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS8,RM_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+24948, 348},
    /*   5 : CCMPZ spec4,reg16,rm16 [wrm:      evex.scc4.dfv.l0.m4.o16 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 04) 300 320 001(3b) 121 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPZ, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+13653, 349},
    /*   6 : CCMPZ spec4,reg32,rm32 [wrm:      evex.scc4.dfv.l0.m4.o32 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 04) 300 321 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPZ, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+13813, 350},
    /*   7 : CCMPZ spec4,reg64,rm64 [wrm:      evex.scc4.dfv.l0.m4.o64 3b /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 04) 300 324 001(3b) 121 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPZ, 3, {IMMEDIATE|FOURBITS,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+13973, 350},
    /*   8 : CCMPZ spec4,rm16,sbyteword16 [wmi:      evex.scc4.dfv.l0.m4.o16 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 04) 300 320 001(83) 217 276 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,SBYTEWORD|BITS16|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2422, 349},
    /*   9 : CCMPZ spec4,rm32,sbytedword32 [wmi:      evex.scc4.dfv.l0.m4.o32 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 04) 300 321 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,SBYTEDWORD|BITS32|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2598, 350},
    /*  10 : CCMPZ spec4,rm64,sbytedword64 [wmi:      evex.scc4.dfv.l0.m4.o64 83 /7 ib,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 04) 300 324 001(83) 217 276 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SBYTEDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+2774, 350},
    /*  11 : CCMPZ spec4,rm8,imm8 [wmi:      evex.scc4.dfv.l0.m4.o8 80 /7 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 04) 300 001(80) 217 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14133, 348},
    /*  12 : CCMPZ spec4,rm16,imm16 [wmi:      evex.scc4.dfv.l0.m4.o16 81 /7 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 04) 300 320 001(81) 217 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+2950, 349},
    /*  13 : CCMPZ spec4,rm32,imm32 [wmi:      evex.scc4.dfv.l0.m4.o32 81 /7 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 04) 300 321 001(81) 217 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3126, 350},
    /*  14 : CCMPZ spec4,rm64,sdword64 [wmi:      evex.scc4.dfv.l0.m4.o64 81 /7 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 04) 300 324 001(81) 217 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CCMPZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3302, 350},
};

static const struct itemplate instrux_CTEST[12] = {
    /*   0 : CTEST spec4,rm8,reg8 [wmr:      evex.scc11.dfv.l0.m4.o8 84 /r       ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0b) 300 001(84) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTEST, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+25047, 348},
    /*   1 : CTEST spec4,rm16,reg16 [wmr:      evex.scc11.dfv.l0.m4.o16 85 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 0b) 300 320 001(85) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTEST, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+14243, 349},
    /*   2 : CTEST spec4,rm32,reg32 [wmr:      evex.scc11.dfv.l0.m4.o32 85 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0b) 300 321 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTEST, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+14403, 350},
    /*   3 : CTEST spec4,rm64,reg64 [wmr:      evex.scc11.dfv.l0.m4.o64 85 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 0b) 300 324 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTEST, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14563, 350},
    /*   4 : CTEST spec4,rm8,imm8 [wmi:      evex.scc11.dfv.l0.m4.o8 f6 /0 ib    ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0b) 300 001(f6) 210 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTEST, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14723, 348},
    /*   5 : CTEST spec4,rm16,imm16 [wmi:      evex.scc11.dfv.l0.m4.o16 f7 /0 iw   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 0b) 300 320 001(f7) 210 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTEST, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3423, 349},
    /*   6 : CTEST spec4,rm32,imm32 [wmi:      evex.scc11.dfv.l0.m4.o32 f7 /0 id   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0b) 300 321 001(f7) 210 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTEST, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3599, 350},
    /*   7 : CTEST spec4,rm64,sdword64 [wmi:      evex.scc11.dfv.l0.m4.o64 f7 /0 id,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 0b) 300 324 001(f7) 210 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTEST, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3775, 350},
    /*   8 : CTEST spec4,rm8,imm8 [wmi:      evex.scc11.dfv.l0.m4.o8 f6 /1 ib    ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0b) 300 001(f6) 211 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTEST, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14883, 348},
    /*   9 : CTEST spec4,rm16,imm16 [wmi:      evex.scc11.dfv.l0.m4.o16 f7 /1 iw   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 0b) 300 320 001(f7) 211 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTEST, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3951, 349},
    /*  10 : CTEST spec4,rm32,imm32 [wmi:      evex.scc11.dfv.l0.m4.o32 f7 /1 id   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0b) 300 321 001(f7) 211 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTEST, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+4127, 350},
    /*  11 : CTEST spec4,rm64,sdword64 [wmi:      evex.scc11.dfv.l0.m4.o64 f7 /1 id,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 0b) 300 324 001(f7) 211 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTEST, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+4303, 350},
};

static const struct itemplate instrux_CTESTA[12] = {
    /*   0 : CTESTA spec4,rm8,reg8 [wmr:      evex.scc7.dfv.l0.m4.o8 84 /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 07) 300 001(84) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+25056, 348},
    /*   1 : CTESTA spec4,rm16,reg16 [wmr:      evex.scc7.dfv.l0.m4.o16 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 07) 300 320 001(85) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+14253, 349},
    /*   2 : CTESTA spec4,rm32,reg32 [wmr:      evex.scc7.dfv.l0.m4.o32 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 07) 300 321 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+14413, 350},
    /*   3 : CTESTA spec4,rm64,reg64 [wmr:      evex.scc7.dfv.l0.m4.o64 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 07) 300 324 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14573, 350},
    /*   4 : CTESTA spec4,rm8,imm8 [wmi:      evex.scc7.dfv.l0.m4.o8 f6 /0 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 07) 300 001(f6) 210 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14733, 348},
    /*   5 : CTESTA spec4,rm16,imm16 [wmi:      evex.scc7.dfv.l0.m4.o16 f7 /0 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 07) 300 320 001(f7) 210 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3434, 349},
    /*   6 : CTESTA spec4,rm32,imm32 [wmi:      evex.scc7.dfv.l0.m4.o32 f7 /0 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 07) 300 321 001(f7) 210 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3610, 350},
    /*   7 : CTESTA spec4,rm64,sdword64 [wmi:      evex.scc7.dfv.l0.m4.o64 f7 /0 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 07) 300 324 001(f7) 210 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3786, 350},
    /*   8 : CTESTA spec4,rm8,imm8 [wmi:      evex.scc7.dfv.l0.m4.o8 f6 /1 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 07) 300 001(f6) 211 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14893, 348},
    /*   9 : CTESTA spec4,rm16,imm16 [wmi:      evex.scc7.dfv.l0.m4.o16 f7 /1 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 07) 300 320 001(f7) 211 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3962, 349},
    /*  10 : CTESTA spec4,rm32,imm32 [wmi:      evex.scc7.dfv.l0.m4.o32 f7 /1 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 07) 300 321 001(f7) 211 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+4138, 350},
    /*  11 : CTESTA spec4,rm64,sdword64 [wmi:      evex.scc7.dfv.l0.m4.o64 f7 /1 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 07) 300 324 001(f7) 211 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+4314, 350},
};

static const struct itemplate instrux_CTESTAE[12] = {
    /*   0 : CTESTAE spec4,rm8,reg8 [wmr:      evex.scc3.dfv.l0.m4.o8 84 /r       ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 03) 300 001(84) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+25065, 348},
    /*   1 : CTESTAE spec4,rm16,reg16 [wmr:      evex.scc3.dfv.l0.m4.o16 85 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 03) 300 320 001(85) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+14263, 349},
    /*   2 : CTESTAE spec4,rm32,reg32 [wmr:      evex.scc3.dfv.l0.m4.o32 85 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 03) 300 321 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+14423, 350},
    /*   3 : CTESTAE spec4,rm64,reg64 [wmr:      evex.scc3.dfv.l0.m4.o64 85 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 03) 300 324 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14583, 350},
    /*   4 : CTESTAE spec4,rm8,imm8 [wmi:      evex.scc3.dfv.l0.m4.o8 f6 /0 ib    ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 03) 300 001(f6) 210 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14743, 348},
    /*   5 : CTESTAE spec4,rm16,imm16 [wmi:      evex.scc3.dfv.l0.m4.o16 f7 /0 iw   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 03) 300 320 001(f7) 210 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3445, 349},
    /*   6 : CTESTAE spec4,rm32,imm32 [wmi:      evex.scc3.dfv.l0.m4.o32 f7 /0 id   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 03) 300 321 001(f7) 210 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3621, 350},
    /*   7 : CTESTAE spec4,rm64,sdword64 [wmi:      evex.scc3.dfv.l0.m4.o64 f7 /0 id,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 03) 300 324 001(f7) 210 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3797, 350},
    /*   8 : CTESTAE spec4,rm8,imm8 [wmi:      evex.scc3.dfv.l0.m4.o8 f6 /1 ib    ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 03) 300 001(f6) 211 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14903, 348},
    /*   9 : CTESTAE spec4,rm16,imm16 [wmi:      evex.scc3.dfv.l0.m4.o16 f7 /1 iw   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 03) 300 320 001(f7) 211 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3973, 349},
    /*  10 : CTESTAE spec4,rm32,imm32 [wmi:      evex.scc3.dfv.l0.m4.o32 f7 /1 id   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 03) 300 321 001(f7) 211 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+4149, 350},
    /*  11 : CTESTAE spec4,rm64,sdword64 [wmi:      evex.scc3.dfv.l0.m4.o64 f7 /1 id,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 03) 300 324 001(f7) 211 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+4325, 350},
};

static const struct itemplate instrux_CTESTB[12] = {
    /*   0 : CTESTB spec4,rm8,reg8 [wmr:      evex.scc2.dfv.l0.m4.o8 84 /r       ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 02) 300 001(84) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+25074, 348},
    /*   1 : CTESTB spec4,rm16,reg16 [wmr:      evex.scc2.dfv.l0.m4.o16 85 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 02) 300 320 001(85) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+14273, 349},
    /*   2 : CTESTB spec4,rm32,reg32 [wmr:      evex.scc2.dfv.l0.m4.o32 85 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 02) 300 321 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+14433, 350},
    /*   3 : CTESTB spec4,rm64,reg64 [wmr:      evex.scc2.dfv.l0.m4.o64 85 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 02) 300 324 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14593, 350},
    /*   4 : CTESTB spec4,rm8,imm8 [wmi:      evex.scc2.dfv.l0.m4.o8 f6 /0 ib    ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 02) 300 001(f6) 210 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14753, 348},
    /*   5 : CTESTB spec4,rm16,imm16 [wmi:      evex.scc2.dfv.l0.m4.o16 f7 /0 iw   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 02) 300 320 001(f7) 210 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3456, 349},
    /*   6 : CTESTB spec4,rm32,imm32 [wmi:      evex.scc2.dfv.l0.m4.o32 f7 /0 id   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 02) 300 321 001(f7) 210 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3632, 350},
    /*   7 : CTESTB spec4,rm64,sdword64 [wmi:      evex.scc2.dfv.l0.m4.o64 f7 /0 id,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 02) 300 324 001(f7) 210 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3808, 350},
    /*   8 : CTESTB spec4,rm8,imm8 [wmi:      evex.scc2.dfv.l0.m4.o8 f6 /1 ib    ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 02) 300 001(f6) 211 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14913, 348},
    /*   9 : CTESTB spec4,rm16,imm16 [wmi:      evex.scc2.dfv.l0.m4.o16 f7 /1 iw   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 02) 300 320 001(f7) 211 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3984, 349},
    /*  10 : CTESTB spec4,rm32,imm32 [wmi:      evex.scc2.dfv.l0.m4.o32 f7 /1 id   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 02) 300 321 001(f7) 211 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+4160, 350},
    /*  11 : CTESTB spec4,rm64,sdword64 [wmi:      evex.scc2.dfv.l0.m4.o64 f7 /1 id,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 02) 300 324 001(f7) 211 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+4336, 350},
};

static const struct itemplate instrux_CTESTBE[12] = {
    /*   0 : CTESTBE spec4,rm8,reg8 [wmr:      evex.scc6.dfv.l0.m4.o8 84 /r       ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 06) 300 001(84) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+25083, 348},
    /*   1 : CTESTBE spec4,rm16,reg16 [wmr:      evex.scc6.dfv.l0.m4.o16 85 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 06) 300 320 001(85) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+14283, 349},
    /*   2 : CTESTBE spec4,rm32,reg32 [wmr:      evex.scc6.dfv.l0.m4.o32 85 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 06) 300 321 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+14443, 350},
    /*   3 : CTESTBE spec4,rm64,reg64 [wmr:      evex.scc6.dfv.l0.m4.o64 85 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 06) 300 324 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14603, 350},
    /*   4 : CTESTBE spec4,rm8,imm8 [wmi:      evex.scc6.dfv.l0.m4.o8 f6 /0 ib    ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 06) 300 001(f6) 210 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14763, 348},
    /*   5 : CTESTBE spec4,rm16,imm16 [wmi:      evex.scc6.dfv.l0.m4.o16 f7 /0 iw   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 06) 300 320 001(f7) 210 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3467, 349},
    /*   6 : CTESTBE spec4,rm32,imm32 [wmi:      evex.scc6.dfv.l0.m4.o32 f7 /0 id   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 06) 300 321 001(f7) 210 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3643, 350},
    /*   7 : CTESTBE spec4,rm64,sdword64 [wmi:      evex.scc6.dfv.l0.m4.o64 f7 /0 id,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 06) 300 324 001(f7) 210 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3819, 350},
    /*   8 : CTESTBE spec4,rm8,imm8 [wmi:      evex.scc6.dfv.l0.m4.o8 f6 /1 ib    ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 06) 300 001(f6) 211 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14923, 348},
    /*   9 : CTESTBE spec4,rm16,imm16 [wmi:      evex.scc6.dfv.l0.m4.o16 f7 /1 iw   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 06) 300 320 001(f7) 211 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3995, 349},
    /*  10 : CTESTBE spec4,rm32,imm32 [wmi:      evex.scc6.dfv.l0.m4.o32 f7 /1 id   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 06) 300 321 001(f7) 211 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+4171, 350},
    /*  11 : CTESTBE spec4,rm64,sdword64 [wmi:      evex.scc6.dfv.l0.m4.o64 f7 /1 id,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 06) 300 324 001(f7) 211 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+4347, 350},
};

static const struct itemplate instrux_CTESTC[12] = {
    /*   0 : CTESTC spec4,rm8,reg8 [wmr:      evex.scc2.dfv.l0.m4.o8 84 /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 02) 300 001(84) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+25074, 348},
    /*   1 : CTESTC spec4,rm16,reg16 [wmr:      evex.scc2.dfv.l0.m4.o16 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 02) 300 320 001(85) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+14273, 349},
    /*   2 : CTESTC spec4,rm32,reg32 [wmr:      evex.scc2.dfv.l0.m4.o32 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 02) 300 321 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+14433, 350},
    /*   3 : CTESTC spec4,rm64,reg64 [wmr:      evex.scc2.dfv.l0.m4.o64 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 02) 300 324 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14593, 350},
    /*   4 : CTESTC spec4,rm8,imm8 [wmi:      evex.scc2.dfv.l0.m4.o8 f6 /0 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 02) 300 001(f6) 210 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14753, 348},
    /*   5 : CTESTC spec4,rm16,imm16 [wmi:      evex.scc2.dfv.l0.m4.o16 f7 /0 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 02) 300 320 001(f7) 210 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3456, 349},
    /*   6 : CTESTC spec4,rm32,imm32 [wmi:      evex.scc2.dfv.l0.m4.o32 f7 /0 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 02) 300 321 001(f7) 210 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3632, 350},
    /*   7 : CTESTC spec4,rm64,sdword64 [wmi:      evex.scc2.dfv.l0.m4.o64 f7 /0 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 02) 300 324 001(f7) 210 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3808, 350},
    /*   8 : CTESTC spec4,rm8,imm8 [wmi:      evex.scc2.dfv.l0.m4.o8 f6 /1 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 02) 300 001(f6) 211 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14913, 348},
    /*   9 : CTESTC spec4,rm16,imm16 [wmi:      evex.scc2.dfv.l0.m4.o16 f7 /1 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 02) 300 320 001(f7) 211 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3984, 349},
    /*  10 : CTESTC spec4,rm32,imm32 [wmi:      evex.scc2.dfv.l0.m4.o32 f7 /1 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 02) 300 321 001(f7) 211 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+4160, 350},
    /*  11 : CTESTC spec4,rm64,sdword64 [wmi:      evex.scc2.dfv.l0.m4.o64 f7 /1 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 02) 300 324 001(f7) 211 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+4336, 350},
};

static const struct itemplate instrux_CTESTE[12] = {
    /*   0 : CTESTE spec4,rm8,reg8 [wmr:      evex.scc4.dfv.l0.m4.o8 84 /r       ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 04) 300 001(84) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+25092, 348},
    /*   1 : CTESTE spec4,rm16,reg16 [wmr:      evex.scc4.dfv.l0.m4.o16 85 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 04) 300 320 001(85) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+14293, 349},
    /*   2 : CTESTE spec4,rm32,reg32 [wmr:      evex.scc4.dfv.l0.m4.o32 85 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 04) 300 321 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+14453, 350},
    /*   3 : CTESTE spec4,rm64,reg64 [wmr:      evex.scc4.dfv.l0.m4.o64 85 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 04) 300 324 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14613, 350},
    /*   4 : CTESTE spec4,rm8,imm8 [wmi:      evex.scc4.dfv.l0.m4.o8 f6 /0 ib    ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 04) 300 001(f6) 210 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14773, 348},
    /*   5 : CTESTE spec4,rm16,imm16 [wmi:      evex.scc4.dfv.l0.m4.o16 f7 /0 iw   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 04) 300 320 001(f7) 210 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3478, 349},
    /*   6 : CTESTE spec4,rm32,imm32 [wmi:      evex.scc4.dfv.l0.m4.o32 f7 /0 id   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 04) 300 321 001(f7) 210 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3654, 350},
    /*   7 : CTESTE spec4,rm64,sdword64 [wmi:      evex.scc4.dfv.l0.m4.o64 f7 /0 id,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 04) 300 324 001(f7) 210 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3830, 350},
    /*   8 : CTESTE spec4,rm8,imm8 [wmi:      evex.scc4.dfv.l0.m4.o8 f6 /1 ib    ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 04) 300 001(f6) 211 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14933, 348},
    /*   9 : CTESTE spec4,rm16,imm16 [wmi:      evex.scc4.dfv.l0.m4.o16 f7 /1 iw   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 04) 300 320 001(f7) 211 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+4006, 349},
    /*  10 : CTESTE spec4,rm32,imm32 [wmi:      evex.scc4.dfv.l0.m4.o32 f7 /1 id   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 04) 300 321 001(f7) 211 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+4182, 350},
    /*  11 : CTESTE spec4,rm64,sdword64 [wmi:      evex.scc4.dfv.l0.m4.o64 f7 /1 id,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 04) 300 324 001(f7) 211 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+4358, 350},
};

static const struct itemplate instrux_CTESTF[12] = {
    /*   0 : CTESTF spec4,rm8,reg8 [wmr:      evex.scc11.dfv.l0.m4.o8 84 /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0b) 300 001(84) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTF, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+25047, 348},
    /*   1 : CTESTF spec4,rm16,reg16 [wmr:      evex.scc11.dfv.l0.m4.o16 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0b) 300 320 001(85) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTF, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+14243, 349},
    /*   2 : CTESTF spec4,rm32,reg32 [wmr:      evex.scc11.dfv.l0.m4.o32 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0b) 300 321 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTF, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+14403, 350},
    /*   3 : CTESTF spec4,rm64,reg64 [wmr:      evex.scc11.dfv.l0.m4.o64 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0b) 300 324 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTF, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14563, 350},
    /*   4 : CTESTF spec4,rm8,imm8 [wmi:      evex.scc11.dfv.l0.m4.o8 f6 /0 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0b) 300 001(f6) 210 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTF, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14723, 348},
    /*   5 : CTESTF spec4,rm16,imm16 [wmi:      evex.scc11.dfv.l0.m4.o16 f7 /0 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0b) 300 320 001(f7) 210 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTF, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3423, 349},
    /*   6 : CTESTF spec4,rm32,imm32 [wmi:      evex.scc11.dfv.l0.m4.o32 f7 /0 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0b) 300 321 001(f7) 210 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTF, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3599, 350},
    /*   7 : CTESTF spec4,rm64,sdword64 [wmi:      evex.scc11.dfv.l0.m4.o64 f7 /0 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0b) 300 324 001(f7) 210 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTF, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3775, 350},
    /*   8 : CTESTF spec4,rm8,imm8 [wmi:      evex.scc11.dfv.l0.m4.o8 f6 /1 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0b) 300 001(f6) 211 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTF, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14883, 348},
    /*   9 : CTESTF spec4,rm16,imm16 [wmi:      evex.scc11.dfv.l0.m4.o16 f7 /1 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0b) 300 320 001(f7) 211 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTF, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3951, 349},
    /*  10 : CTESTF spec4,rm32,imm32 [wmi:      evex.scc11.dfv.l0.m4.o32 f7 /1 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0b) 300 321 001(f7) 211 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTF, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+4127, 350},
    /*  11 : CTESTF spec4,rm64,sdword64 [wmi:      evex.scc11.dfv.l0.m4.o64 f7 /1 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0b) 300 324 001(f7) 211 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTF, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+4303, 350},
};

static const struct itemplate instrux_CTESTG[12] = {
    /*   0 : CTESTG spec4,rm8,reg8 [wmr:      evex.scc15.dfv.l0.m4.o8 84 /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0f) 300 001(84) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+25101, 348},
    /*   1 : CTESTG spec4,rm16,reg16 [wmr:      evex.scc15.dfv.l0.m4.o16 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0f) 300 320 001(85) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+14303, 349},
    /*   2 : CTESTG spec4,rm32,reg32 [wmr:      evex.scc15.dfv.l0.m4.o32 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0f) 300 321 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+14463, 350},
    /*   3 : CTESTG spec4,rm64,reg64 [wmr:      evex.scc15.dfv.l0.m4.o64 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0f) 300 324 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14623, 350},
    /*   4 : CTESTG spec4,rm8,imm8 [wmi:      evex.scc15.dfv.l0.m4.o8 f6 /0 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0f) 300 001(f6) 210 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14783, 348},
    /*   5 : CTESTG spec4,rm16,imm16 [wmi:      evex.scc15.dfv.l0.m4.o16 f7 /0 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0f) 300 320 001(f7) 210 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3489, 349},
    /*   6 : CTESTG spec4,rm32,imm32 [wmi:      evex.scc15.dfv.l0.m4.o32 f7 /0 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0f) 300 321 001(f7) 210 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3665, 350},
    /*   7 : CTESTG spec4,rm64,sdword64 [wmi:      evex.scc15.dfv.l0.m4.o64 f7 /0 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0f) 300 324 001(f7) 210 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3841, 350},
    /*   8 : CTESTG spec4,rm8,imm8 [wmi:      evex.scc15.dfv.l0.m4.o8 f6 /1 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0f) 300 001(f6) 211 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14943, 348},
    /*   9 : CTESTG spec4,rm16,imm16 [wmi:      evex.scc15.dfv.l0.m4.o16 f7 /1 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0f) 300 320 001(f7) 211 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+4017, 349},
    /*  10 : CTESTG spec4,rm32,imm32 [wmi:      evex.scc15.dfv.l0.m4.o32 f7 /1 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0f) 300 321 001(f7) 211 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+4193, 350},
    /*  11 : CTESTG spec4,rm64,sdword64 [wmi:      evex.scc15.dfv.l0.m4.o64 f7 /1 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0f) 300 324 001(f7) 211 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+4369, 350},
};

static const struct itemplate instrux_CTESTGE[12] = {
    /*   0 : CTESTGE spec4,rm8,reg8 [wmr:      evex.scc13.dfv.l0.m4.o8 84 /r       ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0d) 300 001(84) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+25110, 348},
    /*   1 : CTESTGE spec4,rm16,reg16 [wmr:      evex.scc13.dfv.l0.m4.o16 85 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 0d) 300 320 001(85) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+14313, 349},
    /*   2 : CTESTGE spec4,rm32,reg32 [wmr:      evex.scc13.dfv.l0.m4.o32 85 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0d) 300 321 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+14473, 350},
    /*   3 : CTESTGE spec4,rm64,reg64 [wmr:      evex.scc13.dfv.l0.m4.o64 85 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 0d) 300 324 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14633, 350},
    /*   4 : CTESTGE spec4,rm8,imm8 [wmi:      evex.scc13.dfv.l0.m4.o8 f6 /0 ib    ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0d) 300 001(f6) 210 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14793, 348},
    /*   5 : CTESTGE spec4,rm16,imm16 [wmi:      evex.scc13.dfv.l0.m4.o16 f7 /0 iw   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 0d) 300 320 001(f7) 210 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3500, 349},
    /*   6 : CTESTGE spec4,rm32,imm32 [wmi:      evex.scc13.dfv.l0.m4.o32 f7 /0 id   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0d) 300 321 001(f7) 210 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3676, 350},
    /*   7 : CTESTGE spec4,rm64,sdword64 [wmi:      evex.scc13.dfv.l0.m4.o64 f7 /0 id,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 0d) 300 324 001(f7) 210 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3852, 350},
    /*   8 : CTESTGE spec4,rm8,imm8 [wmi:      evex.scc13.dfv.l0.m4.o8 f6 /1 ib    ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0d) 300 001(f6) 211 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14953, 348},
    /*   9 : CTESTGE spec4,rm16,imm16 [wmi:      evex.scc13.dfv.l0.m4.o16 f7 /1 iw   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 0d) 300 320 001(f7) 211 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+4028, 349},
    /*  10 : CTESTGE spec4,rm32,imm32 [wmi:      evex.scc13.dfv.l0.m4.o32 f7 /1 id   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0d) 300 321 001(f7) 211 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+4204, 350},
    /*  11 : CTESTGE spec4,rm64,sdword64 [wmi:      evex.scc13.dfv.l0.m4.o64 f7 /1 id,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 0d) 300 324 001(f7) 211 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+4380, 350},
};

static const struct itemplate instrux_CTESTL[12] = {
    /*   0 : CTESTL spec4,rm8,reg8 [wmr:      evex.scc12.dfv.l0.m4.o8 84 /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0c) 300 001(84) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+25119, 348},
    /*   1 : CTESTL spec4,rm16,reg16 [wmr:      evex.scc12.dfv.l0.m4.o16 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0c) 300 320 001(85) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+14323, 349},
    /*   2 : CTESTL spec4,rm32,reg32 [wmr:      evex.scc12.dfv.l0.m4.o32 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0c) 300 321 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+14483, 350},
    /*   3 : CTESTL spec4,rm64,reg64 [wmr:      evex.scc12.dfv.l0.m4.o64 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0c) 300 324 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14643, 350},
    /*   4 : CTESTL spec4,rm8,imm8 [wmi:      evex.scc12.dfv.l0.m4.o8 f6 /0 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0c) 300 001(f6) 210 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14803, 348},
    /*   5 : CTESTL spec4,rm16,imm16 [wmi:      evex.scc12.dfv.l0.m4.o16 f7 /0 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0c) 300 320 001(f7) 210 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3511, 349},
    /*   6 : CTESTL spec4,rm32,imm32 [wmi:      evex.scc12.dfv.l0.m4.o32 f7 /0 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0c) 300 321 001(f7) 210 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3687, 350},
    /*   7 : CTESTL spec4,rm64,sdword64 [wmi:      evex.scc12.dfv.l0.m4.o64 f7 /0 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0c) 300 324 001(f7) 210 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3863, 350},
    /*   8 : CTESTL spec4,rm8,imm8 [wmi:      evex.scc12.dfv.l0.m4.o8 f6 /1 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0c) 300 001(f6) 211 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14963, 348},
    /*   9 : CTESTL spec4,rm16,imm16 [wmi:      evex.scc12.dfv.l0.m4.o16 f7 /1 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0c) 300 320 001(f7) 211 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+4039, 349},
    /*  10 : CTESTL spec4,rm32,imm32 [wmi:      evex.scc12.dfv.l0.m4.o32 f7 /1 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0c) 300 321 001(f7) 211 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+4215, 350},
    /*  11 : CTESTL spec4,rm64,sdword64 [wmi:      evex.scc12.dfv.l0.m4.o64 f7 /1 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0c) 300 324 001(f7) 211 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+4391, 350},
};

static const struct itemplate instrux_CTESTLE[12] = {
    /*   0 : CTESTLE spec4,rm8,reg8 [wmr:      evex.scc14.dfv.l0.m4.o8 84 /r       ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0e) 300 001(84) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+25128, 348},
    /*   1 : CTESTLE spec4,rm16,reg16 [wmr:      evex.scc14.dfv.l0.m4.o16 85 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 0e) 300 320 001(85) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+14333, 349},
    /*   2 : CTESTLE spec4,rm32,reg32 [wmr:      evex.scc14.dfv.l0.m4.o32 85 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0e) 300 321 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+14493, 350},
    /*   3 : CTESTLE spec4,rm64,reg64 [wmr:      evex.scc14.dfv.l0.m4.o64 85 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 0e) 300 324 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14653, 350},
    /*   4 : CTESTLE spec4,rm8,imm8 [wmi:      evex.scc14.dfv.l0.m4.o8 f6 /0 ib    ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0e) 300 001(f6) 210 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14813, 348},
    /*   5 : CTESTLE spec4,rm16,imm16 [wmi:      evex.scc14.dfv.l0.m4.o16 f7 /0 iw   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 0e) 300 320 001(f7) 210 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3522, 349},
    /*   6 : CTESTLE spec4,rm32,imm32 [wmi:      evex.scc14.dfv.l0.m4.o32 f7 /0 id   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0e) 300 321 001(f7) 210 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3698, 350},
    /*   7 : CTESTLE spec4,rm64,sdword64 [wmi:      evex.scc14.dfv.l0.m4.o64 f7 /0 id,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 0e) 300 324 001(f7) 210 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3874, 350},
    /*   8 : CTESTLE spec4,rm8,imm8 [wmi:      evex.scc14.dfv.l0.m4.o8 f6 /1 ib    ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0e) 300 001(f6) 211 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14973, 348},
    /*   9 : CTESTLE spec4,rm16,imm16 [wmi:      evex.scc14.dfv.l0.m4.o16 f7 /1 iw   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 0e) 300 320 001(f7) 211 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+4050, 349},
    /*  10 : CTESTLE spec4,rm32,imm32 [wmi:      evex.scc14.dfv.l0.m4.o32 f7 /1 id   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0e) 300 321 001(f7) 211 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+4226, 350},
    /*  11 : CTESTLE spec4,rm64,sdword64 [wmi:      evex.scc14.dfv.l0.m4.o64 f7 /1 id,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 0e) 300 324 001(f7) 211 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+4402, 350},
};

static const struct itemplate instrux_CTESTNA[12] = {
    /*   0 : CTESTNA spec4,rm8,reg8 [wmr:      evex.scc6.dfv.l0.m4.o8 84 /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 06) 300 001(84) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+25083, 348},
    /*   1 : CTESTNA spec4,rm16,reg16 [wmr:      evex.scc6.dfv.l0.m4.o16 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 06) 300 320 001(85) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+14283, 349},
    /*   2 : CTESTNA spec4,rm32,reg32 [wmr:      evex.scc6.dfv.l0.m4.o32 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 06) 300 321 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+14443, 350},
    /*   3 : CTESTNA spec4,rm64,reg64 [wmr:      evex.scc6.dfv.l0.m4.o64 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 06) 300 324 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14603, 350},
    /*   4 : CTESTNA spec4,rm8,imm8 [wmi:      evex.scc6.dfv.l0.m4.o8 f6 /0 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 06) 300 001(f6) 210 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14763, 348},
    /*   5 : CTESTNA spec4,rm16,imm16 [wmi:      evex.scc6.dfv.l0.m4.o16 f7 /0 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 06) 300 320 001(f7) 210 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3467, 349},
    /*   6 : CTESTNA spec4,rm32,imm32 [wmi:      evex.scc6.dfv.l0.m4.o32 f7 /0 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 06) 300 321 001(f7) 210 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3643, 350},
    /*   7 : CTESTNA spec4,rm64,sdword64 [wmi:      evex.scc6.dfv.l0.m4.o64 f7 /0 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 06) 300 324 001(f7) 210 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3819, 350},
    /*   8 : CTESTNA spec4,rm8,imm8 [wmi:      evex.scc6.dfv.l0.m4.o8 f6 /1 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 06) 300 001(f6) 211 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14923, 348},
    /*   9 : CTESTNA spec4,rm16,imm16 [wmi:      evex.scc6.dfv.l0.m4.o16 f7 /1 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 06) 300 320 001(f7) 211 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3995, 349},
    /*  10 : CTESTNA spec4,rm32,imm32 [wmi:      evex.scc6.dfv.l0.m4.o32 f7 /1 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 06) 300 321 001(f7) 211 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+4171, 350},
    /*  11 : CTESTNA spec4,rm64,sdword64 [wmi:      evex.scc6.dfv.l0.m4.o64 f7 /1 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 06) 300 324 001(f7) 211 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNA, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+4347, 350},
};

static const struct itemplate instrux_CTESTNAE[12] = {
    /*   0 : CTESTNAE spec4,rm8,reg8 [wmr:      evex.scc2.dfv.l0.m4.o8 84 /r       ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 02) 300 001(84) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+25074, 348},
    /*   1 : CTESTNAE spec4,rm16,reg16 [wmr:      evex.scc2.dfv.l0.m4.o16 85 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 02) 300 320 001(85) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+14273, 349},
    /*   2 : CTESTNAE spec4,rm32,reg32 [wmr:      evex.scc2.dfv.l0.m4.o32 85 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 02) 300 321 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+14433, 350},
    /*   3 : CTESTNAE spec4,rm64,reg64 [wmr:      evex.scc2.dfv.l0.m4.o64 85 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 02) 300 324 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14593, 350},
    /*   4 : CTESTNAE spec4,rm8,imm8 [wmi:      evex.scc2.dfv.l0.m4.o8 f6 /0 ib    ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 02) 300 001(f6) 210 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14753, 348},
    /*   5 : CTESTNAE spec4,rm16,imm16 [wmi:      evex.scc2.dfv.l0.m4.o16 f7 /0 iw   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 02) 300 320 001(f7) 210 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3456, 349},
    /*   6 : CTESTNAE spec4,rm32,imm32 [wmi:      evex.scc2.dfv.l0.m4.o32 f7 /0 id   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 02) 300 321 001(f7) 210 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3632, 350},
    /*   7 : CTESTNAE spec4,rm64,sdword64 [wmi:      evex.scc2.dfv.l0.m4.o64 f7 /0 id,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 02) 300 324 001(f7) 210 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3808, 350},
    /*   8 : CTESTNAE spec4,rm8,imm8 [wmi:      evex.scc2.dfv.l0.m4.o8 f6 /1 ib    ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 02) 300 001(f6) 211 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14913, 348},
    /*   9 : CTESTNAE spec4,rm16,imm16 [wmi:      evex.scc2.dfv.l0.m4.o16 f7 /1 iw   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 02) 300 320 001(f7) 211 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3984, 349},
    /*  10 : CTESTNAE spec4,rm32,imm32 [wmi:      evex.scc2.dfv.l0.m4.o32 f7 /1 id   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 02) 300 321 001(f7) 211 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+4160, 350},
    /*  11 : CTESTNAE spec4,rm64,sdword64 [wmi:      evex.scc2.dfv.l0.m4.o64 f7 /1 id,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 02) 300 324 001(f7) 211 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNAE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+4336, 350},
};

static const struct itemplate instrux_CTESTNB[12] = {
    /*   0 : CTESTNB spec4,rm8,reg8 [wmr:      evex.scc3.dfv.l0.m4.o8 84 /r       ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 03) 300 001(84) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+25065, 348},
    /*   1 : CTESTNB spec4,rm16,reg16 [wmr:      evex.scc3.dfv.l0.m4.o16 85 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 03) 300 320 001(85) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+14263, 349},
    /*   2 : CTESTNB spec4,rm32,reg32 [wmr:      evex.scc3.dfv.l0.m4.o32 85 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 03) 300 321 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+14423, 350},
    /*   3 : CTESTNB spec4,rm64,reg64 [wmr:      evex.scc3.dfv.l0.m4.o64 85 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 03) 300 324 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14583, 350},
    /*   4 : CTESTNB spec4,rm8,imm8 [wmi:      evex.scc3.dfv.l0.m4.o8 f6 /0 ib    ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 03) 300 001(f6) 210 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14743, 348},
    /*   5 : CTESTNB spec4,rm16,imm16 [wmi:      evex.scc3.dfv.l0.m4.o16 f7 /0 iw   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 03) 300 320 001(f7) 210 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3445, 349},
    /*   6 : CTESTNB spec4,rm32,imm32 [wmi:      evex.scc3.dfv.l0.m4.o32 f7 /0 id   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 03) 300 321 001(f7) 210 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3621, 350},
    /*   7 : CTESTNB spec4,rm64,sdword64 [wmi:      evex.scc3.dfv.l0.m4.o64 f7 /0 id,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 03) 300 324 001(f7) 210 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3797, 350},
    /*   8 : CTESTNB spec4,rm8,imm8 [wmi:      evex.scc3.dfv.l0.m4.o8 f6 /1 ib    ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 03) 300 001(f6) 211 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14903, 348},
    /*   9 : CTESTNB spec4,rm16,imm16 [wmi:      evex.scc3.dfv.l0.m4.o16 f7 /1 iw   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 03) 300 320 001(f7) 211 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3973, 349},
    /*  10 : CTESTNB spec4,rm32,imm32 [wmi:      evex.scc3.dfv.l0.m4.o32 f7 /1 id   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 03) 300 321 001(f7) 211 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+4149, 350},
    /*  11 : CTESTNB spec4,rm64,sdword64 [wmi:      evex.scc3.dfv.l0.m4.o64 f7 /1 id,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 03) 300 324 001(f7) 211 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNB, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+4325, 350},
};

static const struct itemplate instrux_CTESTNBE[12] = {
    /*   0 : CTESTNBE spec4,rm8,reg8 [wmr:      evex.scc7.dfv.l0.m4.o8 84 /r       ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 07) 300 001(84) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+25056, 348},
    /*   1 : CTESTNBE spec4,rm16,reg16 [wmr:      evex.scc7.dfv.l0.m4.o16 85 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 07) 300 320 001(85) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+14253, 349},
    /*   2 : CTESTNBE spec4,rm32,reg32 [wmr:      evex.scc7.dfv.l0.m4.o32 85 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 07) 300 321 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+14413, 350},
    /*   3 : CTESTNBE spec4,rm64,reg64 [wmr:      evex.scc7.dfv.l0.m4.o64 85 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 07) 300 324 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14573, 350},
    /*   4 : CTESTNBE spec4,rm8,imm8 [wmi:      evex.scc7.dfv.l0.m4.o8 f6 /0 ib    ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 07) 300 001(f6) 210 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14733, 348},
    /*   5 : CTESTNBE spec4,rm16,imm16 [wmi:      evex.scc7.dfv.l0.m4.o16 f7 /0 iw   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 07) 300 320 001(f7) 210 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3434, 349},
    /*   6 : CTESTNBE spec4,rm32,imm32 [wmi:      evex.scc7.dfv.l0.m4.o32 f7 /0 id   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 07) 300 321 001(f7) 210 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3610, 350},
    /*   7 : CTESTNBE spec4,rm64,sdword64 [wmi:      evex.scc7.dfv.l0.m4.o64 f7 /0 id,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 07) 300 324 001(f7) 210 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3786, 350},
    /*   8 : CTESTNBE spec4,rm8,imm8 [wmi:      evex.scc7.dfv.l0.m4.o8 f6 /1 ib    ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 07) 300 001(f6) 211 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14893, 348},
    /*   9 : CTESTNBE spec4,rm16,imm16 [wmi:      evex.scc7.dfv.l0.m4.o16 f7 /1 iw   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 07) 300 320 001(f7) 211 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3962, 349},
    /*  10 : CTESTNBE spec4,rm32,imm32 [wmi:      evex.scc7.dfv.l0.m4.o32 f7 /1 id   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 07) 300 321 001(f7) 211 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+4138, 350},
    /*  11 : CTESTNBE spec4,rm64,sdword64 [wmi:      evex.scc7.dfv.l0.m4.o64 f7 /1 id,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 07) 300 324 001(f7) 211 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNBE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+4314, 350},
};

static const struct itemplate instrux_CTESTNC[12] = {
    /*   0 : CTESTNC spec4,rm8,reg8 [wmr:      evex.scc3.dfv.l0.m4.o8 84 /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 03) 300 001(84) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+25065, 348},
    /*   1 : CTESTNC spec4,rm16,reg16 [wmr:      evex.scc3.dfv.l0.m4.o16 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 03) 300 320 001(85) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+14263, 349},
    /*   2 : CTESTNC spec4,rm32,reg32 [wmr:      evex.scc3.dfv.l0.m4.o32 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 03) 300 321 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+14423, 350},
    /*   3 : CTESTNC spec4,rm64,reg64 [wmr:      evex.scc3.dfv.l0.m4.o64 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 03) 300 324 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14583, 350},
    /*   4 : CTESTNC spec4,rm8,imm8 [wmi:      evex.scc3.dfv.l0.m4.o8 f6 /0 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 03) 300 001(f6) 210 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14743, 348},
    /*   5 : CTESTNC spec4,rm16,imm16 [wmi:      evex.scc3.dfv.l0.m4.o16 f7 /0 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 03) 300 320 001(f7) 210 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3445, 349},
    /*   6 : CTESTNC spec4,rm32,imm32 [wmi:      evex.scc3.dfv.l0.m4.o32 f7 /0 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 03) 300 321 001(f7) 210 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3621, 350},
    /*   7 : CTESTNC spec4,rm64,sdword64 [wmi:      evex.scc3.dfv.l0.m4.o64 f7 /0 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 03) 300 324 001(f7) 210 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3797, 350},
    /*   8 : CTESTNC spec4,rm8,imm8 [wmi:      evex.scc3.dfv.l0.m4.o8 f6 /1 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 03) 300 001(f6) 211 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14903, 348},
    /*   9 : CTESTNC spec4,rm16,imm16 [wmi:      evex.scc3.dfv.l0.m4.o16 f7 /1 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 03) 300 320 001(f7) 211 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3973, 349},
    /*  10 : CTESTNC spec4,rm32,imm32 [wmi:      evex.scc3.dfv.l0.m4.o32 f7 /1 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 03) 300 321 001(f7) 211 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+4149, 350},
    /*  11 : CTESTNC spec4,rm64,sdword64 [wmi:      evex.scc3.dfv.l0.m4.o64 f7 /1 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 03) 300 324 001(f7) 211 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNC, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+4325, 350},
};

static const struct itemplate instrux_CTESTNE[12] = {
    /*   0 : CTESTNE spec4,rm8,reg8 [wmr:      evex.scc5.dfv.l0.m4.o8 84 /r       ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 05) 300 001(84) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+25137, 348},
    /*   1 : CTESTNE spec4,rm16,reg16 [wmr:      evex.scc5.dfv.l0.m4.o16 85 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 05) 300 320 001(85) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+14343, 349},
    /*   2 : CTESTNE spec4,rm32,reg32 [wmr:      evex.scc5.dfv.l0.m4.o32 85 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 05) 300 321 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+14503, 350},
    /*   3 : CTESTNE spec4,rm64,reg64 [wmr:      evex.scc5.dfv.l0.m4.o64 85 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 05) 300 324 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14663, 350},
    /*   4 : CTESTNE spec4,rm8,imm8 [wmi:      evex.scc5.dfv.l0.m4.o8 f6 /0 ib    ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 05) 300 001(f6) 210 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14823, 348},
    /*   5 : CTESTNE spec4,rm16,imm16 [wmi:      evex.scc5.dfv.l0.m4.o16 f7 /0 iw   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 05) 300 320 001(f7) 210 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3533, 349},
    /*   6 : CTESTNE spec4,rm32,imm32 [wmi:      evex.scc5.dfv.l0.m4.o32 f7 /0 id   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 05) 300 321 001(f7) 210 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3709, 350},
    /*   7 : CTESTNE spec4,rm64,sdword64 [wmi:      evex.scc5.dfv.l0.m4.o64 f7 /0 id,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 05) 300 324 001(f7) 210 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3885, 350},
    /*   8 : CTESTNE spec4,rm8,imm8 [wmi:      evex.scc5.dfv.l0.m4.o8 f6 /1 ib    ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 05) 300 001(f6) 211 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14983, 348},
    /*   9 : CTESTNE spec4,rm16,imm16 [wmi:      evex.scc5.dfv.l0.m4.o16 f7 /1 iw   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 05) 300 320 001(f7) 211 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+4061, 349},
    /*  10 : CTESTNE spec4,rm32,imm32 [wmi:      evex.scc5.dfv.l0.m4.o32 f7 /1 id   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 05) 300 321 001(f7) 211 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+4237, 350},
    /*  11 : CTESTNE spec4,rm64,sdword64 [wmi:      evex.scc5.dfv.l0.m4.o64 f7 /1 id,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 05) 300 324 001(f7) 211 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+4413, 350},
};

static const struct itemplate instrux_CTESTNG[12] = {
    /*   0 : CTESTNG spec4,rm8,reg8 [wmr:      evex.scc14.dfv.l0.m4.o8 84 /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0e) 300 001(84) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+25128, 348},
    /*   1 : CTESTNG spec4,rm16,reg16 [wmr:      evex.scc14.dfv.l0.m4.o16 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0e) 300 320 001(85) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+14333, 349},
    /*   2 : CTESTNG spec4,rm32,reg32 [wmr:      evex.scc14.dfv.l0.m4.o32 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0e) 300 321 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+14493, 350},
    /*   3 : CTESTNG spec4,rm64,reg64 [wmr:      evex.scc14.dfv.l0.m4.o64 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0e) 300 324 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14653, 350},
    /*   4 : CTESTNG spec4,rm8,imm8 [wmi:      evex.scc14.dfv.l0.m4.o8 f6 /0 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0e) 300 001(f6) 210 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14813, 348},
    /*   5 : CTESTNG spec4,rm16,imm16 [wmi:      evex.scc14.dfv.l0.m4.o16 f7 /0 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0e) 300 320 001(f7) 210 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3522, 349},
    /*   6 : CTESTNG spec4,rm32,imm32 [wmi:      evex.scc14.dfv.l0.m4.o32 f7 /0 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0e) 300 321 001(f7) 210 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3698, 350},
    /*   7 : CTESTNG spec4,rm64,sdword64 [wmi:      evex.scc14.dfv.l0.m4.o64 f7 /0 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0e) 300 324 001(f7) 210 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3874, 350},
    /*   8 : CTESTNG spec4,rm8,imm8 [wmi:      evex.scc14.dfv.l0.m4.o8 f6 /1 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0e) 300 001(f6) 211 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14973, 348},
    /*   9 : CTESTNG spec4,rm16,imm16 [wmi:      evex.scc14.dfv.l0.m4.o16 f7 /1 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0e) 300 320 001(f7) 211 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+4050, 349},
    /*  10 : CTESTNG spec4,rm32,imm32 [wmi:      evex.scc14.dfv.l0.m4.o32 f7 /1 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0e) 300 321 001(f7) 211 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+4226, 350},
    /*  11 : CTESTNG spec4,rm64,sdword64 [wmi:      evex.scc14.dfv.l0.m4.o64 f7 /1 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0e) 300 324 001(f7) 211 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNG, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+4402, 350},
};

static const struct itemplate instrux_CTESTNGE[12] = {
    /*   0 : CTESTNGE spec4,rm8,reg8 [wmr:      evex.scc12.dfv.l0.m4.o8 84 /r       ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0c) 300 001(84) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+25119, 348},
    /*   1 : CTESTNGE spec4,rm16,reg16 [wmr:      evex.scc12.dfv.l0.m4.o16 85 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 0c) 300 320 001(85) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+14323, 349},
    /*   2 : CTESTNGE spec4,rm32,reg32 [wmr:      evex.scc12.dfv.l0.m4.o32 85 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0c) 300 321 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+14483, 350},
    /*   3 : CTESTNGE spec4,rm64,reg64 [wmr:      evex.scc12.dfv.l0.m4.o64 85 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 0c) 300 324 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14643, 350},
    /*   4 : CTESTNGE spec4,rm8,imm8 [wmi:      evex.scc12.dfv.l0.m4.o8 f6 /0 ib    ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0c) 300 001(f6) 210 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14803, 348},
    /*   5 : CTESTNGE spec4,rm16,imm16 [wmi:      evex.scc12.dfv.l0.m4.o16 f7 /0 iw   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 0c) 300 320 001(f7) 210 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3511, 349},
    /*   6 : CTESTNGE spec4,rm32,imm32 [wmi:      evex.scc12.dfv.l0.m4.o32 f7 /0 id   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0c) 300 321 001(f7) 210 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3687, 350},
    /*   7 : CTESTNGE spec4,rm64,sdword64 [wmi:      evex.scc12.dfv.l0.m4.o64 f7 /0 id,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 0c) 300 324 001(f7) 210 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3863, 350},
    /*   8 : CTESTNGE spec4,rm8,imm8 [wmi:      evex.scc12.dfv.l0.m4.o8 f6 /1 ib    ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0c) 300 001(f6) 211 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14963, 348},
    /*   9 : CTESTNGE spec4,rm16,imm16 [wmi:      evex.scc12.dfv.l0.m4.o16 f7 /1 iw   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 0c) 300 320 001(f7) 211 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+4039, 349},
    /*  10 : CTESTNGE spec4,rm32,imm32 [wmi:      evex.scc12.dfv.l0.m4.o32 f7 /1 id   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0c) 300 321 001(f7) 211 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+4215, 350},
    /*  11 : CTESTNGE spec4,rm64,sdword64 [wmi:      evex.scc12.dfv.l0.m4.o64 f7 /1 id,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 0c) 300 324 001(f7) 211 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNGE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+4391, 350},
};

static const struct itemplate instrux_CTESTNL[12] = {
    /*   0 : CTESTNL spec4,rm8,reg8 [wmr:      evex.scc13.dfv.l0.m4.o8 84 /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0d) 300 001(84) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+25110, 348},
    /*   1 : CTESTNL spec4,rm16,reg16 [wmr:      evex.scc13.dfv.l0.m4.o16 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0d) 300 320 001(85) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+14313, 349},
    /*   2 : CTESTNL spec4,rm32,reg32 [wmr:      evex.scc13.dfv.l0.m4.o32 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0d) 300 321 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+14473, 350},
    /*   3 : CTESTNL spec4,rm64,reg64 [wmr:      evex.scc13.dfv.l0.m4.o64 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0d) 300 324 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14633, 350},
    /*   4 : CTESTNL spec4,rm8,imm8 [wmi:      evex.scc13.dfv.l0.m4.o8 f6 /0 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0d) 300 001(f6) 210 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14793, 348},
    /*   5 : CTESTNL spec4,rm16,imm16 [wmi:      evex.scc13.dfv.l0.m4.o16 f7 /0 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0d) 300 320 001(f7) 210 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3500, 349},
    /*   6 : CTESTNL spec4,rm32,imm32 [wmi:      evex.scc13.dfv.l0.m4.o32 f7 /0 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0d) 300 321 001(f7) 210 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3676, 350},
    /*   7 : CTESTNL spec4,rm64,sdword64 [wmi:      evex.scc13.dfv.l0.m4.o64 f7 /0 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0d) 300 324 001(f7) 210 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3852, 350},
    /*   8 : CTESTNL spec4,rm8,imm8 [wmi:      evex.scc13.dfv.l0.m4.o8 f6 /1 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0d) 300 001(f6) 211 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14953, 348},
    /*   9 : CTESTNL spec4,rm16,imm16 [wmi:      evex.scc13.dfv.l0.m4.o16 f7 /1 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0d) 300 320 001(f7) 211 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+4028, 349},
    /*  10 : CTESTNL spec4,rm32,imm32 [wmi:      evex.scc13.dfv.l0.m4.o32 f7 /1 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0d) 300 321 001(f7) 211 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+4204, 350},
    /*  11 : CTESTNL spec4,rm64,sdword64 [wmi:      evex.scc13.dfv.l0.m4.o64 f7 /1 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0d) 300 324 001(f7) 211 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNL, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+4380, 350},
};

static const struct itemplate instrux_CTESTNLE[12] = {
    /*   0 : CTESTNLE spec4,rm8,reg8 [wmr:      evex.scc15.dfv.l0.m4.o8 84 /r       ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0f) 300 001(84) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+25101, 348},
    /*   1 : CTESTNLE spec4,rm16,reg16 [wmr:      evex.scc15.dfv.l0.m4.o16 85 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 0f) 300 320 001(85) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+14303, 349},
    /*   2 : CTESTNLE spec4,rm32,reg32 [wmr:      evex.scc15.dfv.l0.m4.o32 85 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0f) 300 321 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+14463, 350},
    /*   3 : CTESTNLE spec4,rm64,reg64 [wmr:      evex.scc15.dfv.l0.m4.o64 85 /r      ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 0f) 300 324 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14623, 350},
    /*   4 : CTESTNLE spec4,rm8,imm8 [wmi:      evex.scc15.dfv.l0.m4.o8 f6 /0 ib    ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0f) 300 001(f6) 210 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14783, 348},
    /*   5 : CTESTNLE spec4,rm16,imm16 [wmi:      evex.scc15.dfv.l0.m4.o16 f7 /0 iw   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 0f) 300 320 001(f7) 210 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3489, 349},
    /*   6 : CTESTNLE spec4,rm32,imm32 [wmi:      evex.scc15.dfv.l0.m4.o32 f7 /0 id   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0f) 300 321 001(f7) 210 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3665, 350},
    /*   7 : CTESTNLE spec4,rm64,sdword64 [wmi:      evex.scc15.dfv.l0.m4.o64 f7 /0 id,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 0f) 300 324 001(f7) 210 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3841, 350},
    /*   8 : CTESTNLE spec4,rm8,imm8 [wmi:      evex.scc15.dfv.l0.m4.o8 f6 /1 ib    ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0f) 300 001(f6) 211 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14943, 348},
    /*   9 : CTESTNLE spec4,rm16,imm16 [wmi:      evex.scc15.dfv.l0.m4.o16 f7 /1 iw   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 05 0f) 300 320 001(f7) 211 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+4017, 349},
    /*  10 : CTESTNLE spec4,rm32,imm32 [wmi:      evex.scc15.dfv.l0.m4.o32 f7 /1 id   ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 04 0f) 300 321 001(f7) 211 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+4193, 350},
    /*  11 : CTESTNLE spec4,rm64,sdword64 [wmi:      evex.scc15.dfv.l0.m4.o64 f7 /1 id,s ] SM1-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 84 0f) 300 324 001(f7) 211 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNLE, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+4369, 350},
};

static const struct itemplate instrux_CTESTNO[12] = {
    /*   0 : CTESTNO spec4,rm8,reg8 [wmr:      evex.scc1.dfv.l0.m4.o8 84 /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 01) 300 001(84) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+25146, 348},
    /*   1 : CTESTNO spec4,rm16,reg16 [wmr:      evex.scc1.dfv.l0.m4.o16 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 01) 300 320 001(85) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+14353, 349},
    /*   2 : CTESTNO spec4,rm32,reg32 [wmr:      evex.scc1.dfv.l0.m4.o32 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 01) 300 321 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+14513, 350},
    /*   3 : CTESTNO spec4,rm64,reg64 [wmr:      evex.scc1.dfv.l0.m4.o64 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 01) 300 324 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14673, 350},
    /*   4 : CTESTNO spec4,rm8,imm8 [wmi:      evex.scc1.dfv.l0.m4.o8 f6 /0 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 01) 300 001(f6) 210 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14833, 348},
    /*   5 : CTESTNO spec4,rm16,imm16 [wmi:      evex.scc1.dfv.l0.m4.o16 f7 /0 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 01) 300 320 001(f7) 210 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3544, 349},
    /*   6 : CTESTNO spec4,rm32,imm32 [wmi:      evex.scc1.dfv.l0.m4.o32 f7 /0 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 01) 300 321 001(f7) 210 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3720, 350},
    /*   7 : CTESTNO spec4,rm64,sdword64 [wmi:      evex.scc1.dfv.l0.m4.o64 f7 /0 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 01) 300 324 001(f7) 210 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3896, 350},
    /*   8 : CTESTNO spec4,rm8,imm8 [wmi:      evex.scc1.dfv.l0.m4.o8 f6 /1 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 01) 300 001(f6) 211 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14993, 348},
    /*   9 : CTESTNO spec4,rm16,imm16 [wmi:      evex.scc1.dfv.l0.m4.o16 f7 /1 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 01) 300 320 001(f7) 211 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+4072, 349},
    /*  10 : CTESTNO spec4,rm32,imm32 [wmi:      evex.scc1.dfv.l0.m4.o32 f7 /1 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 01) 300 321 001(f7) 211 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+4248, 350},
    /*  11 : CTESTNO spec4,rm64,sdword64 [wmi:      evex.scc1.dfv.l0.m4.o64 f7 /1 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 01) 300 324 001(f7) 211 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+4424, 350},
};

static const struct itemplate instrux_CTESTNS[12] = {
    /*   0 : CTESTNS spec4,rm8,reg8 [wmr:      evex.scc9.dfv.l0.m4.o8 84 /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 09) 300 001(84) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+25155, 348},
    /*   1 : CTESTNS spec4,rm16,reg16 [wmr:      evex.scc9.dfv.l0.m4.o16 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 09) 300 320 001(85) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+14363, 349},
    /*   2 : CTESTNS spec4,rm32,reg32 [wmr:      evex.scc9.dfv.l0.m4.o32 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 09) 300 321 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+14523, 350},
    /*   3 : CTESTNS spec4,rm64,reg64 [wmr:      evex.scc9.dfv.l0.m4.o64 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 09) 300 324 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14683, 350},
    /*   4 : CTESTNS spec4,rm8,imm8 [wmi:      evex.scc9.dfv.l0.m4.o8 f6 /0 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 09) 300 001(f6) 210 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14843, 348},
    /*   5 : CTESTNS spec4,rm16,imm16 [wmi:      evex.scc9.dfv.l0.m4.o16 f7 /0 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 09) 300 320 001(f7) 210 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3555, 349},
    /*   6 : CTESTNS spec4,rm32,imm32 [wmi:      evex.scc9.dfv.l0.m4.o32 f7 /0 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 09) 300 321 001(f7) 210 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3731, 350},
    /*   7 : CTESTNS spec4,rm64,sdword64 [wmi:      evex.scc9.dfv.l0.m4.o64 f7 /0 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 09) 300 324 001(f7) 210 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3907, 350},
    /*   8 : CTESTNS spec4,rm8,imm8 [wmi:      evex.scc9.dfv.l0.m4.o8 f6 /1 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 09) 300 001(f6) 211 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15003, 348},
    /*   9 : CTESTNS spec4,rm16,imm16 [wmi:      evex.scc9.dfv.l0.m4.o16 f7 /1 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 09) 300 320 001(f7) 211 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+4083, 349},
    /*  10 : CTESTNS spec4,rm32,imm32 [wmi:      evex.scc9.dfv.l0.m4.o32 f7 /1 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 09) 300 321 001(f7) 211 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+4259, 350},
    /*  11 : CTESTNS spec4,rm64,sdword64 [wmi:      evex.scc9.dfv.l0.m4.o64 f7 /1 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 09) 300 324 001(f7) 211 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+4435, 350},
};

static const struct itemplate instrux_CTESTNZ[12] = {
    /*   0 : CTESTNZ spec4,rm8,reg8 [wmr:      evex.scc5.dfv.l0.m4.o8 84 /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 05) 300 001(84) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+25137, 348},
    /*   1 : CTESTNZ spec4,rm16,reg16 [wmr:      evex.scc5.dfv.l0.m4.o16 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 05) 300 320 001(85) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+14343, 349},
    /*   2 : CTESTNZ spec4,rm32,reg32 [wmr:      evex.scc5.dfv.l0.m4.o32 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 05) 300 321 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+14503, 350},
    /*   3 : CTESTNZ spec4,rm64,reg64 [wmr:      evex.scc5.dfv.l0.m4.o64 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 05) 300 324 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14663, 350},
    /*   4 : CTESTNZ spec4,rm8,imm8 [wmi:      evex.scc5.dfv.l0.m4.o8 f6 /0 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 05) 300 001(f6) 210 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14823, 348},
    /*   5 : CTESTNZ spec4,rm16,imm16 [wmi:      evex.scc5.dfv.l0.m4.o16 f7 /0 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 05) 300 320 001(f7) 210 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3533, 349},
    /*   6 : CTESTNZ spec4,rm32,imm32 [wmi:      evex.scc5.dfv.l0.m4.o32 f7 /0 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 05) 300 321 001(f7) 210 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3709, 350},
    /*   7 : CTESTNZ spec4,rm64,sdword64 [wmi:      evex.scc5.dfv.l0.m4.o64 f7 /0 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 05) 300 324 001(f7) 210 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3885, 350},
    /*   8 : CTESTNZ spec4,rm8,imm8 [wmi:      evex.scc5.dfv.l0.m4.o8 f6 /1 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 05) 300 001(f6) 211 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14983, 348},
    /*   9 : CTESTNZ spec4,rm16,imm16 [wmi:      evex.scc5.dfv.l0.m4.o16 f7 /1 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 05) 300 320 001(f7) 211 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+4061, 349},
    /*  10 : CTESTNZ spec4,rm32,imm32 [wmi:      evex.scc5.dfv.l0.m4.o32 f7 /1 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 05) 300 321 001(f7) 211 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+4237, 350},
    /*  11 : CTESTNZ spec4,rm64,sdword64 [wmi:      evex.scc5.dfv.l0.m4.o64 f7 /1 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 05) 300 324 001(f7) 211 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTNZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+4413, 350},
};

static const struct itemplate instrux_CTESTO[12] = {
    /*   0 : CTESTO spec4,rm8,reg8 [wmr:      evex.scc0.dfv.l0.m4.o8 84 /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 00) 300 001(84) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+25164, 348},
    /*   1 : CTESTO spec4,rm16,reg16 [wmr:      evex.scc0.dfv.l0.m4.o16 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 00) 300 320 001(85) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+14373, 349},
    /*   2 : CTESTO spec4,rm32,reg32 [wmr:      evex.scc0.dfv.l0.m4.o32 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 00) 300 321 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+14533, 350},
    /*   3 : CTESTO spec4,rm64,reg64 [wmr:      evex.scc0.dfv.l0.m4.o64 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 00) 300 324 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14693, 350},
    /*   4 : CTESTO spec4,rm8,imm8 [wmi:      evex.scc0.dfv.l0.m4.o8 f6 /0 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 00) 300 001(f6) 210 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14853, 348},
    /*   5 : CTESTO spec4,rm16,imm16 [wmi:      evex.scc0.dfv.l0.m4.o16 f7 /0 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 00) 300 320 001(f7) 210 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3566, 349},
    /*   6 : CTESTO spec4,rm32,imm32 [wmi:      evex.scc0.dfv.l0.m4.o32 f7 /0 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 00) 300 321 001(f7) 210 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3742, 350},
    /*   7 : CTESTO spec4,rm64,sdword64 [wmi:      evex.scc0.dfv.l0.m4.o64 f7 /0 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 00) 300 324 001(f7) 210 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3918, 350},
    /*   8 : CTESTO spec4,rm8,imm8 [wmi:      evex.scc0.dfv.l0.m4.o8 f6 /1 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 00) 300 001(f6) 211 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15013, 348},
    /*   9 : CTESTO spec4,rm16,imm16 [wmi:      evex.scc0.dfv.l0.m4.o16 f7 /1 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 00) 300 320 001(f7) 211 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+4094, 349},
    /*  10 : CTESTO spec4,rm32,imm32 [wmi:      evex.scc0.dfv.l0.m4.o32 f7 /1 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 00) 300 321 001(f7) 211 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+4270, 350},
    /*  11 : CTESTO spec4,rm64,sdword64 [wmi:      evex.scc0.dfv.l0.m4.o64 f7 /1 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 00) 300 324 001(f7) 211 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTO, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+4446, 350},
};

static const struct itemplate instrux_CTESTS[12] = {
    /*   0 : CTESTS spec4,rm8,reg8 [wmr:      evex.scc8.dfv.l0.m4.o8 84 /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 08) 300 001(84) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+25173, 348},
    /*   1 : CTESTS spec4,rm16,reg16 [wmr:      evex.scc8.dfv.l0.m4.o16 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 08) 300 320 001(85) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+14383, 349},
    /*   2 : CTESTS spec4,rm32,reg32 [wmr:      evex.scc8.dfv.l0.m4.o32 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 08) 300 321 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+14543, 350},
    /*   3 : CTESTS spec4,rm64,reg64 [wmr:      evex.scc8.dfv.l0.m4.o64 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 08) 300 324 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14703, 350},
    /*   4 : CTESTS spec4,rm8,imm8 [wmi:      evex.scc8.dfv.l0.m4.o8 f6 /0 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 08) 300 001(f6) 210 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14863, 348},
    /*   5 : CTESTS spec4,rm16,imm16 [wmi:      evex.scc8.dfv.l0.m4.o16 f7 /0 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 08) 300 320 001(f7) 210 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3577, 349},
    /*   6 : CTESTS spec4,rm32,imm32 [wmi:      evex.scc8.dfv.l0.m4.o32 f7 /0 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 08) 300 321 001(f7) 210 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3753, 350},
    /*   7 : CTESTS spec4,rm64,sdword64 [wmi:      evex.scc8.dfv.l0.m4.o64 f7 /0 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 08) 300 324 001(f7) 210 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3929, 350},
    /*   8 : CTESTS spec4,rm8,imm8 [wmi:      evex.scc8.dfv.l0.m4.o8 f6 /1 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 08) 300 001(f6) 211 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15023, 348},
    /*   9 : CTESTS spec4,rm16,imm16 [wmi:      evex.scc8.dfv.l0.m4.o16 f7 /1 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 08) 300 320 001(f7) 211 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+4105, 349},
    /*  10 : CTESTS spec4,rm32,imm32 [wmi:      evex.scc8.dfv.l0.m4.o32 f7 /1 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 08) 300 321 001(f7) 211 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+4281, 350},
    /*  11 : CTESTS spec4,rm64,sdword64 [wmi:      evex.scc8.dfv.l0.m4.o64 f7 /1 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 08) 300 324 001(f7) 211 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTS, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+4457, 350},
};

static const struct itemplate instrux_CTESTT[12] = {
    /*   0 : CTESTT spec4,rm8,reg8 [wmr:      evex.scc10.dfv.l0.m4.o8 84 /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0a) 300 001(84) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTT, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+25182, 348},
    /*   1 : CTESTT spec4,rm16,reg16 [wmr:      evex.scc10.dfv.l0.m4.o16 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0a) 300 320 001(85) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTT, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+14393, 349},
    /*   2 : CTESTT spec4,rm32,reg32 [wmr:      evex.scc10.dfv.l0.m4.o32 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0a) 300 321 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTT, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+14553, 350},
    /*   3 : CTESTT spec4,rm64,reg64 [wmr:      evex.scc10.dfv.l0.m4.o64 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0a) 300 324 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTT, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14713, 350},
    /*   4 : CTESTT spec4,rm8,imm8 [wmi:      evex.scc10.dfv.l0.m4.o8 f6 /0 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0a) 300 001(f6) 210 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTT, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14873, 348},
    /*   5 : CTESTT spec4,rm16,imm16 [wmi:      evex.scc10.dfv.l0.m4.o16 f7 /0 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0a) 300 320 001(f7) 210 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTT, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3588, 349},
    /*   6 : CTESTT spec4,rm32,imm32 [wmi:      evex.scc10.dfv.l0.m4.o32 f7 /0 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0a) 300 321 001(f7) 210 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTT, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3764, 350},
    /*   7 : CTESTT spec4,rm64,sdword64 [wmi:      evex.scc10.dfv.l0.m4.o64 f7 /0 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0a) 300 324 001(f7) 210 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTT, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3940, 350},
    /*   8 : CTESTT spec4,rm8,imm8 [wmi:      evex.scc10.dfv.l0.m4.o8 f6 /1 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0a) 300 001(f6) 211 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTT, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15033, 348},
    /*   9 : CTESTT spec4,rm16,imm16 [wmi:      evex.scc10.dfv.l0.m4.o16 f7 /1 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 0a) 300 320 001(f7) 211 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTT, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+4116, 349},
    /*  10 : CTESTT spec4,rm32,imm32 [wmi:      evex.scc10.dfv.l0.m4.o32 f7 /1 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 0a) 300 321 001(f7) 211 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTT, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+4292, 350},
    /*  11 : CTESTT spec4,rm64,sdword64 [wmi:      evex.scc10.dfv.l0.m4.o64 f7 /1 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 0a) 300 324 001(f7) 211 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTT, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+4468, 350},
};

static const struct itemplate instrux_CTESTZ[12] = {
    /*   0 : CTESTZ spec4,rm8,reg8 [wmr:      evex.scc4.dfv.l0.m4.o8 84 /r       ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 04) 300 001(84) 112 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,REG_GPR|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+25092, 348},
    /*   1 : CTESTZ spec4,rm16,reg16 [wmr:      evex.scc4.dfv.l0.m4.o16 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 04) 300 320 001(85) 112 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,REG_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+14293, 349},
    /*   2 : CTESTZ spec4,rm32,reg32 [wmr:      evex.scc4.dfv.l0.m4.o32 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 04) 300 321 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+14453, 350},
    /*   3 : CTESTZ spec4,rm64,reg64 [wmr:      evex.scc4.dfv.l0.m4.o64 85 /r      ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 04) 300 324 001(85) 112 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14613, 350},
    /*   4 : CTESTZ spec4,rm8,imm8 [wmi:      evex.scc4.dfv.l0.m4.o8 f6 /0 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 04) 300 001(f6) 210 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14773, 348},
    /*   5 : CTESTZ spec4,rm16,imm16 [wmi:      evex.scc4.dfv.l0.m4.o16 f7 /0 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 04) 300 320 001(f7) 210 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+3478, 349},
    /*   6 : CTESTZ spec4,rm32,imm32 [wmi:      evex.scc4.dfv.l0.m4.o32 f7 /0 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 04) 300 321 001(f7) 210 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+3654, 350},
    /*   7 : CTESTZ spec4,rm64,sdword64 [wmi:      evex.scc4.dfv.l0.m4.o64 f7 /0 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 04) 300 324 001(f7) 210 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+3830, 350},
    /*   8 : CTESTZ spec4,rm8,imm8 [wmi:      evex.scc4.dfv.l0.m4.o8 f6 /1 ib    ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 04) 300 001(f6) 211 022 : SM1,SM2,WIG,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14933, 348},
    /*   9 : CTESTZ spec4,rm16,imm16 [wmi:      evex.scc4.dfv.l0.m4.o16 f7 /1 iw   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 05 04) 300 320 001(f7) 211 032 : SM1,SM2,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS16,IMM_NORMAL|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+4006, 349},
    /*  10 : CTESTZ spec4,rm32,imm32 [wmi:      evex.scc4.dfv.l0.m4.o32 f7 /1 id   ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 04 04) 300 321 001(f7) 211 042 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS32,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+4182, 350},
    /*  11 : CTESTZ spec4,rm64,sdword64 [wmi:      evex.scc4.dfv.l0.m4.o64 f7 /1 id,s ] SM1-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 84 04) 300 324 001(f7) 211 256 : SM1,SM2,WW,LONG,SCC,DFV,EVEX,PROT,APX,X86_64 */
        {I_CTESTZ, 3, {IMMEDIATE|FOURBITS,RM_GPR|BITS64,SDWORD|BITS64|IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+4358, 350},
};

static const struct itemplate instrux_CMOVA[6] = {
    /*   0 : CMOVA reg16,rm16 [rm:       o16 0f 47 /r                    ] SM0-1,P6 */
        /* 320 355 001(47) 110 : SM0,SM1,P6 */
        {I_CMOVA, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67916, 351},
    /*   1 : CMOVA reg32,rm32 [rm:       o32 0f 47 /r                    ] SM0-1,P6 */
        /* 321 355 001(47) 110 : SM0,SM1,P6 */
        {I_CMOVA, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68012, 351},
    /*   2 : CMOVA reg64,rm64 [rm:       o64 0f 47 /r                    ] SM0-1,LONG,PROT,X86_64 */
        /* 324 355 001(47) 110 : SM0,SM1,LONG,PROT,X86_64 */
        {I_CMOVA, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+68108, 14},
    /*   3 : CMOVA reg16,reg16,rm16 [vrm:      evex.nf0.nd1.l0.m4.o16 47 /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(47) 121 : SM0,SM1,SM2,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVA, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+15043, 352},
    /*   4 : CMOVA reg32,reg32,rm32 [vrm:      evex.nf0.nd1.l0.m4.o32 47 /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(47) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVA, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+15203, 353},
    /*   5 : CMOVA reg64,reg64,rm64 [vrm:      evex.nf0.nd1.l0.m4.o64 47 /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(47) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVA, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+15363, 353},
};

static const struct itemplate instrux_CMOVAE[6] = {
    /*   0 : CMOVAE reg16,rm16 [rm:       o16 0f 43 /r                    ] SM0-1,P6,ND */
        /* 320 355 001(43) 110 : SM0,SM1,P6 */
        {I_CMOVAE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67922, 351},
    /*   1 : CMOVAE reg32,rm32 [rm:       o32 0f 43 /r                    ] SM0-1,P6,ND */
        /* 321 355 001(43) 110 : SM0,SM1,P6 */
        {I_CMOVAE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68018, 351},
    /*   2 : CMOVAE reg64,rm64 [rm:       o64 0f 43 /r                    ] SM0-1,LONG,PROT,X86_64,ND */
        /* 324 355 001(43) 110 : SM0,SM1,LONG,PROT,X86_64 */
        {I_CMOVAE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+68114, 14},
    /*   3 : CMOVAE reg16,reg16,rm16 [vrm:      evex.nf0.nd1.l0.m4.o16 43 /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7d 18) 300 320 001(43) 121 : SM0,SM1,SM2,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVAE, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+15053, 352},
    /*   4 : CMOVAE reg32,reg32,rm32 [vrm:      evex.nf0.nd1.l0.m4.o32 43 /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7c 18) 300 321 001(43) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVAE, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+15213, 353},
    /*   5 : CMOVAE reg64,reg64,rm64 [vrm:      evex.nf0.nd1.l0.m4.o64 43 /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 fc 18) 300 324 001(43) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVAE, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+15373, 353},
};

static const struct itemplate instrux_CMOVB[6] = {
    /*   0 : CMOVB reg16,rm16 [rm:       o16 0f 42 /r                    ] SM0-1,P6,ND */
        /* 320 355 001(42) 110 : SM0,SM1,P6 */
        {I_CMOVB, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67928, 351},
    /*   1 : CMOVB reg32,rm32 [rm:       o32 0f 42 /r                    ] SM0-1,P6,ND */
        /* 321 355 001(42) 110 : SM0,SM1,P6 */
        {I_CMOVB, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68024, 351},
    /*   2 : CMOVB reg64,rm64 [rm:       o64 0f 42 /r                    ] SM0-1,LONG,PROT,X86_64,ND */
        /* 324 355 001(42) 110 : SM0,SM1,LONG,PROT,X86_64 */
        {I_CMOVB, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+68120, 14},
    /*   3 : CMOVB reg16,reg16,rm16 [vrm:      evex.nf0.nd1.l0.m4.o16 42 /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7d 18) 300 320 001(42) 121 : SM0,SM1,SM2,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVB, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+15063, 352},
    /*   4 : CMOVB reg32,reg32,rm32 [vrm:      evex.nf0.nd1.l0.m4.o32 42 /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7c 18) 300 321 001(42) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVB, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+15223, 353},
    /*   5 : CMOVB reg64,reg64,rm64 [vrm:      evex.nf0.nd1.l0.m4.o64 42 /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 fc 18) 300 324 001(42) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVB, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+15383, 353},
};

static const struct itemplate instrux_CMOVBE[6] = {
    /*   0 : CMOVBE reg16,rm16 [rm:       o16 0f 46 /r                    ] SM0-1,P6,ND */
        /* 320 355 001(46) 110 : SM0,SM1,P6 */
        {I_CMOVBE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67934, 351},
    /*   1 : CMOVBE reg32,rm32 [rm:       o32 0f 46 /r                    ] SM0-1,P6,ND */
        /* 321 355 001(46) 110 : SM0,SM1,P6 */
        {I_CMOVBE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68030, 351},
    /*   2 : CMOVBE reg64,rm64 [rm:       o64 0f 46 /r                    ] SM0-1,LONG,PROT,X86_64,ND */
        /* 324 355 001(46) 110 : SM0,SM1,LONG,PROT,X86_64 */
        {I_CMOVBE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+68126, 14},
    /*   3 : CMOVBE reg16,reg16,rm16 [vrm:      evex.nf0.nd1.l0.m4.o16 46 /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7d 18) 300 320 001(46) 121 : SM0,SM1,SM2,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVBE, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+15073, 352},
    /*   4 : CMOVBE reg32,reg32,rm32 [vrm:      evex.nf0.nd1.l0.m4.o32 46 /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7c 18) 300 321 001(46) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVBE, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+15233, 353},
    /*   5 : CMOVBE reg64,reg64,rm64 [vrm:      evex.nf0.nd1.l0.m4.o64 46 /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 fc 18) 300 324 001(46) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVBE, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+15393, 353},
};

static const struct itemplate instrux_CMOVC[6] = {
    /*   0 : CMOVC reg16,rm16 [rm:       o16 0f 42 /r                    ] SM0-1,P6 */
        /* 320 355 001(42) 110 : SM0,SM1,P6 */
        {I_CMOVC, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67928, 351},
    /*   1 : CMOVC reg32,rm32 [rm:       o32 0f 42 /r                    ] SM0-1,P6 */
        /* 321 355 001(42) 110 : SM0,SM1,P6 */
        {I_CMOVC, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68024, 351},
    /*   2 : CMOVC reg64,rm64 [rm:       o64 0f 42 /r                    ] SM0-1,LONG,PROT,X86_64 */
        /* 324 355 001(42) 110 : SM0,SM1,LONG,PROT,X86_64 */
        {I_CMOVC, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+68120, 14},
    /*   3 : CMOVC reg16,reg16,rm16 [vrm:      evex.nf0.nd1.l0.m4.o16 42 /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(42) 121 : SM0,SM1,SM2,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVC, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+15063, 352},
    /*   4 : CMOVC reg32,reg32,rm32 [vrm:      evex.nf0.nd1.l0.m4.o32 42 /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(42) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVC, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+15223, 353},
    /*   5 : CMOVC reg64,reg64,rm64 [vrm:      evex.nf0.nd1.l0.m4.o64 42 /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(42) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVC, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+15383, 353},
};

static const struct itemplate instrux_CMOVE[6] = {
    /*   0 : CMOVE reg16,rm16 [rm:       o16 0f 44 /r                    ] SM0-1,P6,ND */
        /* 320 355 001(44) 110 : SM0,SM1,P6 */
        {I_CMOVE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67940, 351},
    /*   1 : CMOVE reg32,rm32 [rm:       o32 0f 44 /r                    ] SM0-1,P6,ND */
        /* 321 355 001(44) 110 : SM0,SM1,P6 */
        {I_CMOVE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68036, 351},
    /*   2 : CMOVE reg64,rm64 [rm:       o64 0f 44 /r                    ] SM0-1,LONG,PROT,X86_64,ND */
        /* 324 355 001(44) 110 : SM0,SM1,LONG,PROT,X86_64 */
        {I_CMOVE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+68132, 14},
    /*   3 : CMOVE reg16,reg16,rm16 [vrm:      evex.nf0.nd1.l0.m4.o16 44 /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7d 18) 300 320 001(44) 121 : SM0,SM1,SM2,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVE, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+15083, 352},
    /*   4 : CMOVE reg32,reg32,rm32 [vrm:      evex.nf0.nd1.l0.m4.o32 44 /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7c 18) 300 321 001(44) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVE, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+15243, 353},
    /*   5 : CMOVE reg64,reg64,rm64 [vrm:      evex.nf0.nd1.l0.m4.o64 44 /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 fc 18) 300 324 001(44) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVE, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+15403, 353},
};

static const struct itemplate instrux_CMOVG[6] = {
    /*   0 : CMOVG reg16,rm16 [rm:       o16 0f 4f /r                    ] SM0-1,P6 */
        /* 320 355 001(4f) 110 : SM0,SM1,P6 */
        {I_CMOVG, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67946, 351},
    /*   1 : CMOVG reg32,rm32 [rm:       o32 0f 4f /r                    ] SM0-1,P6 */
        /* 321 355 001(4f) 110 : SM0,SM1,P6 */
        {I_CMOVG, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68042, 351},
    /*   2 : CMOVG reg64,rm64 [rm:       o64 0f 4f /r                    ] SM0-1,LONG,PROT,X86_64 */
        /* 324 355 001(4f) 110 : SM0,SM1,LONG,PROT,X86_64 */
        {I_CMOVG, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+68138, 14},
    /*   3 : CMOVG reg16,reg16,rm16 [vrm:      evex.nf0.nd1.l0.m4.o16 4f /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(4f) 121 : SM0,SM1,SM2,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVG, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+15093, 352},
    /*   4 : CMOVG reg32,reg32,rm32 [vrm:      evex.nf0.nd1.l0.m4.o32 4f /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(4f) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVG, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+15253, 353},
    /*   5 : CMOVG reg64,reg64,rm64 [vrm:      evex.nf0.nd1.l0.m4.o64 4f /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(4f) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVG, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+15413, 353},
};

static const struct itemplate instrux_CMOVGE[6] = {
    /*   0 : CMOVGE reg16,rm16 [rm:       o16 0f 4d /r                    ] SM0-1,P6,ND */
        /* 320 355 001(4d) 110 : SM0,SM1,P6 */
        {I_CMOVGE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67952, 351},
    /*   1 : CMOVGE reg32,rm32 [rm:       o32 0f 4d /r                    ] SM0-1,P6,ND */
        /* 321 355 001(4d) 110 : SM0,SM1,P6 */
        {I_CMOVGE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68048, 351},
    /*   2 : CMOVGE reg64,rm64 [rm:       o64 0f 4d /r                    ] SM0-1,LONG,PROT,X86_64,ND */
        /* 324 355 001(4d) 110 : SM0,SM1,LONG,PROT,X86_64 */
        {I_CMOVGE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+68144, 14},
    /*   3 : CMOVGE reg16,reg16,rm16 [vrm:      evex.nf0.nd1.l0.m4.o16 4d /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7d 18) 300 320 001(4d) 121 : SM0,SM1,SM2,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVGE, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+15103, 352},
    /*   4 : CMOVGE reg32,reg32,rm32 [vrm:      evex.nf0.nd1.l0.m4.o32 4d /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7c 18) 300 321 001(4d) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVGE, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+15263, 353},
    /*   5 : CMOVGE reg64,reg64,rm64 [vrm:      evex.nf0.nd1.l0.m4.o64 4d /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 fc 18) 300 324 001(4d) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVGE, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+15423, 353},
};

static const struct itemplate instrux_CMOVL[6] = {
    /*   0 : CMOVL reg16,rm16 [rm:       o16 0f 4c /r                    ] SM0-1,P6 */
        /* 320 355 001(4c) 110 : SM0,SM1,P6 */
        {I_CMOVL, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67958, 351},
    /*   1 : CMOVL reg32,rm32 [rm:       o32 0f 4c /r                    ] SM0-1,P6 */
        /* 321 355 001(4c) 110 : SM0,SM1,P6 */
        {I_CMOVL, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68054, 351},
    /*   2 : CMOVL reg64,rm64 [rm:       o64 0f 4c /r                    ] SM0-1,LONG,PROT,X86_64 */
        /* 324 355 001(4c) 110 : SM0,SM1,LONG,PROT,X86_64 */
        {I_CMOVL, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+68150, 14},
    /*   3 : CMOVL reg16,reg16,rm16 [vrm:      evex.nf0.nd1.l0.m4.o16 4c /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(4c) 121 : SM0,SM1,SM2,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVL, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+15113, 352},
    /*   4 : CMOVL reg32,reg32,rm32 [vrm:      evex.nf0.nd1.l0.m4.o32 4c /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(4c) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVL, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+15273, 353},
    /*   5 : CMOVL reg64,reg64,rm64 [vrm:      evex.nf0.nd1.l0.m4.o64 4c /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(4c) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVL, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+15433, 353},
};

static const struct itemplate instrux_CMOVLE[6] = {
    /*   0 : CMOVLE reg16,rm16 [rm:       o16 0f 4e /r                    ] SM0-1,P6,ND */
        /* 320 355 001(4e) 110 : SM0,SM1,P6 */
        {I_CMOVLE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67964, 351},
    /*   1 : CMOVLE reg32,rm32 [rm:       o32 0f 4e /r                    ] SM0-1,P6,ND */
        /* 321 355 001(4e) 110 : SM0,SM1,P6 */
        {I_CMOVLE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68060, 351},
    /*   2 : CMOVLE reg64,rm64 [rm:       o64 0f 4e /r                    ] SM0-1,LONG,PROT,X86_64,ND */
        /* 324 355 001(4e) 110 : SM0,SM1,LONG,PROT,X86_64 */
        {I_CMOVLE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+68156, 14},
    /*   3 : CMOVLE reg16,reg16,rm16 [vrm:      evex.nf0.nd1.l0.m4.o16 4e /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7d 18) 300 320 001(4e) 121 : SM0,SM1,SM2,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVLE, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+15123, 352},
    /*   4 : CMOVLE reg32,reg32,rm32 [vrm:      evex.nf0.nd1.l0.m4.o32 4e /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7c 18) 300 321 001(4e) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVLE, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+15283, 353},
    /*   5 : CMOVLE reg64,reg64,rm64 [vrm:      evex.nf0.nd1.l0.m4.o64 4e /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 fc 18) 300 324 001(4e) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVLE, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+15443, 353},
};

static const struct itemplate instrux_CMOVNA[6] = {
    /*   0 : CMOVNA reg16,rm16 [rm:       o16 0f 46 /r                    ] SM0-1,P6 */
        /* 320 355 001(46) 110 : SM0,SM1,P6 */
        {I_CMOVNA, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67934, 351},
    /*   1 : CMOVNA reg32,rm32 [rm:       o32 0f 46 /r                    ] SM0-1,P6 */
        /* 321 355 001(46) 110 : SM0,SM1,P6 */
        {I_CMOVNA, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68030, 351},
    /*   2 : CMOVNA reg64,rm64 [rm:       o64 0f 46 /r                    ] SM0-1,LONG,PROT,X86_64 */
        /* 324 355 001(46) 110 : SM0,SM1,LONG,PROT,X86_64 */
        {I_CMOVNA, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+68126, 14},
    /*   3 : CMOVNA reg16,reg16,rm16 [vrm:      evex.nf0.nd1.l0.m4.o16 46 /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(46) 121 : SM0,SM1,SM2,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNA, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+15073, 352},
    /*   4 : CMOVNA reg32,reg32,rm32 [vrm:      evex.nf0.nd1.l0.m4.o32 46 /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(46) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNA, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+15233, 353},
    /*   5 : CMOVNA reg64,reg64,rm64 [vrm:      evex.nf0.nd1.l0.m4.o64 46 /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(46) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNA, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+15393, 353},
};

static const struct itemplate instrux_CMOVNAE[6] = {
    /*   0 : CMOVNAE reg16,rm16 [rm:       o16 0f 42 /r                    ] SM0-1,P6,ND */
        /* 320 355 001(42) 110 : SM0,SM1,P6 */
        {I_CMOVNAE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67928, 351},
    /*   1 : CMOVNAE reg32,rm32 [rm:       o32 0f 42 /r                    ] SM0-1,P6,ND */
        /* 321 355 001(42) 110 : SM0,SM1,P6 */
        {I_CMOVNAE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68024, 351},
    /*   2 : CMOVNAE reg64,rm64 [rm:       o64 0f 42 /r                    ] SM0-1,LONG,PROT,X86_64,ND */
        /* 324 355 001(42) 110 : SM0,SM1,LONG,PROT,X86_64 */
        {I_CMOVNAE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+68120, 14},
    /*   3 : CMOVNAE reg16,reg16,rm16 [vrm:      evex.nf0.nd1.l0.m4.o16 42 /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7d 18) 300 320 001(42) 121 : SM0,SM1,SM2,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNAE, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+15063, 352},
    /*   4 : CMOVNAE reg32,reg32,rm32 [vrm:      evex.nf0.nd1.l0.m4.o32 42 /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7c 18) 300 321 001(42) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNAE, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+15223, 353},
    /*   5 : CMOVNAE reg64,reg64,rm64 [vrm:      evex.nf0.nd1.l0.m4.o64 42 /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 fc 18) 300 324 001(42) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNAE, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+15383, 353},
};

static const struct itemplate instrux_CMOVNB[6] = {
    /*   0 : CMOVNB reg16,rm16 [rm:       o16 0f 43 /r                    ] SM0-1,P6,ND */
        /* 320 355 001(43) 110 : SM0,SM1,P6 */
        {I_CMOVNB, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67922, 351},
    /*   1 : CMOVNB reg32,rm32 [rm:       o32 0f 43 /r                    ] SM0-1,P6,ND */
        /* 321 355 001(43) 110 : SM0,SM1,P6 */
        {I_CMOVNB, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68018, 351},
    /*   2 : CMOVNB reg64,rm64 [rm:       o64 0f 43 /r                    ] SM0-1,LONG,PROT,X86_64,ND */
        /* 324 355 001(43) 110 : SM0,SM1,LONG,PROT,X86_64 */
        {I_CMOVNB, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+68114, 14},
    /*   3 : CMOVNB reg16,reg16,rm16 [vrm:      evex.nf0.nd1.l0.m4.o16 43 /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7d 18) 300 320 001(43) 121 : SM0,SM1,SM2,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNB, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+15053, 352},
    /*   4 : CMOVNB reg32,reg32,rm32 [vrm:      evex.nf0.nd1.l0.m4.o32 43 /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7c 18) 300 321 001(43) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNB, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+15213, 353},
    /*   5 : CMOVNB reg64,reg64,rm64 [vrm:      evex.nf0.nd1.l0.m4.o64 43 /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 fc 18) 300 324 001(43) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNB, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+15373, 353},
};

static const struct itemplate instrux_CMOVNBE[6] = {
    /*   0 : CMOVNBE reg16,rm16 [rm:       o16 0f 47 /r                    ] SM0-1,P6,ND */
        /* 320 355 001(47) 110 : SM0,SM1,P6 */
        {I_CMOVNBE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67916, 351},
    /*   1 : CMOVNBE reg32,rm32 [rm:       o32 0f 47 /r                    ] SM0-1,P6,ND */
        /* 321 355 001(47) 110 : SM0,SM1,P6 */
        {I_CMOVNBE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68012, 351},
    /*   2 : CMOVNBE reg64,rm64 [rm:       o64 0f 47 /r                    ] SM0-1,LONG,PROT,X86_64,ND */
        /* 324 355 001(47) 110 : SM0,SM1,LONG,PROT,X86_64 */
        {I_CMOVNBE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+68108, 14},
    /*   3 : CMOVNBE reg16,reg16,rm16 [vrm:      evex.nf0.nd1.l0.m4.o16 47 /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7d 18) 300 320 001(47) 121 : SM0,SM1,SM2,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNBE, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+15043, 352},
    /*   4 : CMOVNBE reg32,reg32,rm32 [vrm:      evex.nf0.nd1.l0.m4.o32 47 /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7c 18) 300 321 001(47) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNBE, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+15203, 353},
    /*   5 : CMOVNBE reg64,reg64,rm64 [vrm:      evex.nf0.nd1.l0.m4.o64 47 /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 fc 18) 300 324 001(47) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNBE, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+15363, 353},
};

static const struct itemplate instrux_CMOVNC[6] = {
    /*   0 : CMOVNC reg16,rm16 [rm:       o16 0f 43 /r                    ] SM0-1,P6 */
        /* 320 355 001(43) 110 : SM0,SM1,P6 */
        {I_CMOVNC, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67922, 351},
    /*   1 : CMOVNC reg32,rm32 [rm:       o32 0f 43 /r                    ] SM0-1,P6 */
        /* 321 355 001(43) 110 : SM0,SM1,P6 */
        {I_CMOVNC, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68018, 351},
    /*   2 : CMOVNC reg64,rm64 [rm:       o64 0f 43 /r                    ] SM0-1,LONG,PROT,X86_64 */
        /* 324 355 001(43) 110 : SM0,SM1,LONG,PROT,X86_64 */
        {I_CMOVNC, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+68114, 14},
    /*   3 : CMOVNC reg16,reg16,rm16 [vrm:      evex.nf0.nd1.l0.m4.o16 43 /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(43) 121 : SM0,SM1,SM2,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNC, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+15053, 352},
    /*   4 : CMOVNC reg32,reg32,rm32 [vrm:      evex.nf0.nd1.l0.m4.o32 43 /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(43) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNC, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+15213, 353},
    /*   5 : CMOVNC reg64,reg64,rm64 [vrm:      evex.nf0.nd1.l0.m4.o64 43 /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(43) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNC, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+15373, 353},
};

static const struct itemplate instrux_CMOVNE[6] = {
    /*   0 : CMOVNE reg16,rm16 [rm:       o16 0f 45 /r                    ] SM0-1,P6,ND */
        /* 320 355 001(45) 110 : SM0,SM1,P6 */
        {I_CMOVNE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67970, 351},
    /*   1 : CMOVNE reg32,rm32 [rm:       o32 0f 45 /r                    ] SM0-1,P6,ND */
        /* 321 355 001(45) 110 : SM0,SM1,P6 */
        {I_CMOVNE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68066, 351},
    /*   2 : CMOVNE reg64,rm64 [rm:       o64 0f 45 /r                    ] SM0-1,LONG,PROT,X86_64,ND */
        /* 324 355 001(45) 110 : SM0,SM1,LONG,PROT,X86_64 */
        {I_CMOVNE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+68162, 14},
    /*   3 : CMOVNE reg16,reg16,rm16 [vrm:      evex.nf0.nd1.l0.m4.o16 45 /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7d 18) 300 320 001(45) 121 : SM0,SM1,SM2,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNE, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+15133, 352},
    /*   4 : CMOVNE reg32,reg32,rm32 [vrm:      evex.nf0.nd1.l0.m4.o32 45 /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7c 18) 300 321 001(45) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNE, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+15293, 353},
    /*   5 : CMOVNE reg64,reg64,rm64 [vrm:      evex.nf0.nd1.l0.m4.o64 45 /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 fc 18) 300 324 001(45) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNE, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+15453, 353},
};

static const struct itemplate instrux_CMOVNG[6] = {
    /*   0 : CMOVNG reg16,rm16 [rm:       o16 0f 4e /r                    ] SM0-1,P6 */
        /* 320 355 001(4e) 110 : SM0,SM1,P6 */
        {I_CMOVNG, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67964, 351},
    /*   1 : CMOVNG reg32,rm32 [rm:       o32 0f 4e /r                    ] SM0-1,P6 */
        /* 321 355 001(4e) 110 : SM0,SM1,P6 */
        {I_CMOVNG, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68060, 351},
    /*   2 : CMOVNG reg64,rm64 [rm:       o64 0f 4e /r                    ] SM0-1,LONG,PROT,X86_64 */
        /* 324 355 001(4e) 110 : SM0,SM1,LONG,PROT,X86_64 */
        {I_CMOVNG, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+68156, 14},
    /*   3 : CMOVNG reg16,reg16,rm16 [vrm:      evex.nf0.nd1.l0.m4.o16 4e /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(4e) 121 : SM0,SM1,SM2,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNG, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+15123, 352},
    /*   4 : CMOVNG reg32,reg32,rm32 [vrm:      evex.nf0.nd1.l0.m4.o32 4e /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(4e) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNG, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+15283, 353},
    /*   5 : CMOVNG reg64,reg64,rm64 [vrm:      evex.nf0.nd1.l0.m4.o64 4e /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(4e) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNG, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+15443, 353},
};

static const struct itemplate instrux_CMOVNGE[6] = {
    /*   0 : CMOVNGE reg16,rm16 [rm:       o16 0f 4c /r                    ] SM0-1,P6,ND */
        /* 320 355 001(4c) 110 : SM0,SM1,P6 */
        {I_CMOVNGE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67958, 351},
    /*   1 : CMOVNGE reg32,rm32 [rm:       o32 0f 4c /r                    ] SM0-1,P6,ND */
        /* 321 355 001(4c) 110 : SM0,SM1,P6 */
        {I_CMOVNGE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68054, 351},
    /*   2 : CMOVNGE reg64,rm64 [rm:       o64 0f 4c /r                    ] SM0-1,LONG,PROT,X86_64,ND */
        /* 324 355 001(4c) 110 : SM0,SM1,LONG,PROT,X86_64 */
        {I_CMOVNGE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+68150, 14},
    /*   3 : CMOVNGE reg16,reg16,rm16 [vrm:      evex.nf0.nd1.l0.m4.o16 4c /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7d 18) 300 320 001(4c) 121 : SM0,SM1,SM2,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNGE, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+15113, 352},
    /*   4 : CMOVNGE reg32,reg32,rm32 [vrm:      evex.nf0.nd1.l0.m4.o32 4c /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7c 18) 300 321 001(4c) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNGE, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+15273, 353},
    /*   5 : CMOVNGE reg64,reg64,rm64 [vrm:      evex.nf0.nd1.l0.m4.o64 4c /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 fc 18) 300 324 001(4c) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNGE, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+15433, 353},
};

static const struct itemplate instrux_CMOVNL[6] = {
    /*   0 : CMOVNL reg16,rm16 [rm:       o16 0f 4d /r                    ] SM0-1,P6 */
        /* 320 355 001(4d) 110 : SM0,SM1,P6 */
        {I_CMOVNL, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67952, 351},
    /*   1 : CMOVNL reg32,rm32 [rm:       o32 0f 4d /r                    ] SM0-1,P6 */
        /* 321 355 001(4d) 110 : SM0,SM1,P6 */
        {I_CMOVNL, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68048, 351},
    /*   2 : CMOVNL reg64,rm64 [rm:       o64 0f 4d /r                    ] SM0-1,LONG,PROT,X86_64 */
        /* 324 355 001(4d) 110 : SM0,SM1,LONG,PROT,X86_64 */
        {I_CMOVNL, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+68144, 14},
    /*   3 : CMOVNL reg16,reg16,rm16 [vrm:      evex.nf0.nd1.l0.m4.o16 4d /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(4d) 121 : SM0,SM1,SM2,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNL, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+15103, 352},
    /*   4 : CMOVNL reg32,reg32,rm32 [vrm:      evex.nf0.nd1.l0.m4.o32 4d /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(4d) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNL, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+15263, 353},
    /*   5 : CMOVNL reg64,reg64,rm64 [vrm:      evex.nf0.nd1.l0.m4.o64 4d /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(4d) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNL, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+15423, 353},
};

static const struct itemplate instrux_CMOVNLE[6] = {
    /*   0 : CMOVNLE reg16,rm16 [rm:       o16 0f 4f /r                    ] SM0-1,P6,ND */
        /* 320 355 001(4f) 110 : SM0,SM1,P6 */
        {I_CMOVNLE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67946, 351},
    /*   1 : CMOVNLE reg32,rm32 [rm:       o32 0f 4f /r                    ] SM0-1,P6,ND */
        /* 321 355 001(4f) 110 : SM0,SM1,P6 */
        {I_CMOVNLE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68042, 351},
    /*   2 : CMOVNLE reg64,rm64 [rm:       o64 0f 4f /r                    ] SM0-1,LONG,PROT,X86_64,ND */
        /* 324 355 001(4f) 110 : SM0,SM1,LONG,PROT,X86_64 */
        {I_CMOVNLE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+68138, 14},
    /*   3 : CMOVNLE reg16,reg16,rm16 [vrm:      evex.nf0.nd1.l0.m4.o16 4f /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7d 18) 300 320 001(4f) 121 : SM0,SM1,SM2,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNLE, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+15093, 352},
    /*   4 : CMOVNLE reg32,reg32,rm32 [vrm:      evex.nf0.nd1.l0.m4.o32 4f /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7c 18) 300 321 001(4f) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNLE, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+15253, 353},
    /*   5 : CMOVNLE reg64,reg64,rm64 [vrm:      evex.nf0.nd1.l0.m4.o64 4f /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 fc 18) 300 324 001(4f) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNLE, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+15413, 353},
};

static const struct itemplate instrux_CMOVNO[6] = {
    /*   0 : CMOVNO reg16,rm16 [rm:       o16 0f 41 /r                    ] SM0-1,P6 */
        /* 320 355 001(41) 110 : SM0,SM1,P6 */
        {I_CMOVNO, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67976, 351},
    /*   1 : CMOVNO reg32,rm32 [rm:       o32 0f 41 /r                    ] SM0-1,P6 */
        /* 321 355 001(41) 110 : SM0,SM1,P6 */
        {I_CMOVNO, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68072, 351},
    /*   2 : CMOVNO reg64,rm64 [rm:       o64 0f 41 /r                    ] SM0-1,LONG,PROT,X86_64 */
        /* 324 355 001(41) 110 : SM0,SM1,LONG,PROT,X86_64 */
        {I_CMOVNO, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+68168, 14},
    /*   3 : CMOVNO reg16,reg16,rm16 [vrm:      evex.nf0.nd1.l0.m4.o16 41 /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(41) 121 : SM0,SM1,SM2,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNO, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+15143, 352},
    /*   4 : CMOVNO reg32,reg32,rm32 [vrm:      evex.nf0.nd1.l0.m4.o32 41 /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(41) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNO, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+15303, 353},
    /*   5 : CMOVNO reg64,reg64,rm64 [vrm:      evex.nf0.nd1.l0.m4.o64 41 /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(41) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNO, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+15463, 353},
};

static const struct itemplate instrux_CMOVNP[6] = {
    /*   0 : CMOVNP reg16,rm16 [rm:       o16 0f 4b /r                    ] SM0-1,P6,ND */
        /* 320 355 001(4b) 110 : SM0,SM1,P6 */
        {I_CMOVNP, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67982, 351},
    /*   1 : CMOVNP reg32,rm32 [rm:       o32 0f 4b /r                    ] SM0-1,P6,ND */
        /* 321 355 001(4b) 110 : SM0,SM1,P6 */
        {I_CMOVNP, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68078, 351},
    /*   2 : CMOVNP reg64,rm64 [rm:       o64 0f 4b /r                    ] SM0-1,LONG,PROT,X86_64,ND */
        /* 324 355 001(4b) 110 : SM0,SM1,LONG,PROT,X86_64 */
        {I_CMOVNP, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+68174, 14},
    /*   3 : CMOVNP reg16,reg16,rm16 [vrm:      evex.nf0.nd1.l0.m4.o16 4b /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7d 18) 300 320 001(4b) 121 : SM0,SM1,SM2,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNP, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+15153, 352},
    /*   4 : CMOVNP reg32,reg32,rm32 [vrm:      evex.nf0.nd1.l0.m4.o32 4b /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7c 18) 300 321 001(4b) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNP, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+15313, 353},
    /*   5 : CMOVNP reg64,reg64,rm64 [vrm:      evex.nf0.nd1.l0.m4.o64 4b /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 fc 18) 300 324 001(4b) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNP, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+15473, 353},
};

static const struct itemplate instrux_CMOVNS[6] = {
    /*   0 : CMOVNS reg16,rm16 [rm:       o16 0f 49 /r                    ] SM0-1,P6 */
        /* 320 355 001(49) 110 : SM0,SM1,P6 */
        {I_CMOVNS, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67988, 351},
    /*   1 : CMOVNS reg32,rm32 [rm:       o32 0f 49 /r                    ] SM0-1,P6 */
        /* 321 355 001(49) 110 : SM0,SM1,P6 */
        {I_CMOVNS, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68084, 351},
    /*   2 : CMOVNS reg64,rm64 [rm:       o64 0f 49 /r                    ] SM0-1,LONG,PROT,X86_64 */
        /* 324 355 001(49) 110 : SM0,SM1,LONG,PROT,X86_64 */
        {I_CMOVNS, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+68180, 14},
    /*   3 : CMOVNS reg16,reg16,rm16 [vrm:      evex.nf0.nd1.l0.m4.o16 49 /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(49) 121 : SM0,SM1,SM2,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNS, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+15163, 352},
    /*   4 : CMOVNS reg32,reg32,rm32 [vrm:      evex.nf0.nd1.l0.m4.o32 49 /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(49) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNS, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+15323, 353},
    /*   5 : CMOVNS reg64,reg64,rm64 [vrm:      evex.nf0.nd1.l0.m4.o64 49 /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(49) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNS, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+15483, 353},
};

static const struct itemplate instrux_CMOVNZ[6] = {
    /*   0 : CMOVNZ reg16,rm16 [rm:       o16 0f 45 /r                    ] SM0-1,P6 */
        /* 320 355 001(45) 110 : SM0,SM1,P6 */
        {I_CMOVNZ, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67970, 351},
    /*   1 : CMOVNZ reg32,rm32 [rm:       o32 0f 45 /r                    ] SM0-1,P6 */
        /* 321 355 001(45) 110 : SM0,SM1,P6 */
        {I_CMOVNZ, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68066, 351},
    /*   2 : CMOVNZ reg64,rm64 [rm:       o64 0f 45 /r                    ] SM0-1,LONG,PROT,X86_64 */
        /* 324 355 001(45) 110 : SM0,SM1,LONG,PROT,X86_64 */
        {I_CMOVNZ, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+68162, 14},
    /*   3 : CMOVNZ reg16,reg16,rm16 [vrm:      evex.nf0.nd1.l0.m4.o16 45 /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(45) 121 : SM0,SM1,SM2,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNZ, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+15133, 352},
    /*   4 : CMOVNZ reg32,reg32,rm32 [vrm:      evex.nf0.nd1.l0.m4.o32 45 /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(45) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNZ, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+15293, 353},
    /*   5 : CMOVNZ reg64,reg64,rm64 [vrm:      evex.nf0.nd1.l0.m4.o64 45 /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(45) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVNZ, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+15453, 353},
};

static const struct itemplate instrux_CMOVO[6] = {
    /*   0 : CMOVO reg16,rm16 [rm:       o16 0f 40 /r                    ] SM0-1,P6 */
        /* 320 355 001(40) 110 : SM0,SM1,P6 */
        {I_CMOVO, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67994, 351},
    /*   1 : CMOVO reg32,rm32 [rm:       o32 0f 40 /r                    ] SM0-1,P6 */
        /* 321 355 001(40) 110 : SM0,SM1,P6 */
        {I_CMOVO, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68090, 351},
    /*   2 : CMOVO reg64,rm64 [rm:       o64 0f 40 /r                    ] SM0-1,LONG,PROT,X86_64 */
        /* 324 355 001(40) 110 : SM0,SM1,LONG,PROT,X86_64 */
        {I_CMOVO, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+68186, 14},
    /*   3 : CMOVO reg16,reg16,rm16 [vrm:      evex.nf0.nd1.l0.m4.o16 40 /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(40) 121 : SM0,SM1,SM2,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVO, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+15173, 352},
    /*   4 : CMOVO reg32,reg32,rm32 [vrm:      evex.nf0.nd1.l0.m4.o32 40 /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(40) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVO, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+15333, 353},
    /*   5 : CMOVO reg64,reg64,rm64 [vrm:      evex.nf0.nd1.l0.m4.o64 40 /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(40) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVO, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+15493, 353},
};

static const struct itemplate instrux_CMOVP[6] = {
    /*   0 : CMOVP reg16,rm16 [rm:       o16 0f 4a /r                    ] SM0-1,P6,ND */
        /* 320 355 001(4a) 110 : SM0,SM1,P6 */
        {I_CMOVP, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+68000, 351},
    /*   1 : CMOVP reg32,rm32 [rm:       o32 0f 4a /r                    ] SM0-1,P6,ND */
        /* 321 355 001(4a) 110 : SM0,SM1,P6 */
        {I_CMOVP, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68096, 351},
    /*   2 : CMOVP reg64,rm64 [rm:       o64 0f 4a /r                    ] SM0-1,LONG,PROT,X86_64,ND */
        /* 324 355 001(4a) 110 : SM0,SM1,LONG,PROT,X86_64 */
        {I_CMOVP, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+68192, 14},
    /*   3 : CMOVP reg16,reg16,rm16 [vrm:      evex.nf0.nd1.l0.m4.o16 4a /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7d 18) 300 320 001(4a) 121 : SM0,SM1,SM2,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVP, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+15183, 352},
    /*   4 : CMOVP reg32,reg32,rm32 [vrm:      evex.nf0.nd1.l0.m4.o32 4a /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7c 18) 300 321 001(4a) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVP, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+15343, 353},
    /*   5 : CMOVP reg64,reg64,rm64 [vrm:      evex.nf0.nd1.l0.m4.o64 4a /r    ] SM0-2,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 fc 18) 300 324 001(4a) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVP, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+15503, 353},
};

static const struct itemplate instrux_CMOVPE[6] = {
    /*   0 : CMOVPE reg16,rm16 [rm:       o16 0f 4a /r                    ] SM0-1,P6 */
        /* 320 355 001(4a) 110 : SM0,SM1,P6 */
        {I_CMOVPE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+68000, 351},
    /*   1 : CMOVPE reg32,rm32 [rm:       o32 0f 4a /r                    ] SM0-1,P6 */
        /* 321 355 001(4a) 110 : SM0,SM1,P6 */
        {I_CMOVPE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68096, 351},
    /*   2 : CMOVPE reg64,rm64 [rm:       o64 0f 4a /r                    ] SM0-1,LONG,PROT,X86_64 */
        /* 324 355 001(4a) 110 : SM0,SM1,LONG,PROT,X86_64 */
        {I_CMOVPE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+68192, 14},
    /*   3 : CMOVPE reg16,reg16,rm16 [vrm:      evex.nf0.nd1.l0.m4.o16 4a /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(4a) 121 : SM0,SM1,SM2,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVPE, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+15183, 352},
    /*   4 : CMOVPE reg32,reg32,rm32 [vrm:      evex.nf0.nd1.l0.m4.o32 4a /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(4a) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVPE, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+15343, 353},
    /*   5 : CMOVPE reg64,reg64,rm64 [vrm:      evex.nf0.nd1.l0.m4.o64 4a /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(4a) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVPE, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+15503, 353},
};

static const struct itemplate instrux_CMOVPO[6] = {
    /*   0 : CMOVPO reg16,rm16 [rm:       o16 0f 4b /r                    ] SM0-1,P6 */
        /* 320 355 001(4b) 110 : SM0,SM1,P6 */
        {I_CMOVPO, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67982, 351},
    /*   1 : CMOVPO reg32,rm32 [rm:       o32 0f 4b /r                    ] SM0-1,P6 */
        /* 321 355 001(4b) 110 : SM0,SM1,P6 */
        {I_CMOVPO, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68078, 351},
    /*   2 : CMOVPO reg64,rm64 [rm:       o64 0f 4b /r                    ] SM0-1,LONG,PROT,X86_64 */
        /* 324 355 001(4b) 110 : SM0,SM1,LONG,PROT,X86_64 */
        {I_CMOVPO, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+68174, 14},
    /*   3 : CMOVPO reg16,reg16,rm16 [vrm:      evex.nf0.nd1.l0.m4.o16 4b /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(4b) 121 : SM0,SM1,SM2,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVPO, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+15153, 352},
    /*   4 : CMOVPO reg32,reg32,rm32 [vrm:      evex.nf0.nd1.l0.m4.o32 4b /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(4b) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVPO, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+15313, 353},
    /*   5 : CMOVPO reg64,reg64,rm64 [vrm:      evex.nf0.nd1.l0.m4.o64 4b /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(4b) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVPO, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+15473, 353},
};

static const struct itemplate instrux_CMOVS[6] = {
    /*   0 : CMOVS reg16,rm16 [rm:       o16 0f 48 /r                    ] SM0-1,P6 */
        /* 320 355 001(48) 110 : SM0,SM1,P6 */
        {I_CMOVS, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+68006, 351},
    /*   1 : CMOVS reg32,rm32 [rm:       o32 0f 48 /r                    ] SM0-1,P6 */
        /* 321 355 001(48) 110 : SM0,SM1,P6 */
        {I_CMOVS, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68102, 351},
    /*   2 : CMOVS reg64,rm64 [rm:       o64 0f 48 /r                    ] SM0-1,LONG,PROT,X86_64 */
        /* 324 355 001(48) 110 : SM0,SM1,LONG,PROT,X86_64 */
        {I_CMOVS, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+68198, 14},
    /*   3 : CMOVS reg16,reg16,rm16 [vrm:      evex.nf0.nd1.l0.m4.o16 48 /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(48) 121 : SM0,SM1,SM2,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVS, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+15193, 352},
    /*   4 : CMOVS reg32,reg32,rm32 [vrm:      evex.nf0.nd1.l0.m4.o32 48 /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(48) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVS, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+15353, 353},
    /*   5 : CMOVS reg64,reg64,rm64 [vrm:      evex.nf0.nd1.l0.m4.o64 48 /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(48) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVS, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+15513, 353},
};

static const struct itemplate instrux_CMOVZ[6] = {
    /*   0 : CMOVZ reg16,rm16 [rm:       o16 0f 44 /r                    ] SM0-1,P6 */
        /* 320 355 001(44) 110 : SM0,SM1,P6 */
        {I_CMOVZ, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+67940, 351},
    /*   1 : CMOVZ reg32,rm32 [rm:       o32 0f 44 /r                    ] SM0-1,P6 */
        /* 321 355 001(44) 110 : SM0,SM1,P6 */
        {I_CMOVZ, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68036, 351},
    /*   2 : CMOVZ reg64,rm64 [rm:       o64 0f 44 /r                    ] SM0-1,LONG,PROT,X86_64 */
        /* 324 355 001(44) 110 : SM0,SM1,LONG,PROT,X86_64 */
        {I_CMOVZ, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+68132, 14},
    /*   3 : CMOVZ reg16,reg16,rm16 [vrm:      evex.nf0.nd1.l0.m4.o16 44 /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 18) 300 320 001(44) 121 : SM0,SM1,SM2,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVZ, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+15083, 352},
    /*   4 : CMOVZ reg32,reg32,rm32 [vrm:      evex.nf0.nd1.l0.m4.o32 44 /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 18) 300 321 001(44) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVZ, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+15243, 353},
    /*   5 : CMOVZ reg64,reg64,rm64 [vrm:      evex.nf0.nd1.l0.m4.o64 44 /r    ] SM0-2,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 18) 300 324 001(44) 121 : SM0,SM1,SM2,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CMOVZ, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+15403, 353},
};

static const struct itemplate instrux_CFCMOVA[15] = {
    /*   0 : CFCMOVA rm16,reg16 [mr:       evex.nf1.nd0.l0.m4.o16 47 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 0c) 300 320 001(47) 101 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVA, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+15523, 354},
    /*   1 : CFCMOVA rm32,reg32 [mr:       evex.nf1.nd0.l0.m4.o32 47 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 0c) 300 321 001(47) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVA, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+15683, 355},
    /*   2 : CFCMOVA rm64,reg64 [mr:       evex.nf1.nd0.l0.m4.o64 47 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 0c) 300 324 001(47) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVA, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+15843, 355},
    /*   3 : CFCMOVA reg16,rm16 [rm:       evex.nf0.nd0.l0.m4.o16 47 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(47) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVA, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16003, 354},
    /*   4 : CFCMOVA reg32,rm32 [rm:       evex.nf0.nd0.l0.m4.o32 47 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(47) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVA, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+16163, 355},
    /*   5 : CFCMOVA reg64,rm64 [rm:       evex.nf0.nd0.l0.m4.o64 47 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(47) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVA, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+16323, 355},
    /*   6 : CFCMOVA reg16?,reg16,rm16 [vrm:      evex.nf1.nd1.l0.m4.o16 47 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(47) 121 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVA, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+16483, 356},
    /*   7 : CFCMOVA reg16,rm16 [rm:      evex.nf1.nd0.l0.m4.o16 47 /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 0c) 300 320 001(47) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVA, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16643, 354},
    /*   8 : CFCMOVA reg16?,rm16 [v+rm:      evex.nf1.nd1.l0.m4.o16 47 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(47) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVA, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16803, 357},
    /*   9 : CFCMOVA reg32?,reg32,rm32 [vrm:      evex.nf1.nd1.l0.m4.o32 47 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(47) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVA, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+16963, 358},
    /*  10 : CFCMOVA reg32,rm32 [rm:      evex.nf1.nd0.l0.m4.o32 47 /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 0c) 300 321 001(47) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVA, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17123, 355},
    /*  11 : CFCMOVA reg32?,rm32 [v+rm:      evex.nf1.nd1.l0.m4.o32 47 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(47) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVA, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17283, 359},
    /*  12 : CFCMOVA reg64?,reg64,rm64 [vrm:      evex.nf1.nd1.l0.m4.o64 47 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(47) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVA, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+17443, 358},
    /*  13 : CFCMOVA reg64,rm64 [rm:      evex.nf1.nd0.l0.m4.o64 47 /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 0c) 300 324 001(47) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVA, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17603, 355},
    /*  14 : CFCMOVA reg64?,rm64 [v+rm:      evex.nf1.nd1.l0.m4.o64 47 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(47) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVA, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17763, 359},
};

static const struct itemplate instrux_CFCMOVAE[15] = {
    /*   0 : CFCMOVAE rm16,reg16 [mr:       evex.nf1.nd0.l0.m4.o16 43 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 0c) 300 320 001(43) 101 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVAE, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+15533, 354},
    /*   1 : CFCMOVAE rm32,reg32 [mr:       evex.nf1.nd0.l0.m4.o32 43 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 0c) 300 321 001(43) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVAE, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+15693, 355},
    /*   2 : CFCMOVAE rm64,reg64 [mr:       evex.nf1.nd0.l0.m4.o64 43 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 0c) 300 324 001(43) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVAE, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+15853, 355},
    /*   3 : CFCMOVAE reg16,rm16 [rm:       evex.nf0.nd0.l0.m4.o16 43 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 08) 300 320 001(43) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVAE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16013, 354},
    /*   4 : CFCMOVAE reg32,rm32 [rm:       evex.nf0.nd0.l0.m4.o32 43 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 08) 300 321 001(43) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVAE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+16173, 355},
    /*   5 : CFCMOVAE reg64,rm64 [rm:       evex.nf0.nd0.l0.m4.o64 43 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 08) 300 324 001(43) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVAE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+16333, 355},
    /*   6 : CFCMOVAE reg16?,reg16,rm16 [vrm:      evex.nf1.nd1.l0.m4.o16 43 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7d 1c) 300 320 001(43) 121 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVAE, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+16493, 356},
    /*   7 : CFCMOVAE reg16,rm16 [rm:      evex.nf1.nd0.l0.m4.o16 43 /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 0c) 300 320 001(43) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVAE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16653, 354},
    /*   8 : CFCMOVAE reg16?,rm16 [v+rm:      evex.nf1.nd1.l0.m4.o16 43 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(43) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVAE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16813, 357},
    /*   9 : CFCMOVAE reg32?,reg32,rm32 [vrm:      evex.nf1.nd1.l0.m4.o32 43 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7c 1c) 300 321 001(43) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVAE, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+16973, 358},
    /*  10 : CFCMOVAE reg32,rm32 [rm:      evex.nf1.nd0.l0.m4.o32 43 /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 0c) 300 321 001(43) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVAE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17133, 355},
    /*  11 : CFCMOVAE reg32?,rm32 [v+rm:      evex.nf1.nd1.l0.m4.o32 43 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(43) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVAE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17293, 359},
    /*  12 : CFCMOVAE reg64?,reg64,rm64 [vrm:      evex.nf1.nd1.l0.m4.o64 43 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 fc 1c) 300 324 001(43) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVAE, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+17453, 358},
    /*  13 : CFCMOVAE reg64,rm64 [rm:      evex.nf1.nd0.l0.m4.o64 43 /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 0c) 300 324 001(43) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVAE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17613, 355},
    /*  14 : CFCMOVAE reg64?,rm64 [v+rm:      evex.nf1.nd1.l0.m4.o64 43 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(43) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVAE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17773, 359},
};

static const struct itemplate instrux_CFCMOVB[15] = {
    /*   0 : CFCMOVB rm16,reg16 [mr:       evex.nf1.nd0.l0.m4.o16 42 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 0c) 300 320 001(42) 101 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVB, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+15543, 354},
    /*   1 : CFCMOVB rm32,reg32 [mr:       evex.nf1.nd0.l0.m4.o32 42 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 0c) 300 321 001(42) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVB, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+15703, 355},
    /*   2 : CFCMOVB rm64,reg64 [mr:       evex.nf1.nd0.l0.m4.o64 42 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 0c) 300 324 001(42) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVB, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+15863, 355},
    /*   3 : CFCMOVB reg16,rm16 [rm:       evex.nf0.nd0.l0.m4.o16 42 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 08) 300 320 001(42) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVB, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16023, 354},
    /*   4 : CFCMOVB reg32,rm32 [rm:       evex.nf0.nd0.l0.m4.o32 42 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 08) 300 321 001(42) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVB, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+16183, 355},
    /*   5 : CFCMOVB reg64,rm64 [rm:       evex.nf0.nd0.l0.m4.o64 42 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 08) 300 324 001(42) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVB, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+16343, 355},
    /*   6 : CFCMOVB reg16?,reg16,rm16 [vrm:      evex.nf1.nd1.l0.m4.o16 42 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7d 1c) 300 320 001(42) 121 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVB, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+16503, 356},
    /*   7 : CFCMOVB reg16,rm16 [rm:      evex.nf1.nd0.l0.m4.o16 42 /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 0c) 300 320 001(42) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVB, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16663, 354},
    /*   8 : CFCMOVB reg16?,rm16 [v+rm:      evex.nf1.nd1.l0.m4.o16 42 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(42) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVB, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16823, 357},
    /*   9 : CFCMOVB reg32?,reg32,rm32 [vrm:      evex.nf1.nd1.l0.m4.o32 42 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7c 1c) 300 321 001(42) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVB, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+16983, 358},
    /*  10 : CFCMOVB reg32,rm32 [rm:      evex.nf1.nd0.l0.m4.o32 42 /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 0c) 300 321 001(42) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVB, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17143, 355},
    /*  11 : CFCMOVB reg32?,rm32 [v+rm:      evex.nf1.nd1.l0.m4.o32 42 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(42) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVB, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17303, 359},
    /*  12 : CFCMOVB reg64?,reg64,rm64 [vrm:      evex.nf1.nd1.l0.m4.o64 42 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 fc 1c) 300 324 001(42) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVB, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+17463, 358},
    /*  13 : CFCMOVB reg64,rm64 [rm:      evex.nf1.nd0.l0.m4.o64 42 /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 0c) 300 324 001(42) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVB, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17623, 355},
    /*  14 : CFCMOVB reg64?,rm64 [v+rm:      evex.nf1.nd1.l0.m4.o64 42 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(42) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVB, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17783, 359},
};

static const struct itemplate instrux_CFCMOVBE[15] = {
    /*   0 : CFCMOVBE rm16,reg16 [mr:       evex.nf1.nd0.l0.m4.o16 46 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 0c) 300 320 001(46) 101 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVBE, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+15553, 354},
    /*   1 : CFCMOVBE rm32,reg32 [mr:       evex.nf1.nd0.l0.m4.o32 46 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 0c) 300 321 001(46) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVBE, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+15713, 355},
    /*   2 : CFCMOVBE rm64,reg64 [mr:       evex.nf1.nd0.l0.m4.o64 46 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 0c) 300 324 001(46) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVBE, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+15873, 355},
    /*   3 : CFCMOVBE reg16,rm16 [rm:       evex.nf0.nd0.l0.m4.o16 46 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 08) 300 320 001(46) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVBE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16033, 354},
    /*   4 : CFCMOVBE reg32,rm32 [rm:       evex.nf0.nd0.l0.m4.o32 46 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 08) 300 321 001(46) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVBE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+16193, 355},
    /*   5 : CFCMOVBE reg64,rm64 [rm:       evex.nf0.nd0.l0.m4.o64 46 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 08) 300 324 001(46) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVBE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+16353, 355},
    /*   6 : CFCMOVBE reg16?,reg16,rm16 [vrm:      evex.nf1.nd1.l0.m4.o16 46 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7d 1c) 300 320 001(46) 121 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVBE, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+16513, 356},
    /*   7 : CFCMOVBE reg16,rm16 [rm:      evex.nf1.nd0.l0.m4.o16 46 /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 0c) 300 320 001(46) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVBE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16673, 354},
    /*   8 : CFCMOVBE reg16?,rm16 [v+rm:      evex.nf1.nd1.l0.m4.o16 46 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(46) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVBE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16833, 357},
    /*   9 : CFCMOVBE reg32?,reg32,rm32 [vrm:      evex.nf1.nd1.l0.m4.o32 46 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7c 1c) 300 321 001(46) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVBE, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+16993, 358},
    /*  10 : CFCMOVBE reg32,rm32 [rm:      evex.nf1.nd0.l0.m4.o32 46 /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 0c) 300 321 001(46) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVBE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17153, 355},
    /*  11 : CFCMOVBE reg32?,rm32 [v+rm:      evex.nf1.nd1.l0.m4.o32 46 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(46) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVBE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17313, 359},
    /*  12 : CFCMOVBE reg64?,reg64,rm64 [vrm:      evex.nf1.nd1.l0.m4.o64 46 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 fc 1c) 300 324 001(46) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVBE, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+17473, 358},
    /*  13 : CFCMOVBE reg64,rm64 [rm:      evex.nf1.nd0.l0.m4.o64 46 /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 0c) 300 324 001(46) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVBE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17633, 355},
    /*  14 : CFCMOVBE reg64?,rm64 [v+rm:      evex.nf1.nd1.l0.m4.o64 46 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(46) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVBE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17793, 359},
};

static const struct itemplate instrux_CFCMOVC[15] = {
    /*   0 : CFCMOVC rm16,reg16 [mr:       evex.nf1.nd0.l0.m4.o16 42 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 0c) 300 320 001(42) 101 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVC, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+15543, 354},
    /*   1 : CFCMOVC rm32,reg32 [mr:       evex.nf1.nd0.l0.m4.o32 42 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 0c) 300 321 001(42) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVC, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+15703, 355},
    /*   2 : CFCMOVC rm64,reg64 [mr:       evex.nf1.nd0.l0.m4.o64 42 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 0c) 300 324 001(42) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVC, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+15863, 355},
    /*   3 : CFCMOVC reg16,rm16 [rm:       evex.nf0.nd0.l0.m4.o16 42 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(42) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVC, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16023, 354},
    /*   4 : CFCMOVC reg32,rm32 [rm:       evex.nf0.nd0.l0.m4.o32 42 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(42) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVC, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+16183, 355},
    /*   5 : CFCMOVC reg64,rm64 [rm:       evex.nf0.nd0.l0.m4.o64 42 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(42) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVC, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+16343, 355},
    /*   6 : CFCMOVC reg16?,reg16,rm16 [vrm:      evex.nf1.nd1.l0.m4.o16 42 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(42) 121 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVC, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+16503, 356},
    /*   7 : CFCMOVC reg16,rm16 [rm:      evex.nf1.nd0.l0.m4.o16 42 /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 0c) 300 320 001(42) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVC, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16663, 354},
    /*   8 : CFCMOVC reg16?,rm16 [v+rm:      evex.nf1.nd1.l0.m4.o16 42 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(42) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVC, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16823, 357},
    /*   9 : CFCMOVC reg32?,reg32,rm32 [vrm:      evex.nf1.nd1.l0.m4.o32 42 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(42) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVC, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+16983, 358},
    /*  10 : CFCMOVC reg32,rm32 [rm:      evex.nf1.nd0.l0.m4.o32 42 /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 0c) 300 321 001(42) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVC, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17143, 355},
    /*  11 : CFCMOVC reg32?,rm32 [v+rm:      evex.nf1.nd1.l0.m4.o32 42 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(42) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVC, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17303, 359},
    /*  12 : CFCMOVC reg64?,reg64,rm64 [vrm:      evex.nf1.nd1.l0.m4.o64 42 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(42) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVC, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+17463, 358},
    /*  13 : CFCMOVC reg64,rm64 [rm:      evex.nf1.nd0.l0.m4.o64 42 /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 0c) 300 324 001(42) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVC, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17623, 355},
    /*  14 : CFCMOVC reg64?,rm64 [v+rm:      evex.nf1.nd1.l0.m4.o64 42 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(42) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVC, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17783, 359},
};

static const struct itemplate instrux_CFCMOVE[15] = {
    /*   0 : CFCMOVE rm16,reg16 [mr:       evex.nf1.nd0.l0.m4.o16 44 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 0c) 300 320 001(44) 101 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVE, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+15563, 354},
    /*   1 : CFCMOVE rm32,reg32 [mr:       evex.nf1.nd0.l0.m4.o32 44 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 0c) 300 321 001(44) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVE, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+15723, 355},
    /*   2 : CFCMOVE rm64,reg64 [mr:       evex.nf1.nd0.l0.m4.o64 44 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 0c) 300 324 001(44) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVE, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+15883, 355},
    /*   3 : CFCMOVE reg16,rm16 [rm:       evex.nf0.nd0.l0.m4.o16 44 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 08) 300 320 001(44) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16043, 354},
    /*   4 : CFCMOVE reg32,rm32 [rm:       evex.nf0.nd0.l0.m4.o32 44 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 08) 300 321 001(44) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+16203, 355},
    /*   5 : CFCMOVE reg64,rm64 [rm:       evex.nf0.nd0.l0.m4.o64 44 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 08) 300 324 001(44) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+16363, 355},
    /*   6 : CFCMOVE reg16?,reg16,rm16 [vrm:      evex.nf1.nd1.l0.m4.o16 44 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7d 1c) 300 320 001(44) 121 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVE, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+16523, 356},
    /*   7 : CFCMOVE reg16,rm16 [rm:      evex.nf1.nd0.l0.m4.o16 44 /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 0c) 300 320 001(44) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16683, 354},
    /*   8 : CFCMOVE reg16?,rm16 [v+rm:      evex.nf1.nd1.l0.m4.o16 44 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(44) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16843, 357},
    /*   9 : CFCMOVE reg32?,reg32,rm32 [vrm:      evex.nf1.nd1.l0.m4.o32 44 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7c 1c) 300 321 001(44) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVE, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+17003, 358},
    /*  10 : CFCMOVE reg32,rm32 [rm:      evex.nf1.nd0.l0.m4.o32 44 /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 0c) 300 321 001(44) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17163, 355},
    /*  11 : CFCMOVE reg32?,rm32 [v+rm:      evex.nf1.nd1.l0.m4.o32 44 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(44) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17323, 359},
    /*  12 : CFCMOVE reg64?,reg64,rm64 [vrm:      evex.nf1.nd1.l0.m4.o64 44 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 fc 1c) 300 324 001(44) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVE, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+17483, 358},
    /*  13 : CFCMOVE reg64,rm64 [rm:      evex.nf1.nd0.l0.m4.o64 44 /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 0c) 300 324 001(44) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17643, 355},
    /*  14 : CFCMOVE reg64?,rm64 [v+rm:      evex.nf1.nd1.l0.m4.o64 44 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(44) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17803, 359},
};

static const struct itemplate instrux_CFCMOVG[15] = {
    /*   0 : CFCMOVG rm16,reg16 [mr:       evex.nf1.nd0.l0.m4.o16 4f /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 0c) 300 320 001(4f) 101 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVG, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+15573, 354},
    /*   1 : CFCMOVG rm32,reg32 [mr:       evex.nf1.nd0.l0.m4.o32 4f /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 0c) 300 321 001(4f) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVG, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+15733, 355},
    /*   2 : CFCMOVG rm64,reg64 [mr:       evex.nf1.nd0.l0.m4.o64 4f /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 0c) 300 324 001(4f) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVG, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+15893, 355},
    /*   3 : CFCMOVG reg16,rm16 [rm:       evex.nf0.nd0.l0.m4.o16 4f /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(4f) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVG, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16053, 354},
    /*   4 : CFCMOVG reg32,rm32 [rm:       evex.nf0.nd0.l0.m4.o32 4f /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(4f) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVG, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+16213, 355},
    /*   5 : CFCMOVG reg64,rm64 [rm:       evex.nf0.nd0.l0.m4.o64 4f /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(4f) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVG, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+16373, 355},
    /*   6 : CFCMOVG reg16?,reg16,rm16 [vrm:      evex.nf1.nd1.l0.m4.o16 4f /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(4f) 121 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVG, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+16533, 356},
    /*   7 : CFCMOVG reg16,rm16 [rm:      evex.nf1.nd0.l0.m4.o16 4f /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 0c) 300 320 001(4f) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVG, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16693, 354},
    /*   8 : CFCMOVG reg16?,rm16 [v+rm:      evex.nf1.nd1.l0.m4.o16 4f /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(4f) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVG, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16853, 357},
    /*   9 : CFCMOVG reg32?,reg32,rm32 [vrm:      evex.nf1.nd1.l0.m4.o32 4f /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(4f) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVG, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+17013, 358},
    /*  10 : CFCMOVG reg32,rm32 [rm:      evex.nf1.nd0.l0.m4.o32 4f /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 0c) 300 321 001(4f) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVG, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17173, 355},
    /*  11 : CFCMOVG reg32?,rm32 [v+rm:      evex.nf1.nd1.l0.m4.o32 4f /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(4f) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVG, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17333, 359},
    /*  12 : CFCMOVG reg64?,reg64,rm64 [vrm:      evex.nf1.nd1.l0.m4.o64 4f /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(4f) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVG, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+17493, 358},
    /*  13 : CFCMOVG reg64,rm64 [rm:      evex.nf1.nd0.l0.m4.o64 4f /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 0c) 300 324 001(4f) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVG, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17653, 355},
    /*  14 : CFCMOVG reg64?,rm64 [v+rm:      evex.nf1.nd1.l0.m4.o64 4f /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(4f) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVG, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17813, 359},
};

static const struct itemplate instrux_CFCMOVGE[15] = {
    /*   0 : CFCMOVGE rm16,reg16 [mr:       evex.nf1.nd0.l0.m4.o16 4d /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 0c) 300 320 001(4d) 101 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVGE, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+15583, 354},
    /*   1 : CFCMOVGE rm32,reg32 [mr:       evex.nf1.nd0.l0.m4.o32 4d /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 0c) 300 321 001(4d) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVGE, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+15743, 355},
    /*   2 : CFCMOVGE rm64,reg64 [mr:       evex.nf1.nd0.l0.m4.o64 4d /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 0c) 300 324 001(4d) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVGE, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+15903, 355},
    /*   3 : CFCMOVGE reg16,rm16 [rm:       evex.nf0.nd0.l0.m4.o16 4d /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 08) 300 320 001(4d) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVGE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16063, 354},
    /*   4 : CFCMOVGE reg32,rm32 [rm:       evex.nf0.nd0.l0.m4.o32 4d /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 08) 300 321 001(4d) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVGE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+16223, 355},
    /*   5 : CFCMOVGE reg64,rm64 [rm:       evex.nf0.nd0.l0.m4.o64 4d /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 08) 300 324 001(4d) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVGE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+16383, 355},
    /*   6 : CFCMOVGE reg16?,reg16,rm16 [vrm:      evex.nf1.nd1.l0.m4.o16 4d /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7d 1c) 300 320 001(4d) 121 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVGE, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+16543, 356},
    /*   7 : CFCMOVGE reg16,rm16 [rm:      evex.nf1.nd0.l0.m4.o16 4d /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 0c) 300 320 001(4d) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVGE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16703, 354},
    /*   8 : CFCMOVGE reg16?,rm16 [v+rm:      evex.nf1.nd1.l0.m4.o16 4d /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(4d) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVGE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16863, 357},
    /*   9 : CFCMOVGE reg32?,reg32,rm32 [vrm:      evex.nf1.nd1.l0.m4.o32 4d /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7c 1c) 300 321 001(4d) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVGE, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+17023, 358},
    /*  10 : CFCMOVGE reg32,rm32 [rm:      evex.nf1.nd0.l0.m4.o32 4d /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 0c) 300 321 001(4d) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVGE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17183, 355},
    /*  11 : CFCMOVGE reg32?,rm32 [v+rm:      evex.nf1.nd1.l0.m4.o32 4d /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(4d) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVGE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17343, 359},
    /*  12 : CFCMOVGE reg64?,reg64,rm64 [vrm:      evex.nf1.nd1.l0.m4.o64 4d /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 fc 1c) 300 324 001(4d) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVGE, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+17503, 358},
    /*  13 : CFCMOVGE reg64,rm64 [rm:      evex.nf1.nd0.l0.m4.o64 4d /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 0c) 300 324 001(4d) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVGE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17663, 355},
    /*  14 : CFCMOVGE reg64?,rm64 [v+rm:      evex.nf1.nd1.l0.m4.o64 4d /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(4d) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVGE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17823, 359},
};

static const struct itemplate instrux_CFCMOVL[15] = {
    /*   0 : CFCMOVL rm16,reg16 [mr:       evex.nf1.nd0.l0.m4.o16 4c /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 0c) 300 320 001(4c) 101 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVL, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+15593, 354},
    /*   1 : CFCMOVL rm32,reg32 [mr:       evex.nf1.nd0.l0.m4.o32 4c /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 0c) 300 321 001(4c) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVL, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+15753, 355},
    /*   2 : CFCMOVL rm64,reg64 [mr:       evex.nf1.nd0.l0.m4.o64 4c /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 0c) 300 324 001(4c) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVL, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+15913, 355},
    /*   3 : CFCMOVL reg16,rm16 [rm:       evex.nf0.nd0.l0.m4.o16 4c /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(4c) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVL, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16073, 354},
    /*   4 : CFCMOVL reg32,rm32 [rm:       evex.nf0.nd0.l0.m4.o32 4c /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(4c) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVL, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+16233, 355},
    /*   5 : CFCMOVL reg64,rm64 [rm:       evex.nf0.nd0.l0.m4.o64 4c /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(4c) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVL, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+16393, 355},
    /*   6 : CFCMOVL reg16?,reg16,rm16 [vrm:      evex.nf1.nd1.l0.m4.o16 4c /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(4c) 121 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVL, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+16553, 356},
    /*   7 : CFCMOVL reg16,rm16 [rm:      evex.nf1.nd0.l0.m4.o16 4c /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 0c) 300 320 001(4c) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVL, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16713, 354},
    /*   8 : CFCMOVL reg16?,rm16 [v+rm:      evex.nf1.nd1.l0.m4.o16 4c /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(4c) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVL, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16873, 357},
    /*   9 : CFCMOVL reg32?,reg32,rm32 [vrm:      evex.nf1.nd1.l0.m4.o32 4c /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(4c) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVL, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+17033, 358},
    /*  10 : CFCMOVL reg32,rm32 [rm:      evex.nf1.nd0.l0.m4.o32 4c /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 0c) 300 321 001(4c) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVL, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17193, 355},
    /*  11 : CFCMOVL reg32?,rm32 [v+rm:      evex.nf1.nd1.l0.m4.o32 4c /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(4c) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVL, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17353, 359},
    /*  12 : CFCMOVL reg64?,reg64,rm64 [vrm:      evex.nf1.nd1.l0.m4.o64 4c /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(4c) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVL, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+17513, 358},
    /*  13 : CFCMOVL reg64,rm64 [rm:      evex.nf1.nd0.l0.m4.o64 4c /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 0c) 300 324 001(4c) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVL, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17673, 355},
    /*  14 : CFCMOVL reg64?,rm64 [v+rm:      evex.nf1.nd1.l0.m4.o64 4c /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(4c) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVL, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17833, 359},
};

static const struct itemplate instrux_CFCMOVLE[15] = {
    /*   0 : CFCMOVLE rm16,reg16 [mr:       evex.nf1.nd0.l0.m4.o16 4e /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 0c) 300 320 001(4e) 101 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVLE, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+15603, 354},
    /*   1 : CFCMOVLE rm32,reg32 [mr:       evex.nf1.nd0.l0.m4.o32 4e /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 0c) 300 321 001(4e) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVLE, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+15763, 355},
    /*   2 : CFCMOVLE rm64,reg64 [mr:       evex.nf1.nd0.l0.m4.o64 4e /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 0c) 300 324 001(4e) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVLE, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+15923, 355},
    /*   3 : CFCMOVLE reg16,rm16 [rm:       evex.nf0.nd0.l0.m4.o16 4e /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 08) 300 320 001(4e) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVLE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16083, 354},
    /*   4 : CFCMOVLE reg32,rm32 [rm:       evex.nf0.nd0.l0.m4.o32 4e /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 08) 300 321 001(4e) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVLE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+16243, 355},
    /*   5 : CFCMOVLE reg64,rm64 [rm:       evex.nf0.nd0.l0.m4.o64 4e /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 08) 300 324 001(4e) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVLE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+16403, 355},
    /*   6 : CFCMOVLE reg16?,reg16,rm16 [vrm:      evex.nf1.nd1.l0.m4.o16 4e /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7d 1c) 300 320 001(4e) 121 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVLE, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+16563, 356},
    /*   7 : CFCMOVLE reg16,rm16 [rm:      evex.nf1.nd0.l0.m4.o16 4e /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 0c) 300 320 001(4e) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVLE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16723, 354},
    /*   8 : CFCMOVLE reg16?,rm16 [v+rm:      evex.nf1.nd1.l0.m4.o16 4e /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(4e) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVLE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16883, 357},
    /*   9 : CFCMOVLE reg32?,reg32,rm32 [vrm:      evex.nf1.nd1.l0.m4.o32 4e /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7c 1c) 300 321 001(4e) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVLE, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+17043, 358},
    /*  10 : CFCMOVLE reg32,rm32 [rm:      evex.nf1.nd0.l0.m4.o32 4e /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 0c) 300 321 001(4e) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVLE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17203, 355},
    /*  11 : CFCMOVLE reg32?,rm32 [v+rm:      evex.nf1.nd1.l0.m4.o32 4e /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(4e) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVLE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17363, 359},
    /*  12 : CFCMOVLE reg64?,reg64,rm64 [vrm:      evex.nf1.nd1.l0.m4.o64 4e /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 fc 1c) 300 324 001(4e) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVLE, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+17523, 358},
    /*  13 : CFCMOVLE reg64,rm64 [rm:      evex.nf1.nd0.l0.m4.o64 4e /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 0c) 300 324 001(4e) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVLE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17683, 355},
    /*  14 : CFCMOVLE reg64?,rm64 [v+rm:      evex.nf1.nd1.l0.m4.o64 4e /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(4e) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVLE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17843, 359},
};

static const struct itemplate instrux_CFCMOVNA[15] = {
    /*   0 : CFCMOVNA rm16,reg16 [mr:       evex.nf1.nd0.l0.m4.o16 46 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 0c) 300 320 001(46) 101 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNA, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+15553, 354},
    /*   1 : CFCMOVNA rm32,reg32 [mr:       evex.nf1.nd0.l0.m4.o32 46 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 0c) 300 321 001(46) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNA, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+15713, 355},
    /*   2 : CFCMOVNA rm64,reg64 [mr:       evex.nf1.nd0.l0.m4.o64 46 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 0c) 300 324 001(46) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNA, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+15873, 355},
    /*   3 : CFCMOVNA reg16,rm16 [rm:       evex.nf0.nd0.l0.m4.o16 46 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(46) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNA, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16033, 354},
    /*   4 : CFCMOVNA reg32,rm32 [rm:       evex.nf0.nd0.l0.m4.o32 46 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(46) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNA, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+16193, 355},
    /*   5 : CFCMOVNA reg64,rm64 [rm:       evex.nf0.nd0.l0.m4.o64 46 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(46) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNA, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+16353, 355},
    /*   6 : CFCMOVNA reg16?,reg16,rm16 [vrm:      evex.nf1.nd1.l0.m4.o16 46 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(46) 121 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNA, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+16513, 356},
    /*   7 : CFCMOVNA reg16,rm16 [rm:      evex.nf1.nd0.l0.m4.o16 46 /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 0c) 300 320 001(46) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNA, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16673, 354},
    /*   8 : CFCMOVNA reg16?,rm16 [v+rm:      evex.nf1.nd1.l0.m4.o16 46 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(46) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNA, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16833, 357},
    /*   9 : CFCMOVNA reg32?,reg32,rm32 [vrm:      evex.nf1.nd1.l0.m4.o32 46 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(46) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNA, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+16993, 358},
    /*  10 : CFCMOVNA reg32,rm32 [rm:      evex.nf1.nd0.l0.m4.o32 46 /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 0c) 300 321 001(46) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNA, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17153, 355},
    /*  11 : CFCMOVNA reg32?,rm32 [v+rm:      evex.nf1.nd1.l0.m4.o32 46 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(46) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNA, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17313, 359},
    /*  12 : CFCMOVNA reg64?,reg64,rm64 [vrm:      evex.nf1.nd1.l0.m4.o64 46 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(46) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNA, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+17473, 358},
    /*  13 : CFCMOVNA reg64,rm64 [rm:      evex.nf1.nd0.l0.m4.o64 46 /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 0c) 300 324 001(46) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNA, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17633, 355},
    /*  14 : CFCMOVNA reg64?,rm64 [v+rm:      evex.nf1.nd1.l0.m4.o64 46 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(46) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNA, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17793, 359},
};

static const struct itemplate instrux_CFCMOVNAE[15] = {
    /*   0 : CFCMOVNAE rm16,reg16 [mr:       evex.nf1.nd0.l0.m4.o16 42 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 0c) 300 320 001(42) 101 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNAE, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+15543, 354},
    /*   1 : CFCMOVNAE rm32,reg32 [mr:       evex.nf1.nd0.l0.m4.o32 42 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 0c) 300 321 001(42) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNAE, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+15703, 355},
    /*   2 : CFCMOVNAE rm64,reg64 [mr:       evex.nf1.nd0.l0.m4.o64 42 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 0c) 300 324 001(42) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNAE, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+15863, 355},
    /*   3 : CFCMOVNAE reg16,rm16 [rm:       evex.nf0.nd0.l0.m4.o16 42 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 08) 300 320 001(42) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNAE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16023, 354},
    /*   4 : CFCMOVNAE reg32,rm32 [rm:       evex.nf0.nd0.l0.m4.o32 42 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 08) 300 321 001(42) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNAE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+16183, 355},
    /*   5 : CFCMOVNAE reg64,rm64 [rm:       evex.nf0.nd0.l0.m4.o64 42 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 08) 300 324 001(42) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNAE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+16343, 355},
    /*   6 : CFCMOVNAE reg16?,reg16,rm16 [vrm:      evex.nf1.nd1.l0.m4.o16 42 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7d 1c) 300 320 001(42) 121 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNAE, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+16503, 356},
    /*   7 : CFCMOVNAE reg16,rm16 [rm:      evex.nf1.nd0.l0.m4.o16 42 /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 0c) 300 320 001(42) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNAE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16663, 354},
    /*   8 : CFCMOVNAE reg16?,rm16 [v+rm:      evex.nf1.nd1.l0.m4.o16 42 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(42) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNAE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16823, 357},
    /*   9 : CFCMOVNAE reg32?,reg32,rm32 [vrm:      evex.nf1.nd1.l0.m4.o32 42 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7c 1c) 300 321 001(42) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNAE, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+16983, 358},
    /*  10 : CFCMOVNAE reg32,rm32 [rm:      evex.nf1.nd0.l0.m4.o32 42 /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 0c) 300 321 001(42) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNAE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17143, 355},
    /*  11 : CFCMOVNAE reg32?,rm32 [v+rm:      evex.nf1.nd1.l0.m4.o32 42 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(42) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNAE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17303, 359},
    /*  12 : CFCMOVNAE reg64?,reg64,rm64 [vrm:      evex.nf1.nd1.l0.m4.o64 42 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 fc 1c) 300 324 001(42) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNAE, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+17463, 358},
    /*  13 : CFCMOVNAE reg64,rm64 [rm:      evex.nf1.nd0.l0.m4.o64 42 /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 0c) 300 324 001(42) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNAE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17623, 355},
    /*  14 : CFCMOVNAE reg64?,rm64 [v+rm:      evex.nf1.nd1.l0.m4.o64 42 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(42) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNAE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17783, 359},
};

static const struct itemplate instrux_CFCMOVNB[15] = {
    /*   0 : CFCMOVNB rm16,reg16 [mr:       evex.nf1.nd0.l0.m4.o16 43 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 0c) 300 320 001(43) 101 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNB, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+15533, 354},
    /*   1 : CFCMOVNB rm32,reg32 [mr:       evex.nf1.nd0.l0.m4.o32 43 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 0c) 300 321 001(43) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNB, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+15693, 355},
    /*   2 : CFCMOVNB rm64,reg64 [mr:       evex.nf1.nd0.l0.m4.o64 43 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 0c) 300 324 001(43) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNB, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+15853, 355},
    /*   3 : CFCMOVNB reg16,rm16 [rm:       evex.nf0.nd0.l0.m4.o16 43 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 08) 300 320 001(43) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNB, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16013, 354},
    /*   4 : CFCMOVNB reg32,rm32 [rm:       evex.nf0.nd0.l0.m4.o32 43 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 08) 300 321 001(43) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNB, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+16173, 355},
    /*   5 : CFCMOVNB reg64,rm64 [rm:       evex.nf0.nd0.l0.m4.o64 43 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 08) 300 324 001(43) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNB, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+16333, 355},
    /*   6 : CFCMOVNB reg16?,reg16,rm16 [vrm:      evex.nf1.nd1.l0.m4.o16 43 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7d 1c) 300 320 001(43) 121 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNB, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+16493, 356},
    /*   7 : CFCMOVNB reg16,rm16 [rm:      evex.nf1.nd0.l0.m4.o16 43 /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 0c) 300 320 001(43) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNB, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16653, 354},
    /*   8 : CFCMOVNB reg16?,rm16 [v+rm:      evex.nf1.nd1.l0.m4.o16 43 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(43) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNB, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16813, 357},
    /*   9 : CFCMOVNB reg32?,reg32,rm32 [vrm:      evex.nf1.nd1.l0.m4.o32 43 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7c 1c) 300 321 001(43) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNB, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+16973, 358},
    /*  10 : CFCMOVNB reg32,rm32 [rm:      evex.nf1.nd0.l0.m4.o32 43 /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 0c) 300 321 001(43) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNB, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17133, 355},
    /*  11 : CFCMOVNB reg32?,rm32 [v+rm:      evex.nf1.nd1.l0.m4.o32 43 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(43) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNB, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17293, 359},
    /*  12 : CFCMOVNB reg64?,reg64,rm64 [vrm:      evex.nf1.nd1.l0.m4.o64 43 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 fc 1c) 300 324 001(43) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNB, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+17453, 358},
    /*  13 : CFCMOVNB reg64,rm64 [rm:      evex.nf1.nd0.l0.m4.o64 43 /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 0c) 300 324 001(43) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNB, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17613, 355},
    /*  14 : CFCMOVNB reg64?,rm64 [v+rm:      evex.nf1.nd1.l0.m4.o64 43 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(43) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNB, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17773, 359},
};

static const struct itemplate instrux_CFCMOVNBE[15] = {
    /*   0 : CFCMOVNBE rm16,reg16 [mr:       evex.nf1.nd0.l0.m4.o16 47 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 0c) 300 320 001(47) 101 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNBE, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+15523, 354},
    /*   1 : CFCMOVNBE rm32,reg32 [mr:       evex.nf1.nd0.l0.m4.o32 47 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 0c) 300 321 001(47) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNBE, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+15683, 355},
    /*   2 : CFCMOVNBE rm64,reg64 [mr:       evex.nf1.nd0.l0.m4.o64 47 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 0c) 300 324 001(47) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNBE, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+15843, 355},
    /*   3 : CFCMOVNBE reg16,rm16 [rm:       evex.nf0.nd0.l0.m4.o16 47 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 08) 300 320 001(47) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNBE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16003, 354},
    /*   4 : CFCMOVNBE reg32,rm32 [rm:       evex.nf0.nd0.l0.m4.o32 47 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 08) 300 321 001(47) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNBE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+16163, 355},
    /*   5 : CFCMOVNBE reg64,rm64 [rm:       evex.nf0.nd0.l0.m4.o64 47 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 08) 300 324 001(47) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNBE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+16323, 355},
    /*   6 : CFCMOVNBE reg16?,reg16,rm16 [vrm:      evex.nf1.nd1.l0.m4.o16 47 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7d 1c) 300 320 001(47) 121 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNBE, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+16483, 356},
    /*   7 : CFCMOVNBE reg16,rm16 [rm:      evex.nf1.nd0.l0.m4.o16 47 /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 0c) 300 320 001(47) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNBE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16643, 354},
    /*   8 : CFCMOVNBE reg16?,rm16 [v+rm:      evex.nf1.nd1.l0.m4.o16 47 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(47) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNBE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16803, 357},
    /*   9 : CFCMOVNBE reg32?,reg32,rm32 [vrm:      evex.nf1.nd1.l0.m4.o32 47 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7c 1c) 300 321 001(47) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNBE, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+16963, 358},
    /*  10 : CFCMOVNBE reg32,rm32 [rm:      evex.nf1.nd0.l0.m4.o32 47 /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 0c) 300 321 001(47) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNBE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17123, 355},
    /*  11 : CFCMOVNBE reg32?,rm32 [v+rm:      evex.nf1.nd1.l0.m4.o32 47 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(47) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNBE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17283, 359},
    /*  12 : CFCMOVNBE reg64?,reg64,rm64 [vrm:      evex.nf1.nd1.l0.m4.o64 47 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 fc 1c) 300 324 001(47) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNBE, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+17443, 358},
    /*  13 : CFCMOVNBE reg64,rm64 [rm:      evex.nf1.nd0.l0.m4.o64 47 /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 0c) 300 324 001(47) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNBE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17603, 355},
    /*  14 : CFCMOVNBE reg64?,rm64 [v+rm:      evex.nf1.nd1.l0.m4.o64 47 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(47) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNBE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17763, 359},
};

static const struct itemplate instrux_CFCMOVNC[15] = {
    /*   0 : CFCMOVNC rm16,reg16 [mr:       evex.nf1.nd0.l0.m4.o16 43 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 0c) 300 320 001(43) 101 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNC, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+15533, 354},
    /*   1 : CFCMOVNC rm32,reg32 [mr:       evex.nf1.nd0.l0.m4.o32 43 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 0c) 300 321 001(43) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNC, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+15693, 355},
    /*   2 : CFCMOVNC rm64,reg64 [mr:       evex.nf1.nd0.l0.m4.o64 43 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 0c) 300 324 001(43) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNC, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+15853, 355},
    /*   3 : CFCMOVNC reg16,rm16 [rm:       evex.nf0.nd0.l0.m4.o16 43 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(43) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNC, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16013, 354},
    /*   4 : CFCMOVNC reg32,rm32 [rm:       evex.nf0.nd0.l0.m4.o32 43 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(43) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNC, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+16173, 355},
    /*   5 : CFCMOVNC reg64,rm64 [rm:       evex.nf0.nd0.l0.m4.o64 43 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(43) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNC, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+16333, 355},
    /*   6 : CFCMOVNC reg16?,reg16,rm16 [vrm:      evex.nf1.nd1.l0.m4.o16 43 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(43) 121 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNC, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+16493, 356},
    /*   7 : CFCMOVNC reg16,rm16 [rm:      evex.nf1.nd0.l0.m4.o16 43 /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 0c) 300 320 001(43) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNC, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16653, 354},
    /*   8 : CFCMOVNC reg16?,rm16 [v+rm:      evex.nf1.nd1.l0.m4.o16 43 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(43) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNC, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16813, 357},
    /*   9 : CFCMOVNC reg32?,reg32,rm32 [vrm:      evex.nf1.nd1.l0.m4.o32 43 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(43) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNC, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+16973, 358},
    /*  10 : CFCMOVNC reg32,rm32 [rm:      evex.nf1.nd0.l0.m4.o32 43 /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 0c) 300 321 001(43) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNC, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17133, 355},
    /*  11 : CFCMOVNC reg32?,rm32 [v+rm:      evex.nf1.nd1.l0.m4.o32 43 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(43) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNC, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17293, 359},
    /*  12 : CFCMOVNC reg64?,reg64,rm64 [vrm:      evex.nf1.nd1.l0.m4.o64 43 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(43) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNC, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+17453, 358},
    /*  13 : CFCMOVNC reg64,rm64 [rm:      evex.nf1.nd0.l0.m4.o64 43 /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 0c) 300 324 001(43) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNC, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17613, 355},
    /*  14 : CFCMOVNC reg64?,rm64 [v+rm:      evex.nf1.nd1.l0.m4.o64 43 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(43) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNC, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17773, 359},
};

static const struct itemplate instrux_CFCMOVNE[15] = {
    /*   0 : CFCMOVNE rm16,reg16 [mr:       evex.nf1.nd0.l0.m4.o16 45 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 0c) 300 320 001(45) 101 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNE, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+15613, 354},
    /*   1 : CFCMOVNE rm32,reg32 [mr:       evex.nf1.nd0.l0.m4.o32 45 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 0c) 300 321 001(45) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNE, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+15773, 355},
    /*   2 : CFCMOVNE rm64,reg64 [mr:       evex.nf1.nd0.l0.m4.o64 45 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 0c) 300 324 001(45) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNE, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+15933, 355},
    /*   3 : CFCMOVNE reg16,rm16 [rm:       evex.nf0.nd0.l0.m4.o16 45 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 08) 300 320 001(45) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16093, 354},
    /*   4 : CFCMOVNE reg32,rm32 [rm:       evex.nf0.nd0.l0.m4.o32 45 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 08) 300 321 001(45) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+16253, 355},
    /*   5 : CFCMOVNE reg64,rm64 [rm:       evex.nf0.nd0.l0.m4.o64 45 /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 08) 300 324 001(45) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+16413, 355},
    /*   6 : CFCMOVNE reg16?,reg16,rm16 [vrm:      evex.nf1.nd1.l0.m4.o16 45 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7d 1c) 300 320 001(45) 121 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNE, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+16573, 356},
    /*   7 : CFCMOVNE reg16,rm16 [rm:      evex.nf1.nd0.l0.m4.o16 45 /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 0c) 300 320 001(45) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16733, 354},
    /*   8 : CFCMOVNE reg16?,rm16 [v+rm:      evex.nf1.nd1.l0.m4.o16 45 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(45) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16893, 357},
    /*   9 : CFCMOVNE reg32?,reg32,rm32 [vrm:      evex.nf1.nd1.l0.m4.o32 45 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7c 1c) 300 321 001(45) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNE, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+17053, 358},
    /*  10 : CFCMOVNE reg32,rm32 [rm:      evex.nf1.nd0.l0.m4.o32 45 /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 0c) 300 321 001(45) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17213, 355},
    /*  11 : CFCMOVNE reg32?,rm32 [v+rm:      evex.nf1.nd1.l0.m4.o32 45 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(45) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17373, 359},
    /*  12 : CFCMOVNE reg64?,reg64,rm64 [vrm:      evex.nf1.nd1.l0.m4.o64 45 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 fc 1c) 300 324 001(45) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNE, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+17533, 358},
    /*  13 : CFCMOVNE reg64,rm64 [rm:      evex.nf1.nd0.l0.m4.o64 45 /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 0c) 300 324 001(45) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17693, 355},
    /*  14 : CFCMOVNE reg64?,rm64 [v+rm:      evex.nf1.nd1.l0.m4.o64 45 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(45) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17853, 359},
};

static const struct itemplate instrux_CFCMOVNG[15] = {
    /*   0 : CFCMOVNG rm16,reg16 [mr:       evex.nf1.nd0.l0.m4.o16 4e /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 0c) 300 320 001(4e) 101 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNG, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+15603, 354},
    /*   1 : CFCMOVNG rm32,reg32 [mr:       evex.nf1.nd0.l0.m4.o32 4e /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 0c) 300 321 001(4e) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNG, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+15763, 355},
    /*   2 : CFCMOVNG rm64,reg64 [mr:       evex.nf1.nd0.l0.m4.o64 4e /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 0c) 300 324 001(4e) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNG, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+15923, 355},
    /*   3 : CFCMOVNG reg16,rm16 [rm:       evex.nf0.nd0.l0.m4.o16 4e /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(4e) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNG, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16083, 354},
    /*   4 : CFCMOVNG reg32,rm32 [rm:       evex.nf0.nd0.l0.m4.o32 4e /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(4e) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNG, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+16243, 355},
    /*   5 : CFCMOVNG reg64,rm64 [rm:       evex.nf0.nd0.l0.m4.o64 4e /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(4e) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNG, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+16403, 355},
    /*   6 : CFCMOVNG reg16?,reg16,rm16 [vrm:      evex.nf1.nd1.l0.m4.o16 4e /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(4e) 121 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNG, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+16563, 356},
    /*   7 : CFCMOVNG reg16,rm16 [rm:      evex.nf1.nd0.l0.m4.o16 4e /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 0c) 300 320 001(4e) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNG, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16723, 354},
    /*   8 : CFCMOVNG reg16?,rm16 [v+rm:      evex.nf1.nd1.l0.m4.o16 4e /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(4e) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNG, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16883, 357},
    /*   9 : CFCMOVNG reg32?,reg32,rm32 [vrm:      evex.nf1.nd1.l0.m4.o32 4e /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(4e) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNG, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+17043, 358},
    /*  10 : CFCMOVNG reg32,rm32 [rm:      evex.nf1.nd0.l0.m4.o32 4e /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 0c) 300 321 001(4e) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNG, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17203, 355},
    /*  11 : CFCMOVNG reg32?,rm32 [v+rm:      evex.nf1.nd1.l0.m4.o32 4e /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(4e) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNG, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17363, 359},
    /*  12 : CFCMOVNG reg64?,reg64,rm64 [vrm:      evex.nf1.nd1.l0.m4.o64 4e /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(4e) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNG, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+17523, 358},
    /*  13 : CFCMOVNG reg64,rm64 [rm:      evex.nf1.nd0.l0.m4.o64 4e /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 0c) 300 324 001(4e) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNG, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17683, 355},
    /*  14 : CFCMOVNG reg64?,rm64 [v+rm:      evex.nf1.nd1.l0.m4.o64 4e /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(4e) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNG, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17843, 359},
};

static const struct itemplate instrux_CFCMOVNGE[15] = {
    /*   0 : CFCMOVNGE rm16,reg16 [mr:       evex.nf1.nd0.l0.m4.o16 4c /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 0c) 300 320 001(4c) 101 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNGE, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+15593, 354},
    /*   1 : CFCMOVNGE rm32,reg32 [mr:       evex.nf1.nd0.l0.m4.o32 4c /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 0c) 300 321 001(4c) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNGE, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+15753, 355},
    /*   2 : CFCMOVNGE rm64,reg64 [mr:       evex.nf1.nd0.l0.m4.o64 4c /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 0c) 300 324 001(4c) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNGE, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+15913, 355},
    /*   3 : CFCMOVNGE reg16,rm16 [rm:       evex.nf0.nd0.l0.m4.o16 4c /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 08) 300 320 001(4c) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNGE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16073, 354},
    /*   4 : CFCMOVNGE reg32,rm32 [rm:       evex.nf0.nd0.l0.m4.o32 4c /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 08) 300 321 001(4c) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNGE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+16233, 355},
    /*   5 : CFCMOVNGE reg64,rm64 [rm:       evex.nf0.nd0.l0.m4.o64 4c /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 08) 300 324 001(4c) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNGE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+16393, 355},
    /*   6 : CFCMOVNGE reg16?,reg16,rm16 [vrm:      evex.nf1.nd1.l0.m4.o16 4c /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7d 1c) 300 320 001(4c) 121 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNGE, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+16553, 356},
    /*   7 : CFCMOVNGE reg16,rm16 [rm:      evex.nf1.nd0.l0.m4.o16 4c /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 0c) 300 320 001(4c) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNGE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16713, 354},
    /*   8 : CFCMOVNGE reg16?,rm16 [v+rm:      evex.nf1.nd1.l0.m4.o16 4c /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(4c) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNGE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16873, 357},
    /*   9 : CFCMOVNGE reg32?,reg32,rm32 [vrm:      evex.nf1.nd1.l0.m4.o32 4c /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7c 1c) 300 321 001(4c) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNGE, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+17033, 358},
    /*  10 : CFCMOVNGE reg32,rm32 [rm:      evex.nf1.nd0.l0.m4.o32 4c /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 0c) 300 321 001(4c) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNGE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17193, 355},
    /*  11 : CFCMOVNGE reg32?,rm32 [v+rm:      evex.nf1.nd1.l0.m4.o32 4c /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(4c) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNGE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17353, 359},
    /*  12 : CFCMOVNGE reg64?,reg64,rm64 [vrm:      evex.nf1.nd1.l0.m4.o64 4c /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 fc 1c) 300 324 001(4c) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNGE, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+17513, 358},
    /*  13 : CFCMOVNGE reg64,rm64 [rm:      evex.nf1.nd0.l0.m4.o64 4c /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 0c) 300 324 001(4c) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNGE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17673, 355},
    /*  14 : CFCMOVNGE reg64?,rm64 [v+rm:      evex.nf1.nd1.l0.m4.o64 4c /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(4c) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNGE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17833, 359},
};

static const struct itemplate instrux_CFCMOVNL[15] = {
    /*   0 : CFCMOVNL rm16,reg16 [mr:       evex.nf1.nd0.l0.m4.o16 4d /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 0c) 300 320 001(4d) 101 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNL, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+15583, 354},
    /*   1 : CFCMOVNL rm32,reg32 [mr:       evex.nf1.nd0.l0.m4.o32 4d /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 0c) 300 321 001(4d) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNL, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+15743, 355},
    /*   2 : CFCMOVNL rm64,reg64 [mr:       evex.nf1.nd0.l0.m4.o64 4d /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 0c) 300 324 001(4d) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNL, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+15903, 355},
    /*   3 : CFCMOVNL reg16,rm16 [rm:       evex.nf0.nd0.l0.m4.o16 4d /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(4d) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNL, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16063, 354},
    /*   4 : CFCMOVNL reg32,rm32 [rm:       evex.nf0.nd0.l0.m4.o32 4d /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(4d) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNL, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+16223, 355},
    /*   5 : CFCMOVNL reg64,rm64 [rm:       evex.nf0.nd0.l0.m4.o64 4d /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(4d) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNL, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+16383, 355},
    /*   6 : CFCMOVNL reg16?,reg16,rm16 [vrm:      evex.nf1.nd1.l0.m4.o16 4d /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(4d) 121 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNL, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+16543, 356},
    /*   7 : CFCMOVNL reg16,rm16 [rm:      evex.nf1.nd0.l0.m4.o16 4d /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 0c) 300 320 001(4d) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNL, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16703, 354},
    /*   8 : CFCMOVNL reg16?,rm16 [v+rm:      evex.nf1.nd1.l0.m4.o16 4d /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(4d) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNL, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16863, 357},
    /*   9 : CFCMOVNL reg32?,reg32,rm32 [vrm:      evex.nf1.nd1.l0.m4.o32 4d /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(4d) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNL, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+17023, 358},
    /*  10 : CFCMOVNL reg32,rm32 [rm:      evex.nf1.nd0.l0.m4.o32 4d /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 0c) 300 321 001(4d) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNL, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17183, 355},
    /*  11 : CFCMOVNL reg32?,rm32 [v+rm:      evex.nf1.nd1.l0.m4.o32 4d /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(4d) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNL, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17343, 359},
    /*  12 : CFCMOVNL reg64?,reg64,rm64 [vrm:      evex.nf1.nd1.l0.m4.o64 4d /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(4d) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNL, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+17503, 358},
    /*  13 : CFCMOVNL reg64,rm64 [rm:      evex.nf1.nd0.l0.m4.o64 4d /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 0c) 300 324 001(4d) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNL, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17663, 355},
    /*  14 : CFCMOVNL reg64?,rm64 [v+rm:      evex.nf1.nd1.l0.m4.o64 4d /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(4d) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNL, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17823, 359},
};

static const struct itemplate instrux_CFCMOVNLE[15] = {
    /*   0 : CFCMOVNLE rm16,reg16 [mr:       evex.nf1.nd0.l0.m4.o16 4f /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 0c) 300 320 001(4f) 101 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNLE, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+15573, 354},
    /*   1 : CFCMOVNLE rm32,reg32 [mr:       evex.nf1.nd0.l0.m4.o32 4f /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 0c) 300 321 001(4f) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNLE, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+15733, 355},
    /*   2 : CFCMOVNLE rm64,reg64 [mr:       evex.nf1.nd0.l0.m4.o64 4f /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 0c) 300 324 001(4f) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNLE, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+15893, 355},
    /*   3 : CFCMOVNLE reg16,rm16 [rm:       evex.nf0.nd0.l0.m4.o16 4f /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 08) 300 320 001(4f) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNLE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16053, 354},
    /*   4 : CFCMOVNLE reg32,rm32 [rm:       evex.nf0.nd0.l0.m4.o32 4f /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 08) 300 321 001(4f) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNLE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+16213, 355},
    /*   5 : CFCMOVNLE reg64,rm64 [rm:       evex.nf0.nd0.l0.m4.o64 4f /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 08) 300 324 001(4f) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNLE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+16373, 355},
    /*   6 : CFCMOVNLE reg16?,reg16,rm16 [vrm:      evex.nf1.nd1.l0.m4.o16 4f /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7d 1c) 300 320 001(4f) 121 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNLE, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+16533, 356},
    /*   7 : CFCMOVNLE reg16,rm16 [rm:      evex.nf1.nd0.l0.m4.o16 4f /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 0c) 300 320 001(4f) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNLE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16693, 354},
    /*   8 : CFCMOVNLE reg16?,rm16 [v+rm:      evex.nf1.nd1.l0.m4.o16 4f /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(4f) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNLE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16853, 357},
    /*   9 : CFCMOVNLE reg32?,reg32,rm32 [vrm:      evex.nf1.nd1.l0.m4.o32 4f /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7c 1c) 300 321 001(4f) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNLE, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+17013, 358},
    /*  10 : CFCMOVNLE reg32,rm32 [rm:      evex.nf1.nd0.l0.m4.o32 4f /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 0c) 300 321 001(4f) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNLE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17173, 355},
    /*  11 : CFCMOVNLE reg32?,rm32 [v+rm:      evex.nf1.nd1.l0.m4.o32 4f /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(4f) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNLE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17333, 359},
    /*  12 : CFCMOVNLE reg64?,reg64,rm64 [vrm:      evex.nf1.nd1.l0.m4.o64 4f /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 fc 1c) 300 324 001(4f) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNLE, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+17493, 358},
    /*  13 : CFCMOVNLE reg64,rm64 [rm:      evex.nf1.nd0.l0.m4.o64 4f /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 0c) 300 324 001(4f) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNLE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17653, 355},
    /*  14 : CFCMOVNLE reg64?,rm64 [v+rm:      evex.nf1.nd1.l0.m4.o64 4f /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(4f) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNLE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17813, 359},
};

static const struct itemplate instrux_CFCMOVNO[15] = {
    /*   0 : CFCMOVNO rm16,reg16 [mr:       evex.nf1.nd0.l0.m4.o16 41 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 0c) 300 320 001(41) 101 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNO, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+15623, 354},
    /*   1 : CFCMOVNO rm32,reg32 [mr:       evex.nf1.nd0.l0.m4.o32 41 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 0c) 300 321 001(41) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNO, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+15783, 355},
    /*   2 : CFCMOVNO rm64,reg64 [mr:       evex.nf1.nd0.l0.m4.o64 41 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 0c) 300 324 001(41) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNO, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+15943, 355},
    /*   3 : CFCMOVNO reg16,rm16 [rm:       evex.nf0.nd0.l0.m4.o16 41 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(41) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNO, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16103, 354},
    /*   4 : CFCMOVNO reg32,rm32 [rm:       evex.nf0.nd0.l0.m4.o32 41 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(41) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNO, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+16263, 355},
    /*   5 : CFCMOVNO reg64,rm64 [rm:       evex.nf0.nd0.l0.m4.o64 41 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(41) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNO, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+16423, 355},
    /*   6 : CFCMOVNO reg16?,reg16,rm16 [vrm:      evex.nf1.nd1.l0.m4.o16 41 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(41) 121 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNO, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+16583, 356},
    /*   7 : CFCMOVNO reg16,rm16 [rm:      evex.nf1.nd0.l0.m4.o16 41 /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 0c) 300 320 001(41) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNO, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16743, 354},
    /*   8 : CFCMOVNO reg16?,rm16 [v+rm:      evex.nf1.nd1.l0.m4.o16 41 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(41) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNO, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16903, 357},
    /*   9 : CFCMOVNO reg32?,reg32,rm32 [vrm:      evex.nf1.nd1.l0.m4.o32 41 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(41) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNO, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+17063, 358},
    /*  10 : CFCMOVNO reg32,rm32 [rm:      evex.nf1.nd0.l0.m4.o32 41 /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 0c) 300 321 001(41) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNO, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17223, 355},
    /*  11 : CFCMOVNO reg32?,rm32 [v+rm:      evex.nf1.nd1.l0.m4.o32 41 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(41) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNO, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17383, 359},
    /*  12 : CFCMOVNO reg64?,reg64,rm64 [vrm:      evex.nf1.nd1.l0.m4.o64 41 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(41) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNO, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+17543, 358},
    /*  13 : CFCMOVNO reg64,rm64 [rm:      evex.nf1.nd0.l0.m4.o64 41 /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 0c) 300 324 001(41) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNO, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17703, 355},
    /*  14 : CFCMOVNO reg64?,rm64 [v+rm:      evex.nf1.nd1.l0.m4.o64 41 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(41) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNO, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17863, 359},
};

static const struct itemplate instrux_CFCMOVNP[15] = {
    /*   0 : CFCMOVNP rm16,reg16 [mr:       evex.nf1.nd0.l0.m4.o16 4b /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 0c) 300 320 001(4b) 101 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNP, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+15633, 354},
    /*   1 : CFCMOVNP rm32,reg32 [mr:       evex.nf1.nd0.l0.m4.o32 4b /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 0c) 300 321 001(4b) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNP, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+15793, 355},
    /*   2 : CFCMOVNP rm64,reg64 [mr:       evex.nf1.nd0.l0.m4.o64 4b /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 0c) 300 324 001(4b) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNP, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+15953, 355},
    /*   3 : CFCMOVNP reg16,rm16 [rm:       evex.nf0.nd0.l0.m4.o16 4b /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 08) 300 320 001(4b) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNP, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16113, 354},
    /*   4 : CFCMOVNP reg32,rm32 [rm:       evex.nf0.nd0.l0.m4.o32 4b /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 08) 300 321 001(4b) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNP, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+16273, 355},
    /*   5 : CFCMOVNP reg64,rm64 [rm:       evex.nf0.nd0.l0.m4.o64 4b /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 08) 300 324 001(4b) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNP, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+16433, 355},
    /*   6 : CFCMOVNP reg16?,reg16,rm16 [vrm:      evex.nf1.nd1.l0.m4.o16 4b /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7d 1c) 300 320 001(4b) 121 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNP, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+16593, 356},
    /*   7 : CFCMOVNP reg16,rm16 [rm:      evex.nf1.nd0.l0.m4.o16 4b /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 0c) 300 320 001(4b) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNP, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16753, 354},
    /*   8 : CFCMOVNP reg16?,rm16 [v+rm:      evex.nf1.nd1.l0.m4.o16 4b /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(4b) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNP, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16913, 357},
    /*   9 : CFCMOVNP reg32?,reg32,rm32 [vrm:      evex.nf1.nd1.l0.m4.o32 4b /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7c 1c) 300 321 001(4b) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNP, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+17073, 358},
    /*  10 : CFCMOVNP reg32,rm32 [rm:      evex.nf1.nd0.l0.m4.o32 4b /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 0c) 300 321 001(4b) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNP, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17233, 355},
    /*  11 : CFCMOVNP reg32?,rm32 [v+rm:      evex.nf1.nd1.l0.m4.o32 4b /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(4b) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNP, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17393, 359},
    /*  12 : CFCMOVNP reg64?,reg64,rm64 [vrm:      evex.nf1.nd1.l0.m4.o64 4b /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 fc 1c) 300 324 001(4b) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNP, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+17553, 358},
    /*  13 : CFCMOVNP reg64,rm64 [rm:      evex.nf1.nd0.l0.m4.o64 4b /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 0c) 300 324 001(4b) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNP, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17713, 355},
    /*  14 : CFCMOVNP reg64?,rm64 [v+rm:      evex.nf1.nd1.l0.m4.o64 4b /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(4b) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNP, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17873, 359},
};

static const struct itemplate instrux_CFCMOVNS[15] = {
    /*   0 : CFCMOVNS rm16,reg16 [mr:       evex.nf1.nd0.l0.m4.o16 49 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 0c) 300 320 001(49) 101 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNS, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+15643, 354},
    /*   1 : CFCMOVNS rm32,reg32 [mr:       evex.nf1.nd0.l0.m4.o32 49 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 0c) 300 321 001(49) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNS, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+15803, 355},
    /*   2 : CFCMOVNS rm64,reg64 [mr:       evex.nf1.nd0.l0.m4.o64 49 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 0c) 300 324 001(49) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNS, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+15963, 355},
    /*   3 : CFCMOVNS reg16,rm16 [rm:       evex.nf0.nd0.l0.m4.o16 49 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(49) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNS, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16123, 354},
    /*   4 : CFCMOVNS reg32,rm32 [rm:       evex.nf0.nd0.l0.m4.o32 49 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(49) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNS, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+16283, 355},
    /*   5 : CFCMOVNS reg64,rm64 [rm:       evex.nf0.nd0.l0.m4.o64 49 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(49) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNS, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+16443, 355},
    /*   6 : CFCMOVNS reg16?,reg16,rm16 [vrm:      evex.nf1.nd1.l0.m4.o16 49 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(49) 121 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNS, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+16603, 356},
    /*   7 : CFCMOVNS reg16,rm16 [rm:      evex.nf1.nd0.l0.m4.o16 49 /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 0c) 300 320 001(49) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNS, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16763, 354},
    /*   8 : CFCMOVNS reg16?,rm16 [v+rm:      evex.nf1.nd1.l0.m4.o16 49 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(49) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNS, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16923, 357},
    /*   9 : CFCMOVNS reg32?,reg32,rm32 [vrm:      evex.nf1.nd1.l0.m4.o32 49 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(49) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNS, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+17083, 358},
    /*  10 : CFCMOVNS reg32,rm32 [rm:      evex.nf1.nd0.l0.m4.o32 49 /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 0c) 300 321 001(49) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNS, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17243, 355},
    /*  11 : CFCMOVNS reg32?,rm32 [v+rm:      evex.nf1.nd1.l0.m4.o32 49 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(49) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNS, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17403, 359},
    /*  12 : CFCMOVNS reg64?,reg64,rm64 [vrm:      evex.nf1.nd1.l0.m4.o64 49 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(49) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNS, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+17563, 358},
    /*  13 : CFCMOVNS reg64,rm64 [rm:      evex.nf1.nd0.l0.m4.o64 49 /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 0c) 300 324 001(49) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNS, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17723, 355},
    /*  14 : CFCMOVNS reg64?,rm64 [v+rm:      evex.nf1.nd1.l0.m4.o64 49 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(49) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNS, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17883, 359},
};

static const struct itemplate instrux_CFCMOVNZ[15] = {
    /*   0 : CFCMOVNZ rm16,reg16 [mr:       evex.nf1.nd0.l0.m4.o16 45 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 0c) 300 320 001(45) 101 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNZ, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+15613, 354},
    /*   1 : CFCMOVNZ rm32,reg32 [mr:       evex.nf1.nd0.l0.m4.o32 45 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 0c) 300 321 001(45) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNZ, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+15773, 355},
    /*   2 : CFCMOVNZ rm64,reg64 [mr:       evex.nf1.nd0.l0.m4.o64 45 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 0c) 300 324 001(45) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNZ, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+15933, 355},
    /*   3 : CFCMOVNZ reg16,rm16 [rm:       evex.nf0.nd0.l0.m4.o16 45 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(45) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNZ, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16093, 354},
    /*   4 : CFCMOVNZ reg32,rm32 [rm:       evex.nf0.nd0.l0.m4.o32 45 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(45) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNZ, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+16253, 355},
    /*   5 : CFCMOVNZ reg64,rm64 [rm:       evex.nf0.nd0.l0.m4.o64 45 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(45) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNZ, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+16413, 355},
    /*   6 : CFCMOVNZ reg16?,reg16,rm16 [vrm:      evex.nf1.nd1.l0.m4.o16 45 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(45) 121 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNZ, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+16573, 356},
    /*   7 : CFCMOVNZ reg16,rm16 [rm:      evex.nf1.nd0.l0.m4.o16 45 /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 0c) 300 320 001(45) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNZ, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16733, 354},
    /*   8 : CFCMOVNZ reg16?,rm16 [v+rm:      evex.nf1.nd1.l0.m4.o16 45 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(45) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNZ, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16893, 357},
    /*   9 : CFCMOVNZ reg32?,reg32,rm32 [vrm:      evex.nf1.nd1.l0.m4.o32 45 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(45) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNZ, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+17053, 358},
    /*  10 : CFCMOVNZ reg32,rm32 [rm:      evex.nf1.nd0.l0.m4.o32 45 /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 0c) 300 321 001(45) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNZ, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17213, 355},
    /*  11 : CFCMOVNZ reg32?,rm32 [v+rm:      evex.nf1.nd1.l0.m4.o32 45 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(45) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNZ, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17373, 359},
    /*  12 : CFCMOVNZ reg64?,reg64,rm64 [vrm:      evex.nf1.nd1.l0.m4.o64 45 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(45) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNZ, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+17533, 358},
    /*  13 : CFCMOVNZ reg64,rm64 [rm:      evex.nf1.nd0.l0.m4.o64 45 /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 0c) 300 324 001(45) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNZ, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17693, 355},
    /*  14 : CFCMOVNZ reg64?,rm64 [v+rm:      evex.nf1.nd1.l0.m4.o64 45 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(45) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVNZ, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17853, 359},
};

static const struct itemplate instrux_CFCMOVO[15] = {
    /*   0 : CFCMOVO rm16,reg16 [mr:       evex.nf1.nd0.l0.m4.o16 40 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 0c) 300 320 001(40) 101 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVO, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+15653, 354},
    /*   1 : CFCMOVO rm32,reg32 [mr:       evex.nf1.nd0.l0.m4.o32 40 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 0c) 300 321 001(40) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVO, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+15813, 355},
    /*   2 : CFCMOVO rm64,reg64 [mr:       evex.nf1.nd0.l0.m4.o64 40 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 0c) 300 324 001(40) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVO, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+15973, 355},
    /*   3 : CFCMOVO reg16,rm16 [rm:       evex.nf0.nd0.l0.m4.o16 40 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(40) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVO, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16133, 354},
    /*   4 : CFCMOVO reg32,rm32 [rm:       evex.nf0.nd0.l0.m4.o32 40 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(40) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVO, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+16293, 355},
    /*   5 : CFCMOVO reg64,rm64 [rm:       evex.nf0.nd0.l0.m4.o64 40 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(40) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVO, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+16453, 355},
    /*   6 : CFCMOVO reg16?,reg16,rm16 [vrm:      evex.nf1.nd1.l0.m4.o16 40 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(40) 121 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVO, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+16613, 356},
    /*   7 : CFCMOVO reg16,rm16 [rm:      evex.nf1.nd0.l0.m4.o16 40 /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 0c) 300 320 001(40) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVO, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16773, 354},
    /*   8 : CFCMOVO reg16?,rm16 [v+rm:      evex.nf1.nd1.l0.m4.o16 40 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(40) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVO, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16933, 357},
    /*   9 : CFCMOVO reg32?,reg32,rm32 [vrm:      evex.nf1.nd1.l0.m4.o32 40 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(40) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVO, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+17093, 358},
    /*  10 : CFCMOVO reg32,rm32 [rm:      evex.nf1.nd0.l0.m4.o32 40 /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 0c) 300 321 001(40) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVO, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17253, 355},
    /*  11 : CFCMOVO reg32?,rm32 [v+rm:      evex.nf1.nd1.l0.m4.o32 40 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(40) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVO, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17413, 359},
    /*  12 : CFCMOVO reg64?,reg64,rm64 [vrm:      evex.nf1.nd1.l0.m4.o64 40 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(40) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVO, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+17573, 358},
    /*  13 : CFCMOVO reg64,rm64 [rm:      evex.nf1.nd0.l0.m4.o64 40 /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 0c) 300 324 001(40) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVO, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17733, 355},
    /*  14 : CFCMOVO reg64?,rm64 [v+rm:      evex.nf1.nd1.l0.m4.o64 40 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(40) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVO, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17893, 359},
};

static const struct itemplate instrux_CFCMOVP[15] = {
    /*   0 : CFCMOVP rm16,reg16 [mr:       evex.nf1.nd0.l0.m4.o16 4a /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 0c) 300 320 001(4a) 101 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVP, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+15663, 354},
    /*   1 : CFCMOVP rm32,reg32 [mr:       evex.nf1.nd0.l0.m4.o32 4a /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 0c) 300 321 001(4a) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVP, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+15823, 355},
    /*   2 : CFCMOVP rm64,reg64 [mr:       evex.nf1.nd0.l0.m4.o64 4a /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 0c) 300 324 001(4a) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVP, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+15983, 355},
    /*   3 : CFCMOVP reg16,rm16 [rm:       evex.nf0.nd0.l0.m4.o16 4a /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 08) 300 320 001(4a) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVP, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16143, 354},
    /*   4 : CFCMOVP reg32,rm32 [rm:       evex.nf0.nd0.l0.m4.o32 4a /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 08) 300 321 001(4a) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVP, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+16303, 355},
    /*   5 : CFCMOVP reg64,rm64 [rm:       evex.nf0.nd0.l0.m4.o64 4a /r    ] SM0-1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 08) 300 324 001(4a) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVP, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+16463, 355},
    /*   6 : CFCMOVP reg16?,reg16,rm16 [vrm:      evex.nf1.nd1.l0.m4.o16 4a /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7d 1c) 300 320 001(4a) 121 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVP, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+16623, 356},
    /*   7 : CFCMOVP reg16,rm16 [rm:      evex.nf1.nd0.l0.m4.o16 4a /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7d 0c) 300 320 001(4a) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVP, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16783, 354},
    /*   8 : CFCMOVP reg16?,rm16 [v+rm:      evex.nf1.nd1.l0.m4.o16 4a /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(4a) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVP, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16943, 357},
    /*   9 : CFCMOVP reg32?,reg32,rm32 [vrm:      evex.nf1.nd1.l0.m4.o32 4a /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 7c 1c) 300 321 001(4a) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVP, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+17103, 358},
    /*  10 : CFCMOVP reg32,rm32 [rm:      evex.nf1.nd0.l0.m4.o32 4a /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7c 0c) 300 321 001(4a) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVP, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17263, 355},
    /*  11 : CFCMOVP reg32?,rm32 [v+rm:      evex.nf1.nd1.l0.m4.o32 4a /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(4a) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVP, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17423, 359},
    /*  12 : CFCMOVP reg64?,reg64,rm64 [vrm:      evex.nf1.nd1.l0.m4.o64 4a /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64,ND */
        /* 240(f4 fc 1c) 300 324 001(4a) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVP, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+17583, 358},
    /*  13 : CFCMOVP reg64,rm64 [rm:      evex.nf1.nd0.l0.m4.o64 4a /r    ] SM0,SM1,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 fc 0c) 300 324 001(4a) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVP, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17743, 355},
    /*  14 : CFCMOVP reg64?,rm64 [v+rm:      evex.nf1.nd1.l0.m4.o64 4a /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(4a) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVP, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17903, 359},
};

static const struct itemplate instrux_CFCMOVPE[15] = {
    /*   0 : CFCMOVPE rm16,reg16 [mr:       evex.nf1.nd0.l0.m4.o16 4a /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 0c) 300 320 001(4a) 101 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVPE, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+15663, 354},
    /*   1 : CFCMOVPE rm32,reg32 [mr:       evex.nf1.nd0.l0.m4.o32 4a /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 0c) 300 321 001(4a) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVPE, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+15823, 355},
    /*   2 : CFCMOVPE rm64,reg64 [mr:       evex.nf1.nd0.l0.m4.o64 4a /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 0c) 300 324 001(4a) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVPE, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+15983, 355},
    /*   3 : CFCMOVPE reg16,rm16 [rm:       evex.nf0.nd0.l0.m4.o16 4a /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(4a) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVPE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16143, 354},
    /*   4 : CFCMOVPE reg32,rm32 [rm:       evex.nf0.nd0.l0.m4.o32 4a /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(4a) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVPE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+16303, 355},
    /*   5 : CFCMOVPE reg64,rm64 [rm:       evex.nf0.nd0.l0.m4.o64 4a /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(4a) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVPE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+16463, 355},
    /*   6 : CFCMOVPE reg16?,reg16,rm16 [vrm:      evex.nf1.nd1.l0.m4.o16 4a /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(4a) 121 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVPE, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+16623, 356},
    /*   7 : CFCMOVPE reg16,rm16 [rm:      evex.nf1.nd0.l0.m4.o16 4a /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 0c) 300 320 001(4a) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVPE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16783, 354},
    /*   8 : CFCMOVPE reg16?,rm16 [v+rm:      evex.nf1.nd1.l0.m4.o16 4a /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(4a) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVPE, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16943, 357},
    /*   9 : CFCMOVPE reg32?,reg32,rm32 [vrm:      evex.nf1.nd1.l0.m4.o32 4a /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(4a) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVPE, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+17103, 358},
    /*  10 : CFCMOVPE reg32,rm32 [rm:      evex.nf1.nd0.l0.m4.o32 4a /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 0c) 300 321 001(4a) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVPE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17263, 355},
    /*  11 : CFCMOVPE reg32?,rm32 [v+rm:      evex.nf1.nd1.l0.m4.o32 4a /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(4a) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVPE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17423, 359},
    /*  12 : CFCMOVPE reg64?,reg64,rm64 [vrm:      evex.nf1.nd1.l0.m4.o64 4a /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(4a) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVPE, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+17583, 358},
    /*  13 : CFCMOVPE reg64,rm64 [rm:      evex.nf1.nd0.l0.m4.o64 4a /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 0c) 300 324 001(4a) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVPE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17743, 355},
    /*  14 : CFCMOVPE reg64?,rm64 [v+rm:      evex.nf1.nd1.l0.m4.o64 4a /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(4a) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVPE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17903, 359},
};

static const struct itemplate instrux_CFCMOVPO[15] = {
    /*   0 : CFCMOVPO rm16,reg16 [mr:       evex.nf1.nd0.l0.m4.o16 4b /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 0c) 300 320 001(4b) 101 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVPO, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+15633, 354},
    /*   1 : CFCMOVPO rm32,reg32 [mr:       evex.nf1.nd0.l0.m4.o32 4b /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 0c) 300 321 001(4b) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVPO, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+15793, 355},
    /*   2 : CFCMOVPO rm64,reg64 [mr:       evex.nf1.nd0.l0.m4.o64 4b /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 0c) 300 324 001(4b) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVPO, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+15953, 355},
    /*   3 : CFCMOVPO reg16,rm16 [rm:       evex.nf0.nd0.l0.m4.o16 4b /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(4b) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVPO, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16113, 354},
    /*   4 : CFCMOVPO reg32,rm32 [rm:       evex.nf0.nd0.l0.m4.o32 4b /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(4b) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVPO, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+16273, 355},
    /*   5 : CFCMOVPO reg64,rm64 [rm:       evex.nf0.nd0.l0.m4.o64 4b /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(4b) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVPO, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+16433, 355},
    /*   6 : CFCMOVPO reg16?,reg16,rm16 [vrm:      evex.nf1.nd1.l0.m4.o16 4b /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(4b) 121 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVPO, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+16593, 356},
    /*   7 : CFCMOVPO reg16,rm16 [rm:      evex.nf1.nd0.l0.m4.o16 4b /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 0c) 300 320 001(4b) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVPO, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16753, 354},
    /*   8 : CFCMOVPO reg16?,rm16 [v+rm:      evex.nf1.nd1.l0.m4.o16 4b /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(4b) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVPO, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16913, 357},
    /*   9 : CFCMOVPO reg32?,reg32,rm32 [vrm:      evex.nf1.nd1.l0.m4.o32 4b /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(4b) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVPO, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+17073, 358},
    /*  10 : CFCMOVPO reg32,rm32 [rm:      evex.nf1.nd0.l0.m4.o32 4b /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 0c) 300 321 001(4b) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVPO, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17233, 355},
    /*  11 : CFCMOVPO reg32?,rm32 [v+rm:      evex.nf1.nd1.l0.m4.o32 4b /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(4b) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVPO, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17393, 359},
    /*  12 : CFCMOVPO reg64?,reg64,rm64 [vrm:      evex.nf1.nd1.l0.m4.o64 4b /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(4b) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVPO, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+17553, 358},
    /*  13 : CFCMOVPO reg64,rm64 [rm:      evex.nf1.nd0.l0.m4.o64 4b /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 0c) 300 324 001(4b) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVPO, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17713, 355},
    /*  14 : CFCMOVPO reg64?,rm64 [v+rm:      evex.nf1.nd1.l0.m4.o64 4b /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(4b) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVPO, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17873, 359},
};

static const struct itemplate instrux_CFCMOVS[15] = {
    /*   0 : CFCMOVS rm16,reg16 [mr:       evex.nf1.nd0.l0.m4.o16 48 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 0c) 300 320 001(48) 101 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVS, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+15673, 354},
    /*   1 : CFCMOVS rm32,reg32 [mr:       evex.nf1.nd0.l0.m4.o32 48 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 0c) 300 321 001(48) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVS, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+15833, 355},
    /*   2 : CFCMOVS rm64,reg64 [mr:       evex.nf1.nd0.l0.m4.o64 48 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 0c) 300 324 001(48) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVS, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+15993, 355},
    /*   3 : CFCMOVS reg16,rm16 [rm:       evex.nf0.nd0.l0.m4.o16 48 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(48) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVS, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16153, 354},
    /*   4 : CFCMOVS reg32,rm32 [rm:       evex.nf0.nd0.l0.m4.o32 48 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(48) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVS, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+16313, 355},
    /*   5 : CFCMOVS reg64,rm64 [rm:       evex.nf0.nd0.l0.m4.o64 48 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(48) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVS, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+16473, 355},
    /*   6 : CFCMOVS reg16?,reg16,rm16 [vrm:      evex.nf1.nd1.l0.m4.o16 48 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(48) 121 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVS, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+16633, 356},
    /*   7 : CFCMOVS reg16,rm16 [rm:      evex.nf1.nd0.l0.m4.o16 48 /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 0c) 300 320 001(48) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVS, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16793, 354},
    /*   8 : CFCMOVS reg16?,rm16 [v+rm:      evex.nf1.nd1.l0.m4.o16 48 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(48) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVS, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16953, 357},
    /*   9 : CFCMOVS reg32?,reg32,rm32 [vrm:      evex.nf1.nd1.l0.m4.o32 48 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(48) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVS, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+17113, 358},
    /*  10 : CFCMOVS reg32,rm32 [rm:      evex.nf1.nd0.l0.m4.o32 48 /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 0c) 300 321 001(48) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVS, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17273, 355},
    /*  11 : CFCMOVS reg32?,rm32 [v+rm:      evex.nf1.nd1.l0.m4.o32 48 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(48) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVS, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17433, 359},
    /*  12 : CFCMOVS reg64?,reg64,rm64 [vrm:      evex.nf1.nd1.l0.m4.o64 48 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(48) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVS, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+17593, 358},
    /*  13 : CFCMOVS reg64,rm64 [rm:      evex.nf1.nd0.l0.m4.o64 48 /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 0c) 300 324 001(48) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVS, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17753, 355},
    /*  14 : CFCMOVS reg64?,rm64 [v+rm:      evex.nf1.nd1.l0.m4.o64 48 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(48) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVS, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17913, 359},
};

static const struct itemplate instrux_CFCMOVZ[15] = {
    /*   0 : CFCMOVZ rm16,reg16 [mr:       evex.nf1.nd0.l0.m4.o16 44 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 0c) 300 320 001(44) 101 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVZ, 2, {RM_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+15563, 354},
    /*   1 : CFCMOVZ rm32,reg32 [mr:       evex.nf1.nd0.l0.m4.o32 44 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 0c) 300 321 001(44) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVZ, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+15723, 355},
    /*   2 : CFCMOVZ rm64,reg64 [mr:       evex.nf1.nd0.l0.m4.o64 44 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 0c) 300 324 001(44) 101 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVZ, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+15883, 355},
    /*   3 : CFCMOVZ reg16,rm16 [rm:       evex.nf0.nd0.l0.m4.o16 44 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(44) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVZ, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16043, 354},
    /*   4 : CFCMOVZ reg32,rm32 [rm:       evex.nf0.nd0.l0.m4.o32 44 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(44) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVZ, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+16203, 355},
    /*   5 : CFCMOVZ reg64,rm64 [rm:       evex.nf0.nd0.l0.m4.o64 44 /r    ] SM0-1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(44) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVZ, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+16363, 355},
    /*   6 : CFCMOVZ reg16?,reg16,rm16 [vrm:      evex.nf1.nd1.l0.m4.o16 44 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(44) 121 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVZ, 3, {REG_GPR|BITS16,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+16523, 356},
    /*   7 : CFCMOVZ reg16,rm16 [rm:      evex.nf1.nd0.l0.m4.o16 44 /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7d 0c) 300 320 001(44) 110 : SM0,SM1,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVZ, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16683, 354},
    /*   8 : CFCMOVZ reg16?,rm16 [v+rm:      evex.nf1.nd1.l0.m4.o16 44 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7d 1c) 300 320 001(44) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVZ, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+16843, 357},
    /*   9 : CFCMOVZ reg32?,reg32,rm32 [vrm:      evex.nf1.nd1.l0.m4.o32 44 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(44) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVZ, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+17003, 358},
    /*  10 : CFCMOVZ reg32,rm32 [rm:      evex.nf1.nd0.l0.m4.o32 44 /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 7c 0c) 300 321 001(44) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVZ, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17163, 355},
    /*  11 : CFCMOVZ reg32?,rm32 [v+rm:      evex.nf1.nd1.l0.m4.o32 44 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 7c 1c) 300 321 001(44) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVZ, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17323, 359},
    /*  12 : CFCMOVZ reg64?,reg64,rm64 [vrm:      evex.nf1.nd1.l0.m4.o64 44 /r    ] SM0,SM1,SM2,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(44) 121 : SM0,SM1,SM2,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVZ, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+17483, 358},
    /*  13 : CFCMOVZ reg64,rm64 [rm:      evex.nf1.nd0.l0.m4.o64 44 /r    ] SM0,SM1,LONG,PROT,APX,X86_64 */
        /* 250(f4 fc 0c) 300 324 001(44) 110 : SM0,SM1,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVZ, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17643, 355},
    /*  14 : CFCMOVZ reg64?,rm64 [v+rm:      evex.nf1.nd1.l0.m4.o64 44 /r    ] ND,SM0,SM1,ZU,LONG,PROT,APX,X86_64 */
        /* 240(f4 fc 1c) 300 324 001(44) 110 : SM0,SM1,ZU,WW,LONG,EVEX,PROT,APX,X86_64 */
        {I_CFCMOVZ, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17803, 359},
};

static const struct itemplate instrux_SETA[4] = {
    /*   0 : SETA rm8 [m:        0f 97 /0                        ] AR0,SB,386 */
        /* 355 001(97) 200 : AR0,SB,386 */
        {I_SETA, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72223, 360},
    /*   1 : SETA reg64 [m:        evex.nd1.l0.f2.m4.wig 47 /0     ] ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(47) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETA, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25191, 361},
    /*   2 : SETA reg32 [m:        evex.nd1.l0.f2.m4.wig 47 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(47) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETA, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25191, 361},
    /*   3 : SETA rm8 [m:        evex.zu.l0.f2.m4.wig 47 /0      ] LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 08) 300 001(47) 200 : ZU,ZU_E,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETA, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25335, 362},
};

static const struct itemplate instrux_SETAE[4] = {
    /*   0 : SETAE rm8 [m:        0f 93 /0                        ] AR0,SB,386,ND */
        /* 355 001(93) 200 : AR0,SB,386 */
        {I_SETAE, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72228, 360},
    /*   1 : SETAE reg64 [m:        evex.nd1.l0.f2.m4.wig 43 /0     ] ZU,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7f 18) 300 001(43) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETAE, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25200, 361},
    /*   2 : SETAE reg32 [m:        evex.nd1.l0.f2.m4.wig 43 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(43) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETAE, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25200, 361},
    /*   3 : SETAE rm8 [m:        evex.zu.l0.f2.m4.wig 43 /0      ] LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7f 08) 300 001(43) 200 : ZU,ZU_E,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETAE, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25344, 362},
};

static const struct itemplate instrux_SETB[4] = {
    /*   0 : SETB rm8 [m:        0f 92 /0                        ] AR0,SB,386,ND */
        /* 355 001(92) 200 : AR0,SB,386 */
        {I_SETB, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72233, 360},
    /*   1 : SETB reg64 [m:        evex.nd1.l0.f2.m4.wig 42 /0     ] ZU,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7f 18) 300 001(42) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETB, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25209, 361},
    /*   2 : SETB reg32 [m:        evex.nd1.l0.f2.m4.wig 42 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(42) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETB, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25209, 361},
    /*   3 : SETB rm8 [m:        evex.zu.l0.f2.m4.wig 42 /0      ] LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7f 08) 300 001(42) 200 : ZU,ZU_E,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETB, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25353, 362},
};

static const struct itemplate instrux_SETBE[4] = {
    /*   0 : SETBE rm8 [m:        0f 96 /0                        ] AR0,SB,386,ND */
        /* 355 001(96) 200 : AR0,SB,386 */
        {I_SETBE, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72238, 360},
    /*   1 : SETBE reg64 [m:        evex.nd1.l0.f2.m4.wig 46 /0     ] ZU,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7f 18) 300 001(46) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETBE, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25218, 361},
    /*   2 : SETBE reg32 [m:        evex.nd1.l0.f2.m4.wig 46 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(46) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETBE, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25218, 361},
    /*   3 : SETBE rm8 [m:        evex.zu.l0.f2.m4.wig 46 /0      ] LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7f 08) 300 001(46) 200 : ZU,ZU_E,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETBE, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25362, 362},
};

static const struct itemplate instrux_SETC[4] = {
    /*   0 : SETC rm8 [m:        0f 92 /0                        ] AR0,SB,386 */
        /* 355 001(92) 200 : AR0,SB,386 */
        {I_SETC, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72233, 360},
    /*   1 : SETC reg64 [m:        evex.nd1.l0.f2.m4.wig 42 /0     ] ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(42) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETC, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25209, 361},
    /*   2 : SETC reg32 [m:        evex.nd1.l0.f2.m4.wig 42 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(42) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETC, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25209, 361},
    /*   3 : SETC rm8 [m:        evex.zu.l0.f2.m4.wig 42 /0      ] LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 08) 300 001(42) 200 : ZU,ZU_E,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETC, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25353, 362},
};

static const struct itemplate instrux_SETE[4] = {
    /*   0 : SETE rm8 [m:        0f 94 /0                        ] AR0,SB,386,ND */
        /* 355 001(94) 200 : AR0,SB,386 */
        {I_SETE, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72243, 360},
    /*   1 : SETE reg64 [m:        evex.nd1.l0.f2.m4.wig 44 /0     ] ZU,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7f 18) 300 001(44) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETE, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25227, 361},
    /*   2 : SETE reg32 [m:        evex.nd1.l0.f2.m4.wig 44 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(44) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETE, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25227, 361},
    /*   3 : SETE rm8 [m:        evex.zu.l0.f2.m4.wig 44 /0      ] LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7f 08) 300 001(44) 200 : ZU,ZU_E,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETE, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25371, 362},
};

static const struct itemplate instrux_SETG[4] = {
    /*   0 : SETG rm8 [m:        0f 9f /0                        ] AR0,SB,386 */
        /* 355 001(9f) 200 : AR0,SB,386 */
        {I_SETG, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72248, 360},
    /*   1 : SETG reg64 [m:        evex.nd1.l0.f2.m4.wig 4f /0     ] ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4f) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETG, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25236, 361},
    /*   2 : SETG reg32 [m:        evex.nd1.l0.f2.m4.wig 4f /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4f) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETG, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25236, 361},
    /*   3 : SETG rm8 [m:        evex.zu.l0.f2.m4.wig 4f /0      ] LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 08) 300 001(4f) 200 : ZU,ZU_E,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETG, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25380, 362},
};

static const struct itemplate instrux_SETGE[4] = {
    /*   0 : SETGE rm8 [m:        0f 9d /0                        ] AR0,SB,386,ND */
        /* 355 001(9d) 200 : AR0,SB,386 */
        {I_SETGE, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72253, 360},
    /*   1 : SETGE reg64 [m:        evex.nd1.l0.f2.m4.wig 4d /0     ] ZU,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7f 18) 300 001(4d) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETGE, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25245, 361},
    /*   2 : SETGE reg32 [m:        evex.nd1.l0.f2.m4.wig 4d /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4d) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETGE, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25245, 361},
    /*   3 : SETGE rm8 [m:        evex.zu.l0.f2.m4.wig 4d /0      ] LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7f 08) 300 001(4d) 200 : ZU,ZU_E,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETGE, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25389, 362},
};

static const struct itemplate instrux_SETL[4] = {
    /*   0 : SETL rm8 [m:        0f 9c /0                        ] AR0,SB,386 */
        /* 355 001(9c) 200 : AR0,SB,386 */
        {I_SETL, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72258, 360},
    /*   1 : SETL reg64 [m:        evex.nd1.l0.f2.m4.wig 4c /0     ] ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4c) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETL, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25254, 361},
    /*   2 : SETL reg32 [m:        evex.nd1.l0.f2.m4.wig 4c /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4c) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETL, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25254, 361},
    /*   3 : SETL rm8 [m:        evex.zu.l0.f2.m4.wig 4c /0      ] LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 08) 300 001(4c) 200 : ZU,ZU_E,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETL, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25398, 362},
};

static const struct itemplate instrux_SETLE[4] = {
    /*   0 : SETLE rm8 [m:        0f 9e /0                        ] AR0,SB,386,ND */
        /* 355 001(9e) 200 : AR0,SB,386 */
        {I_SETLE, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72263, 360},
    /*   1 : SETLE reg64 [m:        evex.nd1.l0.f2.m4.wig 4e /0     ] ZU,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7f 18) 300 001(4e) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETLE, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25263, 361},
    /*   2 : SETLE reg32 [m:        evex.nd1.l0.f2.m4.wig 4e /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4e) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETLE, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25263, 361},
    /*   3 : SETLE rm8 [m:        evex.zu.l0.f2.m4.wig 4e /0      ] LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7f 08) 300 001(4e) 200 : ZU,ZU_E,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETLE, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25407, 362},
};

static const struct itemplate instrux_SETNA[4] = {
    /*   0 : SETNA rm8 [m:        0f 96 /0                        ] AR0,SB,386 */
        /* 355 001(96) 200 : AR0,SB,386 */
        {I_SETNA, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72238, 360},
    /*   1 : SETNA reg64 [m:        evex.nd1.l0.f2.m4.wig 46 /0     ] ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(46) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNA, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25218, 361},
    /*   2 : SETNA reg32 [m:        evex.nd1.l0.f2.m4.wig 46 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(46) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNA, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25218, 361},
    /*   3 : SETNA rm8 [m:        evex.zu.l0.f2.m4.wig 46 /0      ] LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 08) 300 001(46) 200 : ZU,ZU_E,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNA, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25362, 362},
};

static const struct itemplate instrux_SETNAE[4] = {
    /*   0 : SETNAE rm8 [m:        0f 92 /0                        ] AR0,SB,386,ND */
        /* 355 001(92) 200 : AR0,SB,386 */
        {I_SETNAE, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72233, 360},
    /*   1 : SETNAE reg64 [m:        evex.nd1.l0.f2.m4.wig 42 /0     ] ZU,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7f 18) 300 001(42) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNAE, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25209, 361},
    /*   2 : SETNAE reg32 [m:        evex.nd1.l0.f2.m4.wig 42 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(42) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNAE, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25209, 361},
    /*   3 : SETNAE rm8 [m:        evex.zu.l0.f2.m4.wig 42 /0      ] LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7f 08) 300 001(42) 200 : ZU,ZU_E,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNAE, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25353, 362},
};

static const struct itemplate instrux_SETNB[4] = {
    /*   0 : SETNB rm8 [m:        0f 93 /0                        ] AR0,SB,386,ND */
        /* 355 001(93) 200 : AR0,SB,386 */
        {I_SETNB, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72228, 360},
    /*   1 : SETNB reg64 [m:        evex.nd1.l0.f2.m4.wig 43 /0     ] ZU,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7f 18) 300 001(43) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNB, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25200, 361},
    /*   2 : SETNB reg32 [m:        evex.nd1.l0.f2.m4.wig 43 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(43) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNB, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25200, 361},
    /*   3 : SETNB rm8 [m:        evex.zu.l0.f2.m4.wig 43 /0      ] LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7f 08) 300 001(43) 200 : ZU,ZU_E,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNB, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25344, 362},
};

static const struct itemplate instrux_SETNBE[4] = {
    /*   0 : SETNBE rm8 [m:        0f 97 /0                        ] AR0,SB,386,ND */
        /* 355 001(97) 200 : AR0,SB,386 */
        {I_SETNBE, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72223, 360},
    /*   1 : SETNBE reg64 [m:        evex.nd1.l0.f2.m4.wig 47 /0     ] ZU,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7f 18) 300 001(47) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNBE, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25191, 361},
    /*   2 : SETNBE reg32 [m:        evex.nd1.l0.f2.m4.wig 47 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(47) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNBE, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25191, 361},
    /*   3 : SETNBE rm8 [m:        evex.zu.l0.f2.m4.wig 47 /0      ] LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7f 08) 300 001(47) 200 : ZU,ZU_E,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNBE, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25335, 362},
};

static const struct itemplate instrux_SETNC[4] = {
    /*   0 : SETNC rm8 [m:        0f 93 /0                        ] AR0,SB,386 */
        /* 355 001(93) 200 : AR0,SB,386 */
        {I_SETNC, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72228, 360},
    /*   1 : SETNC reg64 [m:        evex.nd1.l0.f2.m4.wig 43 /0     ] ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(43) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNC, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25200, 361},
    /*   2 : SETNC reg32 [m:        evex.nd1.l0.f2.m4.wig 43 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(43) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNC, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25200, 361},
    /*   3 : SETNC rm8 [m:        evex.zu.l0.f2.m4.wig 43 /0      ] LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 08) 300 001(43) 200 : ZU,ZU_E,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNC, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25344, 362},
};

static const struct itemplate instrux_SETNE[4] = {
    /*   0 : SETNE rm8 [m:        0f 95 /0                        ] AR0,SB,386,ND */
        /* 355 001(95) 200 : AR0,SB,386 */
        {I_SETNE, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72268, 360},
    /*   1 : SETNE reg64 [m:        evex.nd1.l0.f2.m4.wig 45 /0     ] ZU,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7f 18) 300 001(45) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNE, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25272, 361},
    /*   2 : SETNE reg32 [m:        evex.nd1.l0.f2.m4.wig 45 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(45) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNE, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25272, 361},
    /*   3 : SETNE rm8 [m:        evex.zu.l0.f2.m4.wig 45 /0      ] LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7f 08) 300 001(45) 200 : ZU,ZU_E,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNE, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25416, 362},
};

static const struct itemplate instrux_SETNG[4] = {
    /*   0 : SETNG rm8 [m:        0f 9e /0                        ] AR0,SB,386 */
        /* 355 001(9e) 200 : AR0,SB,386 */
        {I_SETNG, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72263, 360},
    /*   1 : SETNG reg64 [m:        evex.nd1.l0.f2.m4.wig 4e /0     ] ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4e) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNG, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25263, 361},
    /*   2 : SETNG reg32 [m:        evex.nd1.l0.f2.m4.wig 4e /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4e) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNG, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25263, 361},
    /*   3 : SETNG rm8 [m:        evex.zu.l0.f2.m4.wig 4e /0      ] LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 08) 300 001(4e) 200 : ZU,ZU_E,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNG, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25407, 362},
};

static const struct itemplate instrux_SETNGE[4] = {
    /*   0 : SETNGE rm8 [m:        0f 9c /0                        ] AR0,SB,386,ND */
        /* 355 001(9c) 200 : AR0,SB,386 */
        {I_SETNGE, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72258, 360},
    /*   1 : SETNGE reg64 [m:        evex.nd1.l0.f2.m4.wig 4c /0     ] ZU,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7f 18) 300 001(4c) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNGE, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25254, 361},
    /*   2 : SETNGE reg32 [m:        evex.nd1.l0.f2.m4.wig 4c /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4c) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNGE, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25254, 361},
    /*   3 : SETNGE rm8 [m:        evex.zu.l0.f2.m4.wig 4c /0      ] LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7f 08) 300 001(4c) 200 : ZU,ZU_E,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNGE, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25398, 362},
};

static const struct itemplate instrux_SETNL[4] = {
    /*   0 : SETNL rm8 [m:        0f 9d /0                        ] AR0,SB,386 */
        /* 355 001(9d) 200 : AR0,SB,386 */
        {I_SETNL, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72253, 360},
    /*   1 : SETNL reg64 [m:        evex.nd1.l0.f2.m4.wig 4d /0     ] ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4d) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNL, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25245, 361},
    /*   2 : SETNL reg32 [m:        evex.nd1.l0.f2.m4.wig 4d /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4d) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNL, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25245, 361},
    /*   3 : SETNL rm8 [m:        evex.zu.l0.f2.m4.wig 4d /0      ] LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 08) 300 001(4d) 200 : ZU,ZU_E,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNL, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25389, 362},
};

static const struct itemplate instrux_SETNLE[4] = {
    /*   0 : SETNLE rm8 [m:        0f 9f /0                        ] AR0,SB,386,ND */
        /* 355 001(9f) 200 : AR0,SB,386 */
        {I_SETNLE, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72248, 360},
    /*   1 : SETNLE reg64 [m:        evex.nd1.l0.f2.m4.wig 4f /0     ] ZU,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7f 18) 300 001(4f) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNLE, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25236, 361},
    /*   2 : SETNLE reg32 [m:        evex.nd1.l0.f2.m4.wig 4f /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4f) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNLE, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25236, 361},
    /*   3 : SETNLE rm8 [m:        evex.zu.l0.f2.m4.wig 4f /0      ] LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7f 08) 300 001(4f) 200 : ZU,ZU_E,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNLE, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25380, 362},
};

static const struct itemplate instrux_SETNO[4] = {
    /*   0 : SETNO rm8 [m:        0f 91 /0                        ] AR0,SB,386 */
        /* 355 001(91) 200 : AR0,SB,386 */
        {I_SETNO, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72273, 360},
    /*   1 : SETNO reg64 [m:        evex.nd1.l0.f2.m4.wig 41 /0     ] ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(41) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNO, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25281, 361},
    /*   2 : SETNO reg32 [m:        evex.nd1.l0.f2.m4.wig 41 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(41) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNO, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25281, 361},
    /*   3 : SETNO rm8 [m:        evex.zu.l0.f2.m4.wig 41 /0      ] LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 08) 300 001(41) 200 : ZU,ZU_E,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNO, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25425, 362},
};

static const struct itemplate instrux_SETNP[4] = {
    /*   0 : SETNP rm8 [m:        0f 9b /0                        ] AR0,SB,386,ND */
        /* 355 001(9b) 200 : AR0,SB,386 */
        {I_SETNP, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72278, 360},
    /*   1 : SETNP reg64 [m:        evex.nd1.l0.f2.m4.wig 4b /0     ] ZU,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7f 18) 300 001(4b) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNP, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25290, 361},
    /*   2 : SETNP reg32 [m:        evex.nd1.l0.f2.m4.wig 4b /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4b) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNP, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25290, 361},
    /*   3 : SETNP rm8 [m:        evex.zu.l0.f2.m4.wig 4b /0      ] LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7f 08) 300 001(4b) 200 : ZU,ZU_E,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNP, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25434, 362},
};

static const struct itemplate instrux_SETNS[4] = {
    /*   0 : SETNS rm8 [m:        0f 99 /0                        ] AR0,SB,386 */
        /* 355 001(99) 200 : AR0,SB,386 */
        {I_SETNS, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72283, 360},
    /*   1 : SETNS reg64 [m:        evex.nd1.l0.f2.m4.wig 49 /0     ] ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(49) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNS, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25299, 361},
    /*   2 : SETNS reg32 [m:        evex.nd1.l0.f2.m4.wig 49 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(49) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNS, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25299, 361},
    /*   3 : SETNS rm8 [m:        evex.zu.l0.f2.m4.wig 49 /0      ] LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 08) 300 001(49) 200 : ZU,ZU_E,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNS, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25443, 362},
};

static const struct itemplate instrux_SETNZ[4] = {
    /*   0 : SETNZ rm8 [m:        0f 95 /0                        ] AR0,SB,386 */
        /* 355 001(95) 200 : AR0,SB,386 */
        {I_SETNZ, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72268, 360},
    /*   1 : SETNZ reg64 [m:        evex.nd1.l0.f2.m4.wig 45 /0     ] ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(45) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNZ, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25272, 361},
    /*   2 : SETNZ reg32 [m:        evex.nd1.l0.f2.m4.wig 45 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(45) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNZ, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25272, 361},
    /*   3 : SETNZ rm8 [m:        evex.zu.l0.f2.m4.wig 45 /0      ] LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 08) 300 001(45) 200 : ZU,ZU_E,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNZ, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25416, 362},
};

static const struct itemplate instrux_SETO[4] = {
    /*   0 : SETO rm8 [m:        0f 90 /0                        ] AR0,SB,386 */
        /* 355 001(90) 200 : AR0,SB,386 */
        {I_SETO, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72288, 360},
    /*   1 : SETO reg64 [m:        evex.nd1.l0.f2.m4.wig 40 /0     ] ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(40) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETO, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25308, 361},
    /*   2 : SETO reg32 [m:        evex.nd1.l0.f2.m4.wig 40 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(40) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETO, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25308, 361},
    /*   3 : SETO rm8 [m:        evex.zu.l0.f2.m4.wig 40 /0      ] LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 08) 300 001(40) 200 : ZU,ZU_E,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETO, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25452, 362},
};

static const struct itemplate instrux_SETP[4] = {
    /*   0 : SETP rm8 [m:        0f 9a /0                        ] AR0,SB,386,ND */
        /* 355 001(9a) 200 : AR0,SB,386 */
        {I_SETP, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72293, 360},
    /*   1 : SETP reg64 [m:        evex.nd1.l0.f2.m4.wig 4a /0     ] ZU,LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7f 18) 300 001(4a) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETP, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25317, 361},
    /*   2 : SETP reg32 [m:        evex.nd1.l0.f2.m4.wig 4a /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4a) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETP, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25317, 361},
    /*   3 : SETP rm8 [m:        evex.zu.l0.f2.m4.wig 4a /0      ] LONG,PROT,APX,X86_64,ND */
        /* 250(f4 7f 08) 300 001(4a) 200 : ZU,ZU_E,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETP, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25461, 362},
};

static const struct itemplate instrux_SETPE[4] = {
    /*   0 : SETPE rm8 [m:        0f 9a /0                        ] AR0,SB,386 */
        /* 355 001(9a) 200 : AR0,SB,386 */
        {I_SETPE, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72293, 360},
    /*   1 : SETPE reg64 [m:        evex.nd1.l0.f2.m4.wig 4a /0     ] ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4a) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETPE, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25317, 361},
    /*   2 : SETPE reg32 [m:        evex.nd1.l0.f2.m4.wig 4a /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4a) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETPE, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25317, 361},
    /*   3 : SETPE rm8 [m:        evex.zu.l0.f2.m4.wig 4a /0      ] LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 08) 300 001(4a) 200 : ZU,ZU_E,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETPE, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25461, 362},
};

static const struct itemplate instrux_SETPO[4] = {
    /*   0 : SETPO rm8 [m:        0f 9b /0                        ] AR0,SB,386 */
        /* 355 001(9b) 200 : AR0,SB,386 */
        {I_SETPO, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72278, 360},
    /*   1 : SETPO reg64 [m:        evex.nd1.l0.f2.m4.wig 4b /0     ] ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4b) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETPO, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25290, 361},
    /*   2 : SETPO reg32 [m:        evex.nd1.l0.f2.m4.wig 4b /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4b) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETPO, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25290, 361},
    /*   3 : SETPO rm8 [m:        evex.zu.l0.f2.m4.wig 4b /0      ] LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 08) 300 001(4b) 200 : ZU,ZU_E,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETPO, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25434, 362},
};

static const struct itemplate instrux_SETS[4] = {
    /*   0 : SETS rm8 [m:        0f 98 /0                        ] AR0,SB,386 */
        /* 355 001(98) 200 : AR0,SB,386 */
        {I_SETS, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72298, 360},
    /*   1 : SETS reg64 [m:        evex.nd1.l0.f2.m4.wig 48 /0     ] ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(48) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETS, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25326, 361},
    /*   2 : SETS reg32 [m:        evex.nd1.l0.f2.m4.wig 48 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(48) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETS, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25326, 361},
    /*   3 : SETS rm8 [m:        evex.zu.l0.f2.m4.wig 48 /0      ] LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 08) 300 001(48) 200 : ZU,ZU_E,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETS, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25470, 362},
};

static const struct itemplate instrux_SETZ[4] = {
    /*   0 : SETZ rm8 [m:        0f 94 /0                        ] AR0,SB,386 */
        /* 355 001(94) 200 : AR0,SB,386 */
        {I_SETZ, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72243, 360},
    /*   1 : SETZ reg64 [m:        evex.nd1.l0.f2.m4.wig 44 /0     ] ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(44) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETZ, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25227, 361},
    /*   2 : SETZ reg32 [m:        evex.nd1.l0.f2.m4.wig 44 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(44) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETZ, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25227, 361},
    /*   3 : SETZ rm8 [m:        evex.zu.l0.f2.m4.wig 44 /0      ] LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 08) 300 001(44) 200 : ZU,ZU_E,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETZ, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25371, 362},
};

static const struct itemplate instrux_SETAZU[3] = {
    /*   0 : SETAZU reg64 [m:        evex.nd1.l0.f2.m4.wig 47 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(47) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETAZU, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25191, 361},
    /*   1 : SETAZU reg32 [m:        evex.nd1.l0.f2.m4.wig 47 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(47) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETAZU, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25191, 361},
    /*   2 : SETAZU rm8 [m:        evex.nd1.l0.f2.m4.wig 47 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(47) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETAZU, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25191, 361},
};

static const struct itemplate instrux_SETAEZU[3] = {
    /*   0 : SETAEZU reg64 [m:        evex.nd1.l0.f2.m4.wig 43 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(43) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETAEZU, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25200, 361},
    /*   1 : SETAEZU reg32 [m:        evex.nd1.l0.f2.m4.wig 43 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(43) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETAEZU, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25200, 361},
    /*   2 : SETAEZU rm8 [m:        evex.nd1.l0.f2.m4.wig 43 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(43) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETAEZU, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25200, 361},
};

static const struct itemplate instrux_SETBZU[3] = {
    /*   0 : SETBZU reg64 [m:        evex.nd1.l0.f2.m4.wig 42 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(42) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETBZU, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25209, 361},
    /*   1 : SETBZU reg32 [m:        evex.nd1.l0.f2.m4.wig 42 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(42) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETBZU, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25209, 361},
    /*   2 : SETBZU rm8 [m:        evex.nd1.l0.f2.m4.wig 42 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(42) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETBZU, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25209, 361},
};

static const struct itemplate instrux_SETBEZU[3] = {
    /*   0 : SETBEZU reg64 [m:        evex.nd1.l0.f2.m4.wig 46 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(46) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETBEZU, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25218, 361},
    /*   1 : SETBEZU reg32 [m:        evex.nd1.l0.f2.m4.wig 46 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(46) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETBEZU, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25218, 361},
    /*   2 : SETBEZU rm8 [m:        evex.nd1.l0.f2.m4.wig 46 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(46) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETBEZU, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25218, 361},
};

static const struct itemplate instrux_SETCZU[3] = {
    /*   0 : SETCZU reg64 [m:        evex.nd1.l0.f2.m4.wig 42 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(42) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETCZU, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25209, 361},
    /*   1 : SETCZU reg32 [m:        evex.nd1.l0.f2.m4.wig 42 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(42) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETCZU, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25209, 361},
    /*   2 : SETCZU rm8 [m:        evex.nd1.l0.f2.m4.wig 42 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(42) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETCZU, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25209, 361},
};

static const struct itemplate instrux_SETEZU[3] = {
    /*   0 : SETEZU reg64 [m:        evex.nd1.l0.f2.m4.wig 44 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(44) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETEZU, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25227, 361},
    /*   1 : SETEZU reg32 [m:        evex.nd1.l0.f2.m4.wig 44 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(44) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETEZU, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25227, 361},
    /*   2 : SETEZU rm8 [m:        evex.nd1.l0.f2.m4.wig 44 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(44) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETEZU, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25227, 361},
};

static const struct itemplate instrux_SETGZU[3] = {
    /*   0 : SETGZU reg64 [m:        evex.nd1.l0.f2.m4.wig 4f /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4f) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETGZU, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25236, 361},
    /*   1 : SETGZU reg32 [m:        evex.nd1.l0.f2.m4.wig 4f /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4f) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETGZU, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25236, 361},
    /*   2 : SETGZU rm8 [m:        evex.nd1.l0.f2.m4.wig 4f /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4f) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETGZU, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25236, 361},
};

static const struct itemplate instrux_SETGEZU[3] = {
    /*   0 : SETGEZU reg64 [m:        evex.nd1.l0.f2.m4.wig 4d /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4d) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETGEZU, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25245, 361},
    /*   1 : SETGEZU reg32 [m:        evex.nd1.l0.f2.m4.wig 4d /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4d) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETGEZU, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25245, 361},
    /*   2 : SETGEZU rm8 [m:        evex.nd1.l0.f2.m4.wig 4d /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4d) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETGEZU, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25245, 361},
};

static const struct itemplate instrux_SETLZU[3] = {
    /*   0 : SETLZU reg64 [m:        evex.nd1.l0.f2.m4.wig 4c /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4c) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETLZU, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25254, 361},
    /*   1 : SETLZU reg32 [m:        evex.nd1.l0.f2.m4.wig 4c /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4c) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETLZU, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25254, 361},
    /*   2 : SETLZU rm8 [m:        evex.nd1.l0.f2.m4.wig 4c /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4c) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETLZU, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25254, 361},
};

static const struct itemplate instrux_SETLEZU[3] = {
    /*   0 : SETLEZU reg64 [m:        evex.nd1.l0.f2.m4.wig 4e /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4e) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETLEZU, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25263, 361},
    /*   1 : SETLEZU reg32 [m:        evex.nd1.l0.f2.m4.wig 4e /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4e) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETLEZU, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25263, 361},
    /*   2 : SETLEZU rm8 [m:        evex.nd1.l0.f2.m4.wig 4e /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4e) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETLEZU, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25263, 361},
};

static const struct itemplate instrux_SETNAZU[3] = {
    /*   0 : SETNAZU reg64 [m:        evex.nd1.l0.f2.m4.wig 46 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(46) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNAZU, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25218, 361},
    /*   1 : SETNAZU reg32 [m:        evex.nd1.l0.f2.m4.wig 46 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(46) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNAZU, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25218, 361},
    /*   2 : SETNAZU rm8 [m:        evex.nd1.l0.f2.m4.wig 46 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(46) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNAZU, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25218, 361},
};

static const struct itemplate instrux_SETNAEZU[3] = {
    /*   0 : SETNAEZU reg64 [m:        evex.nd1.l0.f2.m4.wig 42 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(42) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNAEZU, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25209, 361},
    /*   1 : SETNAEZU reg32 [m:        evex.nd1.l0.f2.m4.wig 42 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(42) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNAEZU, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25209, 361},
    /*   2 : SETNAEZU rm8 [m:        evex.nd1.l0.f2.m4.wig 42 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(42) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNAEZU, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25209, 361},
};

static const struct itemplate instrux_SETNBZU[3] = {
    /*   0 : SETNBZU reg64 [m:        evex.nd1.l0.f2.m4.wig 43 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(43) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNBZU, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25200, 361},
    /*   1 : SETNBZU reg32 [m:        evex.nd1.l0.f2.m4.wig 43 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(43) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNBZU, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25200, 361},
    /*   2 : SETNBZU rm8 [m:        evex.nd1.l0.f2.m4.wig 43 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(43) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNBZU, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25200, 361},
};

static const struct itemplate instrux_SETNBEZU[3] = {
    /*   0 : SETNBEZU reg64 [m:        evex.nd1.l0.f2.m4.wig 47 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(47) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNBEZU, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25191, 361},
    /*   1 : SETNBEZU reg32 [m:        evex.nd1.l0.f2.m4.wig 47 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(47) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNBEZU, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25191, 361},
    /*   2 : SETNBEZU rm8 [m:        evex.nd1.l0.f2.m4.wig 47 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(47) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNBEZU, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25191, 361},
};

static const struct itemplate instrux_SETNCZU[3] = {
    /*   0 : SETNCZU reg64 [m:        evex.nd1.l0.f2.m4.wig 43 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(43) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNCZU, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25200, 361},
    /*   1 : SETNCZU reg32 [m:        evex.nd1.l0.f2.m4.wig 43 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(43) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNCZU, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25200, 361},
    /*   2 : SETNCZU rm8 [m:        evex.nd1.l0.f2.m4.wig 43 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(43) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNCZU, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25200, 361},
};

static const struct itemplate instrux_SETNEZU[3] = {
    /*   0 : SETNEZU reg64 [m:        evex.nd1.l0.f2.m4.wig 45 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(45) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNEZU, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25272, 361},
    /*   1 : SETNEZU reg32 [m:        evex.nd1.l0.f2.m4.wig 45 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(45) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNEZU, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25272, 361},
    /*   2 : SETNEZU rm8 [m:        evex.nd1.l0.f2.m4.wig 45 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(45) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNEZU, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25272, 361},
};

static const struct itemplate instrux_SETNGZU[3] = {
    /*   0 : SETNGZU reg64 [m:        evex.nd1.l0.f2.m4.wig 4e /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4e) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNGZU, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25263, 361},
    /*   1 : SETNGZU reg32 [m:        evex.nd1.l0.f2.m4.wig 4e /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4e) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNGZU, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25263, 361},
    /*   2 : SETNGZU rm8 [m:        evex.nd1.l0.f2.m4.wig 4e /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4e) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNGZU, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25263, 361},
};

static const struct itemplate instrux_SETNGEZU[3] = {
    /*   0 : SETNGEZU reg64 [m:        evex.nd1.l0.f2.m4.wig 4c /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4c) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNGEZU, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25254, 361},
    /*   1 : SETNGEZU reg32 [m:        evex.nd1.l0.f2.m4.wig 4c /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4c) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNGEZU, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25254, 361},
    /*   2 : SETNGEZU rm8 [m:        evex.nd1.l0.f2.m4.wig 4c /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4c) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNGEZU, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25254, 361},
};

static const struct itemplate instrux_SETNLZU[3] = {
    /*   0 : SETNLZU reg64 [m:        evex.nd1.l0.f2.m4.wig 4d /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4d) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNLZU, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25245, 361},
    /*   1 : SETNLZU reg32 [m:        evex.nd1.l0.f2.m4.wig 4d /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4d) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNLZU, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25245, 361},
    /*   2 : SETNLZU rm8 [m:        evex.nd1.l0.f2.m4.wig 4d /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4d) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNLZU, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25245, 361},
};

static const struct itemplate instrux_SETNLEZU[3] = {
    /*   0 : SETNLEZU reg64 [m:        evex.nd1.l0.f2.m4.wig 4f /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4f) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNLEZU, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25236, 361},
    /*   1 : SETNLEZU reg32 [m:        evex.nd1.l0.f2.m4.wig 4f /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4f) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNLEZU, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25236, 361},
    /*   2 : SETNLEZU rm8 [m:        evex.nd1.l0.f2.m4.wig 4f /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4f) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNLEZU, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25236, 361},
};

static const struct itemplate instrux_SETNOZU[3] = {
    /*   0 : SETNOZU reg64 [m:        evex.nd1.l0.f2.m4.wig 41 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(41) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNOZU, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25281, 361},
    /*   1 : SETNOZU reg32 [m:        evex.nd1.l0.f2.m4.wig 41 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(41) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNOZU, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25281, 361},
    /*   2 : SETNOZU rm8 [m:        evex.nd1.l0.f2.m4.wig 41 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(41) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNOZU, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25281, 361},
};

static const struct itemplate instrux_SETNPZU[3] = {
    /*   0 : SETNPZU reg64 [m:        evex.nd1.l0.f2.m4.wig 4b /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4b) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNPZU, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25290, 361},
    /*   1 : SETNPZU reg32 [m:        evex.nd1.l0.f2.m4.wig 4b /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4b) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNPZU, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25290, 361},
    /*   2 : SETNPZU rm8 [m:        evex.nd1.l0.f2.m4.wig 4b /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4b) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNPZU, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25290, 361},
};

static const struct itemplate instrux_SETNSZU[3] = {
    /*   0 : SETNSZU reg64 [m:        evex.nd1.l0.f2.m4.wig 49 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(49) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNSZU, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25299, 361},
    /*   1 : SETNSZU reg32 [m:        evex.nd1.l0.f2.m4.wig 49 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(49) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNSZU, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25299, 361},
    /*   2 : SETNSZU rm8 [m:        evex.nd1.l0.f2.m4.wig 49 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(49) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNSZU, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25299, 361},
};

static const struct itemplate instrux_SETNZZU[3] = {
    /*   0 : SETNZZU reg64 [m:        evex.nd1.l0.f2.m4.wig 45 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(45) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNZZU, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25272, 361},
    /*   1 : SETNZZU reg32 [m:        evex.nd1.l0.f2.m4.wig 45 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(45) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNZZU, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25272, 361},
    /*   2 : SETNZZU rm8 [m:        evex.nd1.l0.f2.m4.wig 45 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(45) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETNZZU, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25272, 361},
};

static const struct itemplate instrux_SETOZU[3] = {
    /*   0 : SETOZU reg64 [m:        evex.nd1.l0.f2.m4.wig 40 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(40) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETOZU, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25308, 361},
    /*   1 : SETOZU reg32 [m:        evex.nd1.l0.f2.m4.wig 40 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(40) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETOZU, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25308, 361},
    /*   2 : SETOZU rm8 [m:        evex.nd1.l0.f2.m4.wig 40 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(40) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETOZU, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25308, 361},
};

static const struct itemplate instrux_SETPZU[3] = {
    /*   0 : SETPZU reg64 [m:        evex.nd1.l0.f2.m4.wig 4a /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4a) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETPZU, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25317, 361},
    /*   1 : SETPZU reg32 [m:        evex.nd1.l0.f2.m4.wig 4a /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4a) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETPZU, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25317, 361},
    /*   2 : SETPZU rm8 [m:        evex.nd1.l0.f2.m4.wig 4a /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4a) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETPZU, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25317, 361},
};

static const struct itemplate instrux_SETPEZU[3] = {
    /*   0 : SETPEZU reg64 [m:        evex.nd1.l0.f2.m4.wig 4a /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4a) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETPEZU, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25317, 361},
    /*   1 : SETPEZU reg32 [m:        evex.nd1.l0.f2.m4.wig 4a /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4a) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETPEZU, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25317, 361},
    /*   2 : SETPEZU rm8 [m:        evex.nd1.l0.f2.m4.wig 4a /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4a) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETPEZU, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25317, 361},
};

static const struct itemplate instrux_SETPOZU[3] = {
    /*   0 : SETPOZU reg64 [m:        evex.nd1.l0.f2.m4.wig 4b /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4b) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETPOZU, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25290, 361},
    /*   1 : SETPOZU reg32 [m:        evex.nd1.l0.f2.m4.wig 4b /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4b) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETPOZU, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25290, 361},
    /*   2 : SETPOZU rm8 [m:        evex.nd1.l0.f2.m4.wig 4b /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(4b) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETPOZU, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25290, 361},
};

static const struct itemplate instrux_SETSZU[3] = {
    /*   0 : SETSZU reg64 [m:        evex.nd1.l0.f2.m4.wig 48 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(48) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETSZU, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25326, 361},
    /*   1 : SETSZU reg32 [m:        evex.nd1.l0.f2.m4.wig 48 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(48) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETSZU, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25326, 361},
    /*   2 : SETSZU rm8 [m:        evex.nd1.l0.f2.m4.wig 48 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(48) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETSZU, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25326, 361},
};

static const struct itemplate instrux_SETZZU[3] = {
    /*   0 : SETZZU reg64 [m:        evex.nd1.l0.f2.m4.wig 44 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(44) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETZZU, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25227, 361},
    /*   1 : SETZZU reg32 [m:        evex.nd1.l0.f2.m4.wig 44 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(44) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETZZU, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25227, 361},
    /*   2 : SETZZU rm8 [m:        evex.nd1.l0.f2.m4.wig 44 /0     ] ND,ZU,LONG,PROT,APX,X86_64 */
        /* 250(f4 7f 18) 300 001(44) 200 : ZU,WIG,LONG,EVEX,PROT,APX,X86_64 */
        {I_SETZZU, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+25227, 361},
};

static const struct itemplate instrux_CMPAXADD[4] = {
    /*   0 : CMPAXADD mem32,reg32,reg32 [mrv:      vex.128.66.0f38.w0 e7 /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64 */
        /* 262(002 001) 001(e7) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPAXADD, 3, {MEMORY|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57418, 363},
    /*   1 : CMPAXADD mem64,reg64,reg64 [mrv:      vex.128.66.0f38.w1 e7 /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64 */
        /* 262(002 201) 001(e7) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPAXADD, 3, {MEMORY|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57530, 363},
    /*   2 : CMPAXADD mem32,reg32,reg32 [mrv:      evex.nf0.128.66.0f38.w0 e7 /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64 */
        /* 242(f2 7d 08) 300 001(e7) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPAXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+25479, 364},
    /*   3 : CMPAXADD mem64,reg64,reg64 [mrv:      evex.nf0.128.66.0f38.w1 e7 /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64 */
        /* 242(f2 fd 08) 300 001(e7) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPAXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+25623, 364},
};

static const struct itemplate instrux_CMPAEXADD[4] = {
    /*   0 : CMPAEXADD mem32,reg32,reg32 [mrv:      vex.128.66.0f38.w0 e3 /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64,ND */
        /* 262(002 001) 001(e3) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPAEXADD, 3, {MEMORY|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57425, 363},
    /*   1 : CMPAEXADD mem64,reg64,reg64 [mrv:      vex.128.66.0f38.w1 e3 /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64,ND */
        /* 262(002 201) 001(e3) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPAEXADD, 3, {MEMORY|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57537, 363},
    /*   2 : CMPAEXADD mem32,reg32,reg32 [mrv:      evex.nf0.128.66.0f38.w0 e3 /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64,ND */
        /* 242(f2 7d 08) 300 001(e3) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPAEXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+25488, 364},
    /*   3 : CMPAEXADD mem64,reg64,reg64 [mrv:      evex.nf0.128.66.0f38.w1 e3 /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64,ND */
        /* 242(f2 fd 08) 300 001(e3) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPAEXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+25632, 364},
};

static const struct itemplate instrux_CMPBXADD[4] = {
    /*   0 : CMPBXADD mem32,reg32,reg32 [mrv:      vex.128.66.0f38.w0 e2 /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64,ND */
        /* 262(002 001) 001(e2) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPBXADD, 3, {MEMORY|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57432, 363},
    /*   1 : CMPBXADD mem64,reg64,reg64 [mrv:      vex.128.66.0f38.w1 e2 /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64,ND */
        /* 262(002 201) 001(e2) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPBXADD, 3, {MEMORY|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57544, 363},
    /*   2 : CMPBXADD mem32,reg32,reg32 [mrv:      evex.nf0.128.66.0f38.w0 e2 /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64,ND */
        /* 242(f2 7d 08) 300 001(e2) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPBXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+25497, 364},
    /*   3 : CMPBXADD mem64,reg64,reg64 [mrv:      evex.nf0.128.66.0f38.w1 e2 /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64,ND */
        /* 242(f2 fd 08) 300 001(e2) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPBXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+25641, 364},
};

static const struct itemplate instrux_CMPBEXADD[4] = {
    /*   0 : CMPBEXADD mem32,reg32,reg32 [mrv:      vex.128.66.0f38.w0 e6 /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64,ND */
        /* 262(002 001) 001(e6) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPBEXADD, 3, {MEMORY|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57439, 363},
    /*   1 : CMPBEXADD mem64,reg64,reg64 [mrv:      vex.128.66.0f38.w1 e6 /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64,ND */
        /* 262(002 201) 001(e6) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPBEXADD, 3, {MEMORY|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57551, 363},
    /*   2 : CMPBEXADD mem32,reg32,reg32 [mrv:      evex.nf0.128.66.0f38.w0 e6 /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64,ND */
        /* 242(f2 7d 08) 300 001(e6) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPBEXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+25506, 364},
    /*   3 : CMPBEXADD mem64,reg64,reg64 [mrv:      evex.nf0.128.66.0f38.w1 e6 /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64,ND */
        /* 242(f2 fd 08) 300 001(e6) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPBEXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+25650, 364},
};

static const struct itemplate instrux_CMPCXADD[4] = {
    /*   0 : CMPCXADD mem32,reg32,reg32 [mrv:      vex.128.66.0f38.w0 e2 /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64 */
        /* 262(002 001) 001(e2) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPCXADD, 3, {MEMORY|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57432, 363},
    /*   1 : CMPCXADD mem64,reg64,reg64 [mrv:      vex.128.66.0f38.w1 e2 /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64 */
        /* 262(002 201) 001(e2) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPCXADD, 3, {MEMORY|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57544, 363},
    /*   2 : CMPCXADD mem32,reg32,reg32 [mrv:      evex.nf0.128.66.0f38.w0 e2 /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64 */
        /* 242(f2 7d 08) 300 001(e2) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPCXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+25497, 364},
    /*   3 : CMPCXADD mem64,reg64,reg64 [mrv:      evex.nf0.128.66.0f38.w1 e2 /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64 */
        /* 242(f2 fd 08) 300 001(e2) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPCXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+25641, 364},
};

static const struct itemplate instrux_CMPEXADD[4] = {
    /*   0 : CMPEXADD mem32,reg32,reg32 [mrv:      vex.128.66.0f38.w0 e4 /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64,ND */
        /* 262(002 001) 001(e4) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPEXADD, 3, {MEMORY|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57446, 363},
    /*   1 : CMPEXADD mem64,reg64,reg64 [mrv:      vex.128.66.0f38.w1 e4 /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64,ND */
        /* 262(002 201) 001(e4) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPEXADD, 3, {MEMORY|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57558, 363},
    /*   2 : CMPEXADD mem32,reg32,reg32 [mrv:      evex.nf0.128.66.0f38.w0 e4 /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64,ND */
        /* 242(f2 7d 08) 300 001(e4) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPEXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+25515, 364},
    /*   3 : CMPEXADD mem64,reg64,reg64 [mrv:      evex.nf0.128.66.0f38.w1 e4 /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64,ND */
        /* 242(f2 fd 08) 300 001(e4) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPEXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+25659, 364},
};

static const struct itemplate instrux_CMPGXADD[4] = {
    /*   0 : CMPGXADD mem32,reg32,reg32 [mrv:      vex.128.66.0f38.w0 ef /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64 */
        /* 262(002 001) 001(ef) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPGXADD, 3, {MEMORY|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57453, 363},
    /*   1 : CMPGXADD mem64,reg64,reg64 [mrv:      vex.128.66.0f38.w1 ef /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64 */
        /* 262(002 201) 001(ef) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPGXADD, 3, {MEMORY|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57565, 363},
    /*   2 : CMPGXADD mem32,reg32,reg32 [mrv:      evex.nf0.128.66.0f38.w0 ef /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64 */
        /* 242(f2 7d 08) 300 001(ef) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPGXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+25524, 364},
    /*   3 : CMPGXADD mem64,reg64,reg64 [mrv:      evex.nf0.128.66.0f38.w1 ef /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64 */
        /* 242(f2 fd 08) 300 001(ef) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPGXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+25668, 364},
};

static const struct itemplate instrux_CMPGEXADD[4] = {
    /*   0 : CMPGEXADD mem32,reg32,reg32 [mrv:      vex.128.66.0f38.w0 ed /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64,ND */
        /* 262(002 001) 001(ed) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPGEXADD, 3, {MEMORY|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57460, 363},
    /*   1 : CMPGEXADD mem64,reg64,reg64 [mrv:      vex.128.66.0f38.w1 ed /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64,ND */
        /* 262(002 201) 001(ed) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPGEXADD, 3, {MEMORY|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57572, 363},
    /*   2 : CMPGEXADD mem32,reg32,reg32 [mrv:      evex.nf0.128.66.0f38.w0 ed /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64,ND */
        /* 242(f2 7d 08) 300 001(ed) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPGEXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+25533, 364},
    /*   3 : CMPGEXADD mem64,reg64,reg64 [mrv:      evex.nf0.128.66.0f38.w1 ed /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64,ND */
        /* 242(f2 fd 08) 300 001(ed) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPGEXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+25677, 364},
};

static const struct itemplate instrux_CMPLXADD[4] = {
    /*   0 : CMPLXADD mem32,reg32,reg32 [mrv:      vex.128.66.0f38.w0 ec /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64 */
        /* 262(002 001) 001(ec) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPLXADD, 3, {MEMORY|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57467, 363},
    /*   1 : CMPLXADD mem64,reg64,reg64 [mrv:      vex.128.66.0f38.w1 ec /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64 */
        /* 262(002 201) 001(ec) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPLXADD, 3, {MEMORY|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57579, 363},
    /*   2 : CMPLXADD mem32,reg32,reg32 [mrv:      evex.nf0.128.66.0f38.w0 ec /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64 */
        /* 242(f2 7d 08) 300 001(ec) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPLXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+25542, 364},
    /*   3 : CMPLXADD mem64,reg64,reg64 [mrv:      evex.nf0.128.66.0f38.w1 ec /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64 */
        /* 242(f2 fd 08) 300 001(ec) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPLXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+25686, 364},
};

static const struct itemplate instrux_CMPLEXADD[4] = {
    /*   0 : CMPLEXADD mem32,reg32,reg32 [mrv:      vex.128.66.0f38.w0 ee /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64,ND */
        /* 262(002 001) 001(ee) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPLEXADD, 3, {MEMORY|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57474, 363},
    /*   1 : CMPLEXADD mem64,reg64,reg64 [mrv:      vex.128.66.0f38.w1 ee /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64,ND */
        /* 262(002 201) 001(ee) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPLEXADD, 3, {MEMORY|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57586, 363},
    /*   2 : CMPLEXADD mem32,reg32,reg32 [mrv:      evex.nf0.128.66.0f38.w0 ee /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64,ND */
        /* 242(f2 7d 08) 300 001(ee) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPLEXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+25551, 364},
    /*   3 : CMPLEXADD mem64,reg64,reg64 [mrv:      evex.nf0.128.66.0f38.w1 ee /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64,ND */
        /* 242(f2 fd 08) 300 001(ee) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPLEXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+25695, 364},
};

static const struct itemplate instrux_CMPNAXADD[4] = {
    /*   0 : CMPNAXADD mem32,reg32,reg32 [mrv:      vex.128.66.0f38.w0 e6 /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64 */
        /* 262(002 001) 001(e6) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPNAXADD, 3, {MEMORY|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57439, 363},
    /*   1 : CMPNAXADD mem64,reg64,reg64 [mrv:      vex.128.66.0f38.w1 e6 /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64 */
        /* 262(002 201) 001(e6) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPNAXADD, 3, {MEMORY|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57551, 363},
    /*   2 : CMPNAXADD mem32,reg32,reg32 [mrv:      evex.nf0.128.66.0f38.w0 e6 /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64 */
        /* 242(f2 7d 08) 300 001(e6) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPNAXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+25506, 364},
    /*   3 : CMPNAXADD mem64,reg64,reg64 [mrv:      evex.nf0.128.66.0f38.w1 e6 /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64 */
        /* 242(f2 fd 08) 300 001(e6) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPNAXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+25650, 364},
};

static const struct itemplate instrux_CMPNAEXADD[4] = {
    /*   0 : CMPNAEXADD mem32,reg32,reg32 [mrv:      vex.128.66.0f38.w0 e2 /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64,ND */
        /* 262(002 001) 001(e2) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPNAEXADD, 3, {MEMORY|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57432, 363},
    /*   1 : CMPNAEXADD mem64,reg64,reg64 [mrv:      vex.128.66.0f38.w1 e2 /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64,ND */
        /* 262(002 201) 001(e2) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPNAEXADD, 3, {MEMORY|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57544, 363},
    /*   2 : CMPNAEXADD mem32,reg32,reg32 [mrv:      evex.nf0.128.66.0f38.w0 e2 /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64,ND */
        /* 242(f2 7d 08) 300 001(e2) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPNAEXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+25497, 364},
    /*   3 : CMPNAEXADD mem64,reg64,reg64 [mrv:      evex.nf0.128.66.0f38.w1 e2 /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64,ND */
        /* 242(f2 fd 08) 300 001(e2) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPNAEXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+25641, 364},
};

static const struct itemplate instrux_CMPNBXADD[4] = {
    /*   0 : CMPNBXADD mem32,reg32,reg32 [mrv:      vex.128.66.0f38.w0 e3 /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64,ND */
        /* 262(002 001) 001(e3) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPNBXADD, 3, {MEMORY|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57425, 363},
    /*   1 : CMPNBXADD mem64,reg64,reg64 [mrv:      vex.128.66.0f38.w1 e3 /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64,ND */
        /* 262(002 201) 001(e3) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPNBXADD, 3, {MEMORY|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57537, 363},
    /*   2 : CMPNBXADD mem32,reg32,reg32 [mrv:      evex.nf0.128.66.0f38.w0 e3 /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64,ND */
        /* 242(f2 7d 08) 300 001(e3) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPNBXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+25488, 364},
    /*   3 : CMPNBXADD mem64,reg64,reg64 [mrv:      evex.nf0.128.66.0f38.w1 e3 /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64,ND */
        /* 242(f2 fd 08) 300 001(e3) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPNBXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+25632, 364},
};

static const struct itemplate instrux_CMPNBEXADD[4] = {
    /*   0 : CMPNBEXADD mem32,reg32,reg32 [mrv:      vex.128.66.0f38.w0 e7 /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64,ND */
        /* 262(002 001) 001(e7) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPNBEXADD, 3, {MEMORY|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57418, 363},
    /*   1 : CMPNBEXADD mem64,reg64,reg64 [mrv:      vex.128.66.0f38.w1 e7 /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64,ND */
        /* 262(002 201) 001(e7) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPNBEXADD, 3, {MEMORY|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57530, 363},
    /*   2 : CMPNBEXADD mem32,reg32,reg32 [mrv:      evex.nf0.128.66.0f38.w0 e7 /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64,ND */
        /* 242(f2 7d 08) 300 001(e7) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPNBEXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+25479, 364},
    /*   3 : CMPNBEXADD mem64,reg64,reg64 [mrv:      evex.nf0.128.66.0f38.w1 e7 /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64,ND */
        /* 242(f2 fd 08) 300 001(e7) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPNBEXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+25623, 364},
};

static const struct itemplate instrux_CMPNCXADD[4] = {
    /*   0 : CMPNCXADD mem32,reg32,reg32 [mrv:      vex.128.66.0f38.w0 e3 /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64 */
        /* 262(002 001) 001(e3) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPNCXADD, 3, {MEMORY|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57425, 363},
    /*   1 : CMPNCXADD mem64,reg64,reg64 [mrv:      vex.128.66.0f38.w1 e3 /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64 */
        /* 262(002 201) 001(e3) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPNCXADD, 3, {MEMORY|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57537, 363},
    /*   2 : CMPNCXADD mem32,reg32,reg32 [mrv:      evex.nf0.128.66.0f38.w0 e3 /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64 */
        /* 242(f2 7d 08) 300 001(e3) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPNCXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+25488, 364},
    /*   3 : CMPNCXADD mem64,reg64,reg64 [mrv:      evex.nf0.128.66.0f38.w1 e3 /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64 */
        /* 242(f2 fd 08) 300 001(e3) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPNCXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+25632, 364},
};

static const struct itemplate instrux_CMPNEXADD[4] = {
    /*   0 : CMPNEXADD mem32,reg32,reg32 [mrv:      vex.128.66.0f38.w0 e5 /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64,ND */
        /* 262(002 001) 001(e5) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPNEXADD, 3, {MEMORY|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57481, 363},
    /*   1 : CMPNEXADD mem64,reg64,reg64 [mrv:      vex.128.66.0f38.w1 e5 /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64,ND */
        /* 262(002 201) 001(e5) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPNEXADD, 3, {MEMORY|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57593, 363},
    /*   2 : CMPNEXADD mem32,reg32,reg32 [mrv:      evex.nf0.128.66.0f38.w0 e5 /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64,ND */
        /* 242(f2 7d 08) 300 001(e5) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPNEXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+25560, 364},
    /*   3 : CMPNEXADD mem64,reg64,reg64 [mrv:      evex.nf0.128.66.0f38.w1 e5 /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64,ND */
        /* 242(f2 fd 08) 300 001(e5) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPNEXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+25704, 364},
};

static const struct itemplate instrux_CMPNGXADD[4] = {
    /*   0 : CMPNGXADD mem32,reg32,reg32 [mrv:      vex.128.66.0f38.w0 ee /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64 */
        /* 262(002 001) 001(ee) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPNGXADD, 3, {MEMORY|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57474, 363},
    /*   1 : CMPNGXADD mem64,reg64,reg64 [mrv:      vex.128.66.0f38.w1 ee /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64 */
        /* 262(002 201) 001(ee) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPNGXADD, 3, {MEMORY|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57586, 363},
    /*   2 : CMPNGXADD mem32,reg32,reg32 [mrv:      evex.nf0.128.66.0f38.w0 ee /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64 */
        /* 242(f2 7d 08) 300 001(ee) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPNGXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+25551, 364},
    /*   3 : CMPNGXADD mem64,reg64,reg64 [mrv:      evex.nf0.128.66.0f38.w1 ee /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64 */
        /* 242(f2 fd 08) 300 001(ee) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPNGXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+25695, 364},
};

static const struct itemplate instrux_CMPNGEXADD[4] = {
    /*   0 : CMPNGEXADD mem32,reg32,reg32 [mrv:      vex.128.66.0f38.w0 ec /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64,ND */
        /* 262(002 001) 001(ec) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPNGEXADD, 3, {MEMORY|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57467, 363},
    /*   1 : CMPNGEXADD mem64,reg64,reg64 [mrv:      vex.128.66.0f38.w1 ec /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64,ND */
        /* 262(002 201) 001(ec) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPNGEXADD, 3, {MEMORY|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57579, 363},
    /*   2 : CMPNGEXADD mem32,reg32,reg32 [mrv:      evex.nf0.128.66.0f38.w0 ec /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64,ND */
        /* 242(f2 7d 08) 300 001(ec) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPNGEXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+25542, 364},
    /*   3 : CMPNGEXADD mem64,reg64,reg64 [mrv:      evex.nf0.128.66.0f38.w1 ec /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64,ND */
        /* 242(f2 fd 08) 300 001(ec) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPNGEXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+25686, 364},
};

static const struct itemplate instrux_CMPNLXADD[4] = {
    /*   0 : CMPNLXADD mem32,reg32,reg32 [mrv:      vex.128.66.0f38.w0 ed /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64 */
        /* 262(002 001) 001(ed) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPNLXADD, 3, {MEMORY|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57460, 363},
    /*   1 : CMPNLXADD mem64,reg64,reg64 [mrv:      vex.128.66.0f38.w1 ed /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64 */
        /* 262(002 201) 001(ed) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPNLXADD, 3, {MEMORY|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57572, 363},
    /*   2 : CMPNLXADD mem32,reg32,reg32 [mrv:      evex.nf0.128.66.0f38.w0 ed /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64 */
        /* 242(f2 7d 08) 300 001(ed) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPNLXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+25533, 364},
    /*   3 : CMPNLXADD mem64,reg64,reg64 [mrv:      evex.nf0.128.66.0f38.w1 ed /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64 */
        /* 242(f2 fd 08) 300 001(ed) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPNLXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+25677, 364},
};

static const struct itemplate instrux_CMPNLEXADD[4] = {
    /*   0 : CMPNLEXADD mem32,reg32,reg32 [mrv:      vex.128.66.0f38.w0 ef /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64,ND */
        /* 262(002 001) 001(ef) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPNLEXADD, 3, {MEMORY|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57453, 363},
    /*   1 : CMPNLEXADD mem64,reg64,reg64 [mrv:      vex.128.66.0f38.w1 ef /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64,ND */
        /* 262(002 201) 001(ef) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPNLEXADD, 3, {MEMORY|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57565, 363},
    /*   2 : CMPNLEXADD mem32,reg32,reg32 [mrv:      evex.nf0.128.66.0f38.w0 ef /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64,ND */
        /* 242(f2 7d 08) 300 001(ef) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPNLEXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+25524, 364},
    /*   3 : CMPNLEXADD mem64,reg64,reg64 [mrv:      evex.nf0.128.66.0f38.w1 ef /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64,ND */
        /* 242(f2 fd 08) 300 001(ef) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPNLEXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+25668, 364},
};

static const struct itemplate instrux_CMPNOXADD[4] = {
    /*   0 : CMPNOXADD mem32,reg32,reg32 [mrv:      vex.128.66.0f38.w0 e1 /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64 */
        /* 262(002 001) 001(e1) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPNOXADD, 3, {MEMORY|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57488, 363},
    /*   1 : CMPNOXADD mem64,reg64,reg64 [mrv:      vex.128.66.0f38.w1 e1 /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64 */
        /* 262(002 201) 001(e1) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPNOXADD, 3, {MEMORY|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57600, 363},
    /*   2 : CMPNOXADD mem32,reg32,reg32 [mrv:      evex.nf0.128.66.0f38.w0 e1 /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64 */
        /* 242(f2 7d 08) 300 001(e1) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPNOXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+25569, 364},
    /*   3 : CMPNOXADD mem64,reg64,reg64 [mrv:      evex.nf0.128.66.0f38.w1 e1 /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64 */
        /* 242(f2 fd 08) 300 001(e1) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPNOXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+25713, 364},
};

static const struct itemplate instrux_CMPNPXADD[4] = {
    /*   0 : CMPNPXADD mem32,reg32,reg32 [mrv:      vex.128.66.0f38.w0 eb /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64,ND */
        /* 262(002 001) 001(eb) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPNPXADD, 3, {MEMORY|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57495, 363},
    /*   1 : CMPNPXADD mem64,reg64,reg64 [mrv:      vex.128.66.0f38.w1 eb /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64,ND */
        /* 262(002 201) 001(eb) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPNPXADD, 3, {MEMORY|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57607, 363},
    /*   2 : CMPNPXADD mem32,reg32,reg32 [mrv:      evex.nf0.128.66.0f38.w0 eb /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64,ND */
        /* 242(f2 7d 08) 300 001(eb) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPNPXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+25578, 364},
    /*   3 : CMPNPXADD mem64,reg64,reg64 [mrv:      evex.nf0.128.66.0f38.w1 eb /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64,ND */
        /* 242(f2 fd 08) 300 001(eb) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPNPXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+25722, 364},
};

static const struct itemplate instrux_CMPNSXADD[4] = {
    /*   0 : CMPNSXADD mem32,reg32,reg32 [mrv:      vex.128.66.0f38.w0 e9 /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64 */
        /* 262(002 001) 001(e9) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPNSXADD, 3, {MEMORY|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57502, 363},
    /*   1 : CMPNSXADD mem64,reg64,reg64 [mrv:      vex.128.66.0f38.w1 e9 /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64 */
        /* 262(002 201) 001(e9) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPNSXADD, 3, {MEMORY|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57614, 363},
    /*   2 : CMPNSXADD mem32,reg32,reg32 [mrv:      evex.nf0.128.66.0f38.w0 e9 /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64 */
        /* 242(f2 7d 08) 300 001(e9) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPNSXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+25587, 364},
    /*   3 : CMPNSXADD mem64,reg64,reg64 [mrv:      evex.nf0.128.66.0f38.w1 e9 /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64 */
        /* 242(f2 fd 08) 300 001(e9) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPNSXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+25731, 364},
};

static const struct itemplate instrux_CMPNZXADD[4] = {
    /*   0 : CMPNZXADD mem32,reg32,reg32 [mrv:      vex.128.66.0f38.w0 e5 /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64 */
        /* 262(002 001) 001(e5) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPNZXADD, 3, {MEMORY|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57481, 363},
    /*   1 : CMPNZXADD mem64,reg64,reg64 [mrv:      vex.128.66.0f38.w1 e5 /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64 */
        /* 262(002 201) 001(e5) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPNZXADD, 3, {MEMORY|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57593, 363},
    /*   2 : CMPNZXADD mem32,reg32,reg32 [mrv:      evex.nf0.128.66.0f38.w0 e5 /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64 */
        /* 242(f2 7d 08) 300 001(e5) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPNZXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+25560, 364},
    /*   3 : CMPNZXADD mem64,reg64,reg64 [mrv:      evex.nf0.128.66.0f38.w1 e5 /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64 */
        /* 242(f2 fd 08) 300 001(e5) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPNZXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+25704, 364},
};

static const struct itemplate instrux_CMPOXADD[4] = {
    /*   0 : CMPOXADD mem32,reg32,reg32 [mrv:      vex.128.66.0f38.w0 e0 /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64 */
        /* 262(002 001) 001(e0) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPOXADD, 3, {MEMORY|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57509, 363},
    /*   1 : CMPOXADD mem64,reg64,reg64 [mrv:      vex.128.66.0f38.w1 e0 /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64 */
        /* 262(002 201) 001(e0) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPOXADD, 3, {MEMORY|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57621, 363},
    /*   2 : CMPOXADD mem32,reg32,reg32 [mrv:      evex.nf0.128.66.0f38.w0 e0 /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64 */
        /* 242(f2 7d 08) 300 001(e0) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPOXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+25596, 364},
    /*   3 : CMPOXADD mem64,reg64,reg64 [mrv:      evex.nf0.128.66.0f38.w1 e0 /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64 */
        /* 242(f2 fd 08) 300 001(e0) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPOXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+25740, 364},
};

static const struct itemplate instrux_CMPPXADD[4] = {
    /*   0 : CMPPXADD mem32,reg32,reg32 [mrv:      vex.128.66.0f38.w0 ea /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64,ND */
        /* 262(002 001) 001(ea) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPPXADD, 3, {MEMORY|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57516, 363},
    /*   1 : CMPPXADD mem64,reg64,reg64 [mrv:      vex.128.66.0f38.w1 ea /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64,ND */
        /* 262(002 201) 001(ea) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPPXADD, 3, {MEMORY|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57628, 363},
    /*   2 : CMPPXADD mem32,reg32,reg32 [mrv:      evex.nf0.128.66.0f38.w0 ea /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64,ND */
        /* 242(f2 7d 08) 300 001(ea) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPPXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+25605, 364},
    /*   3 : CMPPXADD mem64,reg64,reg64 [mrv:      evex.nf0.128.66.0f38.w1 ea /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64,ND */
        /* 242(f2 fd 08) 300 001(ea) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPPXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+25749, 364},
};

static const struct itemplate instrux_CMPPEXADD[4] = {
    /*   0 : CMPPEXADD mem32,reg32,reg32 [mrv:      vex.128.66.0f38.w0 ea /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64 */
        /* 262(002 001) 001(ea) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPPEXADD, 3, {MEMORY|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57516, 363},
    /*   1 : CMPPEXADD mem64,reg64,reg64 [mrv:      vex.128.66.0f38.w1 ea /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64 */
        /* 262(002 201) 001(ea) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPPEXADD, 3, {MEMORY|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57628, 363},
    /*   2 : CMPPEXADD mem32,reg32,reg32 [mrv:      evex.nf0.128.66.0f38.w0 ea /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64 */
        /* 242(f2 7d 08) 300 001(ea) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPPEXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+25605, 364},
    /*   3 : CMPPEXADD mem64,reg64,reg64 [mrv:      evex.nf0.128.66.0f38.w1 ea /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64 */
        /* 242(f2 fd 08) 300 001(ea) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPPEXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+25749, 364},
};

static const struct itemplate instrux_CMPPOXADD[4] = {
    /*   0 : CMPPOXADD mem32,reg32,reg32 [mrv:      vex.128.66.0f38.w0 eb /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64 */
        /* 262(002 001) 001(eb) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPPOXADD, 3, {MEMORY|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57495, 363},
    /*   1 : CMPPOXADD mem64,reg64,reg64 [mrv:      vex.128.66.0f38.w1 eb /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64 */
        /* 262(002 201) 001(eb) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPPOXADD, 3, {MEMORY|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57607, 363},
    /*   2 : CMPPOXADD mem32,reg32,reg32 [mrv:      evex.nf0.128.66.0f38.w0 eb /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64 */
        /* 242(f2 7d 08) 300 001(eb) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPPOXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+25578, 364},
    /*   3 : CMPPOXADD mem64,reg64,reg64 [mrv:      evex.nf0.128.66.0f38.w1 eb /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64 */
        /* 242(f2 fd 08) 300 001(eb) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPPOXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+25722, 364},
};

static const struct itemplate instrux_CMPSXADD[4] = {
    /*   0 : CMPSXADD mem32,reg32,reg32 [mrv:      vex.128.66.0f38.w0 e8 /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64 */
        /* 262(002 001) 001(e8) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPSXADD, 3, {MEMORY|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57523, 363},
    /*   1 : CMPSXADD mem64,reg64,reg64 [mrv:      vex.128.66.0f38.w1 e8 /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64 */
        /* 262(002 201) 001(e8) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPSXADD, 3, {MEMORY|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57635, 363},
    /*   2 : CMPSXADD mem32,reg32,reg32 [mrv:      evex.nf0.128.66.0f38.w0 e8 /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64 */
        /* 242(f2 7d 08) 300 001(e8) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPSXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+25614, 364},
    /*   3 : CMPSXADD mem64,reg64,reg64 [mrv:      evex.nf0.128.66.0f38.w1 e8 /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64 */
        /* 242(f2 fd 08) 300 001(e8) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPSXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+25758, 364},
};

static const struct itemplate instrux_CMPZXADD[4] = {
    /*   0 : CMPZXADD mem32,reg32,reg32 [mrv:      vex.128.66.0f38.w0 e4 /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64 */
        /* 262(002 001) 001(e4) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPZXADD, 3, {MEMORY|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57446, 363},
    /*   1 : CMPZXADD mem64,reg64,reg64 [mrv:      vex.128.66.0f38.w1 e4 /r        ] SM0-2,LONG,PROT,CMPCCXADD,X86_64 */
        /* 262(002 201) 001(e4) 101 : SM0,SM1,SM2,NOAPX,LONG,VEX,PROT,CMPCCXADD,X86_64 */
        {I_CMPZXADD, 3, {MEMORY|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+57558, 363},
    /*   2 : CMPZXADD mem32,reg32,reg32 [mrv:      evex.nf0.128.66.0f38.w0 e4 /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64 */
        /* 242(f2 7d 08) 300 001(e4) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPZXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+25515, 364},
    /*   3 : CMPZXADD mem64,reg64,reg64 [mrv:      evex.nf0.128.66.0f38.w1 e4 /r   ] SM0-2,LONG,PROT,CMPCCXADD,APX,X86_64 */
        /* 242(f2 fd 08) 300 001(e4) 101 : SM0,SM1,SM2,LONG,EVEX,PROT,CMPCCXADD,APX,X86_64 */
        {I_CMPZXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+25659, 364},
};

static const struct itemplate instrux_ADDPS[1] = {
    /*   0 : ADDPS xmmreg,xmmrm128 [rm:       np 0f 58 /r                       ] SSE,KATMAI */
        /* 360 355 001(58) 110 : SSE,KATMAI */
        {I_ADDPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+68204, 365},
};

static const struct itemplate instrux_ADDSS[1] = {
    /*   0 : ADDSS xmmreg,xmmrm32 [rm:       f3 0f 58 /r                       ] SSE,KATMAI */
        /* 333 355 001(58) 110 : SSE,KATMAI */
        {I_ADDSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68210, 365},
};

static const struct itemplate instrux_ANDNPS[1] = {
    /*   0 : ANDNPS xmmreg,xmmrm128 [rm:       np 0f 55 /r                       ] SSE,KATMAI */
        /* 360 355 001(55) 110 : SSE,KATMAI */
        {I_ANDNPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+68216, 365},
};

static const struct itemplate instrux_ANDPS[1] = {
    /*   0 : ANDPS xmmreg,xmmrm128 [rm:       np 0f 54 /r                       ] SSE,KATMAI */
        /* 360 355 001(54) 110 : SSE,KATMAI */
        {I_ANDPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+68222, 365},
};

static const struct itemplate instrux_CMPEQPS[1] = {
    /*   0 : CMPEQPS xmmreg,xmmrm128 [rm:       np 0f c2 /r 00                    ] SSE,KATMAI */
        /* 360 355 001(c2) 110 001(00) : SSE,KATMAI */
        {I_CMPEQPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+51261, 365},
};

static const struct itemplate instrux_CMPEQSS[1] = {
    /*   0 : CMPEQSS xmmreg,xmmrm32 [rm:       f3 0f c2 /r 00                    ] SSE,KATMAI */
        /* 333 355 001(c2) 110 001(00) : SSE,KATMAI */
        {I_CMPEQSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+51269, 365},
};

static const struct itemplate instrux_CMPLEPS[1] = {
    /*   0 : CMPLEPS xmmreg,xmmrm128 [rm:       np 0f c2 /r 02                    ] SSE,KATMAI */
        /* 360 355 001(c2) 110 001(02) : SSE,KATMAI */
        {I_CMPLEPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+51277, 365},
};

static const struct itemplate instrux_CMPLESS[1] = {
    /*   0 : CMPLESS xmmreg,xmmrm32 [rm:       f3 0f c2 /r 02                    ] SSE,KATMAI */
        /* 333 355 001(c2) 110 001(02) : SSE,KATMAI */
        {I_CMPLESS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+51285, 365},
};

static const struct itemplate instrux_CMPLTPS[1] = {
    /*   0 : CMPLTPS xmmreg,xmmrm128 [rm:       np 0f c2 /r 01                    ] SSE,KATMAI */
        /* 360 355 001(c2) 110 001(01) : SSE,KATMAI */
        {I_CMPLTPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+51293, 365},
};

static const struct itemplate instrux_CMPLTSS[1] = {
    /*   0 : CMPLTSS xmmreg,xmmrm32 [rm:       f3 0f c2 /r 01                    ] SSE,KATMAI */
        /* 333 355 001(c2) 110 001(01) : SSE,KATMAI */
        {I_CMPLTSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+51301, 365},
};

static const struct itemplate instrux_CMPNEQPS[1] = {
    /*   0 : CMPNEQPS xmmreg,xmmrm128 [rm:       np 0f c2 /r 04                    ] SSE,KATMAI */
        /* 360 355 001(c2) 110 001(04) : SSE,KATMAI */
        {I_CMPNEQPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+51309, 365},
};

static const struct itemplate instrux_CMPNEQSS[1] = {
    /*   0 : CMPNEQSS xmmreg,xmmrm32 [rm:       f3 0f c2 /r 04                    ] SSE,KATMAI */
        /* 333 355 001(c2) 110 001(04) : SSE,KATMAI */
        {I_CMPNEQSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+51317, 365},
};

static const struct itemplate instrux_CMPNLEPS[1] = {
    /*   0 : CMPNLEPS xmmreg,xmmrm128 [rm:       np 0f c2 /r 06                    ] SSE,KATMAI */
        /* 360 355 001(c2) 110 001(06) : SSE,KATMAI */
        {I_CMPNLEPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+51325, 365},
};

static const struct itemplate instrux_CMPNLESS[1] = {
    /*   0 : CMPNLESS xmmreg,xmmrm32 [rm:       f3 0f c2 /r 06                    ] SSE,KATMAI */
        /* 333 355 001(c2) 110 001(06) : SSE,KATMAI */
        {I_CMPNLESS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+51333, 365},
};

static const struct itemplate instrux_CMPNLTPS[1] = {
    /*   0 : CMPNLTPS xmmreg,xmmrm128 [rm:       np 0f c2 /r 05                    ] SSE,KATMAI */
        /* 360 355 001(c2) 110 001(05) : SSE,KATMAI */
        {I_CMPNLTPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+51341, 365},
};

static const struct itemplate instrux_CMPNLTSS[1] = {
    /*   0 : CMPNLTSS xmmreg,xmmrm32 [rm:       f3 0f c2 /r 05                    ] SSE,KATMAI */
        /* 333 355 001(c2) 110 001(05) : SSE,KATMAI */
        {I_CMPNLTSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+51349, 365},
};

static const struct itemplate instrux_CMPORDPS[1] = {
    /*   0 : CMPORDPS xmmreg,xmmrm128 [rm:       np 0f c2 /r 07                    ] SSE,KATMAI */
        /* 360 355 001(c2) 110 001(07) : SSE,KATMAI */
        {I_CMPORDPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+51357, 365},
};

static const struct itemplate instrux_CMPORDSS[1] = {
    /*   0 : CMPORDSS xmmreg,xmmrm32 [rm:       f3 0f c2 /r 07                    ] SSE,KATMAI */
        /* 333 355 001(c2) 110 001(07) : SSE,KATMAI */
        {I_CMPORDSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+51365, 365},
};

static const struct itemplate instrux_CMPUNORDPS[1] = {
    /*   0 : CMPUNORDPS xmmreg,xmmrm128 [rm:       np 0f c2 /r 03                    ] SSE,KATMAI */
        /* 360 355 001(c2) 110 001(03) : SSE,KATMAI */
        {I_CMPUNORDPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+51373, 365},
};

static const struct itemplate instrux_CMPUNORDSS[1] = {
    /*   0 : CMPUNORDSS xmmreg,xmmrm32 [rm:       f3 0f c2 /r 03                    ] SSE,KATMAI */
        /* 333 355 001(c2) 110 001(03) : SSE,KATMAI */
        {I_CMPUNORDSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+51381, 365},
};

static const struct itemplate instrux_CMPPS[1] = {
    /*   0 : CMPPS xmmreg,xmmrm128,imm8 [rmi:      np 0f c2 /r ib,u                  ] SSE,KATMAI */
        /* 360 355 001(c2) 110 026 : SSE,KATMAI */
        {I_CMPPS, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+57642, 365},
};

static const struct itemplate instrux_CMPSS[1] = {
    /*   0 : CMPSS xmmreg,xmmrm32,imm8 [rmi:      f3 0f c2 /r ib,u                  ] SSE,KATMAI */
        /* 333 355 001(c2) 110 026 : SSE,KATMAI */
        {I_CMPSS, 3, {XMMREG,RM_XMM|BITS32,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+57649, 365},
};

static const struct itemplate instrux_COMISS[1] = {
    /*   0 : COMISS xmmreg,xmmrm32 [rm:       np 0f 2f /r                       ] FL,SSE,KATMAI */
        /* 360 355 001(2f) 110 : FL,SSE,KATMAI */
        {I_COMISS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68228, 366},
};

static const struct itemplate instrux_CVTPI2PS[1] = {
    /*   0 : CVTPI2PS xmmreg,mmxrm64 [rm:       np 0f 2a /r                       ] MMX,SSE,KATMAI */
        /* 360 355 001(2a) 110 : MMX,SSE,KATMAI */
        {I_CVTPI2PS, 2, {XMMREG,RM_MMX|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+68234, 367},
};

static const struct itemplate instrux_CVTPS2PI[1] = {
    /*   0 : CVTPS2PI mmxreg,xmmrm64 [rm:       np 0f 2d /r                       ] MMX,SSE,KATMAI */
        /* 360 355 001(2d) 110 : MMX,SSE,KATMAI */
        {I_CVTPS2PI, 2, {MMXREG,RM_XMM|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+68240, 367},
};

static const struct itemplate instrux_CVTSI2SS[2] = {
    /*   0 : CVTSI2SS xmmreg,rm32 [rm:       f3 0f 2a /r                       ] SSE,KATMAI */
        /* 333 355 001(2a) 110 : SSE,KATMAI */
        {I_CVTSI2SS, 2, {XMMREG,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+57657, 365},
    /*   1 : CVTSI2SS xmmreg,rm64 [rm:       o64 f3 0f 2a /r                   ] AR1,SX,LONG,PROT,SSE,X86_64 */
        /* 324 333 355 001(2a) 110 : AR1,SX,LONG,PROT,SSE,X86_64 */
        {I_CVTSI2SS, 2, {XMMREG,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+57656, 368},
};

static const struct itemplate instrux_CVTSS2SI[2] = {
    /*   0 : CVTSS2SI reg32,xmmrm32 [rm:       f3 0f 2d /r                       ] SSE,KATMAI */
        /* 333 355 001(2d) 110 : SSE,KATMAI */
        {I_CVTSS2SI, 2, {REG_GPR|BITS32,RM_XMM|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+57664, 365},
    /*   1 : CVTSS2SI reg64,xmmrm32 [rm:       o64 f3 0f 2d /r                   ] LONG,PROT,SSE,X86_64 */
        /* 324 333 355 001(2d) 110 : LONG,PROT,SSE,X86_64 */
        {I_CVTSS2SI, 2, {REG_GPR|BITS64,RM_XMM|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+57663, 369},
};

static const struct itemplate instrux_CVTTPS2PI[1] = {
    /*   0 : CVTTPS2PI mmxreg,xmmrm64 [rm:       np 0f 2c /r                       ] MMX,SSE,KATMAI */
        /* 360 355 001(2c) 110 : MMX,SSE,KATMAI */
        {I_CVTTPS2PI, 2, {MMXREG,RM_XMM|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+68246, 367},
};

static const struct itemplate instrux_CVTTSS2SI[2] = {
    /*   0 : CVTTSS2SI reg32,xmmrm32 [rm:       f3 0f 2c /r                       ] SSE,KATMAI */
        /* 333 355 001(2c) 110 : SSE,KATMAI */
        {I_CVTTSS2SI, 2, {REG_GPR|BITS32,RM_XMM|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+57671, 365},
    /*   1 : CVTTSS2SI reg64,xmmrm32 [rm:       o64 f3 0f 2c /r                   ] LONG,PROT,SSE,X86_64 */
        /* 324 333 355 001(2c) 110 : LONG,PROT,SSE,X86_64 */
        {I_CVTTSS2SI, 2, {REG_GPR|BITS64,RM_XMM|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+57670, 369},
};

static const struct itemplate instrux_DIVPS[1] = {
    /*   0 : DIVPS xmmreg,xmmrm128 [rm:       np 0f 5e /r                       ] SSE,KATMAI */
        /* 360 355 001(5e) 110 : SSE,KATMAI */
        {I_DIVPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+68252, 365},
};

static const struct itemplate instrux_DIVSS[1] = {
    /*   0 : DIVSS xmmreg,xmmrm32 [rm:       f3 0f 5e /r                       ] SSE,KATMAI */
        /* 333 355 001(5e) 110 : SSE,KATMAI */
        {I_DIVSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68258, 365},
};

static const struct itemplate instrux_LDMXCSR[1] = {
    /*   0 : LDMXCSR mem32 [m:        np 0f ae /2                       ] SSE,KATMAI */
        /* 360 355 001(ae) 202 : SSE,KATMAI */
        {I_LDMXCSR, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+68264, 365},
};

static const struct itemplate instrux_MAXPS[1] = {
    /*   0 : MAXPS xmmreg,xmmrm128 [rm:       np 0f 5f /r                       ] SSE,KATMAI */
        /* 360 355 001(5f) 110 : SSE,KATMAI */
        {I_MAXPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+68270, 365},
};

static const struct itemplate instrux_MAXSS[1] = {
    /*   0 : MAXSS xmmreg,xmmrm32 [rm:       f3 0f 5f /r                       ] SSE,KATMAI */
        /* 333 355 001(5f) 110 : SSE,KATMAI */
        {I_MAXSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68276, 365},
};

static const struct itemplate instrux_MINPS[1] = {
    /*   0 : MINPS xmmreg,xmmrm128 [rm:       np 0f 5d /r                       ] SSE,KATMAI */
        /* 360 355 001(5d) 110 : SSE,KATMAI */
        {I_MINPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+68282, 365},
};

static const struct itemplate instrux_MINSS[1] = {
    /*   0 : MINSS xmmreg,xmmrm32 [rm:       f3 0f 5d /r                       ] SSE,KATMAI */
        /* 333 355 001(5d) 110 : SSE,KATMAI */
        {I_MINSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68288, 365},
};

static const struct itemplate instrux_MOVAPS[2] = {
    /*   0 : MOVAPS xmmreg,xmmrm128 [rm:       np 0f 28 /r                       ] SSE,KATMAI */
        /* 360 355 001(28) 110 : SSE,KATMAI */
        {I_MOVAPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+68294, 365},
    /*   1 : MOVAPS xmmrm128,xmmreg [mr:       np 0f 29 /r                       ] SSE,KATMAI */
        /* 360 355 001(29) 101 : SSE,KATMAI */
        {I_MOVAPS, 2, {RM_XMM|BITS128,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+68300, 365},
};

static const struct itemplate instrux_MOVHPS[2] = {
    /*   0 : MOVHPS xmmreg,mem64 [rm:       np 0f 16 /r                       ] SSE,KATMAI */
        /* 360 355 001(16) 110 : SSE,KATMAI */
        {I_MOVHPS, 2, {XMMREG,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+68306, 365},
    /*   1 : MOVHPS mem64,xmmreg [mr:       np 0f 17 /r                       ] SSE,KATMAI */
        /* 360 355 001(17) 101 : SSE,KATMAI */
        {I_MOVHPS, 2, {MEMORY|BITS64,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+68312, 365},
};

static const struct itemplate instrux_MOVLHPS[1] = {
    /*   0 : MOVLHPS xmmreg,xmmreg [rm:       np 0f 16 /r                       ] SSE,KATMAI */
        /* 360 355 001(16) 110 : SSE,KATMAI */
        {I_MOVLHPS, 2, {XMMREG,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+68306, 365},
};

static const struct itemplate instrux_MOVLPS[2] = {
    /*   0 : MOVLPS xmmreg,mem64 [rm:       np 0f 12 /r                       ] SSE,KATMAI */
        /* 360 355 001(12) 110 : SSE,KATMAI */
        {I_MOVLPS, 2, {XMMREG,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+67286, 365},
    /*   1 : MOVLPS mem64,xmmreg [mr:       np 0f 13 /r                       ] SSE,KATMAI */
        /* 360 355 001(13) 101 : SSE,KATMAI */
        {I_MOVLPS, 2, {MEMORY|BITS64,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+68318, 365},
};

static const struct itemplate instrux_MOVHLPS[1] = {
    /*   0 : MOVHLPS xmmreg,xmmreg [rm:       np 0f 12 /r                       ] SSE,KATMAI */
        /* 360 355 001(12) 110 : SSE,KATMAI */
        {I_MOVHLPS, 2, {XMMREG,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+67286, 365},
};

static const struct itemplate instrux_MOVMSKPS[2] = {
    /*   0 : MOVMSKPS reg32,xmmreg [rm:       np 0f 50 /r                       ] SSE,KATMAI */
        /* 360 355 001(50) 110 : SSE,KATMAI */
        {I_MOVMSKPS, 2, {REG_GPR|BITS32,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+68324, 365},
    /*   1 : MOVMSKPS reg64,xmmreg [rm:       np o64 0f 50 /r                   ] LONG,PROT,SSE,X86_64 */
        /* 360 324 355 001(50) 110 : LONG,PROT,SSE,X86_64 */
        {I_MOVMSKPS, 2, {REG_GPR|BITS64,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+57677, 369},
};

static const struct itemplate instrux_MOVNTPS[1] = {
    /*   0 : MOVNTPS mem128,xmmreg [mr:       np 0f 2b /r                       ] SSE,KATMAI */
        /* 360 355 001(2b) 101 : SSE,KATMAI */
        {I_MOVNTPS, 2, {MEMORY|BITS128,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+68330, 365},
};

static const struct itemplate instrux_MOVSS[2] = {
    /*   0 : MOVSS xmmreg,xmmrm32 [rm:       f3 0f 10 /r                       ] SSE,KATMAI */
        /* 333 355 001(10) 110 : SSE,KATMAI */
        {I_MOVSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68336, 365},
    /*   1 : MOVSS xmmrm32,xmmreg [mr:       f3 0f 11 /r                       ] SSE,KATMAI */
        /* 333 355 001(11) 101 : SSE,KATMAI */
        {I_MOVSS, 2, {RM_XMM|BITS32,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+68342, 365},
};

static const struct itemplate instrux_MOVUPS[2] = {
    /*   0 : MOVUPS xmmreg,xmmrm128 [rm:       np 0f 10 /r                       ] SSE,KATMAI */
        /* 360 355 001(10) 110 : SSE,KATMAI */
        {I_MOVUPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+68348, 365},
    /*   1 : MOVUPS xmmrm128,xmmreg [mr:       np 0f 11 /r                       ] SSE,KATMAI */
        /* 360 355 001(11) 101 : SSE,KATMAI */
        {I_MOVUPS, 2, {RM_XMM|BITS128,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+68354, 365},
};

static const struct itemplate instrux_MULPS[1] = {
    /*   0 : MULPS xmmreg,xmmrm128 [rm:       np 0f 59 /r                       ] SSE,KATMAI */
        /* 360 355 001(59) 110 : SSE,KATMAI */
        {I_MULPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+68360, 365},
};

static const struct itemplate instrux_MULSS[1] = {
    /*   0 : MULSS xmmreg,xmmrm32 [rm:       f3 0f 59 /r                       ] SSE,KATMAI */
        /* 333 355 001(59) 110 : SSE,KATMAI */
        {I_MULSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68366, 365},
};

static const struct itemplate instrux_ORPS[1] = {
    /*   0 : ORPS xmmreg,xmmrm128 [rm:       np 0f 56 /r                       ] SSE,KATMAI */
        /* 360 355 001(56) 110 : SSE,KATMAI */
        {I_ORPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+68372, 365},
};

static const struct itemplate instrux_RCPPS[1] = {
    /*   0 : RCPPS xmmreg,xmmrm128 [rm:       np 0f 53 /r                       ] SSE,KATMAI */
        /* 360 355 001(53) 110 : SSE,KATMAI */
        {I_RCPPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+68378, 365},
};

static const struct itemplate instrux_RCPSS[1] = {
    /*   0 : RCPSS xmmreg,xmmrm32 [rm:       f3 0f 53 /r                       ] SSE,KATMAI */
        /* 333 355 001(53) 110 : SSE,KATMAI */
        {I_RCPSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68384, 365},
};

static const struct itemplate instrux_RSQRTPS[1] = {
    /*   0 : RSQRTPS xmmreg,xmmrm128 [rm:       np 0f 52 /r                       ] SSE,KATMAI */
        /* 360 355 001(52) 110 : SSE,KATMAI */
        {I_RSQRTPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+68390, 365},
};

static const struct itemplate instrux_RSQRTSS[1] = {
    /*   0 : RSQRTSS xmmreg,xmmrm32 [rm:       f3 0f 52 /r                       ] SSE,KATMAI */
        /* 333 355 001(52) 110 : SSE,KATMAI */
        {I_RSQRTSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68396, 365},
};

static const struct itemplate instrux_SHUFPS[1] = {
    /*   0 : SHUFPS xmmreg,xmmrm128,imm8 [rmi:      np 0f c6 /r ib,u                  ] SSE,KATMAI */
        /* 360 355 001(c6) 110 026 : SSE,KATMAI */
        {I_SHUFPS, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+57684, 365},
};

static const struct itemplate instrux_SQRTPS[1] = {
    /*   0 : SQRTPS xmmreg,xmmrm128 [rm:       np 0f 51 /r                       ] SSE,KATMAI */
        /* 360 355 001(51) 110 : SSE,KATMAI */
        {I_SQRTPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+68402, 365},
};

static const struct itemplate instrux_SQRTSS[1] = {
    /*   0 : SQRTSS xmmreg,xmmrm32 [rm:       f3 0f 51 /r                       ] SSE,KATMAI */
        /* 333 355 001(51) 110 : SSE,KATMAI */
        {I_SQRTSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68408, 365},
};

static const struct itemplate instrux_STMXCSR[1] = {
    /*   0 : STMXCSR mem32 [m:        np 0f ae /3                       ] SSE,KATMAI */
        /* 360 355 001(ae) 203 : SSE,KATMAI */
        {I_STMXCSR, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+68414, 365},
};

static const struct itemplate instrux_SUBPS[1] = {
    /*   0 : SUBPS xmmreg,xmmrm128 [rm:       np 0f 5c /r                       ] SSE,KATMAI */
        /* 360 355 001(5c) 110 : SSE,KATMAI */
        {I_SUBPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+68420, 365},
};

static const struct itemplate instrux_SUBSS[1] = {
    /*   0 : SUBSS xmmreg,xmmrm32 [rm:       f3 0f 5c /r                       ] SSE,KATMAI */
        /* 333 355 001(5c) 110 : SSE,KATMAI */
        {I_SUBSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68426, 365},
};

static const struct itemplate instrux_UCOMISS[1] = {
    /*   0 : UCOMISS xmmreg,xmmrm32 [rm:       np 0f 2e /r                       ] FL,SSE,KATMAI */
        /* 360 355 001(2e) 110 : FL,SSE,KATMAI */
        {I_UCOMISS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+68432, 366},
};

static const struct itemplate instrux_UNPCKHPS[1] = {
    /*   0 : UNPCKHPS xmmreg,xmmrm128 [rm:       np 0f 15 /r                       ] SSE,KATMAI */
        /* 360 355 001(15) 110 : SSE,KATMAI */
        {I_UNPCKHPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+68438, 365},
};

static const struct itemplate instrux_UNPCKLPS[1] = {
    /*   0 : UNPCKLPS xmmreg,xmmrm128 [rm:       np 0f 14 /r                       ] SSE,KATMAI */
        /* 360 355 001(14) 110 : SSE,KATMAI */
        {I_UNPCKLPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+68444, 365},
};

static const struct itemplate instrux_XORPS[1] = {
    /*   0 : XORPS xmmreg,xmmrm128 [rm:       np 0f 57 /r                       ] SSE,KATMAI */
        /* 360 355 001(57) 110 : SSE,KATMAI */
        {I_XORPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+68450, 365},
};

static const struct itemplate instrux_FXRSTOR[1] = {
    /*   0 : FXRSTOR mem [m:        np 0f ae /1                       ] FPU,SSE,P6 */
        /* 360 355 001(ae) 201 : FPU,SSE,P6 */
        {I_FXRSTOR, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57692, 370},
};

static const struct itemplate instrux_FXRSTOR64[1] = {
    /*   0 : FXRSTOR64 mem [m:        o64 np 0f ae /1                   ] LONG,PROT,FPU,SSE,X86_64 */
        /* 324 360 355 001(ae) 201 : LONG,PROT,FPU,SSE,X86_64 */
        {I_FXRSTOR64, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57691, 371},
};

static const struct itemplate instrux_FXSAVE[1] = {
    /*   0 : FXSAVE mem [m:        np 0f ae /0                       ] FPU,SSE,P6 */
        /* 360 355 001(ae) 200 : FPU,SSE,P6 */
        {I_FXSAVE, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57699, 370},
};

static const struct itemplate instrux_FXSAVE64[1] = {
    /*   0 : FXSAVE64 mem [m:        o64 np 0f ae /0                   ] LONG,PROT,FPU,SSE,X86_64 */
        /* 324 360 355 001(ae) 200 : LONG,PROT,FPU,SSE,X86_64 */
        {I_FXSAVE64, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57698, 371},
};

static const struct itemplate instrux_XGETBV[1] = {
    /*   0 : XGETBV void [          0f 01 d0                          ] NEHALEM */
        /* 355 002(01 d0) : NEHALEM */
        {I_XGETBV, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72303, 372},
};

static const struct itemplate instrux_XSETBV[1] = {
    /*   0 : XSETBV void [          0f 01 d1                          ] PRIV,NEHALEM */
        /* 355 002(01 d1) : PRIV,NEHALEM */
        {I_XSETBV, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72308, 373},
};

static const struct itemplate instrux_XSAVE[1] = {
    /*   0 : XSAVE mem [m:        np 0f ae /4                       ] NOAPX,NEHALEM */
        /* 360 355 001(ae) 204 : NOAPX,NEHALEM */
        {I_XSAVE, 1, {MEMORY|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57706, 374},
};

static const struct itemplate instrux_XSAVE64[1] = {
    /*   0 : XSAVE64 mem [m:        o64 np 0f ae /4                   ] NOAPX,LONG,PROT,X86_64,NEHALEM */
        /* 324 360 355 001(ae) 204 : NOAPX,LONG,PROT,NEHALEM */
        {I_XSAVE64, 1, {MEMORY|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57705, 375},
};

static const struct itemplate instrux_XSAVEC[1] = {
    /*   0 : XSAVEC mem [m:        np 0f c7 /4                       ] NOAPX,FUTURE */
        /* 360 355 001(c7) 204 : NOAPX,FUTURE */
        {I_XSAVEC, 1, {MEMORY|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57713, 284},
};

static const struct itemplate instrux_XSAVEC64[1] = {
    /*   0 : XSAVEC64 mem [m:        o64 np 0f c7 /4                   ] NOAPX,LONG,PROT,X86_64 */
        /* 324 360 355 001(c7) 204 : NOAPX,LONG,PROT,X86_64 */
        {I_XSAVEC64, 1, {MEMORY|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57712, 246},
};

static const struct itemplate instrux_XSAVEOPT[1] = {
    /*   0 : XSAVEOPT mem [m:        np 0f ae /6                       ] NOAPX,FUTURE */
        /* 360 355 001(ae) 206 : NOAPX,FUTURE */
        {I_XSAVEOPT, 1, {MEMORY|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57720, 284},
};

static const struct itemplate instrux_XSAVEOPT64[1] = {
    /*   0 : XSAVEOPT64 mem [m:        o64 np 0f ae /6                   ] NOAPX,LONG,PROT,X86_64 */
        /* 324 360 355 001(ae) 206 : NOAPX,LONG,PROT,X86_64 */
        {I_XSAVEOPT64, 1, {MEMORY|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57719, 246},
};

static const struct itemplate instrux_XSAVES[1] = {
    /*   0 : XSAVES mem [m:        np 0f c7 /5                       ] NOAPX,FUTURE */
        /* 360 355 001(c7) 205 : NOAPX,FUTURE */
        {I_XSAVES, 1, {MEMORY|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57727, 284},
};

static const struct itemplate instrux_XSAVES64[1] = {
    /*   0 : XSAVES64 mem [m:        o64 np 0f c7 /5                   ] NOAPX,LONG,PROT,X86_64 */
        /* 324 360 355 001(c7) 205 : NOAPX,LONG,PROT,X86_64 */
        {I_XSAVES64, 1, {MEMORY|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57726, 246},
};

static const struct itemplate instrux_XRSTOR[1] = {
    /*   0 : XRSTOR mem [m:        np 0f ae /5                       ] NOAPX,NEHALEM */
        /* 360 355 001(ae) 205 : NOAPX,NEHALEM */
        {I_XRSTOR, 1, {MEMORY|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57734, 374},
};

static const struct itemplate instrux_XRSTOR64[1] = {
    /*   0 : XRSTOR64 mem [m:        o64 np 0f ae /5                   ] NOAPX,LONG,PROT,X86_64,NEHALEM */
        /* 324 360 355 001(ae) 205 : NOAPX,LONG,PROT,NEHALEM */
        {I_XRSTOR64, 1, {MEMORY|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57733, 375},
};

static const struct itemplate instrux_XRSTORS[1] = {
    /*   0 : XRSTORS mem [m:        np 0f c7 /3                       ] NOAPX,FUTURE */
        /* 360 355 001(c7) 203 : NOAPX,FUTURE */
        {I_XRSTORS, 1, {MEMORY|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57741, 284},
};

static const struct itemplate instrux_XRSTORS64[1] = {
    /*   0 : XRSTORS64 mem [m:        o64 np 0f c7 /3                   ] NOAPX,LONG,PROT,X86_64 */
        /* 324 360 355 001(c7) 203 : NOAPX,LONG,PROT,X86_64 */
        {I_XRSTORS64, 1, {MEMORY|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+57740, 246},
};

static const struct itemplate instrux_PREFETCHNTA[1] = {
    /*   0 : PREFETCHNTA mem8 [m:        0f 18 /0                          ] AR0,SB,KATMAI */
        /* 355 001(18) 200 : AR0,SB,KATMAI */
        {I_PREFETCHNTA, 1, {MEMORY|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70047, 376},
};

static const struct itemplate instrux_PREFETCHT0[1] = {
    /*   0 : PREFETCHT0 mem8 [m:        0f 18 /1                          ] AR0,SB,KATMAI */
        /* 355 001(18) 201 : AR0,SB,KATMAI */
        {I_PREFETCHT0, 1, {MEMORY|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70065, 376},
};

static const struct itemplate instrux_PREFETCHT1[1] = {
    /*   0 : PREFETCHT1 mem8 [m:        0f 18 /2                          ] AR0,SB,KATMAI */
        /* 355 001(18) 202 : AR0,SB,KATMAI */
        {I_PREFETCHT1, 1, {MEMORY|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70083, 376},
};

static const struct itemplate instrux_PREFETCHT2[1] = {
    /*   0 : PREFETCHT2 mem8 [m:        0f 18 /3                          ] AR0,SB,KATMAI */
        /* 355 001(18) 203 : AR0,SB,KATMAI */
        {I_PREFETCHT2, 1, {MEMORY|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70101, 376},
};

static const struct itemplate instrux_PREFETCHIT0[1] = {
    /*   0 : PREFETCHIT0 mem8 [m:        0f 18 /7                          ] AR0,SB,PREFETCHI,FUTURE */
        /* 355 001(18) 207 : AR0,SB,PREFETCHI,FUTURE */
        {I_PREFETCHIT0, 1, {MEMORY|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70173, 377},
};

static const struct itemplate instrux_PREFETCHIT1[1] = {
    /*   0 : PREFETCHIT1 mem8 [m:        0f 18 /6                          ] AR0,SB,PREFETCHI,FUTURE */
        /* 355 001(18) 206 : AR0,SB,PREFETCHI,FUTURE */
        {I_PREFETCHIT1, 1, {MEMORY|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70155, 377},
};

static const struct itemplate instrux_MASKMOVQ[1] = {
    /*   0 : MASKMOVQ mmxreg,mmxreg [rm:       np 0f f7 /r                       ] MMX,KATMAI */
        /* 360 355 001(f7) 110 : MMX,KATMAI */
        {I_MASKMOVQ, 2, {MMXREG,MMXREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+68456, 379},
};

static const struct itemplate instrux_MOVNTQ[1] = {
    /*   0 : MOVNTQ mem,mmxreg [mr:       np 0f e7 /r                       ] AR0-1,SQ,MMX,KATMAI */
        /* 360 355 001(e7) 101 : AR0,AR1,SQ,MMX,KATMAI */
        {I_MOVNTQ, 2, {MEMORY,MMXREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+68462, 380},
};

static const struct itemplate instrux_PAVGB[2] = {
    /*   0 : PAVGB mmxreg,mmxrm [rm:       np 0f e0 /r                       ] AR0-1,SQ,MMX,KATMAI */
        /* 360 355 001(e0) 110 : AR0,AR1,SQ,MMX,KATMAI */
        {I_PAVGB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+68468, 380},
    /*   1 : PAVGB xmmreg,xmmrm [rm:       66 0f e0 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(e0) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PAVGB, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68672, 382},
};

static const struct itemplate instrux_PAVGW[2] = {
    /*   0 : PAVGW mmxreg,mmxrm [rm:       np 0f e3 /r                       ] AR0-1,SQ,MMX,KATMAI */
        /* 360 355 001(e3) 110 : AR0,AR1,SQ,MMX,KATMAI */
        {I_PAVGW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+68474, 380},
    /*   1 : PAVGW xmmreg,xmmrm [rm:       66 0f e3 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(e3) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PAVGW, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68678, 382},
};

static const struct itemplate instrux_PEXTRW[6] = {
    /*   0 : PEXTRW reg32,mmxreg,imm [rmi:      np 0f c5 /r ib,u                  ] AR2,SB,MMX,KATMAI */
        /* 360 355 001(c5) 110 026 : AR2,SB,MMX,KATMAI */
        {I_PEXTRW, 3, {REG_GPR|BITS32,MMXREG,IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+57747, 381},
    /*   1 : PEXTRW reg32,xmmreg,imm [rmi:      66 0f c5 /r ib,u                  ] AR2,SB,SSE2,WILLAMETTE */
        /* 361 355 001(c5) 110 026 : AR2,SB,SSE2,WILLAMETTE */
        {I_PEXTRW, 3, {REG_GPR|BITS32,XMMREG,IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+57838, 389},
    /*   2 : PEXTRW reg64,xmmreg,imm [rmi:      66 0f c5 /r ib,u                  ] ND,AR2,SB,LONG,PROT,SSE2,X86_64 */
        /* 361 355 001(c5) 110 026 : AR2,SB,LONG,PROT,SSE2,X86_64 */
        {I_PEXTRW, 3, {REG_GPR|BITS64,XMMREG,IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+57838, 390},
    /*   3 : PEXTRW reg32,xmmreg,imm8 [mri:      66 0f3a 15 /r ib,u                ] SSE41,FUTURE */
        /* 361 357 001(15) 101 026 : NOAPX,SSE41,FUTURE */
        {I_PEXTRW, 3, {REG_GPR|BITS32|RN_L16,XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51566, 410},
    /*   4 : PEXTRW mem16,xmmreg,imm8 [mri:      66 0f3a 15 /r ib,u                ] SSE41,FUTURE */
        /* 361 357 001(15) 101 026 : NOAPX,SSE41,FUTURE */
        {I_PEXTRW, 3, {MEMORY|BITS16|RN_L16,XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51566, 410},
    /*   5 : PEXTRW reg64,xmmreg,imm8 [mri:      o64 66 0f3a 15 /r ib,u            ] LONG,PROT,SSE41,X86_64 */
        /* 324 361 357 001(15) 101 026 : NOAPX,LONG,PROT,SSE41,X86_64 */
        {I_PEXTRW, 3, {REG_GPR|BITS64|RN_L16,XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51565, 411},
};

static const struct itemplate instrux_PINSRW[8] = {
    /*   0 : PINSRW mmxreg,mem,imm [rmi:      np 0f c4 /r ib,u                  ] AR2,SB,MMX,KATMAI */
        /* 360 355 001(c4) 110 026 : AR2,SB,MMX,KATMAI */
        {I_PINSRW, 3, {MMXREG,MEMORY,IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+57754, 381},
    /*   1 : PINSRW mmxreg,rm16,imm [rmi:      np 0f c4 /r ib,u                  ] AR2,SB,MMX,KATMAI */
        /* 360 355 001(c4) 110 026 : AR2,SB,MMX,KATMAI */
        {I_PINSRW, 3, {MMXREG,RM_GPR|BITS16,IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+57754, 381},
    /*   2 : PINSRW mmxreg,reg32,imm [rmi:      np 0f c4 /r ib,u                  ] AR2,SB,MMX,KATMAI */
        /* 360 355 001(c4) 110 026 : AR2,SB,MMX,KATMAI */
        {I_PINSRW, 3, {MMXREG,REG_GPR|BITS32,IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+57754, 381},
    /*   3 : PINSRW xmmreg,reg16,imm [rmi:      66 0f c4 /r ib,u                  ] AR2,SB,SSE2,WILLAMETTE */
        /* 361 355 001(c4) 110 026 : AR2,SB,SSE2,WILLAMETTE */
        {I_PINSRW, 3, {XMMREG,REG_GPR|BITS16,IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+57845, 389},
    /*   4 : PINSRW xmmreg,reg32,imm [rmi:      66 0f c4 /r ib,u                  ] ND,AR2,SB,SSE2,WILLAMETTE */
        /* 361 355 001(c4) 110 026 : AR2,SB,SSE2,WILLAMETTE */
        {I_PINSRW, 3, {XMMREG,REG_GPR|BITS32,IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+57845, 389},
    /*   5 : PINSRW xmmreg,reg64,imm [rmi:      66 0f c4 /r ib,u                  ] ND,AR2,SB,LONG,PROT,SSE2,X86_64 */
        /* 361 355 001(c4) 110 026 : AR2,SB,LONG,PROT,SSE2,X86_64 */
        {I_PINSRW, 3, {XMMREG,REG_GPR|BITS64,IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+57845, 390},
    /*   6 : PINSRW xmmreg,mem,imm [rmi:      66 0f c4 /r ib,u                  ] AR2,SB,SSE2,WILLAMETTE */
        /* 361 355 001(c4) 110 026 : AR2,SB,SSE2,WILLAMETTE */
        {I_PINSRW, 3, {XMMREG,MEMORY,IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+57845, 389},
    /*   7 : PINSRW xmmreg,mem16,imm [rmi:      66 0f c4 /r ib,u                  ] AR2,SB,SSE2,WILLAMETTE */
        /* 361 355 001(c4) 110 026 : AR2,SB,SSE2,WILLAMETTE */
        {I_PINSRW, 3, {XMMREG,MEMORY|BITS16,IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+57845, 389},
};

static const struct itemplate instrux_PMAXSW[2] = {
    /*   0 : PMAXSW mmxreg,mmxrm [rm:       np 0f ee /r                       ] AR0-1,SQ,MMX,KATMAI */
        /* 360 355 001(ee) 110 : AR0,AR1,SQ,MMX,KATMAI */
        {I_PMAXSW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+68480, 380},
    /*   1 : PMAXSW xmmreg,xmmrm [rm:       66 0f ee /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(ee) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PMAXSW, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68726, 382},
};

static const struct itemplate instrux_PMAXUB[2] = {
    /*   0 : PMAXUB mmxreg,mmxrm [rm:       np 0f de /r                       ] AR0-1,SQ,MMX,KATMAI */
        /* 360 355 001(de) 110 : AR0,AR1,SQ,MMX,KATMAI */
        {I_PMAXUB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+68486, 380},
    /*   1 : PMAXUB xmmreg,xmmrm [rm:       66 0f de /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(de) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PMAXUB, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68732, 382},
};

static const struct itemplate instrux_PMINSW[2] = {
    /*   0 : PMINSW mmxreg,mmxrm [rm:       np 0f ea /r                       ] AR0-1,SQ,MMX,KATMAI */
        /* 360 355 001(ea) 110 : AR0,AR1,SQ,MMX,KATMAI */
        {I_PMINSW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+68492, 380},
    /*   1 : PMINSW xmmreg,xmmrm [rm:       66 0f ea /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(ea) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PMINSW, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68738, 382},
};

static const struct itemplate instrux_PMINUB[2] = {
    /*   0 : PMINUB mmxreg,mmxrm [rm:       np 0f da /r                       ] AR0-1,SQ,MMX,KATMAI */
        /* 360 355 001(da) 110 : AR0,AR1,SQ,MMX,KATMAI */
        {I_PMINUB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+68498, 380},
    /*   1 : PMINUB xmmreg,xmmrm [rm:       66 0f da /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(da) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PMINUB, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68744, 382},
};

static const struct itemplate instrux_PMOVMSKB[2] = {
    /*   0 : PMOVMSKB reg32,mmxreg [rm:       np 0f d7 /r                       ] MMX,KATMAI */
        /* 360 355 001(d7) 110 : MMX,KATMAI */
        {I_PMOVMSKB, 2, {REG_GPR|BITS32,MMXREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+68504, 379},
    /*   1 : PMOVMSKB reg32,xmmreg [rm:       66 0f d7 /r                       ] SSE2,WILLAMETTE */
        /* 361 355 001(d7) 110 : SSE2,WILLAMETTE */
        {I_PMOVMSKB, 2, {REG_GPR|BITS32,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+68750, 250},
};

static const struct itemplate instrux_PMULHUW[2] = {
    /*   0 : PMULHUW mmxreg,mmxrm [rm:       np 0f e4 /r                       ] AR0-1,SQ,MMX,KATMAI */
        /* 360 355 001(e4) 110 : AR0,AR1,SQ,MMX,KATMAI */
        {I_PMULHUW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+68510, 380},
    /*   1 : PMULHUW xmmreg,xmmrm [rm:       66 0f e4 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(e4) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PMULHUW, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68756, 382},
};

static const struct itemplate instrux_PSADBW[2] = {
    /*   0 : PSADBW mmxreg,mmxrm [rm:       np 0f f6 /r                       ] AR0-1,SQ,MMX,KATMAI */
        /* 360 355 001(f6) 110 : AR0,AR1,SQ,MMX,KATMAI */
        {I_PSADBW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+68516, 380},
    /*   1 : PSADBW xmmreg,xmmrm [rm:       66 0f f6 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(f6) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PSADBW, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68792, 382},
};

static const struct itemplate instrux_PSHUFW[1] = {
    /*   0 : PSHUFW mmxreg,mmxrm,imm [rmi:      np 0f 70 /r ib                    ] AR2,SB,MMX,KATMAI */
        /* 360 355 001(70) 110 022 : AR2,SB,MMX,KATMAI */
        {I_PSHUFW, 3, {MMXREG,RM_MMX,IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+57761, 381},
};

static const struct itemplate instrux_PF2IW[1] = {
    /*   0 : PF2IW mmxreg,mmxrm [rm:       0f 0f /r 1c                       ] AR0-1,SQ,3DNOW,PENT */
        /* 355 001(0f) 110 001(1c) : AR0,AR1,SQ,3DNOW,PENT */
        {I_PF2IW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+57768, 338},
};

static const struct itemplate instrux_PFNACC[1] = {
    /*   0 : PFNACC mmxreg,mmxrm [rm:       0f 0f /r 8a                       ] AR0-1,SQ,3DNOW,PENT */
        /* 355 001(0f) 110 001(8a) : AR0,AR1,SQ,3DNOW,PENT */
        {I_PFNACC, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+57775, 338},
};

static const struct itemplate instrux_PFPNACC[1] = {
    /*   0 : PFPNACC mmxreg,mmxrm [rm:       0f 0f /r 8e                       ] AR0-1,SQ,3DNOW,PENT */
        /* 355 001(0f) 110 001(8e) : AR0,AR1,SQ,3DNOW,PENT */
        {I_PFPNACC, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+57782, 338},
};

static const struct itemplate instrux_PI2FW[1] = {
    /*   0 : PI2FW mmxreg,mmxrm [rm:       0f 0f /r 0c                       ] AR0-1,SQ,3DNOW,PENT */
        /* 355 001(0f) 110 001(0c) : AR0,AR1,SQ,3DNOW,PENT */
        {I_PI2FW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+57789, 338},
};

static const struct itemplate instrux_PSWAPD[1] = {
    /*   0 : PSWAPD mmxreg,mmxrm [rm:       0f 0f /r bb                       ] AR0-1,SQ,3DNOW,PENT */
        /* 355 001(0f) 110 001(bb) : AR0,AR1,SQ,3DNOW,PENT */
        {I_PSWAPD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+57796, 338},
};

static const struct itemplate instrux_MASKMOVDQU[1] = {
    /*   0 : MASKMOVDQU xmmreg,xmmreg [rm:       66 0f f7 /r                       ] SSE2,WILLAMETTE */
        /* 361 355 001(f7) 110 : SSE2,WILLAMETTE */
        {I_MASKMOVDQU, 2, {XMMREG,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+68522, 250},
};

static const struct itemplate instrux_MOVNTDQ[1] = {
    /*   0 : MOVNTDQ mem,xmmreg [mr:       66 0f e7 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(e7) 101 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_MOVNTDQ, 2, {MEMORY,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+68528, 382},
};

static const struct itemplate instrux_MOVNTI[2] = {
    /*   0 : MOVNTI mem,reg32 [mr:       np 0f c3 /r                       ] AR0-1,SD,WILLAMETTE */
        /* 360 355 001(c3) 101 : AR0,AR1,SD,WILLAMETTE */
        {I_MOVNTI, 2, {MEMORY,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+57804, 383},
    /*   1 : MOVNTI mem,reg64 [mr:       o64 np 0f c3 /r                   ] AR0-1,SQ,LONG,PROT,X86_64 */
        /* 324 360 355 001(c3) 101 : AR0,AR1,SQ,LONG,PROT,X86_64 */
        {I_MOVNTI, 2, {MEMORY,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+57803, 384},
};

static const struct itemplate instrux_MOVNTPD[1] = {
    /*   0 : MOVNTPD mem,xmmreg [mr:       66 0f 2b /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(2b) 101 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_MOVNTPD, 2, {MEMORY,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+68534, 382},
};

static const struct itemplate instrux_MOVDQA[2] = {
    /*   0 : MOVDQA xmmreg,xmmrm128 [rm:       66 0f 6f /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(6f) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_MOVDQA, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+68540, 382},
    /*   1 : MOVDQA xmmrm128,xmmreg [mr:       66 0f 7f /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(7f) 101 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_MOVDQA, 2, {RM_XMM|BITS128,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+68546, 382},
};

static const struct itemplate instrux_MOVDQU[2] = {
    /*   0 : MOVDQU xmmreg,xmmrm128 [rm:       f3 0f 6f /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 333 355 001(6f) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_MOVDQU, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+68552, 382},
    /*   1 : MOVDQU xmmrm128,xmmreg [mr:       f3 0f 7f /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 333 355 001(7f) 101 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_MOVDQU, 2, {RM_XMM|BITS128,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+68558, 382},
};

static const struct itemplate instrux_MOVDQ2Q[1] = {
    /*   0 : MOVDQ2Q mmxreg,xmmreg [rm:       f2 0f d6 /r                       ] SSE2,WILLAMETTE */
        /* 332 355 001(d6) 110 : SSE2,WILLAMETTE */
        {I_MOVDQ2Q, 2, {MMXREG,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+68564, 250},
};

static const struct itemplate instrux_MOVQ2DQ[1] = {
    /*   0 : MOVQ2DQ xmmreg,mmxreg [rm:       f3 0f d6 /r                       ] SSE2,WILLAMETTE */
        /* 333 355 001(d6) 110 : SSE2,WILLAMETTE */
        {I_MOVQ2DQ, 2, {XMMREG,MMXREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+68582, 250},
};

static const struct itemplate instrux_PADDQ[2] = {
    /*   0 : PADDQ mmxreg,mmxrm [rm:       np 0f d4 /r                       ] AR0-1,SQ,MMX,WILLAMETTE */
        /* 360 355 001(d4) 110 : AR0,AR1,SQ,MMX,WILLAMETTE */
        {I_PADDQ, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+68624, 388},
    /*   1 : PADDQ xmmreg,xmmrm [rm:       66 0f d4 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(d4) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PADDQ, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68630, 382},
};

static const struct itemplate instrux_PMULUDQ[2] = {
    /*   0 : PMULUDQ mmxreg,mmxrm [rm:       np 0f f4 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 360 355 001(f4) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PMULUDQ, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+68774, 382},
    /*   1 : PMULUDQ xmmreg,xmmrm [rm:       66 0f f4 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(f4) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PMULUDQ, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68780, 382},
};

static const struct itemplate instrux_PSHUFD[2] = {
    /*   0 : PSHUFD xmmreg,xmmreg,imm [rmi:      66 0f 70 /r ib                    ] AR2,SB,SSE2,WILLAMETTE */
        /* 361 355 001(70) 110 022 : AR2,SB,SSE2,WILLAMETTE */
        {I_PSHUFD, 3, {XMMREG,XMMREG,IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+57852, 389},
    /*   1 : PSHUFD xmmreg,mem,imm [rmi:      66 0f 70 /r ib                    ] AR2,SB,SSE2,WILLAMETTE */
        /* 361 355 001(70) 110 022 : AR2,SB,SSE2,WILLAMETTE */
        {I_PSHUFD, 3, {XMMREG,MEMORY,IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+57852, 389},
};

static const struct itemplate instrux_PSHUFHW[2] = {
    /*   0 : PSHUFHW xmmreg,xmmreg,imm [rmi:      f3 0f 70 /r ib                    ] AR2,SB,SSE2,WILLAMETTE */
        /* 333 355 001(70) 110 022 : AR2,SB,SSE2,WILLAMETTE */
        {I_PSHUFHW, 3, {XMMREG,XMMREG,IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+57859, 389},
    /*   1 : PSHUFHW xmmreg,mem,imm [rmi:      f3 0f 70 /r ib                    ] AR2,SB,SSE2,WILLAMETTE */
        /* 333 355 001(70) 110 022 : AR2,SB,SSE2,WILLAMETTE */
        {I_PSHUFHW, 3, {XMMREG,MEMORY,IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+57859, 389},
};

static const struct itemplate instrux_PSHUFLW[2] = {
    /*   0 : PSHUFLW xmmreg,xmmreg,imm [rmi:      f2 0f 70 /r ib                    ] AR2,SB,SSE2,WILLAMETTE */
        /* 332 355 001(70) 110 022 : AR2,SB,SSE2,WILLAMETTE */
        {I_PSHUFLW, 3, {XMMREG,XMMREG,IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+57866, 389},
    /*   1 : PSHUFLW xmmreg,mem,imm [rmi:      f2 0f 70 /r ib                    ] AR2,SB,SSE2,WILLAMETTE */
        /* 332 355 001(70) 110 022 : AR2,SB,SSE2,WILLAMETTE */
        {I_PSHUFLW, 3, {XMMREG,MEMORY,IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+57866, 389},
};

static const struct itemplate instrux_PSLLDQ[1] = {
    /*   0 : PSLLDQ xmmreg,imm [mi:       66 0f 73 /7 ib,u                  ] AR1,SB,SSE2,WILLAMETTE */
        /* 361 355 001(73) 207 025 : AR1,SB,SSE2,WILLAMETTE */
        {I_PSLLDQ, 2, {XMMREG,IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+57873, 391},
};

static const struct itemplate instrux_PSRLDQ[1] = {
    /*   0 : PSRLDQ xmmreg,imm [mi:       66 0f 73 /3 ib,u                  ] AR1,SB,SSE2,WILLAMETTE */
        /* 361 355 001(73) 203 025 : AR1,SB,SSE2,WILLAMETTE */
        {I_PSRLDQ, 2, {XMMREG,IMM_NORMAL,0,0,0}, NO_DECORATOR, nasm_bytecodes+57915, 391},
};

static const struct itemplate instrux_PSUBQ[2] = {
    /*   0 : PSUBQ mmxreg,mmxrm [rm:       np 0f fb /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 360 355 001(fb) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PSUBQ, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+68864, 382},
    /*   1 : PSUBQ xmmreg,xmmrm [rm:       66 0f fb /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(fb) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PSUBQ, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68870, 382},
};

static const struct itemplate instrux_PUNPCKHQDQ[1] = {
    /*   0 : PUNPCKHQDQ xmmreg,xmmrm [rm:       66 0f 6d /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(6d) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PUNPCKHQDQ, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68918, 382},
};

static const struct itemplate instrux_PUNPCKLQDQ[1] = {
    /*   0 : PUNPCKLQDQ xmmreg,xmmrm [rm:       66 0f 6c /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(6c) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_PUNPCKLQDQ, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68942, 382},
};

static const struct itemplate instrux_ADDPD[1] = {
    /*   0 : ADDPD xmmreg,xmmrm [rm:       66 0f 58 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(58) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_ADDPD, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68954, 382},
};

static const struct itemplate instrux_ADDSD[1] = {
    /*   0 : ADDSD xmmreg,xmmrm [rm:       f2 0f 58 /r                       ] AR0-1,SQ,SSE2,WILLAMETTE */
        /* 332 355 001(58) 110 : AR0,AR1,SQ,SSE2,WILLAMETTE */
        {I_ADDSD, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68960, 386},
};

static const struct itemplate instrux_ANDNPD[1] = {
    /*   0 : ANDNPD xmmreg,xmmrm [rm:       66 0f 55 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(55) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_ANDNPD, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68966, 382},
};

static const struct itemplate instrux_ANDPD[1] = {
    /*   0 : ANDPD xmmreg,xmmrm [rm:       66 0f 54 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(54) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_ANDPD, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68972, 382},
};

static const struct itemplate instrux_CMPEQPD[1] = {
    /*   0 : CMPEQPD xmmreg,xmmrm [rm:       66 0f c2 /r 00                    ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(c2) 110 001(00) : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_CMPEQPD, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+51389, 382},
};

static const struct itemplate instrux_CMPEQSD[1] = {
    /*   0 : CMPEQSD xmmreg,xmmrm [rm:       f2 0f c2 /r 00                    ] AR0-1,SQ,SSE2,WILLAMETTE */
        /* 332 355 001(c2) 110 001(00) : AR0,AR1,SQ,SSE2,WILLAMETTE */
        {I_CMPEQSD, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+51397, 386},
};

static const struct itemplate instrux_CMPLEPD[1] = {
    /*   0 : CMPLEPD xmmreg,xmmrm [rm:       66 0f c2 /r 02                    ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(c2) 110 001(02) : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_CMPLEPD, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+51405, 382},
};

static const struct itemplate instrux_CMPLESD[1] = {
    /*   0 : CMPLESD xmmreg,xmmrm [rm:       f2 0f c2 /r 02                    ] AR0-1,SQ,SSE2,WILLAMETTE */
        /* 332 355 001(c2) 110 001(02) : AR0,AR1,SQ,SSE2,WILLAMETTE */
        {I_CMPLESD, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+51413, 386},
};

static const struct itemplate instrux_CMPLTPD[1] = {
    /*   0 : CMPLTPD xmmreg,xmmrm [rm:       66 0f c2 /r 01                    ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(c2) 110 001(01) : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_CMPLTPD, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+51421, 382},
};

static const struct itemplate instrux_CMPLTSD[1] = {
    /*   0 : CMPLTSD xmmreg,xmmrm [rm:       f2 0f c2 /r 01                    ] AR0-1,SQ,SSE2,WILLAMETTE */
        /* 332 355 001(c2) 110 001(01) : AR0,AR1,SQ,SSE2,WILLAMETTE */
        {I_CMPLTSD, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+51429, 386},
};

static const struct itemplate instrux_CMPNEQPD[1] = {
    /*   0 : CMPNEQPD xmmreg,xmmrm [rm:       66 0f c2 /r 04                    ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(c2) 110 001(04) : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_CMPNEQPD, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+51437, 382},
};

static const struct itemplate instrux_CMPNEQSD[1] = {
    /*   0 : CMPNEQSD xmmreg,xmmrm [rm:       f2 0f c2 /r 04                    ] AR0-1,SQ,SSE2,WILLAMETTE */
        /* 332 355 001(c2) 110 001(04) : AR0,AR1,SQ,SSE2,WILLAMETTE */
        {I_CMPNEQSD, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+51445, 386},
};

static const struct itemplate instrux_CMPNLEPD[1] = {
    /*   0 : CMPNLEPD xmmreg,xmmrm [rm:       66 0f c2 /r 06                    ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(c2) 110 001(06) : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_CMPNLEPD, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+51453, 382},
};

static const struct itemplate instrux_CMPNLESD[1] = {
    /*   0 : CMPNLESD xmmreg,xmmrm [rm:       f2 0f c2 /r 06                    ] AR0-1,SQ,SSE2,WILLAMETTE */
        /* 332 355 001(c2) 110 001(06) : AR0,AR1,SQ,SSE2,WILLAMETTE */
        {I_CMPNLESD, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+51461, 386},
};

static const struct itemplate instrux_CMPNLTPD[1] = {
    /*   0 : CMPNLTPD xmmreg,xmmrm [rm:       66 0f c2 /r 05                    ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(c2) 110 001(05) : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_CMPNLTPD, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+51469, 382},
};

static const struct itemplate instrux_CMPNLTSD[1] = {
    /*   0 : CMPNLTSD xmmreg,xmmrm [rm:       f2 0f c2 /r 05                    ] AR0-1,SQ,SSE2,WILLAMETTE */
        /* 332 355 001(c2) 110 001(05) : AR0,AR1,SQ,SSE2,WILLAMETTE */
        {I_CMPNLTSD, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+51477, 386},
};

static const struct itemplate instrux_CMPORDPD[1] = {
    /*   0 : CMPORDPD xmmreg,xmmrm [rm:       66 0f c2 /r 07                    ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(c2) 110 001(07) : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_CMPORDPD, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+51485, 382},
};

static const struct itemplate instrux_CMPORDSD[1] = {
    /*   0 : CMPORDSD xmmreg,xmmrm [rm:       f2 0f c2 /r 07                    ] AR0-1,SQ,SSE2,WILLAMETTE */
        /* 332 355 001(c2) 110 001(07) : AR0,AR1,SQ,SSE2,WILLAMETTE */
        {I_CMPORDSD, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+51493, 386},
};

static const struct itemplate instrux_CMPUNORDPD[1] = {
    /*   0 : CMPUNORDPD xmmreg,xmmrm [rm:       66 0f c2 /r 03                    ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(c2) 110 001(03) : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_CMPUNORDPD, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+51501, 382},
};

static const struct itemplate instrux_CMPUNORDSD[1] = {
    /*   0 : CMPUNORDSD xmmreg,xmmrm [rm:       f2 0f c2 /r 03                    ] AR0-1,SQ,SSE2,WILLAMETTE */
        /* 332 355 001(c2) 110 001(03) : AR0,AR1,SQ,SSE2,WILLAMETTE */
        {I_CMPUNORDSD, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+51509, 386},
};

static const struct itemplate instrux_CMPPD[1] = {
    /*   0 : CMPPD xmmreg,xmmrm128,imm8 [rmi:      66 0f c2 /r ib,u                  ] SSE2,WILLAMETTE */
        /* 361 355 001(c2) 110 026 : SSE2,WILLAMETTE */
        {I_CMPPD, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+57943, 250},
};

static const struct itemplate instrux_COMISD[1] = {
    /*   0 : COMISD xmmreg,xmmrm64 [rm:       66 0f 2f /r                       ] FL,SSE2,WILLAMETTE */
        /* 361 355 001(2f) 110 : FL,SSE2,WILLAMETTE */
        {I_COMISD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+68978, 392},
};

static const struct itemplate instrux_CVTDQ2PD[1] = {
    /*   0 : CVTDQ2PD xmmreg,xmmrm [rm:       f3 0f e6 /r                       ] AR0-1,SQ,SSE2,WILLAMETTE */
        /* 333 355 001(e6) 110 : AR0,AR1,SQ,SSE2,WILLAMETTE */
        {I_CVTDQ2PD, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68984, 386},
};

static const struct itemplate instrux_CVTDQ2PS[1] = {
    /*   0 : CVTDQ2PS xmmreg,xmmrm [rm:       np 0f 5b /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 360 355 001(5b) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_CVTDQ2PS, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68990, 382},
};

static const struct itemplate instrux_CVTPD2DQ[1] = {
    /*   0 : CVTPD2DQ xmmreg,xmmrm [rm:       f2 0f e6 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 332 355 001(e6) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_CVTPD2DQ, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+68996, 382},
};

static const struct itemplate instrux_CVTPD2PI[1] = {
    /*   0 : CVTPD2PI mmxreg,xmmrm [rm:       66 0f 2d /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(2d) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_CVTPD2PI, 2, {MMXREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+69002, 382},
};

static const struct itemplate instrux_CVTPD2PS[1] = {
    /*   0 : CVTPD2PS xmmreg,xmmrm [rm:       66 0f 5a /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(5a) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_CVTPD2PS, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+69008, 382},
};

static const struct itemplate instrux_CVTPI2PD[1] = {
    /*   0 : CVTPI2PD xmmreg,mmxrm [rm:       66 0f 2a /r                       ] AR0-1,SQ,SSE2,WILLAMETTE */
        /* 361 355 001(2a) 110 : AR0,AR1,SQ,SSE2,WILLAMETTE */
        {I_CVTPI2PD, 2, {XMMREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+69014, 386},
};

static const struct itemplate instrux_CVTPS2DQ[1] = {
    /*   0 : CVTPS2DQ xmmreg,xmmrm [rm:       66 0f 5b /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(5b) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_CVTPS2DQ, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+69020, 382},
};

static const struct itemplate instrux_CVTPS2PD[1] = {
    /*   0 : CVTPS2PD xmmreg,xmmrm [rm:       np 0f 5a /r                       ] AR0-1,SQ,SSE2,WILLAMETTE */
        /* 360 355 001(5a) 110 : AR0,AR1,SQ,SSE2,WILLAMETTE */
        {I_CVTPS2PD, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+69026, 386},
};

static const struct itemplate instrux_CVTSD2SI[2] = {
    /*   0 : CVTSD2SI reg32,xmmrm64 [rm:       norexw f2 0f 2d /r                ] SSE2,WILLAMETTE */
        /* 317 332 355 001(2d) 110 : SSE2,WILLAMETTE */
        {I_CVTSD2SI, 2, {REG_GPR|BITS32,RM_XMM|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+57957, 250},
    /*   1 : CVTSD2SI reg64,xmmrm64 [rm:       o64 f2 0f 2d /r                   ] LONG,PROT,SSE2,X86_64 */
        /* 324 332 355 001(2d) 110 : LONG,PROT,SSE2,X86_64 */
        {I_CVTSD2SI, 2, {REG_GPR|BITS64,RM_XMM|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+57964, 387},
};

static const struct itemplate instrux_CVTSD2SS[1] = {
    /*   0 : CVTSD2SS xmmreg,xmmrm64 [rm:       f2 0f 5a /r                       ] AR0-1,SQ,SSE2,WILLAMETTE */
        /* 332 355 001(5a) 110 : AR0,AR1,SQ,SSE2,WILLAMETTE */
        {I_CVTSD2SS, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+69032, 386},
};

static const struct itemplate instrux_CVTSI2SD[2] = {
    /*   0 : CVTSI2SD xmmreg,rm32 [rm:       norexw f2 0f 2a /r                ] SSE2,WILLAMETTE */
        /* 317 332 355 001(2a) 110 : SSE2,WILLAMETTE */
        {I_CVTSI2SD, 2, {XMMREG,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+57971, 250},
    /*   1 : CVTSI2SD xmmreg,rm64 [rm:       o64 f2 0f 2a /r                   ] AR1,SX,LONG,PROT,SSE2,X86_64 */
        /* 324 332 355 001(2a) 110 : AR1,SX,LONG,PROT,SSE2,X86_64 */
        {I_CVTSI2SD, 2, {XMMREG,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+57978, 393},
};

static const struct itemplate instrux_CVTSS2SD[1] = {
    /*   0 : CVTSS2SD xmmreg,xmmrm [rm:       f3 0f 5a /r                       ] AR0-1,SD,SSE2,WILLAMETTE */
        /* 333 355 001(5a) 110 : AR0,AR1,SD,SSE2,WILLAMETTE */
        {I_CVTSS2SD, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+69038, 385},
};

static const struct itemplate instrux_CVTTPD2PI[1] = {
    /*   0 : CVTTPD2PI mmxreg,xmmrm [rm:       66 0f 2c /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(2c) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_CVTTPD2PI, 2, {MMXREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+69044, 382},
};

static const struct itemplate instrux_CVTTPD2DQ[1] = {
    /*   0 : CVTTPD2DQ xmmreg,xmmrm [rm:       66 0f e6 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(e6) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_CVTTPD2DQ, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+69050, 382},
};

static const struct itemplate instrux_CVTTPS2DQ[1] = {
    /*   0 : CVTTPS2DQ xmmreg,xmmrm [rm:       f3 0f 5b /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 333 355 001(5b) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_CVTTPS2DQ, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+69056, 382},
};

static const struct itemplate instrux_CVTTSD2SI[2] = {
    /*   0 : CVTTSD2SI reg32,xmmrm64 [rm:       norexw f2 0f 2c /r                ] SSE2,WILLAMETTE */
        /* 317 332 355 001(2c) 110 : SSE2,WILLAMETTE */
        {I_CVTTSD2SI, 2, {REG_GPR|BITS32,RM_XMM|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+57985, 250},
    /*   1 : CVTTSD2SI reg64,xmmrm64 [rm:       o64 f2 0f 2c /r                   ] LONG,PROT,SSE2,X86_64 */
        /* 324 332 355 001(2c) 110 : LONG,PROT,SSE2,X86_64 */
        {I_CVTTSD2SI, 2, {REG_GPR|BITS64,RM_XMM|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+57992, 387},
};

static const struct itemplate instrux_DIVPD[1] = {
    /*   0 : DIVPD xmmreg,xmmrm [rm:       66 0f 5e /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(5e) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_DIVPD, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+69062, 382},
};

static const struct itemplate instrux_DIVSD[1] = {
    /*   0 : DIVSD xmmreg,xmmrm [rm:       f2 0f 5e /r                       ] AR0-1,SQ,SSE2,WILLAMETTE */
        /* 332 355 001(5e) 110 : AR0,AR1,SQ,SSE2,WILLAMETTE */
        {I_DIVSD, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+69068, 386},
};

static const struct itemplate instrux_MAXPD[1] = {
    /*   0 : MAXPD xmmreg,xmmrm [rm:       66 0f 5f /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(5f) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_MAXPD, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+69074, 382},
};

static const struct itemplate instrux_MAXSD[1] = {
    /*   0 : MAXSD xmmreg,xmmrm [rm:       f2 0f 5f /r                       ] AR0-1,SQ,SSE2,WILLAMETTE */
        /* 332 355 001(5f) 110 : AR0,AR1,SQ,SSE2,WILLAMETTE */
        {I_MAXSD, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+69080, 386},
};

static const struct itemplate instrux_MINPD[1] = {
    /*   0 : MINPD xmmreg,xmmrm [rm:       66 0f 5d /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(5d) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_MINPD, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+69086, 382},
};

static const struct itemplate instrux_MINSD[1] = {
    /*   0 : MINSD xmmreg,xmmrm [rm:       f2 0f 5d /r                       ] AR0-1,SQ,SSE2,WILLAMETTE */
        /* 332 355 001(5d) 110 : AR0,AR1,SQ,SSE2,WILLAMETTE */
        {I_MINSD, 2, {XMMREG,RM_XMM,0,0,0}, NO_DECORATOR, nasm_bytecodes+69092, 386},
};

static const struct itemplate instrux_MOVAPD[2] = {
    /*   0 : MOVAPD xmmreg,xmmrm128 [rm:       66 0f 28 /r                       ] SSE2,WILLAMETTE */
        /* 361 355 001(28) 110 : SSE2,WILLAMETTE */
        {I_MOVAPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+69098, 250},
    /*   1 : MOVAPD xmmrm128,xmmreg [mr:       66 0f 29 /r                       ] SSE2,WILLAMETTE */
        /* 361 355 001(29) 101 : SSE2,WILLAMETTE */
        {I_MOVAPD, 2, {RM_XMM|BITS128,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+69104, 250},
};

static const struct itemplate instrux_MOVHPD[2] = {
    /*   0 : MOVHPD mem64,xmmreg [mr:       66 0f 17 /r                       ] SSE2,WILLAMETTE */
        /* 361 355 001(17) 101 : SSE2,WILLAMETTE */
        {I_MOVHPD, 2, {MEMORY|BITS64,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+69110, 250},
    /*   1 : MOVHPD xmmreg,mem64 [rm:       66 0f 16 /r                       ] SSE2,WILLAMETTE */
        /* 361 355 001(16) 110 : SSE2,WILLAMETTE */
        {I_MOVHPD, 2, {XMMREG,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+69116, 250},
};

static const struct itemplate instrux_MOVLPD[2] = {
    /*   0 : MOVLPD mem64,xmmreg [mr:       66 0f 13 /r                       ] SSE2,WILLAMETTE */
        /* 361 355 001(13) 101 : SSE2,WILLAMETTE */
        {I_MOVLPD, 2, {MEMORY|BITS64,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+69122, 250},
    /*   1 : MOVLPD xmmreg,mem64 [rm:       66 0f 12 /r                       ] SSE2,WILLAMETTE */
        /* 361 355 001(12) 110 : SSE2,WILLAMETTE */
        {I_MOVLPD, 2, {XMMREG,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+69128, 250},
};

static const struct itemplate instrux_MOVMSKPD[2] = {
    /*   0 : MOVMSKPD reg32,xmmreg [rm:       66 0f 50 /r                       ] SSE2,WILLAMETTE */
        /* 361 355 001(50) 110 : SSE2,WILLAMETTE */
        {I_MOVMSKPD, 2, {REG_GPR|BITS32,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+69134, 250},
    /*   1 : MOVMSKPD reg64,xmmreg [rm:       66 o64 0f 50 /r                   ] LONG,PROT,SSE2,X86_64 */
        /* 361 324 355 001(50) 110 : LONG,PROT,SSE2,X86_64 */
        {I_MOVMSKPD, 2, {REG_GPR|BITS64,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+57999, 387},
};

static const struct itemplate instrux_MOVUPD[2] = {
    /*   0 : MOVUPD xmmreg,xmmrm128 [rm:       66 0f 10 /r                       ] SSE2,WILLAMETTE */
        /* 361 355 001(10) 110 : SSE2,WILLAMETTE */
        {I_MOVUPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+69152, 250},
    /*   1 : MOVUPD xmmrm128,xmmreg [mr:       66 0f 11 /r                       ] SSE2,WILLAMETTE */
        /* 361 355 001(11) 101 : SSE2,WILLAMETTE */
        {I_MOVUPD, 2, {RM_XMM|BITS128,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+69158, 250},
};

static const struct itemplate instrux_MULPD[1] = {
    /*   0 : MULPD xmmreg,xmmrm128 [rm:       66 0f 59 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(59) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_MULPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+69164, 382},
};

static const struct itemplate instrux_MULSD[1] = {
    /*   0 : MULSD xmmreg,xmmrm64 [rm:       f2 0f 59 /r                       ] AR0-1,SQ,SSE2,WILLAMETTE */
        /* 332 355 001(59) 110 : AR0,AR1,SQ,SSE2,WILLAMETTE */
        {I_MULSD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+69170, 386},
};

static const struct itemplate instrux_ORPD[1] = {
    /*   0 : ORPD xmmreg,xmmrm128 [rm:       66 0f 56 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(56) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_ORPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+69176, 382},
};

static const struct itemplate instrux_SHUFPD[1] = {
    /*   0 : SHUFPD xmmreg,xmmrm128,imm8 [rmi:      66 0f c6 /r ib,u                  ] SSE2,WILLAMETTE */
        /* 361 355 001(c6) 110 026 : SSE2,WILLAMETTE */
        {I_SHUFPD, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+58006, 250},
};

static const struct itemplate instrux_SQRTPD[1] = {
    /*   0 : SQRTPD xmmreg,xmmrm128 [rm:       66 0f 51 /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(51) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_SQRTPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+69182, 382},
};

static const struct itemplate instrux_SQRTSD[1] = {
    /*   0 : SQRTSD xmmreg,xmmrm64 [rm:       f2 0f 51 /r                       ] SSE2,WILLAMETTE */
        /* 332 355 001(51) 110 : SSE2,WILLAMETTE */
        {I_SQRTSD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+69188, 250},
};

static const struct itemplate instrux_SUBPD[1] = {
    /*   0 : SUBPD xmmreg,xmmrm128 [rm:       66 0f 5c /r                       ] AR0-1,SO,SSE2,WILLAMETTE */
        /* 361 355 001(5c) 110 : AR0,AR1,SO,SSE2,WILLAMETTE */
        {I_SUBPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+69194, 382},
};

static const struct itemplate instrux_SUBSD[1] = {
    /*   0 : SUBSD xmmreg,xmmrm64 [rm:       f2 0f 5c /r                       ] SSE2,WILLAMETTE */
        /* 332 355 001(5c) 110 : SSE2,WILLAMETTE */
        {I_SUBSD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+69200, 250},
};

static const struct itemplate instrux_UCOMISD[1] = {
    /*   0 : UCOMISD xmmreg,xmmrm64 [rm:       66 0f 2e /r                       ] FL,SSE2,WILLAMETTE */
        /* 361 355 001(2e) 110 : FL,SSE2,WILLAMETTE */
        {I_UCOMISD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+69206, 392},
};

static const struct itemplate instrux_UNPCKHPD[1] = {
    /*   0 : UNPCKHPD xmmreg,xmmrm128 [rm:       66 0f 15 /r                       ] SSE2,WILLAMETTE */
        /* 361 355 001(15) 110 : SSE2,WILLAMETTE */
        {I_UNPCKHPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+69212, 250},
};

static const struct itemplate instrux_UNPCKLPD[1] = {
    /*   0 : UNPCKLPD xmmreg,xmmrm128 [rm:       66 0f 14 /r                       ] SSE2,WILLAMETTE */
        /* 361 355 001(14) 110 : SSE2,WILLAMETTE */
        {I_UNPCKLPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+69218, 250},
};

static const struct itemplate instrux_XORPD[1] = {
    /*   0 : XORPD xmmreg,xmmrm128 [rm:       66 0f 57 /r                       ] SSE2,WILLAMETTE */
        /* 361 355 001(57) 110 : SSE2,WILLAMETTE */
        {I_XORPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+69224, 250},
};

static const struct itemplate instrux_ADDSUBPD[1] = {
    /*   0 : ADDSUBPD xmmreg,xmmrm128 [rm:       66 0f d0 /r                       ] AR0-1,SO,SSE3,PRESCOTT */
        /* 361 355 001(d0) 110 : AR0,AR1,SO,SSE3,PRESCOTT */
        {I_ADDSUBPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+69230, 394},
};

static const struct itemplate instrux_ADDSUBPS[1] = {
    /*   0 : ADDSUBPS xmmreg,xmmrm128 [rm:       f2 0f d0 /r                       ] AR0-1,SO,SSE3,PRESCOTT */
        /* 332 355 001(d0) 110 : AR0,AR1,SO,SSE3,PRESCOTT */
        {I_ADDSUBPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+69236, 394},
};

static const struct itemplate instrux_HADDPD[1] = {
    /*   0 : HADDPD xmmreg,xmmrm128 [rm:       66 0f 7c /r                       ] AR0-1,SO,SSE3,PRESCOTT */
        /* 361 355 001(7c) 110 : AR0,AR1,SO,SSE3,PRESCOTT */
        {I_HADDPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+69242, 394},
};

static const struct itemplate instrux_HADDPS[1] = {
    /*   0 : HADDPS xmmreg,xmmrm128 [rm:       f2 0f 7c /r                       ] AR0-1,SO,SSE3,PRESCOTT */
        /* 332 355 001(7c) 110 : AR0,AR1,SO,SSE3,PRESCOTT */
        {I_HADDPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+69248, 394},
};

static const struct itemplate instrux_HSUBPD[1] = {
    /*   0 : HSUBPD xmmreg,xmmrm128 [rm:       66 0f 7d /r                       ] AR0-1,SO,SSE3,PRESCOTT */
        /* 361 355 001(7d) 110 : AR0,AR1,SO,SSE3,PRESCOTT */
        {I_HSUBPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+69254, 394},
};

static const struct itemplate instrux_HSUBPS[1] = {
    /*   0 : HSUBPS xmmreg,xmmrm128 [rm:       f2 0f 7d /r                       ] AR0-1,SO,SSE3,PRESCOTT */
        /* 332 355 001(7d) 110 : AR0,AR1,SO,SSE3,PRESCOTT */
        {I_HSUBPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+69260, 394},
};

static const struct itemplate instrux_LDDQU[1] = {
    /*   0 : LDDQU xmmreg,mem128 [rm:       f2 0f f0 /r                       ] AR0-1,SO,SSE3,PRESCOTT */
        /* 332 355 001(f0) 110 : AR0,AR1,SO,SSE3,PRESCOTT */
        {I_LDDQU, 2, {XMMREG,MEMORY|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+69266, 394},
};

static const struct itemplate instrux_MOVDDUP[1] = {
    /*   0 : MOVDDUP xmmreg,xmmrm64 [rm:       f2 0f 12 /r                       ] AR0-1,SQ,SSE3,PRESCOTT */
        /* 332 355 001(12) 110 : AR0,AR1,SQ,SSE3,PRESCOTT */
        {I_MOVDDUP, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+69272, 395},
};

static const struct itemplate instrux_MOVSHDUP[1] = {
    /*   0 : MOVSHDUP xmmreg,xmmrm128 [rm:       f3 0f 16 /r                       ] SSE3,PRESCOTT */
        /* 333 355 001(16) 110 : SSE3,PRESCOTT */
        {I_MOVSHDUP, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+69278, 396},
};

static const struct itemplate instrux_MOVSLDUP[1] = {
    /*   0 : MOVSLDUP xmmreg,xmmrm128 [rm:       f3 0f 12 /r                       ] SSE3,PRESCOTT */
        /* 333 355 001(12) 110 : SSE3,PRESCOTT */
        {I_MOVSLDUP, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+69284, 396},
};

static const struct itemplate instrux_CLGI[1] = {
    /*   0 : CLGI void [          0f 01 dd                          ] VMX,FUTURE,AMD */
        /* 355 002(01 dd) : VMX,FUTURE,AMD */
        {I_CLGI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72313, 397},
};

static const struct itemplate instrux_STGI[1] = {
    /*   0 : STGI void [          0f 01 dc                          ] VMX,FUTURE,AMD */
        /* 355 002(01 dc) : VMX,FUTURE,AMD */
        {I_STGI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72318, 397},
};

static const struct itemplate instrux_VMCALL[1] = {
    /*   0 : VMCALL void [          0f 01 c1                          ] VMX,FUTURE */
        /* 355 002(01 c1) : VMX,FUTURE */
        {I_VMCALL, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+69327, 398},
};

static const struct itemplate instrux_VMCLEAR[1] = {
    /*   0 : VMCLEAR mem [m:        66 0f c7 /6                       ] VMX,FUTURE */
        /* 361 355 001(c7) 206 : VMX,FUTURE */
        {I_VMCLEAR, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+69290, 398},
};

static const struct itemplate instrux_VMFUNC[1] = {
    /*   0 : VMFUNC void [          0f 01 d4                          ] VMX,FUTURE */
        /* 355 002(01 d4) : VMX,FUTURE */
        {I_VMFUNC, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72323, 398},
};

static const struct itemplate instrux_VMLAUNCH[1] = {
    /*   0 : VMLAUNCH void [          0f 01 c2                          ] VMX,FUTURE */
        /* 355 002(01 c2) : VMX,FUTURE */
        {I_VMLAUNCH, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72328, 398},
};

static const struct itemplate instrux_VMLOAD[1] = {
    /*   0 : VMLOAD void [          0f 01 da                          ] VMX,FUTURE,AMD */
        /* 355 002(01 da) : VMX,FUTURE,AMD */
        {I_VMLOAD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72333, 397},
};

static const struct itemplate instrux_VMMCALL[1] = {
    /*   0 : VMMCALL void [          0f 01 d9                          ] VMX,FUTURE,AMD */
        /* 355 002(01 d9) : VMX,FUTURE,AMD */
        {I_VMMCALL, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72338, 397},
};

static const struct itemplate instrux_VMPTRLD[1] = {
    /*   0 : VMPTRLD mem [m:        np 0f c7 /6                       ] VMX,FUTURE */
        /* 360 355 001(c7) 206 : VMX,FUTURE */
        {I_VMPTRLD, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+69296, 398},
};

static const struct itemplate instrux_VMPTRST[1] = {
    /*   0 : VMPTRST mem [m:        np 0f c7 /7                       ] VMX,FUTURE */
        /* 360 355 001(c7) 207 : VMX,FUTURE */
        {I_VMPTRST, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+69302, 398},
};

static const struct itemplate instrux_VMREAD[2] = {
    /*   0 : VMREAD rm32,reg32 [mr:       np 0f 78 /r                       ] AR0-1,SD,NOREX,NOAPX,NOLONG,VMX,FUTURE */
        /* 360 355 001(78) 101 : AR0,AR1,SD,NOREX,NOAPX,NOLONG,VMX,FUTURE */
        {I_VMREAD, 2, {RM_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58014, 399},
    /*   1 : VMREAD rm64,reg64 [mr:       o64nw np 0f 78 /r                 ] AR0-1,SQ,LONG,PROT,VMX,X86_64 */
        /* 323 360 355 001(78) 101 : AR0,AR1,SQ,NWSIZE,LONG,PROT,VMX,X86_64 */
        {I_VMREAD, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+58013, 400},
};

static const struct itemplate instrux_VMRESUME[1] = {
    /*   0 : VMRESUME void [          0f 01 c3                          ] VMX,FUTURE */
        /* 355 002(01 c3) : VMX,FUTURE */
        {I_VMRESUME, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72343, 398},
};

static const struct itemplate instrux_VMRUN[1] = {
    /*   0 : VMRUN void [          0f 01 d8                          ] VMX,FUTURE,AMD */
        /* 355 002(01 d8) : VMX,FUTURE,AMD */
        {I_VMRUN, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72348, 397},
};

static const struct itemplate instrux_VMSAVE[1] = {
    /*   0 : VMSAVE void [          0f 01 db                          ] VMX,FUTURE,AMD */
        /* 355 002(01 db) : VMX,FUTURE,AMD */
        {I_VMSAVE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72353, 397},
};

static const struct itemplate instrux_VMWRITE[2] = {
    /*   0 : VMWRITE reg32,rm32 [rm:       np 0f 79 /r                       ] AR0-1,SD,NOREX,NOAPX,NOLONG,VMX,FUTURE */
        /* 360 355 001(79) 110 : AR0,AR1,SD,NOREX,NOAPX,NOLONG,VMX,FUTURE */
        {I_VMWRITE, 2, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58021, 399},
    /*   1 : VMWRITE reg64,rm64 [rm:       o64nw np 0f 79 /r                 ] AR0-1,SQ,LONG,PROT,VMX,X86_64 */
        /* 323 360 355 001(79) 110 : AR0,AR1,SQ,NWSIZE,LONG,PROT,VMX,X86_64 */
        {I_VMWRITE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+58020, 400},
};

static const struct itemplate instrux_VMXOFF[1] = {
    /*   0 : VMXOFF void [          0f 01 c4                          ] VMX,FUTURE */
        /* 355 002(01 c4) : VMX,FUTURE */
        {I_VMXOFF, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72358, 398},
};

static const struct itemplate instrux_VMXON[1] = {
    /*   0 : VMXON mem [m:        f3 0f c7 /6                       ] VMX,FUTURE */
        /* 333 355 001(c7) 206 : VMX,FUTURE */
        {I_VMXON, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66211, 398},
};

static const struct itemplate instrux_INVEPT[3] = {
    /*   0 : INVEPT reg32,mem [rm:       66 0f38 80 /r                     ] AR0-1,SO,NOREX,NOAPX,NOLONG,VMX,FUTURE */
        /* 361 356 001(80) 110 : AR0,AR1,SO,NOREX,NOAPX,NOLONG,VMX,FUTURE */
        {I_INVEPT, 2, {REG_GPR|BITS32|RN_L16,MEMORY|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58028, 401},
    /*   1 : INVEPT reg64,mem [rm:       o64nw 66 0f38 80 /r               ] AR0-1,SO,LONG,PROT,VMX,X86_64 */
        /* 323 361 356 001(80) 110 : AR0,AR1,SO,NWSIZE,NOAPX,LONG,PROT,VMX,X86_64 */
        {I_INVEPT, 2, {REG_GPR|BITS64|RN_L16,MEMORY|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58027, 402},
    /*   2 : INVEPT reg64,mem128 [rm:       evex.nf0.nd0.l0.f3.m4.w1 f0 /r    ] AR0-1,SO,LONG,PROT,VMX,APX,X86_64 */
        /* 250(f4 fe 08) 300 001(f0) 110 : AR0,AR1,SO,LONG,EVEX,PROT,VMX,APX,X86_64 */
        {I_INVEPT, 2, {REG_GPR|BITS64,MEMORY|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+25767, 403},
};

static const struct itemplate instrux_INVVPID[3] = {
    /*   0 : INVVPID reg32,mem [rm:       66 0f38 81 /r                     ] AR0-1,SO,NOREX,NOAPX,NOLONG,VMX,FUTURE */
        /* 361 356 001(81) 110 : AR0,AR1,SO,NOREX,NOAPX,NOLONG,VMX,FUTURE */
        {I_INVVPID, 2, {REG_GPR|BITS32|RN_L16,MEMORY|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58035, 401},
    /*   1 : INVVPID reg64,mem [rm:       o64nw 66 0f38 81 /r               ] AR0-1,SO,LONG,PROT,VMX,X86_64 */
        /* 323 361 356 001(81) 110 : AR0,AR1,SO,NWSIZE,NOAPX,LONG,PROT,VMX,X86_64 */
        {I_INVVPID, 2, {REG_GPR|BITS64|RN_L16,MEMORY|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58034, 402},
    /*   2 : INVVPID reg64,mem128 [rm:       evex.nf0.nd0.l0.f3.m4.w1 f1 /r    ] AR0-1,SO,LONG,PROT,VMX,APX,X86_64 */
        /* 250(f4 fe 08) 300 001(f1) 110 : AR0,AR1,SO,LONG,EVEX,PROT,VMX,APX,X86_64 */
        {I_INVVPID, 2, {REG_GPR|BITS64,MEMORY|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+25776, 403},
};

static const struct itemplate instrux_PVALIDATE[1] = {
    /*   0 : PVALIDATE void [          f2 0f 01 ff                       ] VMX,FUTURE,AMD */
        /* 332 355 002(01 ff) : VMX,FUTURE,AMD */
        {I_PVALIDATE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+69308, 397},
};

static const struct itemplate instrux_RMPADJUST[1] = {
    /*   0 : RMPADJUST void [          f3 0f 01 fe                       ] VMX,FUTURE,AMD */
        /* 333 355 002(01 fe) : VMX,FUTURE,AMD */
        {I_RMPADJUST, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+69314, 397},
};

static const struct itemplate instrux_VMGEXIT[2] = {
    /*   0 : VMGEXIT void [          f2 0f 01 c1                       ] VMX,FUTURE,AMD */
        /* 332 355 002(01 c1) : VMX,FUTURE,AMD */
        {I_VMGEXIT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+69320, 397},
    /*   1 : VMGEXIT void [          f3 0f 01 c1                       ] VMX,FUTURE,AMD */
        /* 333 355 002(01 c1) : VMX,FUTURE,AMD */
        {I_VMGEXIT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+69326, 397},
};

static const struct itemplate instrux_PABSB[2] = {
    /*   0 : PABSB mmxreg,mmxrm [rm:       np 0f38 1c /r                     ] AR0-1,SQ,MMX,SSSE3,FUTURE */
        /* 360 356 001(1c) 110 : AR0,AR1,SQ,NOAPX,MMX,SSSE3,FUTURE */
        {I_PABSB, 2, {MMXREG|RN_L16,RM_MMX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69332, 404},
    /*   1 : PABSB xmmreg,xmmrm128 [rm:       66 0f38 1c /r                     ] SSSE3,FUTURE */
        /* 361 356 001(1c) 110 : NOAPX,SSSE3,FUTURE */
        {I_PABSB, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69338, 405},
};

static const struct itemplate instrux_PABSW[2] = {
    /*   0 : PABSW mmxreg,mmxrm [rm:       np 0f38 1d /r                     ] AR0-1,SQ,MMX,SSSE3,FUTURE */
        /* 360 356 001(1d) 110 : AR0,AR1,SQ,NOAPX,MMX,SSSE3,FUTURE */
        {I_PABSW, 2, {MMXREG|RN_L16,RM_MMX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69344, 404},
    /*   1 : PABSW xmmreg,xmmrm128 [rm:       66 0f38 1d /r                     ] SSSE3,FUTURE */
        /* 361 356 001(1d) 110 : NOAPX,SSSE3,FUTURE */
        {I_PABSW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69350, 405},
};

static const struct itemplate instrux_PABSD[2] = {
    /*   0 : PABSD mmxreg,mmxrm [rm:       np 0f38 1e /r                     ] AR0-1,SQ,MMX,SSSE3,FUTURE */
        /* 360 356 001(1e) 110 : AR0,AR1,SQ,NOAPX,MMX,SSSE3,FUTURE */
        {I_PABSD, 2, {MMXREG|RN_L16,RM_MMX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69356, 404},
    /*   1 : PABSD xmmreg,xmmrm128 [rm:       66 0f38 1e /r                     ] SSSE3,FUTURE */
        /* 361 356 001(1e) 110 : NOAPX,SSSE3,FUTURE */
        {I_PABSD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69362, 405},
};

static const struct itemplate instrux_PALIGNR[2] = {
    /*   0 : PALIGNR mmxreg,mmxrm,imm [rmi:      np 0f3a 0f /r ib,u                ] AR0-2,SQ,MMX,SSSE3,FUTURE */
        /* 360 357 001(0f) 110 026 : AR0,AR1,AR2,SQ,NOAPX,MMX,SSSE3,FUTURE */
        {I_PALIGNR, 3, {MMXREG|RN_L16,RM_MMX|RN_L16,IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+58041, 406},
    /*   1 : PALIGNR xmmreg,xmmrm,imm [rmi:      66 0f3a 0f /r ib,u                ] SSSE3,FUTURE */
        /* 361 357 001(0f) 110 026 : NOAPX,SSSE3,FUTURE */
        {I_PALIGNR, 3, {XMMREG|RN_L16,RM_XMM|RN_L16,IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+58048, 405},
};

static const struct itemplate instrux_PHADDW[2] = {
    /*   0 : PHADDW mmxreg,mmxrm [rm:       np 0f38 01 /r                     ] AR0-1,SQ,MMX,SSSE3,FUTURE */
        /* 360 356 001(01) 110 : AR0,AR1,SQ,NOAPX,MMX,SSSE3,FUTURE */
        {I_PHADDW, 2, {MMXREG|RN_L16,RM_MMX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69368, 404},
    /*   1 : PHADDW xmmreg,xmmrm128 [rm:       66 0f38 01 /r                     ] SSSE3,FUTURE */
        /* 361 356 001(01) 110 : NOAPX,SSSE3,FUTURE */
        {I_PHADDW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69374, 405},
};

static const struct itemplate instrux_PHADDD[2] = {
    /*   0 : PHADDD mmxreg,mmxrm [rm:       np 0f38 02 /r                     ] AR0-1,SQ,MMX,SSSE3,FUTURE */
        /* 360 356 001(02) 110 : AR0,AR1,SQ,NOAPX,MMX,SSSE3,FUTURE */
        {I_PHADDD, 2, {MMXREG|RN_L16,RM_MMX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69380, 404},
    /*   1 : PHADDD xmmreg,xmmrm128 [rm:       66 0f38 02 /r                     ] SSSE3,FUTURE */
        /* 361 356 001(02) 110 : NOAPX,SSSE3,FUTURE */
        {I_PHADDD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69386, 405},
};

static const struct itemplate instrux_PHADDSW[2] = {
    /*   0 : PHADDSW mmxreg,mmxrm [rm:       np 0f38 03 /r                     ] AR0-1,SQ,MMX,SSSE3,FUTURE */
        /* 360 356 001(03) 110 : AR0,AR1,SQ,NOAPX,MMX,SSSE3,FUTURE */
        {I_PHADDSW, 2, {MMXREG|RN_L16,RM_MMX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69392, 404},
    /*   1 : PHADDSW xmmreg,xmmrm128 [rm:       66 0f38 03 /r                     ] SSSE3,FUTURE */
        /* 361 356 001(03) 110 : NOAPX,SSSE3,FUTURE */
        {I_PHADDSW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69398, 405},
};

static const struct itemplate instrux_PHSUBW[2] = {
    /*   0 : PHSUBW mmxreg,mmxrm [rm:       np 0f38 05 /r                     ] AR0-1,SQ,MMX,SSSE3,FUTURE */
        /* 360 356 001(05) 110 : AR0,AR1,SQ,NOAPX,MMX,SSSE3,FUTURE */
        {I_PHSUBW, 2, {MMXREG|RN_L16,RM_MMX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69404, 404},
    /*   1 : PHSUBW xmmreg,xmmrm128 [rm:       66 0f38 05 /r                     ] SSSE3,FUTURE */
        /* 361 356 001(05) 110 : NOAPX,SSSE3,FUTURE */
        {I_PHSUBW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69410, 405},
};

static const struct itemplate instrux_PHSUBD[2] = {
    /*   0 : PHSUBD mmxreg,mmxrm [rm:       np 0f38 06 /r                     ] AR0-1,SQ,MMX,SSSE3,FUTURE */
        /* 360 356 001(06) 110 : AR0,AR1,SQ,NOAPX,MMX,SSSE3,FUTURE */
        {I_PHSUBD, 2, {MMXREG|RN_L16,RM_MMX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69416, 404},
    /*   1 : PHSUBD xmmreg,xmmrm128 [rm:       66 0f38 06 /r                     ] SSSE3,FUTURE */
        /* 361 356 001(06) 110 : NOAPX,SSSE3,FUTURE */
        {I_PHSUBD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69422, 405},
};

static const struct itemplate instrux_PHSUBSW[2] = {
    /*   0 : PHSUBSW mmxreg,mmxrm [rm:       np 0f38 07 /r                     ] AR0-1,SQ,MMX,SSSE3,FUTURE */
        /* 360 356 001(07) 110 : AR0,AR1,SQ,NOAPX,MMX,SSSE3,FUTURE */
        {I_PHSUBSW, 2, {MMXREG|RN_L16,RM_MMX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69428, 404},
    /*   1 : PHSUBSW xmmreg,xmmrm128 [rm:       66 0f38 07 /r                     ] SSSE3,FUTURE */
        /* 361 356 001(07) 110 : NOAPX,SSSE3,FUTURE */
        {I_PHSUBSW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69434, 405},
};

static const struct itemplate instrux_PMADDUBSW[2] = {
    /*   0 : PMADDUBSW mmxreg,mmxrm [rm:       np 0f38 04 /r                     ] AR0-1,SQ,MMX,SSSE3,FUTURE */
        /* 360 356 001(04) 110 : AR0,AR1,SQ,NOAPX,MMX,SSSE3,FUTURE */
        {I_PMADDUBSW, 2, {MMXREG|RN_L16,RM_MMX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69440, 404},
    /*   1 : PMADDUBSW xmmreg,xmmrm128 [rm:       66 0f38 04 /r                     ] SSSE3,FUTURE */
        /* 361 356 001(04) 110 : NOAPX,SSSE3,FUTURE */
        {I_PMADDUBSW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69446, 405},
};

static const struct itemplate instrux_PMULHRSW[2] = {
    /*   0 : PMULHRSW mmxreg,mmxrm [rm:       np 0f38 0b /r                     ] AR0-1,SQ,MMX,SSSE3,FUTURE */
        /* 360 356 001(0b) 110 : AR0,AR1,SQ,NOAPX,MMX,SSSE3,FUTURE */
        {I_PMULHRSW, 2, {MMXREG|RN_L16,RM_MMX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69452, 404},
    /*   1 : PMULHRSW xmmreg,xmmrm128 [rm:       66 0f38 0b /r                     ] SSSE3,FUTURE */
        /* 361 356 001(0b) 110 : NOAPX,SSSE3,FUTURE */
        {I_PMULHRSW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69458, 405},
};

static const struct itemplate instrux_PSHUFB[2] = {
    /*   0 : PSHUFB mmxreg,mmxrm [rm:       np 0f38 00 /r                     ] AR0-1,SQ,MMX,SSSE3,FUTURE */
        /* 360 356 001(00) 110 : AR0,AR1,SQ,NOAPX,MMX,SSSE3,FUTURE */
        {I_PSHUFB, 2, {MMXREG|RN_L16,RM_MMX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69464, 404},
    /*   1 : PSHUFB xmmreg,xmmrm128 [rm:       66 0f38 00 /r                     ] SSSE3,FUTURE */
        /* 361 356 001(00) 110 : NOAPX,SSSE3,FUTURE */
        {I_PSHUFB, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69470, 405},
};

static const struct itemplate instrux_PSIGNB[2] = {
    /*   0 : PSIGNB mmxreg,mmxrm [rm:       np 0f38 08 /r                     ] AR0-1,SQ,MMX,SSSE3,FUTURE */
        /* 360 356 001(08) 110 : AR0,AR1,SQ,NOAPX,MMX,SSSE3,FUTURE */
        {I_PSIGNB, 2, {MMXREG|RN_L16,RM_MMX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69476, 404},
    /*   1 : PSIGNB xmmreg,xmmrm128 [rm:       66 0f38 08 /r                     ] SSSE3,FUTURE */
        /* 361 356 001(08) 110 : NOAPX,SSSE3,FUTURE */
        {I_PSIGNB, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69482, 405},
};

static const struct itemplate instrux_PSIGNW[2] = {
    /*   0 : PSIGNW mmxreg,mmxrm [rm:       np 0f38 09 /r                     ] AR0-1,SQ,MMX,SSSE3,FUTURE */
        /* 360 356 001(09) 110 : AR0,AR1,SQ,NOAPX,MMX,SSSE3,FUTURE */
        {I_PSIGNW, 2, {MMXREG|RN_L16,RM_MMX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69488, 404},
    /*   1 : PSIGNW xmmreg,xmmrm128 [rm:       66 0f38 09 /r                     ] SSSE3,FUTURE */
        /* 361 356 001(09) 110 : NOAPX,SSSE3,FUTURE */
        {I_PSIGNW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69494, 405},
};

static const struct itemplate instrux_PSIGND[2] = {
    /*   0 : PSIGND mmxreg,mmxrm [rm:       np 0f38 0a /r                     ] AR0-1,SQ,MMX,SSSE3,FUTURE */
        /* 360 356 001(0a) 110 : AR0,AR1,SQ,NOAPX,MMX,SSSE3,FUTURE */
        {I_PSIGND, 2, {MMXREG|RN_L16,RM_MMX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69500, 404},
    /*   1 : PSIGND xmmreg,xmmrm128 [rm:       66 0f38 0a /r                     ] SSSE3,FUTURE */
        /* 361 356 001(0a) 110 : NOAPX,SSSE3,FUTURE */
        {I_PSIGND, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69506, 405},
};

static const struct itemplate instrux_EXTRQ[2] = {
    /*   0 : EXTRQ xmmreg,imm,imm [mij:      66 0f 78 /0 ib,u ib,u             ] SSE4A,FUTURE,AMD */
        /* 361 355 001(78) 200 025 026 : SSE4A,FUTURE,AMD */
        {I_EXTRQ, 3, {XMMREG,IMM_NORMAL,IMM_NORMAL,0,0}, NO_DECORATOR, nasm_bytecodes+51517, 407},
    /*   1 : EXTRQ xmmreg,xmmreg [rm:       66 0f 79 /r                       ] SSE4A,FUTURE,AMD */
        /* 361 355 001(79) 110 : SSE4A,FUTURE,AMD */
        {I_EXTRQ, 2, {XMMREG,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+69512, 407},
};

static const struct itemplate instrux_INSERTQ[2] = {
    /*   0 : INSERTQ xmmreg,xmmreg,imm,imm [rmij:     f2 0f 78 /r ib,u ib,u             ] SSE4A,FUTURE,AMD */
        /* 332 355 001(78) 110 026 027 : SSE4A,FUTURE,AMD */
        {I_INSERTQ, 4, {XMMREG,XMMREG,IMM_NORMAL,IMM_NORMAL,0}, NO_DECORATOR, nasm_bytecodes+51525, 407},
    /*   1 : INSERTQ xmmreg,xmmreg [rm:       f2 0f 79 /r                       ] SSE4A,FUTURE,AMD */
        /* 332 355 001(79) 110 : SSE4A,FUTURE,AMD */
        {I_INSERTQ, 2, {XMMREG,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+69518, 407},
};

static const struct itemplate instrux_MOVNTSD[1] = {
    /*   0 : MOVNTSD mem64,xmmreg [mr:       f2 0f 2b /r                       ] AR0-1,SQ,SSE4A,FUTURE,AMD */
        /* 332 355 001(2b) 101 : AR0,AR1,SQ,SSE4A,FUTURE,AMD */
        {I_MOVNTSD, 2, {MEMORY|BITS64,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+69524, 408},
};

static const struct itemplate instrux_MOVNTSS[1] = {
    /*   0 : MOVNTSS mem32,xmmreg [mr:       f3 0f 2b /r                       ] AR0-1,SD,SSE4A,FUTURE,AMD */
        /* 333 355 001(2b) 101 : AR0,AR1,SD,SSE4A,FUTURE,AMD */
        {I_MOVNTSS, 2, {MEMORY|BITS32,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+69530, 409},
};

static const struct itemplate instrux_BLENDPD[1] = {
    /*   0 : BLENDPD xmmreg,xmmrm128,imm8 [rmi:      66 0f3a 0d /r ib,u                ] SSE41,FUTURE */
        /* 361 357 001(0d) 110 026 : NOAPX,SSE41,FUTURE */
        {I_BLENDPD, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+58055, 410},
};

static const struct itemplate instrux_BLENDPS[1] = {
    /*   0 : BLENDPS xmmreg,xmmrm128,imm8 [rmi:      66 0f3a 0c /r ib,u                ] SSE41,FUTURE */
        /* 361 357 001(0c) 110 026 : NOAPX,SSE41,FUTURE */
        {I_BLENDPS, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+58062, 410},
};

static const struct itemplate instrux_BLENDVPD[2] = {
    /*   0 : BLENDVPD xmmreg,xmmrm128,xmm0 [rm-:      66 0f38 15 /r                     ] SSE41,FUTURE */
        /* 361 356 001(15) 110 : NOAPX,SSE41,FUTURE */
        {I_BLENDVPD, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_ZERO|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+69536, 410},
    /*   1 : BLENDVPD xmmreg,xmmrm128 [rm:       66 0f38 15 /r                     ] SSE41,FUTURE */
        /* 361 356 001(15) 110 : NOAPX,SSE41,FUTURE */
        {I_BLENDVPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69536, 410},
};

static const struct itemplate instrux_BLENDVPS[2] = {
    /*   0 : BLENDVPS xmmreg,xmmrm128,xmm0 [rm-:      66 0f38 14 /r                     ] SSE41,FUTURE */
        /* 361 356 001(14) 110 : NOAPX,SSE41,FUTURE */
        {I_BLENDVPS, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_ZERO|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+69542, 410},
    /*   1 : BLENDVPS xmmreg,xmmrm128 [rm:       66 0f38 14 /r                     ] SSE41,FUTURE */
        /* 361 356 001(14) 110 : NOAPX,SSE41,FUTURE */
        {I_BLENDVPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69542, 410},
};

static const struct itemplate instrux_DPPD[1] = {
    /*   0 : DPPD xmmreg,xmmrm128,imm8 [rmi:      66 0f3a 41 /r ib,u                ] SSE41,FUTURE */
        /* 361 357 001(41) 110 026 : NOAPX,SSE41,FUTURE */
        {I_DPPD, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+58069, 410},
};

static const struct itemplate instrux_DPPS[1] = {
    /*   0 : DPPS xmmreg,xmmrm128,imm8 [rmi:      66 0f3a 40 /r ib,u                ] SSE41,FUTURE */
        /* 361 357 001(40) 110 026 : NOAPX,SSE41,FUTURE */
        {I_DPPS, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+58076, 410},
};

static const struct itemplate instrux_EXTRACTPS[2] = {
    /*   0 : EXTRACTPS rm32,xmmreg,imm8 [mri:      66 0f3a 17 /r ib,u                ] SSE41,FUTURE */
        /* 361 357 001(17) 101 026 : NOAPX,SSE41,FUTURE */
        {I_EXTRACTPS, 3, {RM_GPR|BITS32|RN_L16,XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51534, 410},
    /*   1 : EXTRACTPS reg64,xmmreg,imm8 [mri:      o64 66 0f3a 17 /r ib,u            ] LONG,PROT,SSE41,X86_64 */
        /* 324 361 357 001(17) 101 026 : NOAPX,LONG,PROT,SSE41,X86_64 */
        {I_EXTRACTPS, 3, {REG_GPR|BITS64|RN_L16,XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51533, 411},
};

static const struct itemplate instrux_INSERTPS[1] = {
    /*   0 : INSERTPS xmmreg,xmmrm32,imm8 [rmi:      66 0f3a 21 /r ib,u                ] SSE41,FUTURE */
        /* 361 357 001(21) 110 026 : NOAPX,SSE41,FUTURE */
        {I_INSERTPS, 3, {XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+58083, 410},
};

static const struct itemplate instrux_MOVNTDQA[1] = {
    /*   0 : MOVNTDQA xmmreg,mem128 [rm:       66 0f38 2a /r                     ] SSE41,FUTURE */
        /* 361 356 001(2a) 110 : NOAPX,SSE41,FUTURE */
        {I_MOVNTDQA, 2, {XMMREG|RN_L16,MEMORY|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69548, 410},
};

static const struct itemplate instrux_MPSADBW[1] = {
    /*   0 : MPSADBW xmmreg,xmmrm128,imm8 [rmi:      66 0f3a 42 /r ib,u                ] SSE41,FUTURE */
        /* 361 357 001(42) 110 026 : NOAPX,SSE41,FUTURE */
        {I_MPSADBW, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+58090, 410},
};

static const struct itemplate instrux_PACKUSDW[1] = {
    /*   0 : PACKUSDW xmmreg,xmmrm128 [rm:       66 0f38 2b /r                     ] SSE41,FUTURE */
        /* 361 356 001(2b) 110 : NOAPX,SSE41,FUTURE */
        {I_PACKUSDW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69554, 410},
};

static const struct itemplate instrux_PBLENDVB[2] = {
    /*   0 : PBLENDVB xmmreg,xmmrm,xmm0 [rm-:      66 0f38 10 /r                     ] SSE41,FUTURE */
        /* 361 356 001(10) 110 : NOAPX,SSE41,FUTURE */
        {I_PBLENDVB, 3, {XMMREG|RN_L16,RM_XMM|RN_L16,XMMREG|RN_ZERO|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+69560, 410},
    /*   1 : PBLENDVB xmmreg,xmmrm128 [rm:       66 0f38 10 /r                     ] SSE41,FUTURE */
        /* 361 356 001(10) 110 : NOAPX,SSE41,FUTURE */
        {I_PBLENDVB, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69560, 410},
};

static const struct itemplate instrux_PBLENDW[1] = {
    /*   0 : PBLENDW xmmreg,xmmrm128,imm8 [rmi:      66 0f3a 0e /r ib,u                ] SSE41,FUTURE */
        /* 361 357 001(0e) 110 026 : NOAPX,SSE41,FUTURE */
        {I_PBLENDW, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+58097, 410},
};

static const struct itemplate instrux_PCMPEQQ[1] = {
    /*   0 : PCMPEQQ xmmreg,xmmrm128 [rm:       66 0f38 29 /r                     ] SSE41,FUTURE */
        /* 361 356 001(29) 110 : NOAPX,SSE41,FUTURE */
        {I_PCMPEQQ, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69566, 410},
};

static const struct itemplate instrux_PEXTRB[3] = {
    /*   0 : PEXTRB reg32,xmmreg,imm8 [mri:      66 0f3a 14 /r ib,u                ] SSE41,FUTURE */
        /* 361 357 001(14) 101 026 : NOAPX,SSE41,FUTURE */
        {I_PEXTRB, 3, {REG_GPR|BITS32|RN_L16,XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51542, 410},
    /*   1 : PEXTRB mem8,xmmreg,imm8 [mri:      66 0f3a 14 /r ib,u                ] SSE41,FUTURE */
        /* 361 357 001(14) 101 026 : NOAPX,SSE41,FUTURE */
        {I_PEXTRB, 3, {MEMORY|BITS8|RN_L16,XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51542, 410},
    /*   2 : PEXTRB reg64,xmmreg,imm8 [mri:      o64nw 66 0f3a 14 /r ib,u          ] LONG,PROT,SSE41,X86_64 */
        /* 323 361 357 001(14) 101 026 : NWSIZE,NOAPX,LONG,PROT,SSE41,X86_64 */
        {I_PEXTRB, 3, {REG_GPR|BITS64|RN_L16,XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51541, 412},
};

static const struct itemplate instrux_PEXTRD[1] = {
    /*   0 : PEXTRD rm32,xmmreg,imm8 [mri:      norexw 66 0f3a 16 /r ib,u         ] SSE41,FUTURE */
        /* 317 361 357 001(16) 101 026 : NOAPX,SSE41,FUTURE */
        {I_PEXTRD, 3, {RM_GPR|BITS32|RN_L16,XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51549, 410},
};

static const struct itemplate instrux_PEXTRQ[1] = {
    /*   0 : PEXTRQ rm64,xmmreg,imm8 [mri:      o64 66 0f3a 16 /r ib,u            ] LONG,PROT,SSE41,X86_64 */
        /* 324 361 357 001(16) 101 026 : NOAPX,LONG,PROT,SSE41,X86_64 */
        {I_PEXTRQ, 3, {RM_GPR|BITS64|RN_L16,XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51557, 411},
};

static const struct itemplate instrux_PHMINPOSUW[1] = {
    /*   0 : PHMINPOSUW xmmreg,xmmrm128 [rm:       66 0f38 41 /r                     ] SSE41,FUTURE */
        /* 361 356 001(41) 110 : NOAPX,SSE41,FUTURE */
        {I_PHMINPOSUW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69572, 410},
};

static const struct itemplate instrux_PINSRB[3] = {
    /*   0 : PINSRB xmmreg,mem,imm8 [rmi:      66 0f3a 20 /r ib,u                ] AR2,SB,SSE41,FUTURE */
        /* 361 357 001(20) 110 026 : AR2,SB,NOAPX,SSE41,FUTURE */
        {I_PINSRB, 3, {XMMREG|RN_L16,MEMORY|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51574, 413},
    /*   1 : PINSRB xmmreg,rm8,imm8 [rmi:      nohi 66 0f3a 20 /r ib,u           ] AR2,SB,SSE41,FUTURE */
        /* 325 361 357 001(20) 110 026 : AR2,SB,NOAPX,SSE41,FUTURE */
        {I_PINSRB, 3, {XMMREG|RN_L16,RM_GPR|BITS8|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51573, 413},
    /*   2 : PINSRB xmmreg,reg32,imm8 [rmi:      66 0f3a 20 /r ib,u                ] AR2,SB,SSE41,FUTURE */
        /* 361 357 001(20) 110 026 : AR2,SB,NOAPX,SSE41,FUTURE */
        {I_PINSRB, 3, {XMMREG|RN_L16,REG_GPR|BITS32|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51574, 413},
};

static const struct itemplate instrux_PINSRD[1] = {
    /*   0 : PINSRD xmmreg,rm32,imm8 [rmi:      norexw 66 0f3a 22 /r ib,u         ] AR2,SB,SSE41,FUTURE */
        /* 317 361 357 001(22) 110 026 : AR2,SB,NOAPX,SSE41,FUTURE */
        {I_PINSRD, 3, {XMMREG|RN_L16,RM_GPR|BITS32|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51581, 413},
};

static const struct itemplate instrux_PINSRQ[1] = {
    /*   0 : PINSRQ xmmreg,rm64,imm8 [rmi:      o64 66 0f3a 22 /r ib,u            ] AR2,SB,LONG,PROT,SSE41,X86_64 */
        /* 324 361 357 001(22) 110 026 : AR2,SB,NOAPX,LONG,PROT,SSE41,X86_64 */
        {I_PINSRQ, 3, {XMMREG|RN_L16,RM_GPR|BITS64|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51589, 414},
};

static const struct itemplate instrux_PMAXSB[1] = {
    /*   0 : PMAXSB xmmreg,xmmrm128 [rm:       66 0f38 3c /r                     ] SSE41,FUTURE */
        /* 361 356 001(3c) 110 : NOAPX,SSE41,FUTURE */
        {I_PMAXSB, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69578, 410},
};

static const struct itemplate instrux_PMAXSD[1] = {
    /*   0 : PMAXSD xmmreg,xmmrm128 [rm:       66 0f38 3d /r                     ] SSE41,FUTURE */
        /* 361 356 001(3d) 110 : NOAPX,SSE41,FUTURE */
        {I_PMAXSD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69584, 410},
};

static const struct itemplate instrux_PMAXUD[1] = {
    /*   0 : PMAXUD xmmreg,xmmrm128 [rm:       66 0f38 3f /r                     ] SSE41,FUTURE */
        /* 361 356 001(3f) 110 : NOAPX,SSE41,FUTURE */
        {I_PMAXUD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69590, 410},
};

static const struct itemplate instrux_PMAXUW[1] = {
    /*   0 : PMAXUW xmmreg,xmmrm128 [rm:       66 0f38 3e /r                     ] SSE41,FUTURE */
        /* 361 356 001(3e) 110 : NOAPX,SSE41,FUTURE */
        {I_PMAXUW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69596, 410},
};

static const struct itemplate instrux_PMINSB[1] = {
    /*   0 : PMINSB xmmreg,xmmrm128 [rm:       66 0f38 38 /r                     ] SSE41,FUTURE */
        /* 361 356 001(38) 110 : NOAPX,SSE41,FUTURE */
        {I_PMINSB, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69602, 410},
};

static const struct itemplate instrux_PMINSD[1] = {
    /*   0 : PMINSD xmmreg,xmmrm128 [rm:       66 0f38 39 /r                     ] SSE41,FUTURE */
        /* 361 356 001(39) 110 : NOAPX,SSE41,FUTURE */
        {I_PMINSD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69608, 410},
};

static const struct itemplate instrux_PMINUD[1] = {
    /*   0 : PMINUD xmmreg,xmmrm128 [rm:       66 0f38 3b /r                     ] SSE41,FUTURE */
        /* 361 356 001(3b) 110 : NOAPX,SSE41,FUTURE */
        {I_PMINUD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69614, 410},
};

static const struct itemplate instrux_PMINUW[1] = {
    /*   0 : PMINUW xmmreg,xmmrm128 [rm:       66 0f38 3a /r                     ] SSE41,FUTURE */
        /* 361 356 001(3a) 110 : NOAPX,SSE41,FUTURE */
        {I_PMINUW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69620, 410},
};

static const struct itemplate instrux_PMOVSXBW[1] = {
    /*   0 : PMOVSXBW xmmreg,xmmrm64 [rm:       66 0f38 20 /r                     ] AR0-1,SQ,SSE41,FUTURE */
        /* 361 356 001(20) 110 : AR0,AR1,SQ,NOAPX,SSE41,FUTURE */
        {I_PMOVSXBW, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69626, 415},
};

static const struct itemplate instrux_PMOVSXBD[1] = {
    /*   0 : PMOVSXBD xmmreg,xmmrm32 [rm:       66 0f38 21 /r                     ] AR0-1,SD,SSE41,FUTURE */
        /* 361 356 001(21) 110 : AR0,AR1,SD,NOAPX,SSE41,FUTURE */
        {I_PMOVSXBD, 2, {XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69632, 416},
};

static const struct itemplate instrux_PMOVSXBQ[1] = {
    /*   0 : PMOVSXBQ xmmreg,xmmrm16 [rm:       66 0f38 22 /r                     ] AR0-1,SW,SSE41,FUTURE */
        /* 361 356 001(22) 110 : AR0,AR1,SW,NOAPX,SSE41,FUTURE */
        {I_PMOVSXBQ, 2, {XMMREG|RN_L16,RM_XMM|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69638, 417},
};

static const struct itemplate instrux_PMOVSXWD[1] = {
    /*   0 : PMOVSXWD xmmreg,xmmrm64 [rm:       66 0f38 23 /r                     ] AR0-1,SQ,SSE41,FUTURE */
        /* 361 356 001(23) 110 : AR0,AR1,SQ,NOAPX,SSE41,FUTURE */
        {I_PMOVSXWD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69644, 415},
};

static const struct itemplate instrux_PMOVSXWQ[1] = {
    /*   0 : PMOVSXWQ xmmreg,xmmrm32 [rm:       66 0f38 24 /r                     ] AR0-1,SD,SSE41,FUTURE */
        /* 361 356 001(24) 110 : AR0,AR1,SD,NOAPX,SSE41,FUTURE */
        {I_PMOVSXWQ, 2, {XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69650, 416},
};

static const struct itemplate instrux_PMOVSXDQ[1] = {
    /*   0 : PMOVSXDQ xmmreg,xmmrm64 [rm:       66 0f38 25 /r                     ] AR0-1,SQ,SSE41,FUTURE */
        /* 361 356 001(25) 110 : AR0,AR1,SQ,NOAPX,SSE41,FUTURE */
        {I_PMOVSXDQ, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69656, 415},
};

static const struct itemplate instrux_PMOVZXBW[1] = {
    /*   0 : PMOVZXBW xmmreg,xmmrm64 [rm:       66 0f38 30 /r                     ] AR0-1,SQ,SSE41,FUTURE */
        /* 361 356 001(30) 110 : AR0,AR1,SQ,NOAPX,SSE41,FUTURE */
        {I_PMOVZXBW, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69662, 415},
};

static const struct itemplate instrux_PMOVZXBD[1] = {
    /*   0 : PMOVZXBD xmmreg,xmmrm32 [rm:       66 0f38 31 /r                     ] AR0-1,SD,SSE41,FUTURE */
        /* 361 356 001(31) 110 : AR0,AR1,SD,NOAPX,SSE41,FUTURE */
        {I_PMOVZXBD, 2, {XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69668, 416},
};

static const struct itemplate instrux_PMOVZXBQ[1] = {
    /*   0 : PMOVZXBQ xmmreg,xmmrm16 [rm:       66 0f38 32 /r                     ] AR0-1,SW,SSE41,FUTURE */
        /* 361 356 001(32) 110 : AR0,AR1,SW,NOAPX,SSE41,FUTURE */
        {I_PMOVZXBQ, 2, {XMMREG|RN_L16,RM_XMM|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69674, 417},
};

static const struct itemplate instrux_PMOVZXWD[1] = {
    /*   0 : PMOVZXWD xmmreg,xmmrm64 [rm:       66 0f38 33 /r                     ] AR0-1,SQ,SSE41,FUTURE */
        /* 361 356 001(33) 110 : AR0,AR1,SQ,NOAPX,SSE41,FUTURE */
        {I_PMOVZXWD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69680, 415},
};

static const struct itemplate instrux_PMOVZXWQ[1] = {
    /*   0 : PMOVZXWQ xmmreg,xmmrm32 [rm:       66 0f38 34 /r                     ] AR0-1,SD,SSE41,FUTURE */
        /* 361 356 001(34) 110 : AR0,AR1,SD,NOAPX,SSE41,FUTURE */
        {I_PMOVZXWQ, 2, {XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69686, 416},
};

static const struct itemplate instrux_PMOVZXDQ[1] = {
    /*   0 : PMOVZXDQ xmmreg,xmmrm64 [rm:       66 0f38 35 /r                     ] AR0-1,SQ,SSE41,FUTURE */
        /* 361 356 001(35) 110 : AR0,AR1,SQ,NOAPX,SSE41,FUTURE */
        {I_PMOVZXDQ, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69692, 415},
};

static const struct itemplate instrux_PMULDQ[1] = {
    /*   0 : PMULDQ xmmreg,xmmrm128 [rm:       66 0f38 28 /r                     ] SSE41,FUTURE */
        /* 361 356 001(28) 110 : NOAPX,SSE41,FUTURE */
        {I_PMULDQ, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69698, 410},
};

static const struct itemplate instrux_PMULLD[1] = {
    /*   0 : PMULLD xmmreg,xmmrm128 [rm:       66 0f38 40 /r                     ] SSE41,FUTURE */
        /* 361 356 001(40) 110 : NOAPX,SSE41,FUTURE */
        {I_PMULLD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69704, 410},
};

static const struct itemplate instrux_PTEST[1] = {
    /*   0 : PTEST xmmreg,xmmrm128 [rm:       66 0f38 17 /r                     ] SSE41,FUTURE */
        /* 361 356 001(17) 110 : NOAPX,SSE41,FUTURE */
        {I_PTEST, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69710, 410},
};

static const struct itemplate instrux_ROUNDPD[1] = {
    /*   0 : ROUNDPD xmmreg,xmmrm128,imm8 [rmi:      66 0f3a 09 /r ib,u                ] SSE41,FUTURE */
        /* 361 357 001(09) 110 026 : NOAPX,SSE41,FUTURE */
        {I_ROUNDPD, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+58104, 410},
};

static const struct itemplate instrux_ROUNDPS[1] = {
    /*   0 : ROUNDPS xmmreg,xmmrm128,imm8 [rmi:      66 0f3a 08 /r ib,u                ] SSE41,FUTURE */
        /* 361 357 001(08) 110 026 : NOAPX,SSE41,FUTURE */
        {I_ROUNDPS, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+58111, 410},
};

static const struct itemplate instrux_ROUNDSD[1] = {
    /*   0 : ROUNDSD xmmreg,xmmrm64,imm8 [rmi:      66 0f3a 0b /r ib,u                ] SSE41,FUTURE */
        /* 361 357 001(0b) 110 026 : NOAPX,SSE41,FUTURE */
        {I_ROUNDSD, 3, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+58118, 410},
};

static const struct itemplate instrux_ROUNDSS[1] = {
    /*   0 : ROUNDSS xmmreg,xmmrm32,imm8 [rmi:      66 0f3a 0a /r ib,u                ] SSE41,FUTURE */
        /* 361 357 001(0a) 110 026 : NOAPX,SSE41,FUTURE */
        {I_ROUNDSS, 3, {XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+58125, 410},
};

static const struct itemplate instrux_CRC32[18] = {
    /*   0 : CRC32 reg32,rm8 [rm:       o8 f2 0f38 f0 /r                  ] SSE42,FUTURE */
        /* 332 356 001(f0) 110 : NOAPX,SSE42,FUTURE */
        {I_CRC32, 2, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58154, 418},
    /*   1 : CRC32 reg32,rm16 [rm:       o16 f2 0f38 f1 /r                 ] SSE42,FUTURE */
        /* 320 332 356 001(f1) 110 : NOAPX,SSE42,FUTURE */
        {I_CRC32, 2, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58132, 418},
    /*   2 : CRC32 reg32,rm32 [rm:       o32 f2 0f38 f1 /r                 ] SSE42,FUTURE */
        /* 321 332 356 001(f1) 110 : NOAPX,SSE42,FUTURE */
        {I_CRC32, 2, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58139, 418},
    /*   3 : CRC32 reg32,rm64 [rm:       o64 f2 0f38 f1 /r                 ] ND,LONG,PROT,SSE42,X86_64 */
        /* 324 332 356 001(f1) 110 : NOAPX,LONG,PROT,SSE42,X86_64 */
        {I_CRC32, 2, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58146, 419},
    /*   4 : CRC32 reg32,rm8 [rm:       evex.l0.m4.o8 f0 /r               ] LONG,PROT,SSE42,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(f0) 110 : WIG,LONG,EVEX,PROT,SSE42,APX,X86_64 */
        {I_CRC32, 2, {REG_GPR|BITS32,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+25785, 420},
    /*   5 : CRC32 reg32,rm16 [rm:       evex.l0.m4.o16 f1 /r              ] LONG,PROT,SSE42,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(f1) 110 : LONG,EVEX,PROT,SSE42,APX,X86_64 */
        {I_CRC32, 2, {REG_GPR|BITS32,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+17923, 421},
    /*   6 : CRC32 reg32,rm32 [rm:       evex.l0.m4.o32 f1 /r              ] LONG,PROT,SSE42,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(f1) 110 : WW,LONG,EVEX,PROT,SSE42,APX,X86_64 */
        {I_CRC32, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17933, 422},
    /*   7 : CRC32 reg32,rm64 [rm:       evex.l0.m4.o64 f1 /r              ] ND,LONG,PROT,SSE42,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(f1) 110 : WW,LONG,EVEX,PROT,SSE42,APX,X86_64 */
        {I_CRC32, 2, {REG_GPR|BITS32,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17943, 422},
    /*   8 : CRC32 reg64,rm8 [rm:       o8 f2 0f38 f0 /r                  ] OPT,LONG,PROT,SSE42,X86_64 */
        /* 332 356 001(f0) 110 : OPT,NOAPX,LONG,PROT,SSE42,X86_64 */
        {I_CRC32, 2, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58154, 423},
    /*   9 : CRC32 reg64,rm16 [rm:       o16 f2 0f38 f1 /r                 ] LONG,PROT,SSE42,X86_64 */
        /* 320 332 356 001(f1) 110 : NOAPX,LONG,PROT,SSE42,X86_64 */
        {I_CRC32, 2, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58132, 419},
    /*  10 : CRC32 reg64,rm32 [rm:       o32 f2 0f38 f1 /r                 ] LONG,PROT,SSE42,X86_64 */
        /* 321 332 356 001(f1) 110 : NOAPX,LONG,PROT,SSE42,X86_64 */
        {I_CRC32, 2, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58139, 419},
    /*  11 : CRC32 reg64,rm64 [rm:       o64 f2 0f38 f1 /r                 ] LONG,PROT,SSE42,X86_64 */
        /* 324 332 356 001(f1) 110 : NOAPX,LONG,PROT,SSE42,X86_64 */
        {I_CRC32, 2, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58146, 419},
    /*  12 : CRC32 reg64,rm8 [rm:       evex.l0.m4.o8 f0 /r               ] OPT,LONG,PROT,SSE42,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(f0) 110 : OPT,WIG,LONG,EVEX,PROT,SSE42,APX,X86_64 */
        {I_CRC32, 2, {REG_GPR|BITS64,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+25785, 424},
    /*  13 : CRC32 reg64,rm16 [rm:       evex.l0.m4.o16 f1 /r              ] LONG,PROT,SSE42,APX,X86_64 */
        /* 250(f4 7d 08) 300 320 001(f1) 110 : LONG,EVEX,PROT,SSE42,APX,X86_64 */
        {I_CRC32, 2, {REG_GPR|BITS64,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+17923, 421},
    /*  14 : CRC32 reg64,rm32 [rm:       evex.l0.m4.o32 f1 /r              ] LONG,PROT,SSE42,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(f1) 110 : WW,LONG,EVEX,PROT,SSE42,APX,X86_64 */
        {I_CRC32, 2, {REG_GPR|BITS64,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17933, 422},
    /*  15 : CRC32 reg64,rm64 [rm:       evex.l0.m4.o64 f1 /r              ] LONG,PROT,SSE42,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(f1) 110 : WW,LONG,EVEX,PROT,SSE42,APX,X86_64 */
        {I_CRC32, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17943, 422},
    /*  16 : CRC32 reg64,rm8 [rm:       o64 f2 0f38 f0 /r                 ] LONG,SSE42,X86_64,FUTURE */
        /* 324 332 356 001(f0) 110 : NOAPX,LONG,PROT,SSE42,FUTURE */
        {I_CRC32, 2, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58153, 425},
    /*  17 : CRC32 reg64,rm8 [rm:       evex.l0.m4.o64 f0 /r              ] LONG,PROT,SSE42,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(f0) 110 : WW,LONG,EVEX,PROT,SSE42,APX,X86_64 */
        {I_CRC32, 2, {REG_GPR|BITS64,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+17953, 422},
};

static const struct itemplate instrux_PCMPESTRI[1] = {
    /*   0 : PCMPESTRI xmmreg,xmmrm128,imm8 [rmi:      66 0f3a 61 /r ib,u                ] SSE42,FUTURE */
        /* 361 357 001(61) 110 026 : NOAPX,SSE42,FUTURE */
        {I_PCMPESTRI, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+58160, 418},
};

static const struct itemplate instrux_PCMPESTRM[1] = {
    /*   0 : PCMPESTRM xmmreg,xmmrm128,imm8 [rmi:      66 0f3a 60 /r ib,u                ] SSE42,FUTURE */
        /* 361 357 001(60) 110 026 : NOAPX,SSE42,FUTURE */
        {I_PCMPESTRM, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+58167, 418},
};

static const struct itemplate instrux_PCMPISTRI[1] = {
    /*   0 : PCMPISTRI xmmreg,xmmrm128,imm8 [rmi:      66 0f3a 63 /r ib,u                ] SSE42,FUTURE */
        /* 361 357 001(63) 110 026 : NOAPX,SSE42,FUTURE */
        {I_PCMPISTRI, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+58174, 418},
};

static const struct itemplate instrux_PCMPISTRM[1] = {
    /*   0 : PCMPISTRM xmmreg,xmmrm128,imm8 [rmi:      66 0f3a 62 /r ib,u                ] SSE42,FUTURE */
        /* 361 357 001(62) 110 026 : NOAPX,SSE42,FUTURE */
        {I_PCMPISTRM, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+58181, 418},
};

static const struct itemplate instrux_PCMPGTQ[1] = {
    /*   0 : PCMPGTQ xmmreg,xmmrm128 [rm:       66 0f38 37 /r                     ] SSE42,FUTURE */
        /* 361 356 001(37) 110 : NOAPX,SSE42,FUTURE */
        {I_PCMPGTQ, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69716, 418},
};

static const struct itemplate instrux_POPCNT[6] = {
    /*   0 : POPCNT reg16,rm16 [rm:       o16 f3i 0f b8 /r                  ] AR0-1,SW,FL,NEHALEM */
        /* 320 333 355 001(b8) 110 : AR0,AR1,SW,FL,NEHALEM */
        {I_POPCNT, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58188, 426},
    /*   1 : POPCNT reg32,rm32 [rm:       o32 f3i 0f b8 /r                  ] AR0-1,SD,FL,NEHALEM */
        /* 321 333 355 001(b8) 110 : AR0,AR1,SD,FL,NEHALEM */
        {I_POPCNT, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+58195, 427},
    /*   2 : POPCNT reg64,rm64 [rm:       o64 f3i 0f b8 /r                  ] AR0-1,SQ,LONG,FL,PROT,X86_64,NEHALEM */
        /* 324 333 355 001(b8) 110 : AR0,AR1,SQ,LONG,FL,PROT,NEHALEM */
        {I_POPCNT, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+58202, 428},
    /*   3 : POPCNT reg16,rm16 [rm:       evex.nf.nd0.l0.m4.o16 88 /r       ] SM0-1,NF,LONG,PROT,APX,X86_64,NEHALEM */
        /* 250(f4 7d 08) 300 320 001(88) 110 : SM0,SM1,NF,NF_E,LONG,EVEX,PROT,APX,NEHALEM */
        {I_POPCNT, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+17963, 429},
    /*   4 : POPCNT reg32,rm32 [rm:       evex.nf.nd0.l0.m4.o32 88 /r       ] SM0-1,NF,LONG,PROT,APX,X86_64,NEHALEM */
        /* 250(f4 7c 08) 300 321 001(88) 110 : SM0,SM1,NF,NF_E,WW,LONG,EVEX,PROT,APX,NEHALEM */
        {I_POPCNT, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+17973, 430},
    /*   5 : POPCNT reg64,rm64 [rm:       evex.nf.nd0.l0.m4.o64 88 /r       ] SM0-1,NF,LONG,PROT,APX,X86_64,NEHALEM */
        /* 250(f4 fc 08) 300 324 001(88) 110 : SM0,SM1,NF,NF_E,WW,LONG,EVEX,PROT,APX,NEHALEM */
        {I_POPCNT, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+17983, 430},
};

static const struct itemplate instrux_GETSEC[1] = {
    /*   0 : GETSEC void [          0f 37                             ] NOAPX,FL,KATMAI */
        /* 355 001(37) : NOAPX,FL,KATMAI */
        {I_GETSEC, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+73289, 431},
};

static const struct itemplate instrux_PFRCPV[1] = {
    /*   0 : PFRCPV mmxreg,mmxrm [rm:       0f 0f /r 86                       ] AR0-1,SQ,3DNOW,PENT,CYRIX */
        /* 355 001(0f) 110 001(86) : AR0,AR1,SQ,3DNOW,PENT,CYRIX */
        {I_PFRCPV, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+58209, 432},
};

static const struct itemplate instrux_PFRSQRTV[1] = {
    /*   0 : PFRSQRTV mmxreg,mmxrm [rm:       0f 0f /r 87                       ] AR0-1,SQ,3DNOW,PENT,CYRIX */
        /* 355 001(0f) 110 001(87) : AR0,AR1,SQ,3DNOW,PENT,CYRIX */
        {I_PFRSQRTV, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+58216, 432},
};

static const struct itemplate instrux_AESENC[1] = {
    /*   0 : AESENC xmmreg,xmmrm128 [rm:       66 0f38 dc /r                     ] SSE,WESTMERE */
        /* 361 356 001(dc) 110 : NOAPX,SSE,WESTMERE */
        {I_AESENC, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69722, 433},
};

static const struct itemplate instrux_AESENCLAST[1] = {
    /*   0 : AESENCLAST xmmreg,xmmrm128 [rm:       66 0f38 dd /r                     ] SSE,WESTMERE */
        /* 361 356 001(dd) 110 : NOAPX,SSE,WESTMERE */
        {I_AESENCLAST, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69728, 433},
};

static const struct itemplate instrux_AESDEC[1] = {
    /*   0 : AESDEC xmmreg,xmmrm128 [rm:       66 0f38 de /r                     ] SSE,WESTMERE */
        /* 361 356 001(de) 110 : NOAPX,SSE,WESTMERE */
        {I_AESDEC, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69734, 433},
};

static const struct itemplate instrux_AESDECLAST[1] = {
    /*   0 : AESDECLAST xmmreg,xmmrm128 [rm:       66 0f38 df /r                     ] SSE,WESTMERE */
        /* 361 356 001(df) 110 : NOAPX,SSE,WESTMERE */
        {I_AESDECLAST, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69740, 433},
};

static const struct itemplate instrux_AESIMC[1] = {
    /*   0 : AESIMC xmmreg,xmmrm128 [rm:       66 0f38 db /r                     ] SSE,WESTMERE */
        /* 361 356 001(db) 110 : NOAPX,SSE,WESTMERE */
        {I_AESIMC, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69746, 433},
};

static const struct itemplate instrux_AESKEYGENASSIST[1] = {
    /*   0 : AESKEYGENASSIST xmmreg,xmmrm128,imm8 [rmi:      66 0f3a df /r ib                  ] SSE,WESTMERE */
        /* 361 357 001(df) 110 022 : NOAPX,SSE,WESTMERE */
        {I_AESKEYGENASSIST, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+58223, 433},
};

static const struct itemplate instrux_VAESENC[10] = {
    /*   0 : VAESENC xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f38 dc /r         ] AVX,SANDYBRIDGE */
        /* 261(002 001) 001(dc) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VAESENC, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58230, 434},
    /*   1 : VAESENC xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f38 dc /r         ] ND,AVX,SANDYBRIDGE */
        /* 260(002 001) 001(dc) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VAESENC, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58237, 434},
    /*   2 : VAESENC ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f38.wig dc /r     ] VAES,FUTURE */
        /* 261(002 005) 001(dc) 120 : NOAPX,WIG,VEX,VAES,FUTURE */
        {I_VAESENC, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58293, 438},
    /*   3 : VAESENC ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f38.wig dc /r     ] ND,VAES,FUTURE */
        /* 260(002 005) 001(dc) 110 : NOAPX,WIG,VEX,VAES,FUTURE */
        {I_VAESENC, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58300, 438},
    /*   4 : VAESENC xmmreg,xmmreg*,xmmrm128 [rvm:fv:   evex.nds.128.66.0f38.wig dc /r    ] AVX512,AVX512VL,VAES,FUTURE */
        /* 241(f2 7d 08) 301 001(dc) 120 : WIG,EVEX,PROT,AVX512,AVX512VL,VAES,FUTURE */
        {I_VAESENC, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+25794, 439},
    /*   5 : VAESENC xmmreg,xmmrm128 [r+vm:fv:   evex.nds.128.66.0f38.wig dc /r    ] ND,AVX512,AVX512VL,VAES,FUTURE */
        /* 240(f2 7d 08) 301 001(dc) 110 : WIG,EVEX,PROT,AVX512,AVX512VL,VAES,FUTURE */
        {I_VAESENC, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+25803, 439},
    /*   6 : VAESENC ymmreg,ymmreg*,ymmrm256 [rvm:fv:   evex.nds.256.66.0f38.wig dc /r    ] AVX512,AVX512VL,VAES,FUTURE */
        /* 241(f2 7d 28) 301 001(dc) 120 : WIG,EVEX,PROT,AVX512,AVX512VL,VAES,FUTURE */
        {I_VAESENC, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+25812, 439},
    /*   7 : VAESENC ymmreg,ymmrm256 [r+vm:fv:   evex.nds.256.66.0f38.wig dc /r    ] ND,AVX512,AVX512VL,VAES,FUTURE */
        /* 240(f2 7d 28) 301 001(dc) 110 : WIG,EVEX,PROT,AVX512,AVX512VL,VAES,FUTURE */
        {I_VAESENC, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+25821, 439},
    /*   8 : VAESENC zmmreg,zmmreg*,zmmrm512 [rvm:fv:   evex.nds.512.66.0f38.wig dc /r    ] AVX512,VAES,FUTURE */
        /* 241(f2 7d 48) 301 001(dc) 120 : WIG,EVEX,PROT,AVX512,VAES,FUTURE */
        {I_VAESENC, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, NO_DECORATOR, nasm_bytecodes+25938, 440},
    /*   9 : VAESENC zmmreg,zmmrm512 [r+vm:fv:   evex.nds.512.66.0f38.wig dc /r    ] ND,AVX512,VAES,FUTURE */
        /* 240(f2 7d 48) 301 001(dc) 110 : WIG,EVEX,PROT,AVX512,VAES,FUTURE */
        {I_VAESENC, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+25947, 440},
};

static const struct itemplate instrux_VAESENCLAST[10] = {
    /*   0 : VAESENCLAST xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f38 dd /r         ] AVX,SANDYBRIDGE */
        /* 261(002 001) 001(dd) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VAESENCLAST, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58244, 434},
    /*   1 : VAESENCLAST xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f38 dd /r         ] ND,AVX,SANDYBRIDGE */
        /* 260(002 001) 001(dd) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VAESENCLAST, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58251, 434},
    /*   2 : VAESENCLAST ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f38.wig dd /r     ] VAES,FUTURE */
        /* 261(002 005) 001(dd) 120 : NOAPX,WIG,VEX,VAES,FUTURE */
        {I_VAESENCLAST, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58307, 438},
    /*   3 : VAESENCLAST ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f38.wig dd /r     ] ND,VAES,FUTURE */
        /* 260(002 005) 001(dd) 110 : NOAPX,WIG,VEX,VAES,FUTURE */
        {I_VAESENCLAST, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58314, 438},
    /*   4 : VAESENCLAST xmmreg,xmmreg*,xmmrm128 [rvm:fv:   evex.nds.128.66.0f38.wig dd /r    ] AVX512,AVX512VL,VAES,FUTURE */
        /* 241(f2 7d 08) 301 001(dd) 120 : WIG,EVEX,PROT,AVX512,AVX512VL,VAES,FUTURE */
        {I_VAESENCLAST, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+25830, 439},
    /*   5 : VAESENCLAST xmmreg,xmmrm128 [r+vm:fv:   evex.nds.128.66.0f38.wig dd /r    ] ND,AVX512,AVX512VL,VAES,FUTURE */
        /* 240(f2 7d 08) 301 001(dd) 110 : WIG,EVEX,PROT,AVX512,AVX512VL,VAES,FUTURE */
        {I_VAESENCLAST, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+25839, 439},
    /*   6 : VAESENCLAST ymmreg,ymmreg*,ymmrm256 [rvm:fv:   evex.nds.256.66.0f38.wig dd /r    ] AVX512,AVX512VL,VAES,FUTURE */
        /* 241(f2 7d 28) 301 001(dd) 120 : WIG,EVEX,PROT,AVX512,AVX512VL,VAES,FUTURE */
        {I_VAESENCLAST, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+25848, 439},
    /*   7 : VAESENCLAST ymmreg,ymmrm256 [r+vm:fv:   evex.nds.256.66.0f38.wig dd /r    ] ND,AVX512,AVX512VL,VAES,FUTURE */
        /* 240(f2 7d 28) 301 001(dd) 110 : WIG,EVEX,PROT,AVX512,AVX512VL,VAES,FUTURE */
        {I_VAESENCLAST, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+25857, 439},
    /*   8 : VAESENCLAST zmmreg,zmmreg*,zmmrm512 [rvm:fv:   evex.nds.512.66.0f38.wig dd /r    ] AVX512,VAES,FUTURE */
        /* 241(f2 7d 48) 301 001(dd) 120 : WIG,EVEX,PROT,AVX512,VAES,FUTURE */
        {I_VAESENCLAST, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, NO_DECORATOR, nasm_bytecodes+25956, 440},
    /*   9 : VAESENCLAST zmmreg,zmmrm512 [r+vm:fv:   evex.nds.512.66.0f38.wig dd /r    ] ND,AVX512,VAES,FUTURE */
        /* 240(f2 7d 48) 301 001(dd) 110 : WIG,EVEX,PROT,AVX512,VAES,FUTURE */
        {I_VAESENCLAST, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+25965, 440},
};

static const struct itemplate instrux_VAESDEC[10] = {
    /*   0 : VAESDEC xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f38 de /r         ] AVX,SANDYBRIDGE */
        /* 261(002 001) 001(de) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VAESDEC, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58258, 434},
    /*   1 : VAESDEC xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f38 de /r         ] ND,AVX,SANDYBRIDGE */
        /* 260(002 001) 001(de) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VAESDEC, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58265, 434},
    /*   2 : VAESDEC ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f38.wig de /r     ] VAES,FUTURE */
        /* 261(002 005) 001(de) 120 : NOAPX,WIG,VEX,VAES,FUTURE */
        {I_VAESDEC, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58321, 438},
    /*   3 : VAESDEC ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f38.wig de /r     ] ND,VAES,FUTURE */
        /* 260(002 005) 001(de) 110 : NOAPX,WIG,VEX,VAES,FUTURE */
        {I_VAESDEC, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58328, 438},
    /*   4 : VAESDEC xmmreg,xmmreg*,xmmrm128 [rvm:fv:   evex.nds.128.66.0f38.wig de /r    ] AVX512,AVX512VL,VAES,FUTURE */
        /* 241(f2 7d 08) 301 001(de) 120 : WIG,EVEX,PROT,AVX512,AVX512VL,VAES,FUTURE */
        {I_VAESDEC, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+25866, 439},
    /*   5 : VAESDEC xmmreg,xmmrm128 [r+vm:fv:   evex.nds.128.66.0f38.wig de /r    ] ND,AVX512,AVX512VL,VAES,FUTURE */
        /* 240(f2 7d 08) 301 001(de) 110 : WIG,EVEX,PROT,AVX512,AVX512VL,VAES,FUTURE */
        {I_VAESDEC, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+25875, 439},
    /*   6 : VAESDEC ymmreg,ymmreg*,ymmrm256 [rvm:fv:   evex.nds.256.66.0f38.wig de /r    ] AVX512,AVX512VL,VAES,FUTURE */
        /* 241(f2 7d 28) 301 001(de) 120 : WIG,EVEX,PROT,AVX512,AVX512VL,VAES,FUTURE */
        {I_VAESDEC, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+25884, 439},
    /*   7 : VAESDEC ymmreg,ymmrm256 [r+vm:fv:   evex.nds.256.66.0f38.wig de /r    ] ND,AVX512,AVX512VL,VAES,FUTURE */
        /* 240(f2 7d 28) 301 001(de) 110 : WIG,EVEX,PROT,AVX512,AVX512VL,VAES,FUTURE */
        {I_VAESDEC, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+25893, 439},
    /*   8 : VAESDEC zmmreg,zmmreg*,zmmrm512 [rvm:fv:   evex.nds.512.66.0f38.wig de /r    ] AVX512,VAES,FUTURE */
        /* 241(f2 7d 48) 301 001(de) 120 : WIG,EVEX,PROT,AVX512,VAES,FUTURE */
        {I_VAESDEC, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, NO_DECORATOR, nasm_bytecodes+25974, 440},
    /*   9 : VAESDEC zmmreg,zmmrm512 [r+vm:fv:   evex.nds.512.66.0f38.wig de /r    ] ND,AVX512,VAES,FUTURE */
        /* 240(f2 7d 48) 301 001(de) 110 : WIG,EVEX,PROT,AVX512,VAES,FUTURE */
        {I_VAESDEC, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+25983, 440},
};

static const struct itemplate instrux_VAESDECLAST[10] = {
    /*   0 : VAESDECLAST xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f38 df /r         ] AVX,SANDYBRIDGE */
        /* 261(002 001) 001(df) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VAESDECLAST, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58272, 434},
    /*   1 : VAESDECLAST xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f38 df /r         ] ND,AVX,SANDYBRIDGE */
        /* 260(002 001) 001(df) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VAESDECLAST, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58279, 434},
    /*   2 : VAESDECLAST ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f38.wig df /r     ] VAES,FUTURE */
        /* 261(002 005) 001(df) 120 : NOAPX,WIG,VEX,VAES,FUTURE */
        {I_VAESDECLAST, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58335, 438},
    /*   3 : VAESDECLAST ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f38.wig df /r     ] ND,VAES,FUTURE */
        /* 260(002 005) 001(df) 110 : NOAPX,WIG,VEX,VAES,FUTURE */
        {I_VAESDECLAST, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58342, 438},
    /*   4 : VAESDECLAST xmmreg,xmmreg*,xmmrm128 [rvm:fv:   evex.nds.128.66.0f38.wig df /r    ] AVX512,AVX512VL,VAES,FUTURE */
        /* 241(f2 7d 08) 301 001(df) 120 : WIG,EVEX,PROT,AVX512,AVX512VL,VAES,FUTURE */
        {I_VAESDECLAST, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+25902, 439},
    /*   5 : VAESDECLAST xmmreg,xmmrm128 [r+vm:fv:   evex.nds.128.66.0f38.wig df /r    ] ND,AVX512,AVX512VL,VAES,FUTURE */
        /* 240(f2 7d 08) 301 001(df) 110 : WIG,EVEX,PROT,AVX512,AVX512VL,VAES,FUTURE */
        {I_VAESDECLAST, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+25911, 439},
    /*   6 : VAESDECLAST ymmreg,ymmreg*,ymmrm256 [rvm:fv:   evex.nds.256.66.0f38.wig df /r    ] AVX512,AVX512VL,VAES,FUTURE */
        /* 241(f2 7d 28) 301 001(df) 120 : WIG,EVEX,PROT,AVX512,AVX512VL,VAES,FUTURE */
        {I_VAESDECLAST, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+25920, 439},
    /*   7 : VAESDECLAST ymmreg,ymmrm256 [r+vm:fv:   evex.nds.256.66.0f38.wig df /r    ] ND,AVX512,AVX512VL,VAES,FUTURE */
        /* 240(f2 7d 28) 301 001(df) 110 : WIG,EVEX,PROT,AVX512,AVX512VL,VAES,FUTURE */
        {I_VAESDECLAST, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+25929, 439},
    /*   8 : VAESDECLAST zmmreg,zmmreg*,zmmrm512 [rvm:fv:   evex.nds.512.66.0f38.wig df /r    ] AVX512,VAES,FUTURE */
        /* 241(f2 7d 48) 301 001(df) 120 : WIG,EVEX,PROT,AVX512,VAES,FUTURE */
        {I_VAESDECLAST, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, NO_DECORATOR, nasm_bytecodes+25992, 440},
    /*   9 : VAESDECLAST zmmreg,zmmrm512 [r+vm:fv:   evex.nds.512.66.0f38.wig df /r    ] ND,AVX512,VAES,FUTURE */
        /* 240(f2 7d 48) 301 001(df) 110 : WIG,EVEX,PROT,AVX512,VAES,FUTURE */
        {I_VAESDECLAST, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+26001, 440},
};

static const struct itemplate instrux_VAESIMC[1] = {
    /*   0 : VAESIMC xmmreg,xmmrm128 [rm:       vex.128.66.0f38 db /r             ] AVX,SANDYBRIDGE */
        /* 270(002 001) 001(db) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VAESIMC, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58286, 434},
};

static const struct itemplate instrux_VAESKEYGENASSIST[1] = {
    /*   0 : VAESKEYGENASSIST xmmreg,xmmrm128,imm8 [rmi:      vex.128.66.0f3a df /r ib          ] AVX,SANDYBRIDGE */
        /* 270(003 001) 001(df) 110 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VAESKEYGENASSIST, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51597, 434},
};

static const struct itemplate instrux_AESDEC128KL[1] = {
    /*   0 : AESDEC128KL xmmreg,mem [rm:       f3 0f38 dd /r                     ] FL,AESKLE,FUTURE */
        /* 333 356 001(dd) 110 : NOAPX,FL,AESKLE,FUTURE */
        {I_AESDEC128KL, 2, {XMMREG|RN_L16,MEMORY|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69752, 435},
};

static const struct itemplate instrux_AESDEC256KL[1] = {
    /*   0 : AESDEC256KL xmmreg,mem512 [rm:       f3 0f38 df /r                     ] FL,AESKLE,FUTURE */
        /* 333 356 001(df) 110 : NOAPX,FL,AESKLE,FUTURE */
        {I_AESDEC256KL, 2, {XMMREG|RN_L16,MEMORY|BITS512|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69758, 435},
};

static const struct itemplate instrux_AESENC128KL[1] = {
    /*   0 : AESENC128KL xmmreg,mem [rm:       f3 0f38 dc /r                     ] FL,AESKLE,FUTURE */
        /* 333 356 001(dc) 110 : NOAPX,FL,AESKLE,FUTURE */
        {I_AESENC128KL, 2, {XMMREG|RN_L16,MEMORY|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69764, 435},
};

static const struct itemplate instrux_AESENC256KL[1] = {
    /*   0 : AESENC256KL xmmreg,mem512 [rm:       f3 0f38 de /r                     ] FL,AESKLE,FUTURE */
        /* 333 356 001(de) 110 : NOAPX,FL,AESKLE,FUTURE */
        {I_AESENC256KL, 2, {XMMREG|RN_L16,MEMORY|BITS512|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69770, 435},
};

static const struct itemplate instrux_ENCODEKEY128[1] = {
    /*   0 : ENCODEKEY128 reg32,reg32 [rm:       f3 0f38 fa /r                     ] AESKLE,FUTURE */
        /* 333 356 001(fa) 110 : NOAPX,AESKLE,FUTURE */
        {I_ENCODEKEY128, 2, {REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69776, 436},
};

static const struct itemplate instrux_ENCODEKEY256[1] = {
    /*   0 : ENCODEKEY256 reg32,reg32 [rm:       f3 0f38 fb /r                     ] AESKLE,FUTURE */
        /* 333 356 001(fb) 110 : NOAPX,AESKLE,FUTURE */
        {I_ENCODEKEY256, 2, {REG_GPR|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69782, 436},
};

static const struct itemplate instrux_LOADIWKEY[1] = {
    /*   0 : LOADIWKEY xmmreg,xmmreg [rm:       f3 0f38 dc /r                     ] FL,AESKLE,FUTURE */
        /* 333 356 001(dc) 110 : NOAPX,FL,AESKLE,FUTURE */
        {I_LOADIWKEY, 2, {XMMREG|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69764, 435},
};

static const struct itemplate instrux_AESDECWIDE128KL[1] = {
    /*   0 : AESDECWIDE128KL mem [m:        f3 0f38 d8 /1                     ] FL,AESKLEWIDE_KL,FUTURE */
        /* 333 356 001(d8) 201 : NOAPX,FL,AESKLEWIDE_KL,FUTURE */
        {I_AESDECWIDE128KL, 1, {MEMORY|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+69788, 437},
};

static const struct itemplate instrux_AESDECWIDE256KL[1] = {
    /*   0 : AESDECWIDE256KL mem512 [m:        f3 0f38 d8 /3                     ] FL,AESKLEWIDE_KL,FUTURE */
        /* 333 356 001(d8) 203 : NOAPX,FL,AESKLEWIDE_KL,FUTURE */
        {I_AESDECWIDE256KL, 1, {MEMORY|BITS512|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+69794, 437},
};

static const struct itemplate instrux_AESENCWIDE128KL[1] = {
    /*   0 : AESENCWIDE128KL mem [m:        f3 0f38 d8 /0                     ] FL,AESKLEWIDE_KL,FUTURE */
        /* 333 356 001(d8) 200 : NOAPX,FL,AESKLEWIDE_KL,FUTURE */
        {I_AESENCWIDE128KL, 1, {MEMORY|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+69800, 437},
};

static const struct itemplate instrux_AESENCWIDE256KL[1] = {
    /*   0 : AESENCWIDE256KL mem512 [m:        f3 0f38 d8 /2                     ] FL,AESKLEWIDE_KL,FUTURE */
        /* 333 356 001(d8) 202 : NOAPX,FL,AESKLEWIDE_KL,FUTURE */
        {I_AESENCWIDE256KL, 1, {MEMORY|BITS512|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+69806, 437},
};

static const struct itemplate instrux_VADDPD[10] = {
    /*   0 : VADDPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f 58 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(58) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VADDPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58349, 434},
    /*   1 : VADDPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f 58 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(58) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VADDPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58356, 434},
    /*   2 : VADDPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f 58 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(58) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VADDPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58363, 434},
    /*   3 : VADDPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f 58 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(58) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VADDPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58370, 434},
    /*   4 : VADDPD xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f.w1 58 /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(58) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VADDPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+30438, 544},
    /*   5 : VADDPD xmmreg|mask|z,xmmrm128|b64 [r+vm:fv:   evex.nds.128.66.0f.w1 58 /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 08) 301 001(58) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VADDPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+30447, 544},
    /*   6 : VADDPD ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f.w1 58 /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(58) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VADDPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+30456, 544},
    /*   7 : VADDPD ymmreg|mask|z,ymmrm256|b64 [r+vm:fv:   evex.nds.256.66.0f.w1 58 /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 28) 301 001(58) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VADDPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+30465, 544},
    /*   8 : VADDPD zmmreg|mask|z,zmmreg*,zmmrm512|b64|er [rvm:fv:   evex.nds.512.66.0f.w1 58 /r       ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(58) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VADDPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+30474, 545},
    /*   9 : VADDPD zmmreg|mask|z,zmmrm512|b64|er [r+vm:fv:   evex.nds.512.66.0f.w1 58 /r       ] ND,AVX512,FUTURE */
        /* 240(f1 fd 48) 301 001(58) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VADDPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+30483, 545},
};

static const struct itemplate instrux_VADDPS[10] = {
    /*   0 : VADDPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f 58 /r              ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(58) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VADDPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58377, 434},
    /*   1 : VADDPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f 58 /r              ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(58) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VADDPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58384, 434},
    /*   2 : VADDPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f 58 /r              ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(58) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VADDPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58391, 434},
    /*   3 : VADDPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f 58 /r              ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(58) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VADDPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58398, 434},
    /*   4 : VADDPS xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.nds.128.0f.w0 58 /r          ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(58) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VADDPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+30492, 544},
    /*   5 : VADDPS xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.nds.128.0f.w0 58 /r          ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7c 08) 301 001(58) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VADDPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30501, 544},
    /*   6 : VADDPS ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.nds.256.0f.w0 58 /r          ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(58) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VADDPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+30510, 544},
    /*   7 : VADDPS ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.nds.256.0f.w0 58 /r          ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7c 28) 301 001(58) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VADDPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30519, 544},
    /*   8 : VADDPS zmmreg|mask|z,zmmreg*,zmmrm512|b32|er [rvm:fv:   evex.nds.512.0f.w0 58 /r          ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(58) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VADDPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+30528, 545},
    /*   9 : VADDPS zmmreg|mask|z,zmmrm512|b32|er [r+vm:fv:   evex.nds.512.0f.w0 58 /r          ] ND,AVX512,FUTURE */
        /* 240(f1 7c 48) 301 001(58) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VADDPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+30537, 545},
};

static const struct itemplate instrux_VADDSD[4] = {
    /*   0 : VADDSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f 58 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(58) 120 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VADDSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58405, 441},
    /*   1 : VADDSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f 58 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(58) 110 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VADDSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58412, 441},
    /*   2 : VADDSD xmmreg|mask|z,xmmreg*,xmmrm64|er [rvm:t1s:  evex.nds.lig.f2.0f.w1 58 /r       ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(58) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VADDSD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+30546, 546},
    /*   3 : VADDSD xmmreg|mask|z,xmmrm64|er [r+vm:t1s:  evex.nds.lig.f2.0f.w1 58 /r       ] ND,AVX512,FUTURE */
        /* 240(f1 ff 08) 306 001(58) 110 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VADDSD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+30555, 546},
};

static const struct itemplate instrux_VADDSS[4] = {
    /*   0 : VADDSS xmmreg,xmmreg*,xmmrm32 [rvm:      vex.nds.lig.f3.0f 58 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(58) 120 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VADDSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58419, 441},
    /*   1 : VADDSS xmmreg,xmmrm32 [r+vm:      vex.nds.lig.f3.0f 58 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(58) 110 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VADDSS, 2, {XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58426, 441},
    /*   2 : VADDSS xmmreg|mask|z,xmmreg*,xmmrm32|er [rvm:t1s:  evex.nds.lig.f3.0f.w0 58 /r       ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(58) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VADDSS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+30564, 546},
    /*   3 : VADDSS xmmreg|mask|z,xmmrm32|er [r+vm:t1s:  evex.nds.lig.f3.0f.w0 58 /r       ] ND,AVX512,FUTURE */
        /* 240(f1 7e 08) 306 001(58) 110 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VADDSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+30573, 546},
};

static const struct itemplate instrux_VADDSUBPD[4] = {
    /*   0 : VADDSUBPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f d0 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(d0) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VADDSUBPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58433, 434},
    /*   1 : VADDSUBPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f d0 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(d0) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VADDSUBPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58440, 434},
    /*   2 : VADDSUBPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f d0 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(d0) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VADDSUBPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58447, 434},
    /*   3 : VADDSUBPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f d0 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(d0) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VADDSUBPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58454, 434},
};

static const struct itemplate instrux_VADDSUBPS[4] = {
    /*   0 : VADDSUBPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.f2.0f d0 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(d0) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VADDSUBPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58461, 434},
    /*   1 : VADDSUBPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.f2.0f d0 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(d0) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VADDSUBPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58468, 434},
    /*   2 : VADDSUBPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.f2.0f d0 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 007) 001(d0) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VADDSUBPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58475, 434},
    /*   3 : VADDSUBPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.f2.0f d0 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 007) 001(d0) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VADDSUBPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58482, 434},
};

static const struct itemplate instrux_VANDPD[10] = {
    /*   0 : VANDPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f 54 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(54) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VANDPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58489, 434},
    /*   1 : VANDPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f 54 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(54) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VANDPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58496, 434},
    /*   2 : VANDPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f 54 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(54) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VANDPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58503, 434},
    /*   3 : VANDPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f 54 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(54) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VANDPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58510, 434},
    /*   4 : VANDPD xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f.w1 54 /r       ] AVX512VL,AVX512DQ,FUTURE */
        /* 241(f1 fd 08) 301 001(54) 120 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VANDPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+30690, 547},
    /*   5 : VANDPD xmmreg|mask|z,xmmrm128|b64 [r+vm:fv:   evex.nds.128.66.0f.w1 54 /r       ] ND,AVX512VL,AVX512DQ,FUTURE */
        /* 240(f1 fd 08) 301 001(54) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VANDPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+30699, 547},
    /*   6 : VANDPD ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f.w1 54 /r       ] AVX512VL,AVX512DQ,FUTURE */
        /* 241(f1 fd 28) 301 001(54) 120 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VANDPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+30708, 547},
    /*   7 : VANDPD ymmreg|mask|z,ymmrm256|b64 [r+vm:fv:   evex.nds.256.66.0f.w1 54 /r       ] ND,AVX512VL,AVX512DQ,FUTURE */
        /* 240(f1 fd 28) 301 001(54) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VANDPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+30717, 547},
    /*   8 : VANDPD zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv:   evex.nds.512.66.0f.w1 54 /r       ] AVX512DQ,FUTURE */
        /* 241(f1 fd 48) 301 001(54) 120 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VANDPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+30726, 548},
    /*   9 : VANDPD zmmreg|mask|z,zmmrm512|b64 [r+vm:fv:   evex.nds.512.66.0f.w1 54 /r       ] ND,AVX512DQ,FUTURE */
        /* 240(f1 fd 48) 301 001(54) 110 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VANDPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+30735, 548},
};

static const struct itemplate instrux_VANDPS[10] = {
    /*   0 : VANDPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f 54 /r              ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(54) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VANDPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58517, 434},
    /*   1 : VANDPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f 54 /r              ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(54) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VANDPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58524, 434},
    /*   2 : VANDPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f 54 /r              ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(54) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VANDPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58531, 434},
    /*   3 : VANDPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f 54 /r              ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(54) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VANDPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58538, 434},
    /*   4 : VANDPS xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.nds.128.0f.w0 54 /r          ] AVX512VL,AVX512DQ,FUTURE */
        /* 241(f1 7c 08) 301 001(54) 120 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VANDPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+30744, 547},
    /*   5 : VANDPS xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.nds.128.0f.w0 54 /r          ] ND,AVX512VL,AVX512DQ,FUTURE */
        /* 240(f1 7c 08) 301 001(54) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VANDPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30753, 547},
    /*   6 : VANDPS ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.nds.256.0f.w0 54 /r          ] AVX512VL,AVX512DQ,FUTURE */
        /* 241(f1 7c 28) 301 001(54) 120 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VANDPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+30762, 547},
    /*   7 : VANDPS ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.nds.256.0f.w0 54 /r          ] ND,AVX512VL,AVX512DQ,FUTURE */
        /* 240(f1 7c 28) 301 001(54) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VANDPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30771, 547},
    /*   8 : VANDPS zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv:   evex.nds.512.0f.w0 54 /r          ] AVX512DQ,FUTURE */
        /* 241(f1 7c 48) 301 001(54) 120 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VANDPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+30780, 548},
    /*   9 : VANDPS zmmreg|mask|z,zmmrm512|b32 [r+vm:fv:   evex.nds.512.0f.w0 54 /r          ] ND,AVX512DQ,FUTURE */
        /* 240(f1 7c 48) 301 001(54) 110 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VANDPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30789, 548},
};

static const struct itemplate instrux_VANDNPD[10] = {
    /*   0 : VANDNPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f 55 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(55) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VANDNPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58545, 434},
    /*   1 : VANDNPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f 55 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(55) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VANDNPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58552, 434},
    /*   2 : VANDNPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f 55 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(55) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VANDNPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58559, 434},
    /*   3 : VANDNPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f 55 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(55) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VANDNPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58566, 434},
    /*   4 : VANDNPD xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f.w1 55 /r       ] AVX512VL,AVX512DQ,FUTURE */
        /* 241(f1 fd 08) 301 001(55) 120 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VANDNPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+30582, 547},
    /*   5 : VANDNPD xmmreg|mask|z,xmmrm128|b64 [r+vm:fv:   evex.nds.128.66.0f.w1 55 /r       ] ND,AVX512VL,AVX512DQ,FUTURE */
        /* 240(f1 fd 08) 301 001(55) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VANDNPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+30591, 547},
    /*   6 : VANDNPD ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f.w1 55 /r       ] AVX512VL,AVX512DQ,FUTURE */
        /* 241(f1 fd 28) 301 001(55) 120 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VANDNPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+30600, 547},
    /*   7 : VANDNPD ymmreg|mask|z,ymmrm256|b64 [r+vm:fv:   evex.nds.256.66.0f.w1 55 /r       ] ND,AVX512VL,AVX512DQ,FUTURE */
        /* 240(f1 fd 28) 301 001(55) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VANDNPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+30609, 547},
    /*   8 : VANDNPD zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv:   evex.nds.512.66.0f.w1 55 /r       ] AVX512DQ,FUTURE */
        /* 241(f1 fd 48) 301 001(55) 120 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VANDNPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+30618, 548},
    /*   9 : VANDNPD zmmreg|mask|z,zmmrm512|b64 [r+vm:fv:   evex.nds.512.66.0f.w1 55 /r       ] ND,AVX512DQ,FUTURE */
        /* 240(f1 fd 48) 301 001(55) 110 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VANDNPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+30627, 548},
};

static const struct itemplate instrux_VANDNPS[10] = {
    /*   0 : VANDNPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f 55 /r              ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(55) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VANDNPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58573, 434},
    /*   1 : VANDNPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f 55 /r              ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(55) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VANDNPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58580, 434},
    /*   2 : VANDNPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f 55 /r              ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(55) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VANDNPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58587, 434},
    /*   3 : VANDNPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f 55 /r              ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(55) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VANDNPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58594, 434},
    /*   4 : VANDNPS xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.nds.128.0f.w0 55 /r          ] AVX512VL,AVX512DQ,FUTURE */
        /* 241(f1 7c 08) 301 001(55) 120 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VANDNPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+30636, 547},
    /*   5 : VANDNPS xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.nds.128.0f.w0 55 /r          ] ND,AVX512VL,AVX512DQ,FUTURE */
        /* 240(f1 7c 08) 301 001(55) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VANDNPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30645, 547},
    /*   6 : VANDNPS ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.nds.256.0f.w0 55 /r          ] AVX512VL,AVX512DQ,FUTURE */
        /* 241(f1 7c 28) 301 001(55) 120 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VANDNPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+30654, 547},
    /*   7 : VANDNPS ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.nds.256.0f.w0 55 /r          ] ND,AVX512VL,AVX512DQ,FUTURE */
        /* 240(f1 7c 28) 301 001(55) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VANDNPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30663, 547},
    /*   8 : VANDNPS zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv:   evex.nds.512.0f.w0 55 /r          ] AVX512DQ,FUTURE */
        /* 241(f1 7c 48) 301 001(55) 120 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VANDNPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+30672, 548},
    /*   9 : VANDNPS zmmreg|mask|z,zmmrm512|b32 [r+vm:fv:   evex.nds.512.0f.w0 55 /r          ] ND,AVX512DQ,FUTURE */
        /* 240(f1 7c 48) 301 001(55) 110 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VANDNPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30681, 548},
};

static const struct itemplate instrux_VBLENDPD[4] = {
    /*   0 : VBLENDPD xmmreg,xmmreg*,xmmrm128,imm8 [rvmi:     vex.nds.128.66.0f3a 0d /r ib      ] AVX,SANDYBRIDGE */
        /* 261(003 001) 001(0d) 120 023 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VBLENDPD, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+51605, 434},
    /*   1 : VBLENDPD xmmreg,xmmrm128,imm8 [r+vmi:     vex.nds.128.66.0f3a 0d /r ib      ] ND,AVX,SANDYBRIDGE */
        /* 260(003 001) 001(0d) 110 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VBLENDPD, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51613, 434},
    /*   2 : VBLENDPD ymmreg,ymmreg*,ymmrm256,imm8 [rvmi:     vex.nds.256.66.0f3a 0d /r ib      ] AVX,SANDYBRIDGE */
        /* 261(003 005) 001(0d) 120 023 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VBLENDPD, 4, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+51621, 434},
    /*   3 : VBLENDPD ymmreg,ymmrm256,imm8 [r+vmi:     vex.nds.256.66.0f3a 0d /r ib      ] ND,AVX,SANDYBRIDGE */
        /* 260(003 005) 001(0d) 110 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VBLENDPD, 3, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51629, 434},
};

static const struct itemplate instrux_VBLENDPS[4] = {
    /*   0 : VBLENDPS xmmreg,xmmreg*,xmmrm128,imm8 [rvmi:     vex.nds.128.66.0f3a 0c /r ib      ] AVX,SANDYBRIDGE */
        /* 261(003 001) 001(0c) 120 023 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VBLENDPS, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+51637, 434},
    /*   1 : VBLENDPS xmmreg,xmmrm128,imm8 [r+vmi:     vex.nds.128.66.0f3a 0c /r ib      ] ND,AVX,SANDYBRIDGE */
        /* 260(003 001) 001(0c) 110 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VBLENDPS, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51645, 434},
    /*   2 : VBLENDPS ymmreg,ymmreg*,ymmrm256,imm8 [rvmi:     vex.nds.256.66.0f3a 0c /r ib      ] AVX,SANDYBRIDGE */
        /* 261(003 005) 001(0c) 120 023 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VBLENDPS, 4, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+51653, 434},
    /*   3 : VBLENDPS ymmreg,ymmrm256,imm8 [r+vmi:     vex.nds.256.66.0f3a 0c /r ib      ] ND,AVX,SANDYBRIDGE */
        /* 260(003 005) 001(0c) 110 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VBLENDPS, 3, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51661, 434},
};

static const struct itemplate instrux_VBLENDVPD[4] = {
    /*   0 : VBLENDVPD xmmreg,xmmreg*,xmmrm128,xmmreg [rvms:     vex.nds.128.66.0f3a.w0 4b /r /is4 ] AVX,SANDYBRIDGE */
        /* 261(003 001) 001(4b) 120 177 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VBLENDVPD, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+51669, 442},
    /*   1 : VBLENDVPD xmmreg,xmmrm128,xmmreg [r+vms:     vex.nds.128.66.0f3a.w0 4b /r /is4 ] ND,AVX,SANDYBRIDGE */
        /* 260(003 001) 001(4b) 110 176 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VBLENDVPD, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+51677, 442},
    /*   2 : VBLENDVPD ymmreg,ymmreg*,ymmrm256,ymmreg [rvms:     vex.nds.256.66.0f3a.w0 4b /r /is4 ] AVX,SANDYBRIDGE */
        /* 261(003 005) 001(4b) 120 177 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VBLENDVPD, 4, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,YMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+51685, 442},
    /*   3 : VBLENDVPD ymmreg,ymmrm256,ymmreg [r+vms:     vex.nds.256.66.0f3a.w0 4b /r /is4 ] ND,AVX,SANDYBRIDGE */
        /* 260(003 005) 001(4b) 110 176 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VBLENDVPD, 3, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,YMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+51693, 442},
};

static const struct itemplate instrux_VBLENDVPS[4] = {
    /*   0 : VBLENDVPS xmmreg,xmmreg*,xmmrm128,xmmreg [rvms:     vex.nds.128.66.0f3a.w0 4a /r /is4 ] AVX,SANDYBRIDGE */
        /* 261(003 001) 001(4a) 120 177 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VBLENDVPS, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+51701, 442},
    /*   1 : VBLENDVPS xmmreg,xmmrm128,xmmreg [r+vms:     vex.nds.128.66.0f3a.w0 4a /r /is4 ] ND,AVX,SANDYBRIDGE */
        /* 260(003 001) 001(4a) 110 176 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VBLENDVPS, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+51709, 442},
    /*   2 : VBLENDVPS ymmreg,ymmreg*,ymmrm256,ymmreg [rvms:     vex.nds.256.66.0f3a.w0 4a /r /is4 ] AVX,SANDYBRIDGE */
        /* 261(003 005) 001(4a) 120 177 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VBLENDVPS, 4, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,YMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+51717, 442},
    /*   3 : VBLENDVPS ymmreg,ymmrm256,ymmreg [r+vms:     vex.nds.256.66.0f3a.w0 4a /r /is4 ] ND,AVX,SANDYBRIDGE */
        /* 260(003 005) 001(4a) 110 176 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VBLENDVPS, 3, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,YMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+51725, 442},
};

static const struct itemplate instrux_VBROADCASTSS[10] = {
    /*   0 : VBROADCASTSS xmmreg,mem32 [rm:       vex.128.66.0f38.w0 18 /r          ] AVX,SANDYBRIDGE */
        /* 270(002 001) 001(18) 110 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VBROADCASTSS, 2, {XMMREG|RN_L16,MEMORY|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58601, 442},
    /*   1 : VBROADCASTSS ymmreg,mem32 [rm:       vex.256.66.0f38.w0 18 /r          ] AVX,SANDYBRIDGE */
        /* 270(002 005) 001(18) 110 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VBROADCASTSS, 2, {YMMREG|RN_L16,MEMORY|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58608, 442},
    /*   2 : VBROADCASTSS xmmreg,xmmreg [rm:       vex.128.66.0f38.w0 18 /r          ] AVX2,FUTURE */
        /* 270(002 001) 001(18) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VBROADCASTSS, 2, {XMMREG|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58601, 469},
    /*   3 : VBROADCASTSS ymmreg,xmmreg [rm:       vex.256.66.0f38.w0 18 /r          ] AVX2,FUTURE */
        /* 270(002 005) 001(18) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VBROADCASTSS, 2, {YMMREG|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58608, 469},
    /*   4 : VBROADCASTSS xmmreg|mask|z,mem32 [rm:t1s:   evex.128.66.0f38.w0 18 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 08) 306 001(18) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VBROADCASTSS, 2, {XMMREG,MEMORY|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+31041, 544},
    /*   5 : VBROADCASTSS ymmreg|mask|z,mem32 [rm:t1s:   evex.256.66.0f38.w0 18 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 28) 306 001(18) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VBROADCASTSS, 2, {YMMREG,MEMORY|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+31050, 544},
    /*   6 : VBROADCASTSS zmmreg|mask|z,mem32 [rm:t1s:   evex.512.66.0f38.w0 18 /r         ] AVX512,FUTURE */
        /* 250(f2 7d 48) 306 001(18) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VBROADCASTSS, 2, {ZMMREG,MEMORY|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+31059, 545},
    /*   7 : VBROADCASTSS xmmreg|mask|z,xmmreg [rm:       evex.128.66.0f38.w0 18 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 08) 300 001(18) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VBROADCASTSS, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+31068, 544},
    /*   8 : VBROADCASTSS ymmreg|mask|z,xmmreg [rm:       evex.256.66.0f38.w0 18 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 28) 300 001(18) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VBROADCASTSS, 2, {YMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+31077, 544},
    /*   9 : VBROADCASTSS zmmreg|mask|z,xmmreg [rm:       evex.512.66.0f38.w0 18 /r         ] AVX512,FUTURE */
        /* 250(f2 7d 48) 300 001(18) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VBROADCASTSS, 2, {ZMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+31086, 545},
};

static const struct itemplate instrux_VBROADCASTSD[6] = {
    /*   0 : VBROADCASTSD ymmreg,mem64 [rm:       vex.256.66.0f38.w0 19 /r          ] AVX,SANDYBRIDGE */
        /* 270(002 005) 001(19) 110 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VBROADCASTSD, 2, {YMMREG|RN_L16,MEMORY|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58615, 442},
    /*   1 : VBROADCASTSD ymmreg,xmmreg [rm:       vex.256.66.0f38.w0 19 /r          ] AVX2,FUTURE */
        /* 270(002 005) 001(19) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VBROADCASTSD, 2, {YMMREG|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58615, 469},
    /*   2 : VBROADCASTSD ymmreg|mask|z,mem64 [rm:t1s:   evex.256.66.0f38.w1 19 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 fd 28) 306 001(19) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VBROADCASTSD, 2, {YMMREG,MEMORY|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+31005, 544},
    /*   3 : VBROADCASTSD zmmreg|mask|z,mem64 [rm:t1s:   evex.512.66.0f38.w1 19 /r         ] AVX512,FUTURE */
        /* 250(f2 fd 48) 306 001(19) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VBROADCASTSD, 2, {ZMMREG,MEMORY|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+31014, 545},
    /*   4 : VBROADCASTSD ymmreg|mask|z,xmmreg [rm:       evex.256.66.0f38.w1 19 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 fd 28) 300 001(19) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VBROADCASTSD, 2, {YMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+31023, 544},
    /*   5 : VBROADCASTSD zmmreg|mask|z,xmmreg [rm:       evex.512.66.0f38.w1 19 /r         ] AVX512,FUTURE */
        /* 250(f2 fd 48) 300 001(19) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VBROADCASTSD, 2, {ZMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+31032, 545},
};

static const struct itemplate instrux_VBROADCASTF128[1] = {
    /*   0 : VBROADCASTF128 ymmreg,mem128 [rm:       vex.256.66.0f38.w0 1a /r          ] AVX,SANDYBRIDGE */
        /* 270(002 005) 001(1a) 110 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VBROADCASTF128, 2, {YMMREG|RN_L16,MEMORY|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58622, 442},
};

static const struct itemplate instrux_VCMPEQ_OSPD[11] = {
    /*   0 : VCMPEQ_OSPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 10        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(10) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_OSPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26010, 434},
    /*   1 : VCMPEQ_OSPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 10        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(10) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_OSPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26019, 434},
    /*   2 : VCMPEQ_OSPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 10        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(10) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_OSPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26028, 434},
    /*   3 : VCMPEQ_OSPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 10        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(10) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_OSPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26037, 434},
    /*   4 : VCMPEQ_OSPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 10        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(10) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_OSPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26010, 434},
    /*   5 : VCMPEQ_OSPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 10        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(10) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_OSPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26019, 434},
    /*   6 : VCMPEQ_OSPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 10        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(10) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_OSPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26028, 434},
    /*   7 : VCMPEQ_OSPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 10        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(10) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_OSPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26037, 434},
    /*   8 : VCMPEQ_OSPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 10    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(10) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPEQ_OSPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+6151, 544},
    /*   9 : VCMPEQ_OSPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 10    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(10) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPEQ_OSPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+6162, 544},
    /*  10 : VCMPEQ_OSPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 10    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(10) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPEQ_OSPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+6173, 545},
};

static const struct itemplate instrux_VCMPEQPD[7] = {
    /*   0 : VCMPEQPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 00        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(00) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26046, 434},
    /*   1 : VCMPEQPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 00        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(00) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26055, 434},
    /*   2 : VCMPEQPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 00        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(00) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26064, 434},
    /*   3 : VCMPEQPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 00        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(00) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26073, 434},
    /*   4 : VCMPEQPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 00    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(00) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPEQPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+4743, 544},
    /*   5 : VCMPEQPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 00    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(00) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPEQPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+4754, 544},
    /*   6 : VCMPEQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 00    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(00) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPEQPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+4765, 545},
};

static const struct itemplate instrux_VCMPLT_OSPD[7] = {
    /*   0 : VCMPLT_OSPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 01        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(01) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLT_OSPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26082, 434},
    /*   1 : VCMPLT_OSPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 01        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(01) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLT_OSPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26091, 434},
    /*   2 : VCMPLT_OSPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 01        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(01) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLT_OSPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26100, 434},
    /*   3 : VCMPLT_OSPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 01        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(01) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLT_OSPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26109, 434},
    /*   4 : VCMPLT_OSPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 01    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(01) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPLT_OSPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+4831, 544},
    /*   5 : VCMPLT_OSPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 01    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(01) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPLT_OSPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+4842, 544},
    /*   6 : VCMPLT_OSPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 01    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(01) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPLT_OSPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+4853, 545},
};

static const struct itemplate instrux_VCMPLTPD[7] = {
    /*   0 : VCMPLTPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 01        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(01) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLTPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26082, 434},
    /*   1 : VCMPLTPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 01        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(01) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLTPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26091, 434},
    /*   2 : VCMPLTPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 01        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(01) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLTPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26100, 434},
    /*   3 : VCMPLTPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 01        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(01) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLTPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26109, 434},
    /*   4 : VCMPLTPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 01    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(01) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPLTPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+4831, 544},
    /*   5 : VCMPLTPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 01    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(01) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPLTPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+4842, 544},
    /*   6 : VCMPLTPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 01    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(01) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPLTPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+4853, 545},
};

static const struct itemplate instrux_VCMPLE_OSPD[7] = {
    /*   0 : VCMPLE_OSPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 02        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(02) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLE_OSPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26118, 434},
    /*   1 : VCMPLE_OSPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 02        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(02) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLE_OSPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26127, 434},
    /*   2 : VCMPLE_OSPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 02        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(02) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLE_OSPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26136, 434},
    /*   3 : VCMPLE_OSPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 02        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(02) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLE_OSPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26145, 434},
    /*   4 : VCMPLE_OSPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 02    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(02) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPLE_OSPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+4919, 544},
    /*   5 : VCMPLE_OSPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 02    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(02) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPLE_OSPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+4930, 544},
    /*   6 : VCMPLE_OSPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 02    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(02) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPLE_OSPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+4941, 545},
};

static const struct itemplate instrux_VCMPLEPD[7] = {
    /*   0 : VCMPLEPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 02        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(02) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLEPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26118, 434},
    /*   1 : VCMPLEPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 02        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(02) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLEPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26127, 434},
    /*   2 : VCMPLEPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 02        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(02) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLEPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26136, 434},
    /*   3 : VCMPLEPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 02        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(02) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLEPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26145, 434},
    /*   4 : VCMPLEPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 02    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(02) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPLEPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+4919, 544},
    /*   5 : VCMPLEPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 02    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(02) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPLEPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+4930, 544},
    /*   6 : VCMPLEPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 02    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(02) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPLEPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+4941, 545},
};

static const struct itemplate instrux_VCMPUNORD_QPD[7] = {
    /*   0 : VCMPUNORD_QPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 03        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(03) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPUNORD_QPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26154, 434},
    /*   1 : VCMPUNORD_QPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 03        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(03) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPUNORD_QPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26163, 434},
    /*   2 : VCMPUNORD_QPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 03        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(03) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPUNORD_QPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26172, 434},
    /*   3 : VCMPUNORD_QPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 03        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(03) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPUNORD_QPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26181, 434},
    /*   4 : VCMPUNORD_QPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 03    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(03) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPUNORD_QPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5007, 544},
    /*   5 : VCMPUNORD_QPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 03    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(03) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPUNORD_QPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5018, 544},
    /*   6 : VCMPUNORD_QPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 03    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(03) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPUNORD_QPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+5029, 545},
};

static const struct itemplate instrux_VCMPUNORDPD[7] = {
    /*   0 : VCMPUNORDPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 03        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(03) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPUNORDPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26154, 434},
    /*   1 : VCMPUNORDPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 03        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(03) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPUNORDPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26163, 434},
    /*   2 : VCMPUNORDPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 03        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(03) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPUNORDPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26172, 434},
    /*   3 : VCMPUNORDPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 03        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(03) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPUNORDPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26181, 434},
    /*   4 : VCMPUNORDPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 03    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(03) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPUNORDPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5007, 544},
    /*   5 : VCMPUNORDPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 03    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(03) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPUNORDPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5018, 544},
    /*   6 : VCMPUNORDPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 03    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(03) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPUNORDPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+5029, 545},
};

static const struct itemplate instrux_VCMPNEQ_UQPD[7] = {
    /*   0 : VCMPNEQ_UQPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 04        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(04) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_UQPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26190, 434},
    /*   1 : VCMPNEQ_UQPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 04        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(04) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_UQPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26199, 434},
    /*   2 : VCMPNEQ_UQPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 04        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(04) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_UQPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26208, 434},
    /*   3 : VCMPNEQ_UQPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 04        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(04) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_UQPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26217, 434},
    /*   4 : VCMPNEQ_UQPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 04    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(04) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNEQ_UQPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5095, 544},
    /*   5 : VCMPNEQ_UQPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 04    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(04) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNEQ_UQPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5106, 544},
    /*   6 : VCMPNEQ_UQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 04    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(04) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNEQ_UQPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+5117, 545},
};

static const struct itemplate instrux_VCMPNEQPD[7] = {
    /*   0 : VCMPNEQPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 04        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(04) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26190, 434},
    /*   1 : VCMPNEQPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 04        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(04) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26199, 434},
    /*   2 : VCMPNEQPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 04        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(04) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26208, 434},
    /*   3 : VCMPNEQPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 04        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(04) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26217, 434},
    /*   4 : VCMPNEQPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 04    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(04) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNEQPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5095, 544},
    /*   5 : VCMPNEQPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 04    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(04) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNEQPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5106, 544},
    /*   6 : VCMPNEQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 04    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(04) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNEQPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+5117, 545},
};

static const struct itemplate instrux_VCMPNLT_USPD[7] = {
    /*   0 : VCMPNLT_USPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 05        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(05) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLT_USPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26226, 434},
    /*   1 : VCMPNLT_USPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 05        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(05) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLT_USPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26235, 434},
    /*   2 : VCMPNLT_USPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 05        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(05) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLT_USPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26244, 434},
    /*   3 : VCMPNLT_USPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 05        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(05) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLT_USPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26253, 434},
    /*   4 : VCMPNLT_USPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 05    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(05) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNLT_USPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5183, 544},
    /*   5 : VCMPNLT_USPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 05    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(05) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNLT_USPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5194, 544},
    /*   6 : VCMPNLT_USPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 05    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(05) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNLT_USPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+5205, 545},
};

static const struct itemplate instrux_VCMPNLTPD[7] = {
    /*   0 : VCMPNLTPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 05        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(05) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLTPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26226, 434},
    /*   1 : VCMPNLTPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 05        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(05) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLTPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26235, 434},
    /*   2 : VCMPNLTPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 05        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(05) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLTPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26244, 434},
    /*   3 : VCMPNLTPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 05        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(05) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLTPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26253, 434},
    /*   4 : VCMPNLTPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 05    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(05) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNLTPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5183, 544},
    /*   5 : VCMPNLTPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 05    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(05) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNLTPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5194, 544},
    /*   6 : VCMPNLTPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 05    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(05) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNLTPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+5205, 545},
};

static const struct itemplate instrux_VCMPNLE_USPD[7] = {
    /*   0 : VCMPNLE_USPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 06        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(06) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLE_USPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26262, 434},
    /*   1 : VCMPNLE_USPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 06        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(06) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLE_USPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26271, 434},
    /*   2 : VCMPNLE_USPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 06        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(06) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLE_USPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26280, 434},
    /*   3 : VCMPNLE_USPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 06        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(06) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLE_USPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26289, 434},
    /*   4 : VCMPNLE_USPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 06    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(06) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNLE_USPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5271, 544},
    /*   5 : VCMPNLE_USPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 06    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(06) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNLE_USPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5282, 544},
    /*   6 : VCMPNLE_USPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 06    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(06) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNLE_USPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+5293, 545},
};

static const struct itemplate instrux_VCMPNLEPD[7] = {
    /*   0 : VCMPNLEPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 06        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(06) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLEPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26262, 434},
    /*   1 : VCMPNLEPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 06        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(06) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLEPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26271, 434},
    /*   2 : VCMPNLEPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 06        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(06) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLEPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26280, 434},
    /*   3 : VCMPNLEPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 06        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(06) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLEPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26289, 434},
    /*   4 : VCMPNLEPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 06    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(06) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNLEPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5271, 544},
    /*   5 : VCMPNLEPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 06    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(06) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNLEPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5282, 544},
    /*   6 : VCMPNLEPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 06    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(06) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNLEPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+5293, 545},
};

static const struct itemplate instrux_VCMPORD_QPD[7] = {
    /*   0 : VCMPORD_QPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 07        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(07) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPORD_QPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26298, 434},
    /*   1 : VCMPORD_QPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 07        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(07) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPORD_QPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26307, 434},
    /*   2 : VCMPORD_QPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 07        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(07) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPORD_QPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26316, 434},
    /*   3 : VCMPORD_QPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 07        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(07) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPORD_QPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26325, 434},
    /*   4 : VCMPORD_QPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 07    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(07) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPORD_QPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5359, 544},
    /*   5 : VCMPORD_QPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 07    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(07) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPORD_QPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5370, 544},
    /*   6 : VCMPORD_QPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 07    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(07) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPORD_QPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+5381, 545},
};

static const struct itemplate instrux_VCMPORDPD[7] = {
    /*   0 : VCMPORDPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 07        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(07) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPORDPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26298, 434},
    /*   1 : VCMPORDPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 07        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(07) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPORDPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26307, 434},
    /*   2 : VCMPORDPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 07        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(07) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPORDPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26316, 434},
    /*   3 : VCMPORDPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 07        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(07) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPORDPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26325, 434},
    /*   4 : VCMPORDPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 07    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(07) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPORDPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5359, 544},
    /*   5 : VCMPORDPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 07    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(07) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPORDPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5370, 544},
    /*   6 : VCMPORDPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 07    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(07) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPORDPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+5381, 545},
};

static const struct itemplate instrux_VCMPEQ_UQPD[7] = {
    /*   0 : VCMPEQ_UQPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 08        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(08) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_UQPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26334, 434},
    /*   1 : VCMPEQ_UQPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 08        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(08) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_UQPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26343, 434},
    /*   2 : VCMPEQ_UQPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 08        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(08) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_UQPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26352, 434},
    /*   3 : VCMPEQ_UQPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 08        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(08) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_UQPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26361, 434},
    /*   4 : VCMPEQ_UQPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 08    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(08) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPEQ_UQPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5447, 544},
    /*   5 : VCMPEQ_UQPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 08    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(08) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPEQ_UQPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5458, 544},
    /*   6 : VCMPEQ_UQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 08    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(08) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPEQ_UQPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+5469, 545},
};

static const struct itemplate instrux_VCMPNGE_USPD[7] = {
    /*   0 : VCMPNGE_USPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 09        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(09) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGE_USPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26370, 434},
    /*   1 : VCMPNGE_USPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 09        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(09) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGE_USPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26379, 434},
    /*   2 : VCMPNGE_USPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 09        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(09) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGE_USPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26388, 434},
    /*   3 : VCMPNGE_USPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 09        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(09) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGE_USPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26397, 434},
    /*   4 : VCMPNGE_USPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 09    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(09) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNGE_USPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5535, 544},
    /*   5 : VCMPNGE_USPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 09    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(09) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNGE_USPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5546, 544},
    /*   6 : VCMPNGE_USPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 09    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(09) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNGE_USPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+5557, 545},
};

static const struct itemplate instrux_VCMPNGEPD[7] = {
    /*   0 : VCMPNGEPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 09        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(09) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGEPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26370, 434},
    /*   1 : VCMPNGEPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 09        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(09) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGEPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26379, 434},
    /*   2 : VCMPNGEPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 09        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(09) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGEPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26388, 434},
    /*   3 : VCMPNGEPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 09        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(09) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGEPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26397, 434},
    /*   4 : VCMPNGEPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 09    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(09) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNGEPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5535, 544},
    /*   5 : VCMPNGEPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 09    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(09) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNGEPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5546, 544},
    /*   6 : VCMPNGEPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 09    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(09) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNGEPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+5557, 545},
};

static const struct itemplate instrux_VCMPNGT_USPD[7] = {
    /*   0 : VCMPNGT_USPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 0a        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(0a) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGT_USPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26406, 434},
    /*   1 : VCMPNGT_USPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 0a        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(0a) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGT_USPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26415, 434},
    /*   2 : VCMPNGT_USPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 0a        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(0a) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGT_USPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26424, 434},
    /*   3 : VCMPNGT_USPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 0a        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(0a) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGT_USPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26433, 434},
    /*   4 : VCMPNGT_USPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 0a    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(0a) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNGT_USPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5623, 544},
    /*   5 : VCMPNGT_USPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 0a    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(0a) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNGT_USPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5634, 544},
    /*   6 : VCMPNGT_USPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 0a    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(0a) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNGT_USPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+5645, 545},
};

static const struct itemplate instrux_VCMPNGTPD[7] = {
    /*   0 : VCMPNGTPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 0a        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(0a) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGTPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26406, 434},
    /*   1 : VCMPNGTPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 0a        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(0a) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGTPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26415, 434},
    /*   2 : VCMPNGTPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 0a        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(0a) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGTPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26424, 434},
    /*   3 : VCMPNGTPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 0a        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(0a) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGTPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26433, 434},
    /*   4 : VCMPNGTPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 0a    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(0a) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNGTPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5623, 544},
    /*   5 : VCMPNGTPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 0a    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(0a) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNGTPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5634, 544},
    /*   6 : VCMPNGTPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 0a    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(0a) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNGTPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+5645, 545},
};

static const struct itemplate instrux_VCMPFALSE_OQPD[7] = {
    /*   0 : VCMPFALSE_OQPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 0b        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(0b) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPFALSE_OQPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26442, 434},
    /*   1 : VCMPFALSE_OQPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 0b        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(0b) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPFALSE_OQPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26451, 434},
    /*   2 : VCMPFALSE_OQPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 0b        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(0b) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPFALSE_OQPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26460, 434},
    /*   3 : VCMPFALSE_OQPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 0b        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(0b) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPFALSE_OQPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26469, 434},
    /*   4 : VCMPFALSE_OQPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 0b    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(0b) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPFALSE_OQPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5711, 544},
    /*   5 : VCMPFALSE_OQPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 0b    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(0b) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPFALSE_OQPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5722, 544},
    /*   6 : VCMPFALSE_OQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 0b    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(0b) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPFALSE_OQPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+5733, 545},
};

static const struct itemplate instrux_VCMPFALSEPD[7] = {
    /*   0 : VCMPFALSEPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 0b        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(0b) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPFALSEPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26442, 434},
    /*   1 : VCMPFALSEPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 0b        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(0b) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPFALSEPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26451, 434},
    /*   2 : VCMPFALSEPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 0b        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(0b) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPFALSEPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26460, 434},
    /*   3 : VCMPFALSEPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 0b        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(0b) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPFALSEPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26469, 434},
    /*   4 : VCMPFALSEPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 0b    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(0b) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPFALSEPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5711, 544},
    /*   5 : VCMPFALSEPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 0b    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(0b) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPFALSEPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5722, 544},
    /*   6 : VCMPFALSEPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 0b    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(0b) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPFALSEPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+5733, 545},
};

static const struct itemplate instrux_VCMPNEQ_OQPD[7] = {
    /*   0 : VCMPNEQ_OQPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 0c        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(0c) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_OQPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26478, 434},
    /*   1 : VCMPNEQ_OQPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 0c        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(0c) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_OQPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26487, 434},
    /*   2 : VCMPNEQ_OQPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 0c        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(0c) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_OQPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26496, 434},
    /*   3 : VCMPNEQ_OQPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 0c        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(0c) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_OQPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26505, 434},
    /*   4 : VCMPNEQ_OQPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 0c    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(0c) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNEQ_OQPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5799, 544},
    /*   5 : VCMPNEQ_OQPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 0c    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(0c) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNEQ_OQPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5810, 544},
    /*   6 : VCMPNEQ_OQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 0c    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(0c) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNEQ_OQPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+5821, 545},
};

static const struct itemplate instrux_VCMPGE_OSPD[7] = {
    /*   0 : VCMPGE_OSPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 0d        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(0d) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGE_OSPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26514, 434},
    /*   1 : VCMPGE_OSPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 0d        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(0d) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGE_OSPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26523, 434},
    /*   2 : VCMPGE_OSPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 0d        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(0d) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGE_OSPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26532, 434},
    /*   3 : VCMPGE_OSPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 0d        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(0d) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGE_OSPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26541, 434},
    /*   4 : VCMPGE_OSPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 0d    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(0d) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPGE_OSPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5887, 544},
    /*   5 : VCMPGE_OSPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 0d    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(0d) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPGE_OSPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5898, 544},
    /*   6 : VCMPGE_OSPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 0d    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(0d) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPGE_OSPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+5909, 545},
};

static const struct itemplate instrux_VCMPGEPD[7] = {
    /*   0 : VCMPGEPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 0d        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(0d) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGEPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26514, 434},
    /*   1 : VCMPGEPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 0d        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(0d) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGEPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26523, 434},
    /*   2 : VCMPGEPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 0d        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(0d) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGEPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26532, 434},
    /*   3 : VCMPGEPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 0d        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(0d) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGEPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26541, 434},
    /*   4 : VCMPGEPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 0d    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(0d) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPGEPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5887, 544},
    /*   5 : VCMPGEPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 0d    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(0d) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPGEPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5898, 544},
    /*   6 : VCMPGEPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 0d    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(0d) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPGEPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+5909, 545},
};

static const struct itemplate instrux_VCMPGT_OSPD[7] = {
    /*   0 : VCMPGT_OSPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 0e        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(0e) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGT_OSPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26550, 434},
    /*   1 : VCMPGT_OSPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 0e        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(0e) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGT_OSPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26559, 434},
    /*   2 : VCMPGT_OSPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 0e        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(0e) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGT_OSPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26568, 434},
    /*   3 : VCMPGT_OSPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 0e        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(0e) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGT_OSPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26577, 434},
    /*   4 : VCMPGT_OSPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 0e    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(0e) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPGT_OSPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5975, 544},
    /*   5 : VCMPGT_OSPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 0e    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(0e) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPGT_OSPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5986, 544},
    /*   6 : VCMPGT_OSPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 0e    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(0e) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPGT_OSPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+5997, 545},
};

static const struct itemplate instrux_VCMPGTPD[7] = {
    /*   0 : VCMPGTPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 0e        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(0e) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGTPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26550, 434},
    /*   1 : VCMPGTPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 0e        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(0e) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGTPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26559, 434},
    /*   2 : VCMPGTPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 0e        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(0e) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGTPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26568, 434},
    /*   3 : VCMPGTPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 0e        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(0e) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGTPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26577, 434},
    /*   4 : VCMPGTPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 0e    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(0e) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPGTPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5975, 544},
    /*   5 : VCMPGTPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 0e    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(0e) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPGTPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+5986, 544},
    /*   6 : VCMPGTPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 0e    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(0e) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPGTPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+5997, 545},
};

static const struct itemplate instrux_VCMPTRUE_UQPD[7] = {
    /*   0 : VCMPTRUE_UQPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 0f        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(0f) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPTRUE_UQPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26586, 434},
    /*   1 : VCMPTRUE_UQPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 0f        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(0f) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPTRUE_UQPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26595, 434},
    /*   2 : VCMPTRUE_UQPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 0f        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(0f) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPTRUE_UQPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26604, 434},
    /*   3 : VCMPTRUE_UQPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 0f        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(0f) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPTRUE_UQPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26613, 434},
    /*   4 : VCMPTRUE_UQPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 0f    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(0f) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPTRUE_UQPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+6063, 544},
    /*   5 : VCMPTRUE_UQPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 0f    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(0f) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPTRUE_UQPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+6074, 544},
    /*   6 : VCMPTRUE_UQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 0f    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(0f) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPTRUE_UQPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+6085, 545},
};

static const struct itemplate instrux_VCMPTRUEPD[7] = {
    /*   0 : VCMPTRUEPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 0f        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(0f) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPTRUEPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26586, 434},
    /*   1 : VCMPTRUEPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 0f        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(0f) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPTRUEPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26595, 434},
    /*   2 : VCMPTRUEPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 0f        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(0f) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPTRUEPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26604, 434},
    /*   3 : VCMPTRUEPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 0f        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(0f) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPTRUEPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26613, 434},
    /*   4 : VCMPTRUEPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 0f    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(0f) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPTRUEPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+6063, 544},
    /*   5 : VCMPTRUEPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 0f    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(0f) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPTRUEPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+6074, 544},
    /*   6 : VCMPTRUEPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 0f    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(0f) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPTRUEPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+6085, 545},
};

static const struct itemplate instrux_VCMPLT_OQPD[7] = {
    /*   0 : VCMPLT_OQPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 11        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(11) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLT_OQPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26622, 434},
    /*   1 : VCMPLT_OQPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 11        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(11) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLT_OQPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26631, 434},
    /*   2 : VCMPLT_OQPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 11        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(11) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLT_OQPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26640, 434},
    /*   3 : VCMPLT_OQPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 11        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(11) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLT_OQPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26649, 434},
    /*   4 : VCMPLT_OQPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 11    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(11) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPLT_OQPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+6239, 544},
    /*   5 : VCMPLT_OQPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 11    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(11) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPLT_OQPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+6250, 544},
    /*   6 : VCMPLT_OQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 11    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(11) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPLT_OQPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+6261, 545},
};

static const struct itemplate instrux_VCMPLE_OQPD[7] = {
    /*   0 : VCMPLE_OQPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 12        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(12) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLE_OQPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26658, 434},
    /*   1 : VCMPLE_OQPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 12        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(12) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLE_OQPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26667, 434},
    /*   2 : VCMPLE_OQPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 12        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(12) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLE_OQPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26676, 434},
    /*   3 : VCMPLE_OQPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 12        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(12) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLE_OQPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26685, 434},
    /*   4 : VCMPLE_OQPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 12    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(12) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPLE_OQPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+6327, 544},
    /*   5 : VCMPLE_OQPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 12    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(12) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPLE_OQPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+6338, 544},
    /*   6 : VCMPLE_OQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 12    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(12) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPLE_OQPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+6349, 545},
};

static const struct itemplate instrux_VCMPUNORD_SPD[7] = {
    /*   0 : VCMPUNORD_SPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 13        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(13) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPUNORD_SPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26694, 434},
    /*   1 : VCMPUNORD_SPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 13        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(13) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPUNORD_SPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26703, 434},
    /*   2 : VCMPUNORD_SPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 13        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(13) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPUNORD_SPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26712, 434},
    /*   3 : VCMPUNORD_SPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 13        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(13) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPUNORD_SPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26721, 434},
    /*   4 : VCMPUNORD_SPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 13    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(13) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPUNORD_SPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+6415, 544},
    /*   5 : VCMPUNORD_SPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 13    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(13) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPUNORD_SPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+6426, 544},
    /*   6 : VCMPUNORD_SPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 13    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(13) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPUNORD_SPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+6437, 545},
};

static const struct itemplate instrux_VCMPNEQ_USPD[7] = {
    /*   0 : VCMPNEQ_USPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 14        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(14) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_USPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26730, 434},
    /*   1 : VCMPNEQ_USPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 14        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(14) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_USPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26739, 434},
    /*   2 : VCMPNEQ_USPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 14        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(14) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_USPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26748, 434},
    /*   3 : VCMPNEQ_USPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 14        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(14) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_USPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26757, 434},
    /*   4 : VCMPNEQ_USPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 14    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(14) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNEQ_USPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+6503, 544},
    /*   5 : VCMPNEQ_USPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 14    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(14) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNEQ_USPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+6514, 544},
    /*   6 : VCMPNEQ_USPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 14    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(14) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNEQ_USPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+6525, 545},
};

static const struct itemplate instrux_VCMPNLT_UQPD[7] = {
    /*   0 : VCMPNLT_UQPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 15        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(15) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLT_UQPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26766, 434},
    /*   1 : VCMPNLT_UQPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 15        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(15) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLT_UQPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26775, 434},
    /*   2 : VCMPNLT_UQPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 15        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(15) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLT_UQPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26784, 434},
    /*   3 : VCMPNLT_UQPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 15        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(15) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLT_UQPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26793, 434},
    /*   4 : VCMPNLT_UQPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 15    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(15) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNLT_UQPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+6591, 544},
    /*   5 : VCMPNLT_UQPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 15    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(15) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNLT_UQPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+6602, 544},
    /*   6 : VCMPNLT_UQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 15    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(15) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNLT_UQPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+6613, 545},
};

static const struct itemplate instrux_VCMPNLE_UQPD[7] = {
    /*   0 : VCMPNLE_UQPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 16        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(16) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLE_UQPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26802, 434},
    /*   1 : VCMPNLE_UQPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 16        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(16) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLE_UQPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26811, 434},
    /*   2 : VCMPNLE_UQPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 16        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(16) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLE_UQPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26820, 434},
    /*   3 : VCMPNLE_UQPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 16        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(16) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLE_UQPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26829, 434},
    /*   4 : VCMPNLE_UQPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 16    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(16) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNLE_UQPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+6679, 544},
    /*   5 : VCMPNLE_UQPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 16    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(16) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNLE_UQPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+6690, 544},
    /*   6 : VCMPNLE_UQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 16    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(16) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNLE_UQPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+6701, 545},
};

static const struct itemplate instrux_VCMPORD_SPD[7] = {
    /*   0 : VCMPORD_SPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 17        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(17) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPORD_SPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26838, 434},
    /*   1 : VCMPORD_SPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 17        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(17) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPORD_SPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26847, 434},
    /*   2 : VCMPORD_SPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 17        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(17) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPORD_SPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26856, 434},
    /*   3 : VCMPORD_SPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 17        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(17) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPORD_SPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26865, 434},
    /*   4 : VCMPORD_SPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 17    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(17) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPORD_SPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+6767, 544},
    /*   5 : VCMPORD_SPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 17    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(17) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPORD_SPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+6778, 544},
    /*   6 : VCMPORD_SPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 17    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(17) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPORD_SPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+6789, 545},
};

static const struct itemplate instrux_VCMPEQ_USPD[7] = {
    /*   0 : VCMPEQ_USPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 18        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(18) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_USPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26874, 434},
    /*   1 : VCMPEQ_USPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 18        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(18) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_USPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26883, 434},
    /*   2 : VCMPEQ_USPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 18        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(18) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_USPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26892, 434},
    /*   3 : VCMPEQ_USPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 18        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(18) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_USPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26901, 434},
    /*   4 : VCMPEQ_USPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 18    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(18) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPEQ_USPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+6855, 544},
    /*   5 : VCMPEQ_USPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 18    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(18) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPEQ_USPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+6866, 544},
    /*   6 : VCMPEQ_USPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 18    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(18) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPEQ_USPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+6877, 545},
};

static const struct itemplate instrux_VCMPNGE_UQPD[7] = {
    /*   0 : VCMPNGE_UQPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 19        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(19) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGE_UQPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26910, 434},
    /*   1 : VCMPNGE_UQPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 19        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(19) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGE_UQPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26919, 434},
    /*   2 : VCMPNGE_UQPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 19        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(19) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGE_UQPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26928, 434},
    /*   3 : VCMPNGE_UQPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 19        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(19) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGE_UQPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26937, 434},
    /*   4 : VCMPNGE_UQPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 19    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(19) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNGE_UQPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+6943, 544},
    /*   5 : VCMPNGE_UQPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 19    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(19) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNGE_UQPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+6954, 544},
    /*   6 : VCMPNGE_UQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 19    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(19) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNGE_UQPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+6965, 545},
};

static const struct itemplate instrux_VCMPNGT_UQPD[7] = {
    /*   0 : VCMPNGT_UQPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 1a        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(1a) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGT_UQPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26946, 434},
    /*   1 : VCMPNGT_UQPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 1a        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(1a) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGT_UQPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26955, 434},
    /*   2 : VCMPNGT_UQPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 1a        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(1a) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGT_UQPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26964, 434},
    /*   3 : VCMPNGT_UQPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 1a        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(1a) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGT_UQPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26973, 434},
    /*   4 : VCMPNGT_UQPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 1a    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(1a) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNGT_UQPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+7031, 544},
    /*   5 : VCMPNGT_UQPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 1a    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(1a) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNGT_UQPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+7042, 544},
    /*   6 : VCMPNGT_UQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 1a    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(1a) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNGT_UQPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+7053, 545},
};

static const struct itemplate instrux_VCMPFALSE_OSPD[7] = {
    /*   0 : VCMPFALSE_OSPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 1b        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(1b) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPFALSE_OSPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+26982, 434},
    /*   1 : VCMPFALSE_OSPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 1b        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(1b) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPFALSE_OSPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+26991, 434},
    /*   2 : VCMPFALSE_OSPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 1b        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(1b) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPFALSE_OSPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27000, 434},
    /*   3 : VCMPFALSE_OSPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 1b        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(1b) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPFALSE_OSPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27009, 434},
    /*   4 : VCMPFALSE_OSPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 1b    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(1b) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPFALSE_OSPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+7119, 544},
    /*   5 : VCMPFALSE_OSPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 1b    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(1b) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPFALSE_OSPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+7130, 544},
    /*   6 : VCMPFALSE_OSPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 1b    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(1b) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPFALSE_OSPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+7141, 545},
};

static const struct itemplate instrux_VCMPNEQ_OSPD[7] = {
    /*   0 : VCMPNEQ_OSPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 1c        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(1c) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_OSPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27018, 434},
    /*   1 : VCMPNEQ_OSPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 1c        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(1c) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_OSPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27027, 434},
    /*   2 : VCMPNEQ_OSPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 1c        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(1c) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_OSPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27036, 434},
    /*   3 : VCMPNEQ_OSPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 1c        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(1c) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_OSPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27045, 434},
    /*   4 : VCMPNEQ_OSPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 1c    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(1c) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNEQ_OSPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+7207, 544},
    /*   5 : VCMPNEQ_OSPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 1c    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(1c) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNEQ_OSPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+7218, 544},
    /*   6 : VCMPNEQ_OSPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 1c    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(1c) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNEQ_OSPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+7229, 545},
};

static const struct itemplate instrux_VCMPGE_OQPD[7] = {
    /*   0 : VCMPGE_OQPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 1d        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(1d) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGE_OQPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27054, 434},
    /*   1 : VCMPGE_OQPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 1d        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(1d) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGE_OQPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27063, 434},
    /*   2 : VCMPGE_OQPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 1d        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(1d) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGE_OQPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27072, 434},
    /*   3 : VCMPGE_OQPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 1d        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(1d) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGE_OQPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27081, 434},
    /*   4 : VCMPGE_OQPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 1d    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(1d) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPGE_OQPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+7295, 544},
    /*   5 : VCMPGE_OQPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 1d    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(1d) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPGE_OQPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+7306, 544},
    /*   6 : VCMPGE_OQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 1d    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(1d) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPGE_OQPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+7317, 545},
};

static const struct itemplate instrux_VCMPGT_OQPD[7] = {
    /*   0 : VCMPGT_OQPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 1e        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(1e) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGT_OQPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27090, 434},
    /*   1 : VCMPGT_OQPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 1e        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(1e) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGT_OQPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27099, 434},
    /*   2 : VCMPGT_OQPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 1e        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(1e) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGT_OQPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27108, 434},
    /*   3 : VCMPGT_OQPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 1e        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(1e) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGT_OQPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27117, 434},
    /*   4 : VCMPGT_OQPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 1e    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(1e) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPGT_OQPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+7383, 544},
    /*   5 : VCMPGT_OQPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 1e    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(1e) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPGT_OQPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+7394, 544},
    /*   6 : VCMPGT_OQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 1e    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(1e) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPGT_OQPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+7405, 545},
};

static const struct itemplate instrux_VCMPTRUE_USPD[7] = {
    /*   0 : VCMPTRUE_USPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f c2 /r 1f        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 001(1f) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPTRUE_USPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27126, 434},
    /*   1 : VCMPTRUE_USPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f c2 /r 1f        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 001(1f) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPTRUE_USPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27135, 434},
    /*   2 : VCMPTRUE_USPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f c2 /r 1f        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 001(1f) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPTRUE_USPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27144, 434},
    /*   3 : VCMPTRUE_USPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f c2 /r 1f        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 001(1f) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPTRUE_USPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27153, 434},
    /*   4 : VCMPTRUE_USPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 1f    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(1f) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPTRUE_USPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+7471, 544},
    /*   5 : VCMPTRUE_USPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 1f    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(1f) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPTRUE_USPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+7482, 544},
    /*   6 : VCMPTRUE_USPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 1f    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(1f) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPTRUE_USPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+7493, 545},
};

static const struct itemplate instrux_VCMPPD[7] = {
    /*   0 : VCMPPD xmmreg,xmmreg*,xmmrm128,imm8 [rvmi:     vex.nds.128.66.0f c2 /r ib        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c2) 120 023 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPPD, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+51733, 434},
    /*   1 : VCMPPD xmmreg,xmmrm128,imm8 [r+vmi:     vex.nds.128.66.0f c2 /r ib        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c2) 110 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPPD, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51741, 434},
    /*   2 : VCMPPD ymmreg,ymmreg*,ymmrm256,imm8 [rvmi:     vex.nds.256.66.0f c2 /r ib        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c2) 120 023 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPPD, 4, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+51749, 434},
    /*   3 : VCMPPD ymmreg,ymmrm256,imm8 [r+vmi:     vex.nds.256.66.0f c2 /r ib        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c2) 110 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPPD, 3, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51757, 434},
    /*   4 : VCMPPD kreg|mask,xmmreg,xmmrm128|b64,imm8 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r ib    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 023 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPPD, 4, {OPMASKREG,XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK,0,B64,0,0}, nasm_bytecodes+18253, 544},
    /*   5 : VCMPPD kreg|mask,ymmreg,ymmrm256|b64,imm8 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r ib    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 023 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPPD, 4, {OPMASKREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK,0,B64,0,0}, nasm_bytecodes+18263, 544},
    /*   6 : VCMPPD kreg|mask,zmmreg,zmmrm512|b64|sae,imm8 [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r ib    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 023 : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPPD, 4, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+18273, 545},
};

static const struct itemplate instrux_VCMPEQ_OSPS[11] = {
    /*   0 : VCMPEQ_OSPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 10           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(10) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_OSPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27162, 434},
    /*   1 : VCMPEQ_OSPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 10           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(10) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_OSPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27171, 434},
    /*   2 : VCMPEQ_OSPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 10           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(10) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_OSPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27180, 434},
    /*   3 : VCMPEQ_OSPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 10           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(10) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_OSPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27189, 434},
    /*   4 : VCMPEQ_OSPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 10           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(10) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_OSPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27162, 434},
    /*   5 : VCMPEQ_OSPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 10           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(10) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_OSPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27171, 434},
    /*   6 : VCMPEQ_OSPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 10           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(10) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_OSPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27180, 434},
    /*   7 : VCMPEQ_OSPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 10           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(10) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_OSPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27189, 434},
    /*   8 : VCMPEQ_OSPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 10       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(10) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPEQ_OSPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+6184, 544},
    /*   9 : VCMPEQ_OSPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 10       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(10) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPEQ_OSPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+6195, 544},
    /*  10 : VCMPEQ_OSPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 10       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(10) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPEQ_OSPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+6206, 545},
};

static const struct itemplate instrux_VCMPEQPS[7] = {
    /*   0 : VCMPEQPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 00           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(00) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27198, 434},
    /*   1 : VCMPEQPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 00           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(00) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27207, 434},
    /*   2 : VCMPEQPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 00           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(00) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27216, 434},
    /*   3 : VCMPEQPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 00           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(00) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27225, 434},
    /*   4 : VCMPEQPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 00       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(00) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPEQPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+4776, 544},
    /*   5 : VCMPEQPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 00       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(00) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPEQPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+4787, 544},
    /*   6 : VCMPEQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 00       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(00) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPEQPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+4798, 545},
};

static const struct itemplate instrux_VCMPLT_OSPS[7] = {
    /*   0 : VCMPLT_OSPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 01           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(01) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLT_OSPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27234, 434},
    /*   1 : VCMPLT_OSPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 01           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(01) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLT_OSPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27243, 434},
    /*   2 : VCMPLT_OSPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 01           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(01) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLT_OSPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27252, 434},
    /*   3 : VCMPLT_OSPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 01           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(01) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLT_OSPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27261, 434},
    /*   4 : VCMPLT_OSPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 01       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(01) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPLT_OSPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+4864, 544},
    /*   5 : VCMPLT_OSPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 01       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(01) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPLT_OSPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+4875, 544},
    /*   6 : VCMPLT_OSPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 01       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(01) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPLT_OSPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+4886, 545},
};

static const struct itemplate instrux_VCMPLTPS[7] = {
    /*   0 : VCMPLTPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 01           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(01) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLTPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27234, 434},
    /*   1 : VCMPLTPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 01           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(01) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLTPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27243, 434},
    /*   2 : VCMPLTPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 01           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(01) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLTPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27252, 434},
    /*   3 : VCMPLTPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 01           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(01) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLTPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27261, 434},
    /*   4 : VCMPLTPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 01       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(01) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPLTPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+4864, 544},
    /*   5 : VCMPLTPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 01       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(01) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPLTPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+4875, 544},
    /*   6 : VCMPLTPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 01       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(01) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPLTPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+4886, 545},
};

static const struct itemplate instrux_VCMPLE_OSPS[7] = {
    /*   0 : VCMPLE_OSPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 02           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(02) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLE_OSPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27270, 434},
    /*   1 : VCMPLE_OSPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 02           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(02) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLE_OSPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27279, 434},
    /*   2 : VCMPLE_OSPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 02           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(02) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLE_OSPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27288, 434},
    /*   3 : VCMPLE_OSPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 02           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(02) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLE_OSPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27297, 434},
    /*   4 : VCMPLE_OSPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 02       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(02) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPLE_OSPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+4952, 544},
    /*   5 : VCMPLE_OSPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 02       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(02) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPLE_OSPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+4963, 544},
    /*   6 : VCMPLE_OSPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 02       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(02) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPLE_OSPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+4974, 545},
};

static const struct itemplate instrux_VCMPLEPS[7] = {
    /*   0 : VCMPLEPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 02           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(02) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLEPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27270, 434},
    /*   1 : VCMPLEPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 02           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(02) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLEPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27279, 434},
    /*   2 : VCMPLEPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 02           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(02) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLEPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27288, 434},
    /*   3 : VCMPLEPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 02           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(02) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLEPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27297, 434},
    /*   4 : VCMPLEPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 02       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(02) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPLEPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+4952, 544},
    /*   5 : VCMPLEPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 02       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(02) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPLEPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+4963, 544},
    /*   6 : VCMPLEPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 02       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(02) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPLEPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+4974, 545},
};

static const struct itemplate instrux_VCMPUNORD_QPS[7] = {
    /*   0 : VCMPUNORD_QPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 03           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(03) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPUNORD_QPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27306, 434},
    /*   1 : VCMPUNORD_QPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 03           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(03) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPUNORD_QPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27315, 434},
    /*   2 : VCMPUNORD_QPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 03           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(03) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPUNORD_QPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27324, 434},
    /*   3 : VCMPUNORD_QPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 03           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(03) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPUNORD_QPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27333, 434},
    /*   4 : VCMPUNORD_QPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 03       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(03) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPUNORD_QPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+5040, 544},
    /*   5 : VCMPUNORD_QPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 03       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(03) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPUNORD_QPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+5051, 544},
    /*   6 : VCMPUNORD_QPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 03       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(03) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPUNORD_QPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+5062, 545},
};

static const struct itemplate instrux_VCMPUNORDPS[7] = {
    /*   0 : VCMPUNORDPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 03           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(03) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPUNORDPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27306, 434},
    /*   1 : VCMPUNORDPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 03           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(03) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPUNORDPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27315, 434},
    /*   2 : VCMPUNORDPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 03           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(03) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPUNORDPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27324, 434},
    /*   3 : VCMPUNORDPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 03           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(03) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPUNORDPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27333, 434},
    /*   4 : VCMPUNORDPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 03       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(03) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPUNORDPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+5040, 544},
    /*   5 : VCMPUNORDPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 03       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(03) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPUNORDPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+5051, 544},
    /*   6 : VCMPUNORDPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 03       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(03) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPUNORDPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+5062, 545},
};

static const struct itemplate instrux_VCMPNEQ_UQPS[7] = {
    /*   0 : VCMPNEQ_UQPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 04           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(04) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_UQPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27342, 434},
    /*   1 : VCMPNEQ_UQPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 04           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(04) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_UQPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27351, 434},
    /*   2 : VCMPNEQ_UQPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 04           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(04) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_UQPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27360, 434},
    /*   3 : VCMPNEQ_UQPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 04           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(04) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_UQPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27369, 434},
    /*   4 : VCMPNEQ_UQPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 04       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(04) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNEQ_UQPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+5128, 544},
    /*   5 : VCMPNEQ_UQPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 04       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(04) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNEQ_UQPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+5139, 544},
    /*   6 : VCMPNEQ_UQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 04       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(04) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNEQ_UQPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+5150, 545},
};

static const struct itemplate instrux_VCMPNEQPS[7] = {
    /*   0 : VCMPNEQPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 04           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(04) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27342, 434},
    /*   1 : VCMPNEQPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 04           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(04) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27351, 434},
    /*   2 : VCMPNEQPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 04           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(04) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27360, 434},
    /*   3 : VCMPNEQPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 04           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(04) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27369, 434},
    /*   4 : VCMPNEQPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 04       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(04) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNEQPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+5128, 544},
    /*   5 : VCMPNEQPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 04       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(04) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNEQPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+5139, 544},
    /*   6 : VCMPNEQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 04       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(04) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNEQPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+5150, 545},
};

static const struct itemplate instrux_VCMPNLT_USPS[7] = {
    /*   0 : VCMPNLT_USPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 05           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(05) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLT_USPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27378, 434},
    /*   1 : VCMPNLT_USPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 05           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(05) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLT_USPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27387, 434},
    /*   2 : VCMPNLT_USPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 05           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(05) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLT_USPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27396, 434},
    /*   3 : VCMPNLT_USPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 05           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(05) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLT_USPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27405, 434},
    /*   4 : VCMPNLT_USPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 05       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(05) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNLT_USPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+5216, 544},
    /*   5 : VCMPNLT_USPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 05       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(05) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNLT_USPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+5227, 544},
    /*   6 : VCMPNLT_USPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 05       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(05) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNLT_USPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+5238, 545},
};

static const struct itemplate instrux_VCMPNLTPS[7] = {
    /*   0 : VCMPNLTPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 05           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(05) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLTPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27378, 434},
    /*   1 : VCMPNLTPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 05           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(05) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLTPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27387, 434},
    /*   2 : VCMPNLTPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 05           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(05) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLTPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27396, 434},
    /*   3 : VCMPNLTPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 05           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(05) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLTPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27405, 434},
    /*   4 : VCMPNLTPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 05       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(05) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNLTPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+5216, 544},
    /*   5 : VCMPNLTPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 05       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(05) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNLTPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+5227, 544},
    /*   6 : VCMPNLTPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 05       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(05) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNLTPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+5238, 545},
};

static const struct itemplate instrux_VCMPNLE_USPS[7] = {
    /*   0 : VCMPNLE_USPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 06           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(06) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLE_USPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27414, 434},
    /*   1 : VCMPNLE_USPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 06           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(06) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLE_USPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27423, 434},
    /*   2 : VCMPNLE_USPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 06           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(06) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLE_USPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27432, 434},
    /*   3 : VCMPNLE_USPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 06           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(06) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLE_USPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27441, 434},
    /*   4 : VCMPNLE_USPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 06       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(06) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNLE_USPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+5304, 544},
    /*   5 : VCMPNLE_USPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 06       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(06) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNLE_USPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+5315, 544},
    /*   6 : VCMPNLE_USPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 06       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(06) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNLE_USPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+5326, 545},
};

static const struct itemplate instrux_VCMPNLEPS[7] = {
    /*   0 : VCMPNLEPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 06           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(06) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLEPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27414, 434},
    /*   1 : VCMPNLEPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 06           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(06) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLEPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27423, 434},
    /*   2 : VCMPNLEPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 06           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(06) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLEPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27432, 434},
    /*   3 : VCMPNLEPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 06           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(06) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLEPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27441, 434},
    /*   4 : VCMPNLEPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 06       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(06) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNLEPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+5304, 544},
    /*   5 : VCMPNLEPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 06       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(06) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNLEPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+5315, 544},
    /*   6 : VCMPNLEPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 06       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(06) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNLEPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+5326, 545},
};

static const struct itemplate instrux_VCMPORD_QPS[7] = {
    /*   0 : VCMPORD_QPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 07           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(07) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPORD_QPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27450, 434},
    /*   1 : VCMPORD_QPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 07           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(07) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPORD_QPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27459, 434},
    /*   2 : VCMPORD_QPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 07           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(07) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPORD_QPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27468, 434},
    /*   3 : VCMPORD_QPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 07           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(07) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPORD_QPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27477, 434},
    /*   4 : VCMPORD_QPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 07       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(07) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPORD_QPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+5392, 544},
    /*   5 : VCMPORD_QPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 07       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(07) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPORD_QPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+5403, 544},
    /*   6 : VCMPORD_QPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 07       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(07) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPORD_QPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+5414, 545},
};

static const struct itemplate instrux_VCMPORDPS[7] = {
    /*   0 : VCMPORDPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 07           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(07) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPORDPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27450, 434},
    /*   1 : VCMPORDPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 07           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(07) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPORDPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27459, 434},
    /*   2 : VCMPORDPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 07           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(07) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPORDPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27468, 434},
    /*   3 : VCMPORDPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 07           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(07) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPORDPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27477, 434},
    /*   4 : VCMPORDPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 07       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(07) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPORDPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+5392, 544},
    /*   5 : VCMPORDPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 07       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(07) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPORDPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+5403, 544},
    /*   6 : VCMPORDPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 07       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(07) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPORDPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+5414, 545},
};

static const struct itemplate instrux_VCMPEQ_UQPS[7] = {
    /*   0 : VCMPEQ_UQPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 08           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(08) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_UQPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27486, 434},
    /*   1 : VCMPEQ_UQPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 08           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(08) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_UQPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27495, 434},
    /*   2 : VCMPEQ_UQPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 08           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(08) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_UQPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27504, 434},
    /*   3 : VCMPEQ_UQPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 08           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(08) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_UQPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27513, 434},
    /*   4 : VCMPEQ_UQPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 08       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(08) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPEQ_UQPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+5480, 544},
    /*   5 : VCMPEQ_UQPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 08       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(08) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPEQ_UQPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+5491, 544},
    /*   6 : VCMPEQ_UQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 08       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(08) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPEQ_UQPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+5502, 545},
};

static const struct itemplate instrux_VCMPNGE_USPS[7] = {
    /*   0 : VCMPNGE_USPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 09           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(09) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGE_USPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27522, 434},
    /*   1 : VCMPNGE_USPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 09           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(09) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGE_USPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27531, 434},
    /*   2 : VCMPNGE_USPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 09           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(09) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGE_USPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27540, 434},
    /*   3 : VCMPNGE_USPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 09           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(09) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGE_USPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27549, 434},
    /*   4 : VCMPNGE_USPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 09       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(09) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNGE_USPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+5568, 544},
    /*   5 : VCMPNGE_USPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 09       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(09) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNGE_USPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+5579, 544},
    /*   6 : VCMPNGE_USPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 09       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(09) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNGE_USPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+5590, 545},
};

static const struct itemplate instrux_VCMPNGEPS[7] = {
    /*   0 : VCMPNGEPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 09           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(09) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGEPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27522, 434},
    /*   1 : VCMPNGEPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 09           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(09) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGEPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27531, 434},
    /*   2 : VCMPNGEPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 09           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(09) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGEPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27540, 434},
    /*   3 : VCMPNGEPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 09           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(09) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGEPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27549, 434},
    /*   4 : VCMPNGEPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 09       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(09) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNGEPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+5568, 544},
    /*   5 : VCMPNGEPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 09       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(09) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNGEPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+5579, 544},
    /*   6 : VCMPNGEPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 09       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(09) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNGEPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+5590, 545},
};

static const struct itemplate instrux_VCMPNGT_USPS[7] = {
    /*   0 : VCMPNGT_USPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 0a           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(0a) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGT_USPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27558, 434},
    /*   1 : VCMPNGT_USPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 0a           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(0a) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGT_USPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27567, 434},
    /*   2 : VCMPNGT_USPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 0a           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(0a) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGT_USPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27576, 434},
    /*   3 : VCMPNGT_USPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 0a           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(0a) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGT_USPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27585, 434},
    /*   4 : VCMPNGT_USPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 0a       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(0a) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNGT_USPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+5656, 544},
    /*   5 : VCMPNGT_USPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 0a       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(0a) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNGT_USPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+5667, 544},
    /*   6 : VCMPNGT_USPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 0a       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(0a) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNGT_USPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+5678, 545},
};

static const struct itemplate instrux_VCMPNGTPS[7] = {
    /*   0 : VCMPNGTPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 0a           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(0a) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGTPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27558, 434},
    /*   1 : VCMPNGTPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 0a           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(0a) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGTPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27567, 434},
    /*   2 : VCMPNGTPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 0a           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(0a) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGTPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27576, 434},
    /*   3 : VCMPNGTPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 0a           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(0a) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGTPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27585, 434},
    /*   4 : VCMPNGTPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 0a       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(0a) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNGTPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+5656, 544},
    /*   5 : VCMPNGTPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 0a       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(0a) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNGTPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+5667, 544},
    /*   6 : VCMPNGTPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 0a       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(0a) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNGTPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+5678, 545},
};

static const struct itemplate instrux_VCMPFALSE_OQPS[7] = {
    /*   0 : VCMPFALSE_OQPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 0b           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(0b) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPFALSE_OQPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27594, 434},
    /*   1 : VCMPFALSE_OQPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 0b           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(0b) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPFALSE_OQPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27603, 434},
    /*   2 : VCMPFALSE_OQPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 0b           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(0b) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPFALSE_OQPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27612, 434},
    /*   3 : VCMPFALSE_OQPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 0b           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(0b) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPFALSE_OQPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27621, 434},
    /*   4 : VCMPFALSE_OQPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 0b       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(0b) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPFALSE_OQPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+5744, 544},
    /*   5 : VCMPFALSE_OQPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 0b       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(0b) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPFALSE_OQPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+5755, 544},
    /*   6 : VCMPFALSE_OQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 0b       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(0b) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPFALSE_OQPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+5766, 545},
};

static const struct itemplate instrux_VCMPFALSEPS[7] = {
    /*   0 : VCMPFALSEPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 0b           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(0b) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPFALSEPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27594, 434},
    /*   1 : VCMPFALSEPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 0b           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(0b) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPFALSEPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27603, 434},
    /*   2 : VCMPFALSEPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 0b           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(0b) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPFALSEPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27612, 434},
    /*   3 : VCMPFALSEPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 0b           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(0b) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPFALSEPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27621, 434},
    /*   4 : VCMPFALSEPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 0b       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(0b) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPFALSEPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+5744, 544},
    /*   5 : VCMPFALSEPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 0b       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(0b) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPFALSEPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+5755, 544},
    /*   6 : VCMPFALSEPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 0b       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(0b) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPFALSEPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+5766, 545},
};

static const struct itemplate instrux_VCMPNEQ_OQPS[7] = {
    /*   0 : VCMPNEQ_OQPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 0c           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(0c) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_OQPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27630, 434},
    /*   1 : VCMPNEQ_OQPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 0c           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(0c) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_OQPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27639, 434},
    /*   2 : VCMPNEQ_OQPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 0c           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(0c) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_OQPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27648, 434},
    /*   3 : VCMPNEQ_OQPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 0c           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(0c) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_OQPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27657, 434},
    /*   4 : VCMPNEQ_OQPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 0c       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(0c) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNEQ_OQPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+5832, 544},
    /*   5 : VCMPNEQ_OQPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 0c       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(0c) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNEQ_OQPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+5843, 544},
    /*   6 : VCMPNEQ_OQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 0c       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(0c) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNEQ_OQPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+5854, 545},
};

static const struct itemplate instrux_VCMPGE_OSPS[7] = {
    /*   0 : VCMPGE_OSPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 0d           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(0d) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGE_OSPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27666, 434},
    /*   1 : VCMPGE_OSPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 0d           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(0d) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGE_OSPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27675, 434},
    /*   2 : VCMPGE_OSPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 0d           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(0d) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGE_OSPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27684, 434},
    /*   3 : VCMPGE_OSPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 0d           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(0d) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGE_OSPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27693, 434},
    /*   4 : VCMPGE_OSPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 0d       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(0d) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPGE_OSPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+5920, 544},
    /*   5 : VCMPGE_OSPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 0d       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(0d) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPGE_OSPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+5931, 544},
    /*   6 : VCMPGE_OSPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 0d       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(0d) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPGE_OSPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+5942, 545},
};

static const struct itemplate instrux_VCMPGEPS[7] = {
    /*   0 : VCMPGEPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 0d           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(0d) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGEPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27666, 434},
    /*   1 : VCMPGEPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 0d           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(0d) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGEPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27675, 434},
    /*   2 : VCMPGEPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 0d           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(0d) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGEPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27684, 434},
    /*   3 : VCMPGEPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 0d           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(0d) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGEPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27693, 434},
    /*   4 : VCMPGEPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 0d       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(0d) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPGEPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+5920, 544},
    /*   5 : VCMPGEPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 0d       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(0d) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPGEPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+5931, 544},
    /*   6 : VCMPGEPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 0d       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(0d) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPGEPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+5942, 545},
};

static const struct itemplate instrux_VCMPGT_OSPS[7] = {
    /*   0 : VCMPGT_OSPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 0e           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(0e) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGT_OSPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27702, 434},
    /*   1 : VCMPGT_OSPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 0e           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(0e) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGT_OSPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27711, 434},
    /*   2 : VCMPGT_OSPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 0e           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(0e) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGT_OSPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27720, 434},
    /*   3 : VCMPGT_OSPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 0e           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(0e) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGT_OSPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27729, 434},
    /*   4 : VCMPGT_OSPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 0e       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(0e) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPGT_OSPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+6008, 544},
    /*   5 : VCMPGT_OSPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 0e       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(0e) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPGT_OSPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+6019, 544},
    /*   6 : VCMPGT_OSPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 0e       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(0e) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPGT_OSPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+6030, 545},
};

static const struct itemplate instrux_VCMPGTPS[7] = {
    /*   0 : VCMPGTPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 0e           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(0e) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGTPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27702, 434},
    /*   1 : VCMPGTPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 0e           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(0e) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGTPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27711, 434},
    /*   2 : VCMPGTPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 0e           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(0e) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGTPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27720, 434},
    /*   3 : VCMPGTPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 0e           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(0e) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGTPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27729, 434},
    /*   4 : VCMPGTPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 0e       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(0e) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPGTPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+6008, 544},
    /*   5 : VCMPGTPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 0e       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(0e) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPGTPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+6019, 544},
    /*   6 : VCMPGTPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 0e       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(0e) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPGTPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+6030, 545},
};

static const struct itemplate instrux_VCMPTRUE_UQPS[7] = {
    /*   0 : VCMPTRUE_UQPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 0f           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(0f) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPTRUE_UQPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27738, 434},
    /*   1 : VCMPTRUE_UQPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 0f           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(0f) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPTRUE_UQPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27747, 434},
    /*   2 : VCMPTRUE_UQPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 0f           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(0f) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPTRUE_UQPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27756, 434},
    /*   3 : VCMPTRUE_UQPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 0f           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(0f) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPTRUE_UQPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27765, 434},
    /*   4 : VCMPTRUE_UQPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 0f       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(0f) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPTRUE_UQPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+6096, 544},
    /*   5 : VCMPTRUE_UQPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 0f       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(0f) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPTRUE_UQPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+6107, 544},
    /*   6 : VCMPTRUE_UQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 0f       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(0f) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPTRUE_UQPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+6118, 545},
};

static const struct itemplate instrux_VCMPTRUEPS[7] = {
    /*   0 : VCMPTRUEPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 0f           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(0f) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPTRUEPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27738, 434},
    /*   1 : VCMPTRUEPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 0f           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(0f) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPTRUEPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27747, 434},
    /*   2 : VCMPTRUEPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 0f           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(0f) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPTRUEPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27756, 434},
    /*   3 : VCMPTRUEPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 0f           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(0f) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPTRUEPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27765, 434},
    /*   4 : VCMPTRUEPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 0f       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(0f) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPTRUEPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+6096, 544},
    /*   5 : VCMPTRUEPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 0f       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(0f) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPTRUEPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+6107, 544},
    /*   6 : VCMPTRUEPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 0f       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(0f) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPTRUEPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+6118, 545},
};

static const struct itemplate instrux_VCMPLT_OQPS[7] = {
    /*   0 : VCMPLT_OQPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 11           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(11) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLT_OQPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27774, 434},
    /*   1 : VCMPLT_OQPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 11           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(11) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLT_OQPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27783, 434},
    /*   2 : VCMPLT_OQPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 11           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(11) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLT_OQPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27792, 434},
    /*   3 : VCMPLT_OQPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 11           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(11) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLT_OQPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27801, 434},
    /*   4 : VCMPLT_OQPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 11       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(11) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPLT_OQPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+6272, 544},
    /*   5 : VCMPLT_OQPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 11       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(11) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPLT_OQPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+6283, 544},
    /*   6 : VCMPLT_OQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 11       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(11) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPLT_OQPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+6294, 545},
};

static const struct itemplate instrux_VCMPLE_OQPS[7] = {
    /*   0 : VCMPLE_OQPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 12           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(12) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLE_OQPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27810, 434},
    /*   1 : VCMPLE_OQPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 12           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(12) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLE_OQPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27819, 434},
    /*   2 : VCMPLE_OQPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 12           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(12) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLE_OQPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27828, 434},
    /*   3 : VCMPLE_OQPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 12           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(12) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLE_OQPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27837, 434},
    /*   4 : VCMPLE_OQPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 12       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(12) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPLE_OQPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+6360, 544},
    /*   5 : VCMPLE_OQPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 12       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(12) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPLE_OQPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+6371, 544},
    /*   6 : VCMPLE_OQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 12       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(12) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPLE_OQPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+6382, 545},
};

static const struct itemplate instrux_VCMPUNORD_SPS[7] = {
    /*   0 : VCMPUNORD_SPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 13           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(13) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPUNORD_SPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27846, 434},
    /*   1 : VCMPUNORD_SPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 13           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(13) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPUNORD_SPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27855, 434},
    /*   2 : VCMPUNORD_SPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 13           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(13) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPUNORD_SPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27864, 434},
    /*   3 : VCMPUNORD_SPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 13           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(13) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPUNORD_SPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27873, 434},
    /*   4 : VCMPUNORD_SPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 13       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(13) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPUNORD_SPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+6448, 544},
    /*   5 : VCMPUNORD_SPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 13       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(13) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPUNORD_SPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+6459, 544},
    /*   6 : VCMPUNORD_SPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 13       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(13) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPUNORD_SPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+6470, 545},
};

static const struct itemplate instrux_VCMPNEQ_USPS[7] = {
    /*   0 : VCMPNEQ_USPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 14           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(14) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_USPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27882, 434},
    /*   1 : VCMPNEQ_USPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 14           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(14) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_USPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27891, 434},
    /*   2 : VCMPNEQ_USPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 14           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(14) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_USPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27900, 434},
    /*   3 : VCMPNEQ_USPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 14           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(14) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_USPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27909, 434},
    /*   4 : VCMPNEQ_USPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 14       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(14) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNEQ_USPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+6536, 544},
    /*   5 : VCMPNEQ_USPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 14       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(14) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNEQ_USPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+6547, 544},
    /*   6 : VCMPNEQ_USPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 14       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(14) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNEQ_USPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+6558, 545},
};

static const struct itemplate instrux_VCMPNLT_UQPS[7] = {
    /*   0 : VCMPNLT_UQPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 15           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(15) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLT_UQPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27918, 434},
    /*   1 : VCMPNLT_UQPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 15           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(15) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLT_UQPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27927, 434},
    /*   2 : VCMPNLT_UQPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 15           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(15) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLT_UQPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27936, 434},
    /*   3 : VCMPNLT_UQPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 15           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(15) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLT_UQPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27945, 434},
    /*   4 : VCMPNLT_UQPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 15       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(15) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNLT_UQPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+6624, 544},
    /*   5 : VCMPNLT_UQPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 15       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(15) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNLT_UQPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+6635, 544},
    /*   6 : VCMPNLT_UQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 15       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(15) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNLT_UQPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+6646, 545},
};

static const struct itemplate instrux_VCMPNLE_UQPS[7] = {
    /*   0 : VCMPNLE_UQPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 16           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(16) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLE_UQPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27954, 434},
    /*   1 : VCMPNLE_UQPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 16           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(16) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLE_UQPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27963, 434},
    /*   2 : VCMPNLE_UQPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 16           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(16) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLE_UQPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27972, 434},
    /*   3 : VCMPNLE_UQPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 16           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(16) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLE_UQPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27981, 434},
    /*   4 : VCMPNLE_UQPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 16       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(16) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNLE_UQPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+6712, 544},
    /*   5 : VCMPNLE_UQPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 16       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(16) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNLE_UQPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+6723, 544},
    /*   6 : VCMPNLE_UQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 16       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(16) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNLE_UQPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+6734, 545},
};

static const struct itemplate instrux_VCMPORD_SPS[7] = {
    /*   0 : VCMPORD_SPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 17           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(17) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPORD_SPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+27990, 434},
    /*   1 : VCMPORD_SPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 17           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(17) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPORD_SPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+27999, 434},
    /*   2 : VCMPORD_SPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 17           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(17) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPORD_SPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28008, 434},
    /*   3 : VCMPORD_SPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 17           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(17) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPORD_SPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28017, 434},
    /*   4 : VCMPORD_SPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 17       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(17) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPORD_SPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+6800, 544},
    /*   5 : VCMPORD_SPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 17       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(17) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPORD_SPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+6811, 544},
    /*   6 : VCMPORD_SPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 17       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(17) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPORD_SPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+6822, 545},
};

static const struct itemplate instrux_VCMPEQ_USPS[7] = {
    /*   0 : VCMPEQ_USPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 18           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(18) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_USPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28026, 434},
    /*   1 : VCMPEQ_USPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 18           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(18) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_USPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28035, 434},
    /*   2 : VCMPEQ_USPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 18           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(18) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_USPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28044, 434},
    /*   3 : VCMPEQ_USPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 18           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(18) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_USPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28053, 434},
    /*   4 : VCMPEQ_USPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 18       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(18) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPEQ_USPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+6888, 544},
    /*   5 : VCMPEQ_USPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 18       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(18) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPEQ_USPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+6899, 544},
    /*   6 : VCMPEQ_USPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 18       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(18) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPEQ_USPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+6910, 545},
};

static const struct itemplate instrux_VCMPNGE_UQPS[7] = {
    /*   0 : VCMPNGE_UQPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 19           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(19) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGE_UQPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28062, 434},
    /*   1 : VCMPNGE_UQPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 19           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(19) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGE_UQPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28071, 434},
    /*   2 : VCMPNGE_UQPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 19           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(19) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGE_UQPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28080, 434},
    /*   3 : VCMPNGE_UQPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 19           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(19) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGE_UQPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28089, 434},
    /*   4 : VCMPNGE_UQPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 19       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(19) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNGE_UQPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+6976, 544},
    /*   5 : VCMPNGE_UQPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 19       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(19) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNGE_UQPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+6987, 544},
    /*   6 : VCMPNGE_UQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 19       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(19) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNGE_UQPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+6998, 545},
};

static const struct itemplate instrux_VCMPNGT_UQPS[7] = {
    /*   0 : VCMPNGT_UQPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 1a           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(1a) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGT_UQPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28098, 434},
    /*   1 : VCMPNGT_UQPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 1a           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(1a) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGT_UQPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28107, 434},
    /*   2 : VCMPNGT_UQPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 1a           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(1a) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGT_UQPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28116, 434},
    /*   3 : VCMPNGT_UQPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 1a           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(1a) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGT_UQPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28125, 434},
    /*   4 : VCMPNGT_UQPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 1a       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(1a) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNGT_UQPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+7064, 544},
    /*   5 : VCMPNGT_UQPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 1a       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(1a) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNGT_UQPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+7075, 544},
    /*   6 : VCMPNGT_UQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 1a       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(1a) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNGT_UQPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+7086, 545},
};

static const struct itemplate instrux_VCMPFALSE_OSPS[7] = {
    /*   0 : VCMPFALSE_OSPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 1b           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(1b) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPFALSE_OSPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28134, 434},
    /*   1 : VCMPFALSE_OSPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 1b           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(1b) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPFALSE_OSPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28143, 434},
    /*   2 : VCMPFALSE_OSPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 1b           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(1b) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPFALSE_OSPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28152, 434},
    /*   3 : VCMPFALSE_OSPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 1b           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(1b) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPFALSE_OSPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28161, 434},
    /*   4 : VCMPFALSE_OSPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 1b       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(1b) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPFALSE_OSPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+7152, 544},
    /*   5 : VCMPFALSE_OSPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 1b       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(1b) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPFALSE_OSPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+7163, 544},
    /*   6 : VCMPFALSE_OSPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 1b       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(1b) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPFALSE_OSPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+7174, 545},
};

static const struct itemplate instrux_VCMPNEQ_OSPS[7] = {
    /*   0 : VCMPNEQ_OSPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 1c           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(1c) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_OSPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28170, 434},
    /*   1 : VCMPNEQ_OSPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 1c           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(1c) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_OSPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28179, 434},
    /*   2 : VCMPNEQ_OSPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 1c           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(1c) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_OSPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28188, 434},
    /*   3 : VCMPNEQ_OSPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 1c           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(1c) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_OSPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28197, 434},
    /*   4 : VCMPNEQ_OSPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 1c       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(1c) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNEQ_OSPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+7240, 544},
    /*   5 : VCMPNEQ_OSPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 1c       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(1c) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPNEQ_OSPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+7251, 544},
    /*   6 : VCMPNEQ_OSPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 1c       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(1c) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNEQ_OSPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+7262, 545},
};

static const struct itemplate instrux_VCMPGE_OQPS[7] = {
    /*   0 : VCMPGE_OQPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 1d           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(1d) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGE_OQPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28206, 434},
    /*   1 : VCMPGE_OQPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 1d           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(1d) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGE_OQPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28215, 434},
    /*   2 : VCMPGE_OQPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 1d           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(1d) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGE_OQPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28224, 434},
    /*   3 : VCMPGE_OQPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 1d           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(1d) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGE_OQPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28233, 434},
    /*   4 : VCMPGE_OQPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 1d       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(1d) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPGE_OQPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+7328, 544},
    /*   5 : VCMPGE_OQPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 1d       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(1d) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPGE_OQPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+7339, 544},
    /*   6 : VCMPGE_OQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 1d       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(1d) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPGE_OQPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+7350, 545},
};

static const struct itemplate instrux_VCMPGT_OQPS[7] = {
    /*   0 : VCMPGT_OQPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 1e           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(1e) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGT_OQPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28242, 434},
    /*   1 : VCMPGT_OQPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 1e           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(1e) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGT_OQPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28251, 434},
    /*   2 : VCMPGT_OQPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 1e           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(1e) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGT_OQPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28260, 434},
    /*   3 : VCMPGT_OQPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 1e           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(1e) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGT_OQPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28269, 434},
    /*   4 : VCMPGT_OQPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 1e       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(1e) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPGT_OQPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+7416, 544},
    /*   5 : VCMPGT_OQPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 1e       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(1e) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPGT_OQPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+7427, 544},
    /*   6 : VCMPGT_OQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 1e       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(1e) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPGT_OQPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+7438, 545},
};

static const struct itemplate instrux_VCMPTRUE_USPS[7] = {
    /*   0 : VCMPTRUE_USPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f c2 /r 1f           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 001(1f) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPTRUE_USPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28278, 434},
    /*   1 : VCMPTRUE_USPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f c2 /r 1f           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 001(1f) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPTRUE_USPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28287, 434},
    /*   2 : VCMPTRUE_USPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f c2 /r 1f           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 001(1f) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPTRUE_USPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28296, 434},
    /*   3 : VCMPTRUE_USPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f c2 /r 1f           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 001(1f) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPTRUE_USPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28305, 434},
    /*   4 : VCMPTRUE_USPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 1f       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(1f) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPTRUE_USPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+7504, 544},
    /*   5 : VCMPTRUE_USPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 1f       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(1f) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPTRUE_USPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+7515, 544},
    /*   6 : VCMPTRUE_USPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 1f       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(1f) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPTRUE_USPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+7526, 545},
};

static const struct itemplate instrux_VCMPPS[7] = {
    /*   0 : VCMPPS xmmreg,xmmreg*,xmmrm128,imm8 [rvmi:     vex.nds.128.0f c2 /r ib           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c2) 120 023 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPPS, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+51765, 434},
    /*   1 : VCMPPS xmmreg,xmmrm128,imm8 [r+vmi:     vex.nds.128.0f c2 /r ib           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c2) 110 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPPS, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51773, 434},
    /*   2 : VCMPPS ymmreg,ymmreg*,ymmrm256,imm8 [rvmi:     vex.nds.256.0f c2 /r ib           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c2) 120 023 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPPS, 4, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+51781, 434},
    /*   3 : VCMPPS ymmreg,ymmrm256,imm8 [r+vmi:     vex.nds.256.0f c2 /r ib           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c2) 110 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPPS, 3, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51789, 434},
    /*   4 : VCMPPS kreg|mask,xmmreg,xmmrm128|b32,imm8 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r ib       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 023 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPPS, 4, {OPMASKREG,XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK,0,B32,0,0}, nasm_bytecodes+18283, 544},
    /*   5 : VCMPPS kreg|mask,ymmreg,ymmrm256|b32,imm8 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r ib       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 023 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPPS, 4, {OPMASKREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK,0,B32,0,0}, nasm_bytecodes+18293, 544},
    /*   6 : VCMPPS kreg|mask,zmmreg,zmmrm512|b32|sae,imm8 [rvmi:fv:  evex.nds.512.0f.w0 c2 /r ib       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 023 : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPPS, 4, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+18303, 545},
};

static const struct itemplate instrux_VCMPEQ_OSSD[5] = {
    /*   0 : VCMPEQ_OSSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 10        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(10) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_OSSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28314, 441},
    /*   1 : VCMPEQ_OSSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 10        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(10) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_OSSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28323, 441},
    /*   2 : VCMPEQ_OSSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 10        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(10) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_OSSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28314, 441},
    /*   3 : VCMPEQ_OSSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 10        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(10) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_OSSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28323, 441},
    /*   4 : VCMPEQ_OSSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 10    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(10) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPEQ_OSSD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+6217, 546},
};

static const struct itemplate instrux_VCMPEQSD[3] = {
    /*   0 : VCMPEQSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 00        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(00) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28332, 441},
    /*   1 : VCMPEQSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 00        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(00) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28341, 441},
    /*   2 : VCMPEQSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 00    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(00) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPEQSD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+4809, 546},
};

static const struct itemplate instrux_VCMPLT_OSSD[3] = {
    /*   0 : VCMPLT_OSSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 01        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(01) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLT_OSSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28350, 441},
    /*   1 : VCMPLT_OSSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 01        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(01) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLT_OSSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28359, 441},
    /*   2 : VCMPLT_OSSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 01    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(01) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPLT_OSSD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+4897, 546},
};

static const struct itemplate instrux_VCMPLTSD[3] = {
    /*   0 : VCMPLTSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 01        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(01) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLTSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28350, 441},
    /*   1 : VCMPLTSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 01        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(01) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLTSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28359, 441},
    /*   2 : VCMPLTSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 01    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(01) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPLTSD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+4897, 546},
};

static const struct itemplate instrux_VCMPLE_OSSD[3] = {
    /*   0 : VCMPLE_OSSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 02        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(02) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLE_OSSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28368, 441},
    /*   1 : VCMPLE_OSSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 02        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(02) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLE_OSSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28377, 441},
    /*   2 : VCMPLE_OSSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 02    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(02) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPLE_OSSD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+4985, 546},
};

static const struct itemplate instrux_VCMPLESD[3] = {
    /*   0 : VCMPLESD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 02        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(02) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLESD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28368, 441},
    /*   1 : VCMPLESD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 02        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(02) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLESD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28377, 441},
    /*   2 : VCMPLESD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 02    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(02) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPLESD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+4985, 546},
};

static const struct itemplate instrux_VCMPUNORD_QSD[3] = {
    /*   0 : VCMPUNORD_QSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 03        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(03) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPUNORD_QSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28386, 441},
    /*   1 : VCMPUNORD_QSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 03        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(03) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPUNORD_QSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28395, 441},
    /*   2 : VCMPUNORD_QSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 03    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(03) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPUNORD_QSD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+5073, 546},
};

static const struct itemplate instrux_VCMPUNORDSD[3] = {
    /*   0 : VCMPUNORDSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 03        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(03) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPUNORDSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28386, 441},
    /*   1 : VCMPUNORDSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 03        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(03) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPUNORDSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28395, 441},
    /*   2 : VCMPUNORDSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 03    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(03) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPUNORDSD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+5073, 546},
};

static const struct itemplate instrux_VCMPNEQ_UQSD[3] = {
    /*   0 : VCMPNEQ_UQSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 04        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(04) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_UQSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28404, 441},
    /*   1 : VCMPNEQ_UQSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 04        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(04) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_UQSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28413, 441},
    /*   2 : VCMPNEQ_UQSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 04    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(04) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNEQ_UQSD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+5161, 546},
};

static const struct itemplate instrux_VCMPNEQSD[3] = {
    /*   0 : VCMPNEQSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 04        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(04) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28404, 441},
    /*   1 : VCMPNEQSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 04        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(04) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28413, 441},
    /*   2 : VCMPNEQSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 04    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(04) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNEQSD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+5161, 546},
};

static const struct itemplate instrux_VCMPNLT_USSD[3] = {
    /*   0 : VCMPNLT_USSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 05        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(05) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLT_USSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28422, 441},
    /*   1 : VCMPNLT_USSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 05        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(05) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLT_USSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28431, 441},
    /*   2 : VCMPNLT_USSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 05    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(05) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNLT_USSD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+5249, 546},
};

static const struct itemplate instrux_VCMPNLTSD[3] = {
    /*   0 : VCMPNLTSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 05        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(05) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLTSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28422, 441},
    /*   1 : VCMPNLTSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 05        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(05) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLTSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28431, 441},
    /*   2 : VCMPNLTSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 05    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(05) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNLTSD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+5249, 546},
};

static const struct itemplate instrux_VCMPNLE_USSD[3] = {
    /*   0 : VCMPNLE_USSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 06        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(06) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLE_USSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28440, 441},
    /*   1 : VCMPNLE_USSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 06        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(06) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLE_USSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28449, 441},
    /*   2 : VCMPNLE_USSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 06    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(06) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNLE_USSD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+5337, 546},
};

static const struct itemplate instrux_VCMPNLESD[3] = {
    /*   0 : VCMPNLESD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 06        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(06) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLESD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28440, 441},
    /*   1 : VCMPNLESD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 06        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(06) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLESD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28449, 441},
    /*   2 : VCMPNLESD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 06    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(06) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNLESD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+5337, 546},
};

static const struct itemplate instrux_VCMPORD_QSD[3] = {
    /*   0 : VCMPORD_QSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 07        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(07) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPORD_QSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28458, 441},
    /*   1 : VCMPORD_QSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 07        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(07) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPORD_QSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28467, 441},
    /*   2 : VCMPORD_QSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 07    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(07) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPORD_QSD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+5425, 546},
};

static const struct itemplate instrux_VCMPORDSD[3] = {
    /*   0 : VCMPORDSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 07        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(07) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPORDSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28458, 441},
    /*   1 : VCMPORDSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 07        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(07) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPORDSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28467, 441},
    /*   2 : VCMPORDSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 07    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(07) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPORDSD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+5425, 546},
};

static const struct itemplate instrux_VCMPEQ_UQSD[3] = {
    /*   0 : VCMPEQ_UQSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 08        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(08) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_UQSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28476, 441},
    /*   1 : VCMPEQ_UQSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 08        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(08) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_UQSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28485, 441},
    /*   2 : VCMPEQ_UQSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 08    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(08) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPEQ_UQSD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+5513, 546},
};

static const struct itemplate instrux_VCMPNGE_USSD[3] = {
    /*   0 : VCMPNGE_USSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 09        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(09) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGE_USSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28494, 441},
    /*   1 : VCMPNGE_USSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 09        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(09) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGE_USSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28503, 441},
    /*   2 : VCMPNGE_USSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 09    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(09) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNGE_USSD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+5601, 546},
};

static const struct itemplate instrux_VCMPNGESD[3] = {
    /*   0 : VCMPNGESD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 09        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(09) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGESD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28494, 441},
    /*   1 : VCMPNGESD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 09        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(09) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGESD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28503, 441},
    /*   2 : VCMPNGESD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 09    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(09) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNGESD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+5601, 546},
};

static const struct itemplate instrux_VCMPNGT_USSD[3] = {
    /*   0 : VCMPNGT_USSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 0a        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(0a) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGT_USSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28512, 441},
    /*   1 : VCMPNGT_USSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 0a        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(0a) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGT_USSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28521, 441},
    /*   2 : VCMPNGT_USSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 0a    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(0a) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNGT_USSD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+5689, 546},
};

static const struct itemplate instrux_VCMPNGTSD[3] = {
    /*   0 : VCMPNGTSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 0a        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(0a) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGTSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28512, 441},
    /*   1 : VCMPNGTSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 0a        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(0a) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGTSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28521, 441},
    /*   2 : VCMPNGTSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 0a    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(0a) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNGTSD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+5689, 546},
};

static const struct itemplate instrux_VCMPFALSE_OQSD[3] = {
    /*   0 : VCMPFALSE_OQSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 0b        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(0b) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPFALSE_OQSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28530, 441},
    /*   1 : VCMPFALSE_OQSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 0b        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(0b) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPFALSE_OQSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28539, 441},
    /*   2 : VCMPFALSE_OQSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 0b    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(0b) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPFALSE_OQSD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+5777, 546},
};

static const struct itemplate instrux_VCMPFALSESD[3] = {
    /*   0 : VCMPFALSESD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 0b        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(0b) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPFALSESD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28530, 441},
    /*   1 : VCMPFALSESD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 0b        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(0b) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPFALSESD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28539, 441},
    /*   2 : VCMPFALSESD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 0b    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(0b) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPFALSESD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+5777, 546},
};

static const struct itemplate instrux_VCMPNEQ_OQSD[3] = {
    /*   0 : VCMPNEQ_OQSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 0c        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(0c) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_OQSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28548, 441},
    /*   1 : VCMPNEQ_OQSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 0c        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(0c) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_OQSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28557, 441},
    /*   2 : VCMPNEQ_OQSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 0c    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(0c) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNEQ_OQSD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+5865, 546},
};

static const struct itemplate instrux_VCMPGE_OSSD[3] = {
    /*   0 : VCMPGE_OSSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 0d        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(0d) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGE_OSSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28566, 441},
    /*   1 : VCMPGE_OSSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 0d        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(0d) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGE_OSSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28575, 441},
    /*   2 : VCMPGE_OSSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 0d    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(0d) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPGE_OSSD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+5953, 546},
};

static const struct itemplate instrux_VCMPGESD[3] = {
    /*   0 : VCMPGESD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 0d        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(0d) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGESD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28566, 441},
    /*   1 : VCMPGESD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 0d        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(0d) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGESD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28575, 441},
    /*   2 : VCMPGESD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 0d    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(0d) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPGESD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+5953, 546},
};

static const struct itemplate instrux_VCMPGT_OSSD[3] = {
    /*   0 : VCMPGT_OSSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 0e        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(0e) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGT_OSSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28584, 441},
    /*   1 : VCMPGT_OSSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 0e        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(0e) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGT_OSSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28593, 441},
    /*   2 : VCMPGT_OSSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 0e    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(0e) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPGT_OSSD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+6041, 546},
};

static const struct itemplate instrux_VCMPGTSD[3] = {
    /*   0 : VCMPGTSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 0e        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(0e) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGTSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28584, 441},
    /*   1 : VCMPGTSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 0e        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(0e) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGTSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28593, 441},
    /*   2 : VCMPGTSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 0e    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(0e) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPGTSD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+6041, 546},
};

static const struct itemplate instrux_VCMPTRUE_UQSD[3] = {
    /*   0 : VCMPTRUE_UQSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 0f        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(0f) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPTRUE_UQSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28602, 441},
    /*   1 : VCMPTRUE_UQSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 0f        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(0f) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPTRUE_UQSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28611, 441},
    /*   2 : VCMPTRUE_UQSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 0f    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(0f) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPTRUE_UQSD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+6129, 546},
};

static const struct itemplate instrux_VCMPTRUESD[3] = {
    /*   0 : VCMPTRUESD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 0f        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(0f) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPTRUESD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28602, 441},
    /*   1 : VCMPTRUESD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 0f        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(0f) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPTRUESD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28611, 441},
    /*   2 : VCMPTRUESD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 0f    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(0f) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPTRUESD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+6129, 546},
};

static const struct itemplate instrux_VCMPLT_OQSD[3] = {
    /*   0 : VCMPLT_OQSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 11        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(11) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLT_OQSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28620, 441},
    /*   1 : VCMPLT_OQSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 11        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(11) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLT_OQSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28629, 441},
    /*   2 : VCMPLT_OQSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 11    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(11) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPLT_OQSD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+6305, 546},
};

static const struct itemplate instrux_VCMPLE_OQSD[3] = {
    /*   0 : VCMPLE_OQSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 12        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(12) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLE_OQSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28638, 441},
    /*   1 : VCMPLE_OQSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 12        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(12) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLE_OQSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28647, 441},
    /*   2 : VCMPLE_OQSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 12    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(12) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPLE_OQSD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+6393, 546},
};

static const struct itemplate instrux_VCMPUNORD_SSD[3] = {
    /*   0 : VCMPUNORD_SSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 13        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(13) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPUNORD_SSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28656, 441},
    /*   1 : VCMPUNORD_SSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 13        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(13) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPUNORD_SSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28665, 441},
    /*   2 : VCMPUNORD_SSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 13    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(13) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPUNORD_SSD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+6481, 546},
};

static const struct itemplate instrux_VCMPNEQ_USSD[3] = {
    /*   0 : VCMPNEQ_USSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 14        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(14) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_USSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28674, 441},
    /*   1 : VCMPNEQ_USSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 14        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(14) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_USSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28683, 441},
    /*   2 : VCMPNEQ_USSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 14    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(14) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNEQ_USSD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+6569, 546},
};

static const struct itemplate instrux_VCMPNLT_UQSD[3] = {
    /*   0 : VCMPNLT_UQSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 15        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(15) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLT_UQSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28692, 441},
    /*   1 : VCMPNLT_UQSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 15        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(15) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLT_UQSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28701, 441},
    /*   2 : VCMPNLT_UQSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 15    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(15) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNLT_UQSD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+6657, 546},
};

static const struct itemplate instrux_VCMPNLE_UQSD[3] = {
    /*   0 : VCMPNLE_UQSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 16        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(16) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLE_UQSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28710, 441},
    /*   1 : VCMPNLE_UQSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 16        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(16) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLE_UQSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28719, 441},
    /*   2 : VCMPNLE_UQSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 16    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(16) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNLE_UQSD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+6745, 546},
};

static const struct itemplate instrux_VCMPORD_SSD[3] = {
    /*   0 : VCMPORD_SSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 17        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(17) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPORD_SSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28728, 441},
    /*   1 : VCMPORD_SSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 17        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(17) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPORD_SSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28737, 441},
    /*   2 : VCMPORD_SSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 17    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(17) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPORD_SSD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+6833, 546},
};

static const struct itemplate instrux_VCMPEQ_USSD[3] = {
    /*   0 : VCMPEQ_USSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 18        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(18) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_USSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28746, 441},
    /*   1 : VCMPEQ_USSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 18        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(18) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_USSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28755, 441},
    /*   2 : VCMPEQ_USSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 18    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(18) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPEQ_USSD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+6921, 546},
};

static const struct itemplate instrux_VCMPNGE_UQSD[3] = {
    /*   0 : VCMPNGE_UQSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 19        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(19) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGE_UQSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28764, 441},
    /*   1 : VCMPNGE_UQSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 19        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(19) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGE_UQSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28773, 441},
    /*   2 : VCMPNGE_UQSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 19    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(19) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNGE_UQSD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+7009, 546},
};

static const struct itemplate instrux_VCMPNGT_UQSD[3] = {
    /*   0 : VCMPNGT_UQSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 1a        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(1a) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGT_UQSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28782, 441},
    /*   1 : VCMPNGT_UQSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 1a        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(1a) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGT_UQSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28791, 441},
    /*   2 : VCMPNGT_UQSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 1a    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(1a) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNGT_UQSD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+7097, 546},
};

static const struct itemplate instrux_VCMPFALSE_OSSD[3] = {
    /*   0 : VCMPFALSE_OSSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 1b        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(1b) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPFALSE_OSSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28800, 441},
    /*   1 : VCMPFALSE_OSSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 1b        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(1b) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPFALSE_OSSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28809, 441},
    /*   2 : VCMPFALSE_OSSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 1b    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(1b) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPFALSE_OSSD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+7185, 546},
};

static const struct itemplate instrux_VCMPNEQ_OSSD[3] = {
    /*   0 : VCMPNEQ_OSSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 1c        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(1c) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_OSSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28818, 441},
    /*   1 : VCMPNEQ_OSSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 1c        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(1c) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_OSSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28827, 441},
    /*   2 : VCMPNEQ_OSSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 1c    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(1c) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNEQ_OSSD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+7273, 546},
};

static const struct itemplate instrux_VCMPGE_OQSD[3] = {
    /*   0 : VCMPGE_OQSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 1d        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(1d) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGE_OQSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28836, 441},
    /*   1 : VCMPGE_OQSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 1d        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(1d) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGE_OQSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28845, 441},
    /*   2 : VCMPGE_OQSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 1d    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(1d) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPGE_OQSD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+7361, 546},
};

static const struct itemplate instrux_VCMPGT_OQSD[3] = {
    /*   0 : VCMPGT_OQSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 1e        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(1e) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGT_OQSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28854, 441},
    /*   1 : VCMPGT_OQSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 1e        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(1e) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGT_OQSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28863, 441},
    /*   2 : VCMPGT_OQSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 1e    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(1e) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPGT_OQSD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+7449, 546},
};

static const struct itemplate instrux_VCMPTRUE_USSD[3] = {
    /*   0 : VCMPTRUE_USSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f c2 /r 1f        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 001(1f) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPTRUE_USSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28872, 441},
    /*   1 : VCMPTRUE_USSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f c2 /r 1f        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 001(1f) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPTRUE_USSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28881, 441},
    /*   2 : VCMPTRUE_USSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 1f    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(1f) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPTRUE_USSD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+7537, 546},
};

static const struct itemplate instrux_VCMPSD[3] = {
    /*   0 : VCMPSD xmmreg,xmmreg*,xmmrm64,imm8 [rvmi:     vex.nds.lig.f2.0f c2 /r ib        ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(c2) 120 023 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPSD, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+51797, 441},
    /*   1 : VCMPSD xmmreg,xmmrm64,imm8 [r+vmi:     vex.nds.lig.f2.0f c2 /r ib        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(c2) 110 022 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPSD, 3, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51805, 441},
    /*   2 : VCMPSD kreg|mask,xmmreg,xmmrm64|sae,imm8 [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r ib    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 023 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPSD, 4, {OPMASKREG,XMMREG,RM_XMM|BITS64,IMM_NORMAL|BITS8,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+18313, 546},
};

static const struct itemplate instrux_VCMPEQ_OSSS[5] = {
    /*   0 : VCMPEQ_OSSS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 10        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(10) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_OSSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28890, 441},
    /*   1 : VCMPEQ_OSSS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 10        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(10) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_OSSS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28899, 441},
    /*   2 : VCMPEQ_OSSS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 10        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(10) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_OSSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28890, 441},
    /*   3 : VCMPEQ_OSSS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 10        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(10) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_OSSS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28899, 441},
    /*   4 : VCMPEQ_OSSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 10    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(10) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPEQ_OSSS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+6228, 546},
};

static const struct itemplate instrux_VCMPEQSS[3] = {
    /*   0 : VCMPEQSS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 00        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(00) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28908, 441},
    /*   1 : VCMPEQSS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 00        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(00) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQSS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28917, 441},
    /*   2 : VCMPEQSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 00    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(00) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPEQSS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+4820, 546},
};

static const struct itemplate instrux_VCMPLT_OSSS[3] = {
    /*   0 : VCMPLT_OSSS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 01        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(01) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLT_OSSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28926, 441},
    /*   1 : VCMPLT_OSSS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 01        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(01) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLT_OSSS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28935, 441},
    /*   2 : VCMPLT_OSSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 01    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(01) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPLT_OSSS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+4908, 546},
};

static const struct itemplate instrux_VCMPLTSS[3] = {
    /*   0 : VCMPLTSS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 01        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(01) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLTSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28926, 441},
    /*   1 : VCMPLTSS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 01        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(01) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLTSS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28935, 441},
    /*   2 : VCMPLTSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 01    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(01) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPLTSS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+4908, 546},
};

static const struct itemplate instrux_VCMPLE_OSSS[3] = {
    /*   0 : VCMPLE_OSSS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 02        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(02) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLE_OSSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28944, 441},
    /*   1 : VCMPLE_OSSS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 02        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(02) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLE_OSSS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28953, 441},
    /*   2 : VCMPLE_OSSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 02    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(02) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPLE_OSSS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+4996, 546},
};

static const struct itemplate instrux_VCMPLESS[3] = {
    /*   0 : VCMPLESS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 02        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(02) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLESS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28944, 441},
    /*   1 : VCMPLESS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 02        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(02) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLESS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28953, 441},
    /*   2 : VCMPLESS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 02    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(02) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPLESS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+4996, 546},
};

static const struct itemplate instrux_VCMPUNORD_QSS[3] = {
    /*   0 : VCMPUNORD_QSS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 03        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(03) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPUNORD_QSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28962, 441},
    /*   1 : VCMPUNORD_QSS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 03        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(03) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPUNORD_QSS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28971, 441},
    /*   2 : VCMPUNORD_QSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 03    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(03) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPUNORD_QSS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+5084, 546},
};

static const struct itemplate instrux_VCMPUNORDSS[3] = {
    /*   0 : VCMPUNORDSS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 03        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(03) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPUNORDSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28962, 441},
    /*   1 : VCMPUNORDSS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 03        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(03) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPUNORDSS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28971, 441},
    /*   2 : VCMPUNORDSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 03    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(03) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPUNORDSS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+5084, 546},
};

static const struct itemplate instrux_VCMPNEQ_UQSS[3] = {
    /*   0 : VCMPNEQ_UQSS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 04        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(04) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_UQSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28980, 441},
    /*   1 : VCMPNEQ_UQSS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 04        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(04) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_UQSS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28989, 441},
    /*   2 : VCMPNEQ_UQSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 04    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(04) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNEQ_UQSS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+5172, 546},
};

static const struct itemplate instrux_VCMPNEQSS[3] = {
    /*   0 : VCMPNEQSS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 04        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(04) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28980, 441},
    /*   1 : VCMPNEQSS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 04        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(04) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQSS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+28989, 441},
    /*   2 : VCMPNEQSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 04    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(04) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNEQSS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+5172, 546},
};

static const struct itemplate instrux_VCMPNLT_USSS[3] = {
    /*   0 : VCMPNLT_USSS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 05        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(05) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLT_USSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28998, 441},
    /*   1 : VCMPNLT_USSS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 05        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(05) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLT_USSS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29007, 441},
    /*   2 : VCMPNLT_USSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 05    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(05) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNLT_USSS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+5260, 546},
};

static const struct itemplate instrux_VCMPNLTSS[3] = {
    /*   0 : VCMPNLTSS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 05        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(05) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLTSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+28998, 441},
    /*   1 : VCMPNLTSS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 05        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(05) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLTSS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29007, 441},
    /*   2 : VCMPNLTSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 05    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(05) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNLTSS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+5260, 546},
};

static const struct itemplate instrux_VCMPNLE_USSS[3] = {
    /*   0 : VCMPNLE_USSS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 06        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(06) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLE_USSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+29016, 441},
    /*   1 : VCMPNLE_USSS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 06        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(06) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLE_USSS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29025, 441},
    /*   2 : VCMPNLE_USSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 06    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(06) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNLE_USSS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+5348, 546},
};

static const struct itemplate instrux_VCMPNLESS[3] = {
    /*   0 : VCMPNLESS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 06        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(06) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLESS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+29016, 441},
    /*   1 : VCMPNLESS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 06        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(06) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLESS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29025, 441},
    /*   2 : VCMPNLESS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 06    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(06) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNLESS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+5348, 546},
};

static const struct itemplate instrux_VCMPORD_QSS[3] = {
    /*   0 : VCMPORD_QSS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 07        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(07) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPORD_QSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+29034, 441},
    /*   1 : VCMPORD_QSS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 07        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(07) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPORD_QSS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29043, 441},
    /*   2 : VCMPORD_QSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 07    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(07) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPORD_QSS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+5436, 546},
};

static const struct itemplate instrux_VCMPORDSS[3] = {
    /*   0 : VCMPORDSS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 07        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(07) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPORDSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+29034, 441},
    /*   1 : VCMPORDSS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 07        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(07) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPORDSS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29043, 441},
    /*   2 : VCMPORDSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 07    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(07) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPORDSS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+5436, 546},
};

static const struct itemplate instrux_VCMPEQ_UQSS[3] = {
    /*   0 : VCMPEQ_UQSS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 08        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(08) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_UQSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+29052, 441},
    /*   1 : VCMPEQ_UQSS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 08        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(08) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_UQSS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29061, 441},
    /*   2 : VCMPEQ_UQSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 08    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(08) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPEQ_UQSS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+5524, 546},
};

static const struct itemplate instrux_VCMPNGE_USSS[3] = {
    /*   0 : VCMPNGE_USSS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 09        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(09) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGE_USSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+29070, 441},
    /*   1 : VCMPNGE_USSS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 09        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(09) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGE_USSS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29079, 441},
    /*   2 : VCMPNGE_USSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 09    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(09) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNGE_USSS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+5612, 546},
};

static const struct itemplate instrux_VCMPNGESS[3] = {
    /*   0 : VCMPNGESS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 09        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(09) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGESS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+29070, 441},
    /*   1 : VCMPNGESS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 09        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(09) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGESS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29079, 441},
    /*   2 : VCMPNGESS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 09    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(09) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNGESS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+5612, 546},
};

static const struct itemplate instrux_VCMPNGT_USSS[3] = {
    /*   0 : VCMPNGT_USSS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 0a        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(0a) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGT_USSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+29088, 441},
    /*   1 : VCMPNGT_USSS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 0a        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(0a) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGT_USSS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29097, 441},
    /*   2 : VCMPNGT_USSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 0a    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(0a) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNGT_USSS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+5700, 546},
};

static const struct itemplate instrux_VCMPNGTSS[3] = {
    /*   0 : VCMPNGTSS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 0a        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(0a) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGTSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+29088, 441},
    /*   1 : VCMPNGTSS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 0a        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(0a) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGTSS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29097, 441},
    /*   2 : VCMPNGTSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 0a    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(0a) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNGTSS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+5700, 546},
};

static const struct itemplate instrux_VCMPFALSE_OQSS[3] = {
    /*   0 : VCMPFALSE_OQSS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 0b        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(0b) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPFALSE_OQSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+29106, 441},
    /*   1 : VCMPFALSE_OQSS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 0b        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(0b) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPFALSE_OQSS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29115, 441},
    /*   2 : VCMPFALSE_OQSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 0b    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(0b) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPFALSE_OQSS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+5788, 546},
};

static const struct itemplate instrux_VCMPFALSESS[3] = {
    /*   0 : VCMPFALSESS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 0b        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(0b) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPFALSESS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+29106, 441},
    /*   1 : VCMPFALSESS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 0b        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(0b) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPFALSESS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29115, 441},
    /*   2 : VCMPFALSESS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 0b    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(0b) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPFALSESS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+5788, 546},
};

static const struct itemplate instrux_VCMPNEQ_OQSS[3] = {
    /*   0 : VCMPNEQ_OQSS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 0c        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(0c) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_OQSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+29124, 441},
    /*   1 : VCMPNEQ_OQSS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 0c        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(0c) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_OQSS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29133, 441},
    /*   2 : VCMPNEQ_OQSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 0c    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(0c) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNEQ_OQSS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+5876, 546},
};

static const struct itemplate instrux_VCMPGE_OSSS[3] = {
    /*   0 : VCMPGE_OSSS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 0d        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(0d) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGE_OSSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+29142, 441},
    /*   1 : VCMPGE_OSSS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 0d        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(0d) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGE_OSSS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29151, 441},
    /*   2 : VCMPGE_OSSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 0d    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(0d) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPGE_OSSS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+5964, 546},
};

static const struct itemplate instrux_VCMPGESS[3] = {
    /*   0 : VCMPGESS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 0d        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(0d) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGESS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+29142, 441},
    /*   1 : VCMPGESS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 0d        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(0d) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGESS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29151, 441},
    /*   2 : VCMPGESS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 0d    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(0d) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPGESS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+5964, 546},
};

static const struct itemplate instrux_VCMPGT_OSSS[3] = {
    /*   0 : VCMPGT_OSSS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 0e        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(0e) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGT_OSSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+29160, 441},
    /*   1 : VCMPGT_OSSS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 0e        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(0e) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGT_OSSS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29169, 441},
    /*   2 : VCMPGT_OSSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 0e    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(0e) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPGT_OSSS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+6052, 546},
};

static const struct itemplate instrux_VCMPGTSS[3] = {
    /*   0 : VCMPGTSS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 0e        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(0e) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGTSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+29160, 441},
    /*   1 : VCMPGTSS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 0e        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(0e) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGTSS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29169, 441},
    /*   2 : VCMPGTSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 0e    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(0e) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPGTSS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+6052, 546},
};

static const struct itemplate instrux_VCMPTRUE_UQSS[3] = {
    /*   0 : VCMPTRUE_UQSS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 0f        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(0f) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPTRUE_UQSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+29178, 441},
    /*   1 : VCMPTRUE_UQSS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 0f        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(0f) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPTRUE_UQSS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29187, 441},
    /*   2 : VCMPTRUE_UQSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 0f    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(0f) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPTRUE_UQSS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+6140, 546},
};

static const struct itemplate instrux_VCMPTRUESS[3] = {
    /*   0 : VCMPTRUESS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 0f        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(0f) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPTRUESS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+29178, 441},
    /*   1 : VCMPTRUESS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 0f        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(0f) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPTRUESS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29187, 441},
    /*   2 : VCMPTRUESS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 0f    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(0f) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPTRUESS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+6140, 546},
};

static const struct itemplate instrux_VCMPLT_OQSS[3] = {
    /*   0 : VCMPLT_OQSS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 11        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(11) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLT_OQSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+29196, 441},
    /*   1 : VCMPLT_OQSS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 11        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(11) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLT_OQSS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29205, 441},
    /*   2 : VCMPLT_OQSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 11    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(11) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPLT_OQSS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+6316, 546},
};

static const struct itemplate instrux_VCMPLE_OQSS[3] = {
    /*   0 : VCMPLE_OQSS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 12        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(12) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLE_OQSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+29214, 441},
    /*   1 : VCMPLE_OQSS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 12        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(12) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPLE_OQSS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29223, 441},
    /*   2 : VCMPLE_OQSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 12    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(12) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPLE_OQSS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+6404, 546},
};

static const struct itemplate instrux_VCMPUNORD_SSS[3] = {
    /*   0 : VCMPUNORD_SSS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 13        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(13) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPUNORD_SSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+29232, 441},
    /*   1 : VCMPUNORD_SSS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 13        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(13) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPUNORD_SSS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29241, 441},
    /*   2 : VCMPUNORD_SSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 13    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(13) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPUNORD_SSS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+6492, 546},
};

static const struct itemplate instrux_VCMPNEQ_USSS[3] = {
    /*   0 : VCMPNEQ_USSS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 14        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(14) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_USSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+29250, 441},
    /*   1 : VCMPNEQ_USSS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 14        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(14) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_USSS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29259, 441},
    /*   2 : VCMPNEQ_USSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 14    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(14) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNEQ_USSS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+6580, 546},
};

static const struct itemplate instrux_VCMPNLT_UQSS[3] = {
    /*   0 : VCMPNLT_UQSS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 15        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(15) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLT_UQSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+29268, 441},
    /*   1 : VCMPNLT_UQSS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 15        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(15) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLT_UQSS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29277, 441},
    /*   2 : VCMPNLT_UQSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 15    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(15) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNLT_UQSS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+6668, 546},
};

static const struct itemplate instrux_VCMPNLE_UQSS[3] = {
    /*   0 : VCMPNLE_UQSS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 16        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(16) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLE_UQSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+29286, 441},
    /*   1 : VCMPNLE_UQSS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 16        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(16) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNLE_UQSS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29295, 441},
    /*   2 : VCMPNLE_UQSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 16    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(16) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNLE_UQSS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+6756, 546},
};

static const struct itemplate instrux_VCMPORD_SSS[3] = {
    /*   0 : VCMPORD_SSS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 17        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(17) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPORD_SSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+29304, 441},
    /*   1 : VCMPORD_SSS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 17        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(17) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPORD_SSS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29313, 441},
    /*   2 : VCMPORD_SSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 17    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(17) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPORD_SSS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+6844, 546},
};

static const struct itemplate instrux_VCMPEQ_USSS[3] = {
    /*   0 : VCMPEQ_USSS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 18        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(18) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_USSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+29322, 441},
    /*   1 : VCMPEQ_USSS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 18        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(18) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPEQ_USSS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29331, 441},
    /*   2 : VCMPEQ_USSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 18    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(18) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPEQ_USSS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+6932, 546},
};

static const struct itemplate instrux_VCMPNGE_UQSS[3] = {
    /*   0 : VCMPNGE_UQSS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 19        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(19) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGE_UQSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+29340, 441},
    /*   1 : VCMPNGE_UQSS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 19        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(19) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGE_UQSS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29349, 441},
    /*   2 : VCMPNGE_UQSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 19    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(19) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNGE_UQSS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+7020, 546},
};

static const struct itemplate instrux_VCMPNGT_UQSS[3] = {
    /*   0 : VCMPNGT_UQSS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 1a        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(1a) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGT_UQSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+29358, 441},
    /*   1 : VCMPNGT_UQSS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 1a        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(1a) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNGT_UQSS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29367, 441},
    /*   2 : VCMPNGT_UQSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 1a    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(1a) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNGT_UQSS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+7108, 546},
};

static const struct itemplate instrux_VCMPFALSE_OSSS[3] = {
    /*   0 : VCMPFALSE_OSSS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 1b        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(1b) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPFALSE_OSSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+29376, 441},
    /*   1 : VCMPFALSE_OSSS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 1b        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(1b) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPFALSE_OSSS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29385, 441},
    /*   2 : VCMPFALSE_OSSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 1b    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(1b) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPFALSE_OSSS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+7196, 546},
};

static const struct itemplate instrux_VCMPNEQ_OSSS[3] = {
    /*   0 : VCMPNEQ_OSSS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 1c        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(1c) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_OSSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+29394, 441},
    /*   1 : VCMPNEQ_OSSS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 1c        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(1c) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPNEQ_OSSS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29403, 441},
    /*   2 : VCMPNEQ_OSSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 1c    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(1c) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPNEQ_OSSS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+7284, 546},
};

static const struct itemplate instrux_VCMPGE_OQSS[3] = {
    /*   0 : VCMPGE_OQSS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 1d        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(1d) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGE_OQSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+29412, 441},
    /*   1 : VCMPGE_OQSS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 1d        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(1d) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGE_OQSS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29421, 441},
    /*   2 : VCMPGE_OQSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 1d    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(1d) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPGE_OQSS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+7372, 546},
};

static const struct itemplate instrux_VCMPGT_OQSS[3] = {
    /*   0 : VCMPGT_OQSS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 1e        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(1e) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGT_OQSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+29430, 441},
    /*   1 : VCMPGT_OQSS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 1e        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(1e) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPGT_OQSS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29439, 441},
    /*   2 : VCMPGT_OQSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 1e    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(1e) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPGT_OQSS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+7460, 546},
};

static const struct itemplate instrux_VCMPTRUE_USSS[3] = {
    /*   0 : VCMPTRUE_USSS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f3.0f c2 /r 1f        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 001(1f) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPTRUE_USSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+29448, 441},
    /*   1 : VCMPTRUE_USSS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f3.0f c2 /r 1f        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 001(1f) : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPTRUE_USSS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29457, 441},
    /*   2 : VCMPTRUE_USSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 1f    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(1f) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPTRUE_USSS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+7548, 546},
};

static const struct itemplate instrux_VCMPSS[3] = {
    /*   0 : VCMPSS xmmreg,xmmreg*,xmmrm64,imm8 [rvmi:     vex.nds.lig.f3.0f c2 /r ib        ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(c2) 120 023 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPSS, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+51813, 441},
    /*   1 : VCMPSS xmmreg,xmmrm64,imm8 [r+vmi:     vex.nds.lig.f3.0f c2 /r ib        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(c2) 110 022 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCMPSS, 3, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51821, 441},
    /*   2 : VCMPSS kreg|mask,xmmreg,xmmrm32|sae,imm8 [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r ib    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 023 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPSS, 4, {OPMASKREG,XMMREG,RM_XMM|BITS32,IMM_NORMAL|BITS8,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+18323, 546},
};

static const struct itemplate instrux_VCOMISD[2] = {
    /*   0 : VCOMISD xmmreg,xmmrm64 [rm:       vex.lig.66.0f 2f /r               ] FL,AVX,SANDYBRIDGE */
        /* 270(001 001) 001(2f) 110 : NOAPX,LIG,WIG,FL,VEX,AVX,SANDYBRIDGE */
        {I_VCOMISD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58629, 443},
    /*   1 : VCOMISD xmmreg,xmmrm64|sae [rm:t1s:   evex.lig.66.0f.w1 2f /r           ] FL,AVX512,FUTURE */
        /* 250(f1 fd 08) 306 001(2f) 110 : LIG,FL,EVEX,PROT,AVX512,FUTURE */
        {I_VCOMISD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+31095, 549},
};

static const struct itemplate instrux_VCOMISS[2] = {
    /*   0 : VCOMISS xmmreg,xmmrm32 [rm:       vex.lig.0f 2f /r                  ] FL,AVX,SANDYBRIDGE */
        /* 270(001 000) 001(2f) 110 : NOAPX,LIG,WIG,FL,VEX,AVX,SANDYBRIDGE */
        {I_VCOMISS, 2, {XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58636, 443},
    /*   1 : VCOMISS xmmreg,xmmrm32|sae [rm:t1s:   evex.lig.0f.w0 2f /r              ] FL,AVX512,FUTURE */
        /* 250(f1 7c 08) 306 001(2f) 110 : LIG,FL,EVEX,PROT,AVX512,FUTURE */
        {I_VCOMISS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+31104, 549},
};

static const struct itemplate instrux_VCVTDQ2PD[5] = {
    /*   0 : VCVTDQ2PD xmmreg,xmmrm64 [rm:       vex.128.f3.0f e6 /r               ] AVX,SANDYBRIDGE */
        /* 270(001 002) 001(e6) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCVTDQ2PD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58643, 434},
    /*   1 : VCVTDQ2PD ymmreg,xmmrm128 [rm:       vex.256.f3.0f e6 /r               ] AVX,SANDYBRIDGE */
        /* 270(001 006) 001(e6) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCVTDQ2PD, 2, {YMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58650, 434},
    /*   2 : VCVTDQ2PD xmmreg|mask|z,xmmrm64|b32 [rm:hv:    evex.128.f3.0f.w0 e6 /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7e 08) 302 001(e6) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCVTDQ2PD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+31221, 544},
    /*   3 : VCVTDQ2PD ymmreg|mask|z,xmmrm128|b32 [rm:hv:    evex.256.f3.0f.w0 e6 /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7e 28) 302 001(e6) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCVTDQ2PD, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+31230, 544},
    /*   4 : VCVTDQ2PD zmmreg|mask|z,ymmrm256|b32|er [rm:hv:    evex.512.f3.0f.w0 e6 /r           ] AVX512,FUTURE */
        /* 250(f1 7e 48) 302 001(e6) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VCVTDQ2PD, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+31239, 545},
};

static const struct itemplate instrux_VCVTDQ2PS[5] = {
    /*   0 : VCVTDQ2PS xmmreg,xmmrm128 [rm:       vex.128.0f 5b /r                  ] AVX,SANDYBRIDGE */
        /* 270(001 000) 001(5b) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCVTDQ2PS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58657, 434},
    /*   1 : VCVTDQ2PS ymmreg,ymmrm256 [rm:       vex.256.0f 5b /r                  ] AVX,SANDYBRIDGE */
        /* 270(001 004) 001(5b) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCVTDQ2PS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58664, 434},
    /*   2 : VCVTDQ2PS xmmreg|mask|z,xmmrm128|b32 [rm:fv:    evex.128.0f.w0 5b /r              ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7c 08) 301 001(5b) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCVTDQ2PS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+31248, 544},
    /*   3 : VCVTDQ2PS ymmreg|mask|z,ymmrm256|b32 [rm:fv:    evex.256.0f.w0 5b /r              ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7c 28) 301 001(5b) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCVTDQ2PS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+31257, 544},
    /*   4 : VCVTDQ2PS zmmreg|mask|z,zmmrm512|b32|er [rm:fv:    evex.512.0f.w0 5b /r              ] AVX512,FUTURE */
        /* 250(f1 7c 48) 301 001(5b) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VCVTDQ2PS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+31266, 545},
};

static const struct itemplate instrux_VCVTPD2DQ[7] = {
    /*   0 : VCVTPD2DQ xmmreg,xmmreg [rm:       vex.128.f2.0f e6 /r               ] AVX,SANDYBRIDGE */
        /* 270(001 003) 001(e6) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCVTPD2DQ, 2, {XMMREG|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58671, 434},
    /*   1 : VCVTPD2DQ xmmreg,mem128 [rm:       vex.128.f2.0f e6 /r               ] AR0-1,SO,AVX,SANDYBRIDGE */
        /* 270(001 003) 001(e6) 110 : AR0,AR1,SO,NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCVTPD2DQ, 2, {XMMREG|RN_L16,MEMORY|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58671, 444},
    /*   2 : VCVTPD2DQ xmmreg,ymmreg [rm:       vex.256.f2.0f e6 /r               ] AVX,SANDYBRIDGE */
        /* 270(001 007) 001(e6) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCVTPD2DQ, 2, {XMMREG|RN_L16,YMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58678, 434},
    /*   3 : VCVTPD2DQ xmmreg,mem256 [rm:       vex.256.f2.0f e6 /r               ] AR0-1,SY,AVX,SANDYBRIDGE */
        /* 270(001 007) 001(e6) 110 : AR0,AR1,SY,NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCVTPD2DQ, 2, {XMMREG|RN_L16,MEMORY|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58678, 445},
    /*   4 : VCVTPD2DQ xmmreg|mask|z,xmmrm128|b64 [rm:fv:    evex.128.f2.0f.w1 e6 /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 ff 08) 301 001(e6) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCVTPD2DQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+31275, 544},
    /*   5 : VCVTPD2DQ xmmreg|mask|z,ymmrm256|b64 [rm:fv:    evex.256.f2.0f.w1 e6 /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 ff 28) 301 001(e6) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCVTPD2DQ, 2, {XMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+31284, 544},
    /*   6 : VCVTPD2DQ ymmreg|mask|z,zmmrm512|b64|er [rm:fv:    evex.512.f2.0f.w1 e6 /r           ] AVX512,FUTURE */
        /* 250(f1 ff 48) 301 001(e6) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VCVTPD2DQ, 2, {YMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+31293, 545},
};

static const struct itemplate instrux_VCVTPD2PS[7] = {
    /*   0 : VCVTPD2PS xmmreg,xmmreg [rm:       vex.128.66.0f 5a /r               ] AVX,SANDYBRIDGE */
        /* 270(001 001) 001(5a) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCVTPD2PS, 2, {XMMREG|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58685, 434},
    /*   1 : VCVTPD2PS xmmreg,mem128 [rm:       vex.128.66.0f 5a /r               ] AR0-1,SO,AVX,SANDYBRIDGE */
        /* 270(001 001) 001(5a) 110 : AR0,AR1,SO,NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCVTPD2PS, 2, {XMMREG|RN_L16,MEMORY|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58685, 444},
    /*   2 : VCVTPD2PS xmmreg,ymmreg [rm:       vex.256.66.0f 5a /r               ] AVX,SANDYBRIDGE */
        /* 270(001 005) 001(5a) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCVTPD2PS, 2, {XMMREG|RN_L16,YMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58692, 434},
    /*   3 : VCVTPD2PS xmmreg,mem256 [rm:       vex.256.66.0f 5a /r               ] AR0-1,SY,AVX,SANDYBRIDGE */
        /* 270(001 005) 001(5a) 110 : AR0,AR1,SY,NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCVTPD2PS, 2, {XMMREG|RN_L16,MEMORY|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58692, 445},
    /*   4 : VCVTPD2PS xmmreg|mask|z,xmmrm128|b64 [rm:fv:    evex.128.66.0f.w1 5a /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 fd 08) 301 001(5a) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCVTPD2PS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+31302, 544},
    /*   5 : VCVTPD2PS xmmreg|mask|z,ymmrm256|b64 [rm:fv:    evex.256.66.0f.w1 5a /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 fd 28) 301 001(5a) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCVTPD2PS, 2, {XMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+31311, 544},
    /*   6 : VCVTPD2PS ymmreg|mask|z,zmmrm512|b64|er [rm:fv:    evex.512.66.0f.w1 5a /r           ] AVX512,FUTURE */
        /* 250(f1 fd 48) 301 001(5a) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VCVTPD2PS, 2, {YMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+31320, 545},
};

static const struct itemplate instrux_VCVTPS2DQ[5] = {
    /*   0 : VCVTPS2DQ xmmreg,xmmrm128 [rm:       vex.128.66.0f 5b /r               ] AVX,SANDYBRIDGE */
        /* 270(001 001) 001(5b) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCVTPS2DQ, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58699, 434},
    /*   1 : VCVTPS2DQ ymmreg,ymmrm256 [rm:       vex.256.66.0f 5b /r               ] AVX,SANDYBRIDGE */
        /* 270(001 005) 001(5b) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCVTPS2DQ, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58706, 434},
    /*   2 : VCVTPS2DQ xmmreg|mask|z,xmmrm128|b32 [rm:fv:    evex.128.66.0f.w0 5b /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7d 08) 301 001(5b) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCVTPS2DQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+31437, 544},
    /*   3 : VCVTPS2DQ ymmreg|mask|z,ymmrm256|b32 [rm:fv:    evex.256.66.0f.w0 5b /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7d 28) 301 001(5b) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCVTPS2DQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+31446, 544},
    /*   4 : VCVTPS2DQ zmmreg|mask|z,zmmrm512|b32|er [rm:fv:    evex.512.66.0f.w0 5b /r           ] AVX512,FUTURE */
        /* 250(f1 7d 48) 301 001(5b) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VCVTPS2DQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+31455, 545},
};

static const struct itemplate instrux_VCVTPS2PD[5] = {
    /*   0 : VCVTPS2PD xmmreg,xmmrm64 [rm:       vex.128.0f 5a /r                  ] AVX,SANDYBRIDGE */
        /* 270(001 000) 001(5a) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCVTPS2PD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58713, 434},
    /*   1 : VCVTPS2PD ymmreg,xmmrm128 [rm:       vex.256.0f 5a /r                  ] AVX,SANDYBRIDGE */
        /* 270(001 004) 001(5a) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCVTPS2PD, 2, {YMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58720, 434},
    /*   2 : VCVTPS2PD xmmreg|mask|z,xmmrm64|b32 [rm:hv:    evex.128.0f.w0 5a /r              ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7c 08) 302 001(5a) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCVTPS2PD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+31464, 544},
    /*   3 : VCVTPS2PD ymmreg|mask|z,xmmrm128|b32 [rm:hv:    evex.256.0f.w0 5a /r              ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7c 28) 302 001(5a) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCVTPS2PD, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+31473, 544},
    /*   4 : VCVTPS2PD zmmreg|mask|z,ymmrm256|b32|sae [rm:hv:    evex.512.0f.w0 5a /r              ] AVX512,FUTURE */
        /* 250(f1 7c 48) 302 001(5a) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VCVTPS2PD, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+31482, 545},
};

static const struct itemplate instrux_VCVTSD2SI[4] = {
    /*   0 : VCVTSD2SI reg32,xmmrm64 [rm:       vex.lig.f2.0f.w0 2d /r            ] AVX,SANDYBRIDGE */
        /* 270(001 003) 001(2d) 110 : NOAPX,LIG,VEX,AVX,SANDYBRIDGE */
        {I_VCVTSD2SI, 2, {REG_GPR|BITS32|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58727, 446},
    /*   1 : VCVTSD2SI reg64,xmmrm64 [rm:       vex.lig.f2.0f.w1 2d /r            ] LONG,PROT,AVX,X86_64,SANDYBRIDGE */
        /* 270(001 203) 001(2d) 110 : NOAPX,LIG,LONG,VEX,PROT,AVX,SANDYBRIDGE */
        {I_VCVTSD2SI, 2, {REG_GPR|BITS64|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58734, 447},
    /*   2 : VCVTSD2SI reg32,xmmrm64|er [rm:t1f64: evex.128.f2.0f.w0 2d /r           ] AVX512,FUTURE */
        /* 250(f1 7f 08) 310 001(2d) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VCVTSD2SI, 2, {REG_GPR|BITS32,RM_XMM|BITS64,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+31626, 545},
    /*   3 : VCVTSD2SI reg64,xmmrm64|er [rm:t1f64: evex.128.f2.0f.w1 2d /r           ] AVX512,FUTURE */
        /* 250(f1 ff 08) 310 001(2d) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VCVTSD2SI, 2, {REG_GPR|BITS64,RM_XMM|BITS64,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+31635, 545},
};

static const struct itemplate instrux_VCVTSD2SS[4] = {
    /*   0 : VCVTSD2SS xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f 5a /r           ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(5a) 120 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCVTSD2SS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58741, 441},
    /*   1 : VCVTSD2SS xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f 5a /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(5a) 110 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCVTSD2SS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58748, 441},
    /*   2 : VCVTSD2SS xmmreg|mask|z,xmmreg*,xmmrm64|er [rvm:t1s:  evex.nds.lig.f2.0f.w1 5a /r       ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(5a) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCVTSD2SS, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+31644, 546},
    /*   3 : VCVTSD2SS xmmreg|mask|z,xmmrm64|er [r+vm:t1s:  evex.nds.lig.f2.0f.w1 5a /r       ] ND,AVX512,FUTURE */
        /* 240(f1 ff 08) 306 001(5a) 110 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCVTSD2SS, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+31653, 546},
};

static const struct itemplate instrux_VCVTSI2SD[10] = {
    /*   0 : VCVTSI2SD xmmreg,xmmreg*,rm32 [rvm:      vex.nds.lig.f2.0f.w0 2a /r        ] AR0,AR1,AR2,SD,AVX,SANDYBRIDGE */
        /* 261(001 003) 001(2a) 120 : AR0,AR1,AR2,SD,NOAPX,LIG,VEX,AVX,SANDYBRIDGE */
        {I_VCVTSI2SD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58755, 448},
    /*   1 : VCVTSI2SD xmmreg,rm32 [r+vm:      vex.nds.lig.f2.0f.w0 2a /r        ] ND,AR0,AR1,SD,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(2a) 110 : AR0,AR1,SD,NOAPX,LIG,VEX,AVX,SANDYBRIDGE */
        {I_VCVTSI2SD, 2, {XMMREG|RN_L16,RM_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58762, 449},
    /*   2 : VCVTSI2SD xmmreg,xmmreg*,mem32 [rvm:      vex.nds.lig.f2.0f.w0 2a /r        ] ND,AR0,AR1,AR2,SD,AVX,SANDYBRIDGE */
        /* 261(001 003) 001(2a) 120 : AR0,AR1,AR2,SD,NOAPX,LIG,VEX,AVX,SANDYBRIDGE */
        {I_VCVTSI2SD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,MEMORY|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58755, 448},
    /*   3 : VCVTSI2SD xmmreg,mem32 [r+vm:      vex.nds.lig.f2.0f.w0 2a /r        ] ND,AR0,AR1,SD,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(2a) 110 : AR0,AR1,SD,NOAPX,LIG,VEX,AVX,SANDYBRIDGE */
        {I_VCVTSI2SD, 2, {XMMREG|RN_L16,MEMORY|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58762, 449},
    /*   4 : VCVTSI2SD xmmreg,xmmreg*,rm64 [rvm:      vex.nds.lig.f2.0f.w1 2a /r        ] AR0,AR1,AR2,SQ,LONG,PROT,AVX,X86_64,SANDYBRIDGE */
        /* 261(001 203) 001(2a) 120 : AR0,AR1,AR2,SQ,NOAPX,LIG,LONG,VEX,PROT,AVX,SANDYBRIDGE */
        {I_VCVTSI2SD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58769, 450},
    /*   5 : VCVTSI2SD xmmreg,rm64 [r+vm:      vex.nds.lig.f2.0f.w1 2a /r        ] ND,AR0,AR1,SQ,LONG,PROT,AVX,X86_64,SANDYBRIDGE */
        /* 260(001 203) 001(2a) 110 : AR0,AR1,SQ,NOAPX,LIG,LONG,VEX,PROT,AVX,SANDYBRIDGE */
        {I_VCVTSI2SD, 2, {XMMREG|RN_L16,RM_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58776, 451},
    /*   6 : VCVTSI2SD xmmreg,xmmreg*,rm32 [rvm:t1s:  evex.nds.lig.f2.0f.w0 2a /r       ] AVX512,FUTURE */
        /* 241(f1 7f 08) 306 001(2a) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCVTSI2SD, 3, {XMMREG,XMMREG,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+31680, 546},
    /*   7 : VCVTSI2SD xmmreg,rm32 [r+vm:t1s:  evex.nds.lig.f2.0f.w0 2a /r       ] ND,AVX512,FUTURE */
        /* 240(f1 7f 08) 306 001(2a) 110 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCVTSI2SD, 2, {XMMREG,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+31689, 546},
    /*   8 : VCVTSI2SD xmmreg,xmmreg*,rm64|er [rvm:t1s:  evex.nds.lig.f2.0f.w1 2a /r       ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(2a) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCVTSI2SD, 3, {XMMREG,XMMREG,RM_GPR|BITS64,0,0}, {0,0,ER,0,0}, nasm_bytecodes+31698, 546},
    /*   9 : VCVTSI2SD xmmreg,rm64|er [r+vm:t1s:  evex.nds.lig.f2.0f.w1 2a /r       ] ND,AVX512,FUTURE */
        /* 240(f1 ff 08) 306 001(2a) 110 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCVTSI2SD, 2, {XMMREG,RM_GPR|BITS64,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+31707, 546},
};

static const struct itemplate instrux_VCVTSI2SS[10] = {
    /*   0 : VCVTSI2SS xmmreg,xmmreg*,rm32 [rvm:      vex.nds.lig.f3.0f.w0 2a /r        ] AR0,AR1,AR2,SD,AVX,SANDYBRIDGE */
        /* 261(001 002) 001(2a) 120 : AR0,AR1,AR2,SD,NOAPX,LIG,VEX,AVX,SANDYBRIDGE */
        {I_VCVTSI2SS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58783, 448},
    /*   1 : VCVTSI2SS xmmreg,rm32 [r+vm:      vex.nds.lig.f3.0f.w0 2a /r        ] ND,AR0,AR1,SD,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(2a) 110 : AR0,AR1,SD,NOAPX,LIG,VEX,AVX,SANDYBRIDGE */
        {I_VCVTSI2SS, 2, {XMMREG|RN_L16,RM_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58790, 449},
    /*   2 : VCVTSI2SS xmmreg,xmmreg*,mem32 [rvm:      vex.nds.lig.f3.0f.w0 2a /r        ] ND,AR0,AR1,AR2,SD,AVX,SANDYBRIDGE */
        /* 261(001 002) 001(2a) 120 : AR0,AR1,AR2,SD,NOAPX,LIG,VEX,AVX,SANDYBRIDGE */
        {I_VCVTSI2SS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,MEMORY|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58783, 448},
    /*   3 : VCVTSI2SS xmmreg,mem32 [r+vm:      vex.nds.lig.f3.0f.w0 2a /r        ] ND,AR0,AR1,SD,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(2a) 110 : AR0,AR1,SD,NOAPX,LIG,VEX,AVX,SANDYBRIDGE */
        {I_VCVTSI2SS, 2, {XMMREG|RN_L16,MEMORY|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58790, 449},
    /*   4 : VCVTSI2SS xmmreg,xmmreg*,rm64 [rvm:      vex.nds.lig.f3.0f.w1 2a /r        ] AR0,AR1,AR2,SQ,LONG,PROT,AVX,X86_64,SANDYBRIDGE */
        /* 261(001 202) 001(2a) 120 : AR0,AR1,AR2,SQ,NOAPX,LIG,LONG,VEX,PROT,AVX,SANDYBRIDGE */
        {I_VCVTSI2SS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_GPR|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58797, 450},
    /*   5 : VCVTSI2SS xmmreg,rm64 [r+vm:      vex.nds.lig.f3.0f.w1 2a /r        ] ND,AR0,AR1,SQ,LONG,PROT,AVX,X86_64,SANDYBRIDGE */
        /* 260(001 202) 001(2a) 110 : AR0,AR1,SQ,NOAPX,LIG,LONG,VEX,PROT,AVX,SANDYBRIDGE */
        {I_VCVTSI2SS, 2, {XMMREG|RN_L16,RM_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58804, 451},
    /*   6 : VCVTSI2SS xmmreg,xmmreg*,rm32|er [rvm:t1s:  evex.nds.lig.f3.0f.w0 2a /r       ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(2a) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCVTSI2SS, 3, {XMMREG,XMMREG,RM_GPR|BITS32,0,0}, {0,0,ER,0,0}, nasm_bytecodes+31716, 546},
    /*   7 : VCVTSI2SS xmmreg,rm32|er [r+vm:t1s:  evex.nds.lig.f3.0f.w0 2a /r       ] ND,AVX512,FUTURE */
        /* 240(f1 7e 08) 306 001(2a) 110 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCVTSI2SS, 2, {XMMREG,RM_GPR|BITS32,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+31725, 546},
    /*   8 : VCVTSI2SS xmmreg,xmmreg*,rm64|er [rvm:t1s:  evex.nds.lig.f3.0f.w1 2a /r       ] AVX512,FUTURE */
        /* 241(f1 fe 08) 306 001(2a) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCVTSI2SS, 3, {XMMREG,XMMREG,RM_GPR|BITS64,0,0}, {0,0,ER,0,0}, nasm_bytecodes+31734, 546},
    /*   9 : VCVTSI2SS xmmreg,rm64|er [r+vm:t1s:  evex.nds.lig.f3.0f.w1 2a /r       ] ND,AVX512,FUTURE */
        /* 240(f1 fe 08) 306 001(2a) 110 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCVTSI2SS, 2, {XMMREG,RM_GPR|BITS64,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+31743, 546},
};

static const struct itemplate instrux_VCVTSS2SD[4] = {
    /*   0 : VCVTSS2SD xmmreg,xmmreg*,xmmrm32 [rvm:      vex.nds.lig.f3.0f 5a /r           ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(5a) 120 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCVTSS2SD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58811, 441},
    /*   1 : VCVTSS2SD xmmreg,xmmrm32 [r+vm:      vex.nds.lig.f3.0f 5a /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(5a) 110 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCVTSS2SD, 2, {XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58818, 441},
    /*   2 : VCVTSS2SD xmmreg|mask|z,xmmreg*,xmmrm32|sae [rvm:t1s:  evex.nds.lig.f3.0f.w0 5a /r       ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(5a) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCVTSS2SD, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+31752, 546},
    /*   3 : VCVTSS2SD xmmreg|mask|z,xmmrm32|sae [r+vm:t1s:  evex.nds.lig.f3.0f.w0 5a /r       ] ND,AVX512,FUTURE */
        /* 240(f1 7e 08) 306 001(5a) 110 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCVTSS2SD, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+31761, 546},
};

static const struct itemplate instrux_VCVTSS2SI[4] = {
    /*   0 : VCVTSS2SI reg32,xmmrm32 [rm:       vex.lig.f3.0f.w0 2d /r            ] AVX,SANDYBRIDGE */
        /* 270(001 002) 001(2d) 110 : NOAPX,LIG,VEX,AVX,SANDYBRIDGE */
        {I_VCVTSS2SI, 2, {REG_GPR|BITS32|RN_L16,RM_XMM|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58825, 446},
    /*   1 : VCVTSS2SI reg64,xmmrm32 [rm:       vex.lig.f3.0f.w1 2d /r            ] LONG,PROT,AVX,X86_64,SANDYBRIDGE */
        /* 270(001 202) 001(2d) 110 : NOAPX,LIG,LONG,VEX,PROT,AVX,SANDYBRIDGE */
        {I_VCVTSS2SI, 2, {REG_GPR|BITS64|RN_L16,RM_XMM|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58832, 447},
    /*   2 : VCVTSS2SI reg32,xmmrm32|er [rm:t1f32: evex.128.f3.0f.w0 2d /r           ] AVX512,FUTURE */
        /* 250(f1 7e 08) 307 001(2d) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VCVTSS2SI, 2, {REG_GPR|BITS32,RM_XMM|BITS32,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+31770, 545},
    /*   3 : VCVTSS2SI reg64,xmmrm32|er [rm:t1f32: evex.128.f3.0f.w1 2d /r           ] AVX512,FUTURE */
        /* 250(f1 fe 08) 307 001(2d) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VCVTSS2SI, 2, {REG_GPR|BITS64,RM_XMM|BITS32,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+31779, 545},
};

static const struct itemplate instrux_VCVTTPD2DQ[7] = {
    /*   0 : VCVTTPD2DQ xmmreg,xmmreg [rm:       vex.128.66.0f e6 /r               ] AVX,SANDYBRIDGE */
        /* 270(001 001) 001(e6) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCVTTPD2DQ, 2, {XMMREG|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58839, 434},
    /*   1 : VCVTTPD2DQ xmmreg,mem128 [rm:       vex.128.66.0f e6 /r               ] AR0-1,SO,AVX,SANDYBRIDGE */
        /* 270(001 001) 001(e6) 110 : AR0,AR1,SO,NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCVTTPD2DQ, 2, {XMMREG|RN_L16,MEMORY|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58839, 444},
    /*   2 : VCVTTPD2DQ xmmreg,ymmreg [rm:       vex.256.66.0f e6 /r               ] AVX,SANDYBRIDGE */
        /* 270(001 005) 001(e6) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCVTTPD2DQ, 2, {XMMREG|RN_L16,YMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58846, 434},
    /*   3 : VCVTTPD2DQ xmmreg,mem256 [rm:       vex.256.66.0f e6 /r               ] AR0-1,SY,AVX,SANDYBRIDGE */
        /* 270(001 005) 001(e6) 110 : AR0,AR1,SY,NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCVTTPD2DQ, 2, {XMMREG|RN_L16,MEMORY|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58846, 445},
    /*   4 : VCVTTPD2DQ xmmreg|mask|z,xmmrm128|b64 [rm:fv:    evex.128.66.0f.w1 e6 /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 fd 08) 301 001(e6) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCVTTPD2DQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+31806, 544},
    /*   5 : VCVTTPD2DQ xmmreg|mask|z,ymmrm256|b64 [rm:fv:    evex.256.66.0f.w1 e6 /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 fd 28) 301 001(e6) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCVTTPD2DQ, 2, {XMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+31815, 544},
    /*   6 : VCVTTPD2DQ ymmreg|mask|z,zmmrm512|b64|sae [rm:fv:    evex.512.66.0f.w1 e6 /r           ] AVX512,FUTURE */
        /* 250(f1 fd 48) 301 001(e6) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VCVTTPD2DQ, 2, {YMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+31824, 545},
};

static const struct itemplate instrux_VCVTTPS2DQ[5] = {
    /*   0 : VCVTTPS2DQ xmmreg,xmmrm128 [rm:       vex.128.f3.0f 5b /r               ] AVX,SANDYBRIDGE */
        /* 270(001 002) 001(5b) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCVTTPS2DQ, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58853, 434},
    /*   1 : VCVTTPS2DQ ymmreg,ymmrm256 [rm:       vex.256.f3.0f 5b /r               ] AVX,SANDYBRIDGE */
        /* 270(001 006) 001(5b) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VCVTTPS2DQ, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58860, 434},
    /*   2 : VCVTTPS2DQ xmmreg|mask|z,xmmrm128|b32 [rm:fv:    evex.128.f3.0f.w0 5b /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7e 08) 301 001(5b) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCVTTPS2DQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+31914, 544},
    /*   3 : VCVTTPS2DQ ymmreg|mask|z,ymmrm256|b32 [rm:fv:    evex.256.f3.0f.w0 5b /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7e 28) 301 001(5b) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCVTTPS2DQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+31923, 544},
    /*   4 : VCVTTPS2DQ zmmreg|mask|z,zmmrm512|b32|sae [rm:fv:    evex.512.f3.0f.w0 5b /r           ] AVX512,FUTURE */
        /* 250(f1 7e 48) 301 001(5b) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VCVTTPS2DQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+31932, 545},
};

static const struct itemplate instrux_VCVTTSD2SI[4] = {
    /*   0 : VCVTTSD2SI reg32,xmmrm64 [rm:       vex.lig.f2.0f.w0 2c /r            ] AVX,SANDYBRIDGE */
        /* 270(001 003) 001(2c) 110 : NOAPX,LIG,VEX,AVX,SANDYBRIDGE */
        {I_VCVTTSD2SI, 2, {REG_GPR|BITS32|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58867, 446},
    /*   1 : VCVTTSD2SI reg64,xmmrm64 [rm:       vex.lig.f2.0f.w1 2c /r            ] LONG,PROT,AVX,X86_64,SANDYBRIDGE */
        /* 270(001 203) 001(2c) 110 : NOAPX,LIG,LONG,VEX,PROT,AVX,SANDYBRIDGE */
        {I_VCVTTSD2SI, 2, {REG_GPR|BITS64|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58874, 447},
    /*   2 : VCVTTSD2SI reg32,xmmrm64|sae [rm:t1f64: evex.128.f2.0f.w0 2c /r           ] AVX512,FUTURE */
        /* 250(f1 7f 08) 310 001(2c) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VCVTTSD2SI, 2, {REG_GPR|BITS32,RM_XMM|BITS64,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+32022, 545},
    /*   3 : VCVTTSD2SI reg64,xmmrm64|sae [rm:t1f64: evex.128.f2.0f.w1 2c /r           ] AVX512,FUTURE */
        /* 250(f1 ff 08) 310 001(2c) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VCVTTSD2SI, 2, {REG_GPR|BITS64,RM_XMM|BITS64,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+32031, 545},
};

static const struct itemplate instrux_VCVTTSS2SI[4] = {
    /*   0 : VCVTTSS2SI reg32,xmmrm32 [rm:       vex.lig.f3.0f.w0 2c /r            ] AVX,SANDYBRIDGE */
        /* 270(001 002) 001(2c) 110 : NOAPX,LIG,VEX,AVX,SANDYBRIDGE */
        {I_VCVTTSS2SI, 2, {REG_GPR|BITS32|RN_L16,RM_XMM|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58881, 446},
    /*   1 : VCVTTSS2SI reg64,xmmrm32 [rm:       vex.lig.f3.0f.w1 2c /r            ] LONG,PROT,AVX,X86_64,SANDYBRIDGE */
        /* 270(001 202) 001(2c) 110 : NOAPX,LIG,LONG,VEX,PROT,AVX,SANDYBRIDGE */
        {I_VCVTTSS2SI, 2, {REG_GPR|BITS64|RN_L16,RM_XMM|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58888, 447},
    /*   2 : VCVTTSS2SI reg32,xmmrm32|sae [rm:t1f32: evex.128.f3.0f.w0 2c /r           ] AVX512,FUTURE */
        /* 250(f1 7e 08) 307 001(2c) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VCVTTSS2SI, 2, {REG_GPR|BITS32,RM_XMM|BITS32,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+32058, 545},
    /*   3 : VCVTTSS2SI reg64,xmmrm32|sae [rm:t1f32: evex.128.f3.0f.w1 2c /r           ] AVX512,FUTURE */
        /* 250(f1 fe 08) 307 001(2c) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VCVTTSS2SI, 2, {REG_GPR|BITS64,RM_XMM|BITS32,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+32067, 545},
};

static const struct itemplate instrux_VDIVPD[10] = {
    /*   0 : VDIVPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f 5e /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(5e) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VDIVPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58895, 434},
    /*   1 : VDIVPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f 5e /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(5e) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VDIVPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58902, 434},
    /*   2 : VDIVPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f 5e /r           ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(5e) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VDIVPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58909, 434},
    /*   3 : VDIVPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f 5e /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(5e) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VDIVPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58916, 434},
    /*   4 : VDIVPD xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f.w1 5e /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(5e) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VDIVPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+32238, 544},
    /*   5 : VDIVPD xmmreg|mask|z,xmmrm128|b64 [r+vm:fv:   evex.nds.128.66.0f.w1 5e /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 08) 301 001(5e) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VDIVPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+32247, 544},
    /*   6 : VDIVPD ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f.w1 5e /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(5e) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VDIVPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+32256, 544},
    /*   7 : VDIVPD ymmreg|mask|z,ymmrm256|b64 [r+vm:fv:   evex.nds.256.66.0f.w1 5e /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 28) 301 001(5e) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VDIVPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+32265, 544},
    /*   8 : VDIVPD zmmreg|mask|z,zmmreg*,zmmrm512|b64|er [rvm:fv:   evex.nds.512.66.0f.w1 5e /r       ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(5e) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VDIVPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+32274, 545},
    /*   9 : VDIVPD zmmreg|mask|z,zmmrm512|b64|er [r+vm:fv:   evex.nds.512.66.0f.w1 5e /r       ] ND,AVX512,FUTURE */
        /* 240(f1 fd 48) 301 001(5e) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VDIVPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+32283, 545},
};

static const struct itemplate instrux_VDIVPS[10] = {
    /*   0 : VDIVPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f 5e /r              ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(5e) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VDIVPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58923, 434},
    /*   1 : VDIVPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f 5e /r              ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(5e) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VDIVPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58930, 434},
    /*   2 : VDIVPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f 5e /r              ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(5e) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VDIVPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58937, 434},
    /*   3 : VDIVPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f 5e /r              ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(5e) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VDIVPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58944, 434},
    /*   4 : VDIVPS xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.nds.128.0f.w0 5e /r          ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(5e) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VDIVPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+32292, 544},
    /*   5 : VDIVPS xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.nds.128.0f.w0 5e /r          ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7c 08) 301 001(5e) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VDIVPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+32301, 544},
    /*   6 : VDIVPS ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.nds.256.0f.w0 5e /r          ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(5e) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VDIVPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+32310, 544},
    /*   7 : VDIVPS ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.nds.256.0f.w0 5e /r          ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7c 28) 301 001(5e) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VDIVPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+32319, 544},
    /*   8 : VDIVPS zmmreg|mask|z,zmmreg*,zmmrm512|b32|er [rvm:fv:   evex.nds.512.0f.w0 5e /r          ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(5e) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VDIVPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+32328, 545},
    /*   9 : VDIVPS zmmreg|mask|z,zmmrm512|b32|er [r+vm:fv:   evex.nds.512.0f.w0 5e /r          ] ND,AVX512,FUTURE */
        /* 240(f1 7c 48) 301 001(5e) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VDIVPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+32337, 545},
};

static const struct itemplate instrux_VDIVSD[4] = {
    /*   0 : VDIVSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f 5e /r           ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(5e) 120 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VDIVSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58951, 441},
    /*   1 : VDIVSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f 5e /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(5e) 110 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VDIVSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58958, 441},
    /*   2 : VDIVSD xmmreg|mask|z,xmmreg*,xmmrm64|er [rvm:t1s:  evex.nds.lig.f2.0f.w1 5e /r       ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(5e) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VDIVSD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+32346, 546},
    /*   3 : VDIVSD xmmreg|mask|z,xmmrm64|er [r+vm:t1s:  evex.nds.lig.f2.0f.w1 5e /r       ] ND,AVX512,FUTURE */
        /* 240(f1 ff 08) 306 001(5e) 110 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VDIVSD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+32355, 546},
};

static const struct itemplate instrux_VDIVSS[4] = {
    /*   0 : VDIVSS xmmreg,xmmreg*,xmmrm32 [rvm:      vex.nds.lig.f3.0f 5e /r           ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(5e) 120 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VDIVSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58965, 441},
    /*   1 : VDIVSS xmmreg,xmmrm32 [r+vm:      vex.nds.lig.f3.0f 5e /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(5e) 110 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VDIVSS, 2, {XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58972, 441},
    /*   2 : VDIVSS xmmreg|mask|z,xmmreg*,xmmrm32|er [rvm:t1s:  evex.nds.lig.f3.0f.w0 5e /r       ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(5e) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VDIVSS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+32364, 546},
    /*   3 : VDIVSS xmmreg|mask|z,xmmrm32|er [r+vm:t1s:  evex.nds.lig.f3.0f.w0 5e /r       ] ND,AVX512,FUTURE */
        /* 240(f1 7e 08) 306 001(5e) 110 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VDIVSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+32373, 546},
};

static const struct itemplate instrux_VDPPD[2] = {
    /*   0 : VDPPD xmmreg,xmmreg*,xmmrm128,imm8 [rvmi:     vex.nds.128.66.0f3a 41 /r ib      ] AVX,SANDYBRIDGE */
        /* 261(003 001) 001(41) 120 023 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VDPPD, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+51829, 434},
    /*   1 : VDPPD xmmreg,xmmrm128,imm8 [r+vmi:     vex.nds.128.66.0f3a 41 /r ib      ] ND,AVX,SANDYBRIDGE */
        /* 260(003 001) 001(41) 110 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VDPPD, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51837, 434},
};

static const struct itemplate instrux_VDPPS[4] = {
    /*   0 : VDPPS xmmreg,xmmreg*,xmmrm128,imm8 [rvmi:     vex.nds.128.66.0f3a 40 /r ib      ] AVX,SANDYBRIDGE */
        /* 261(003 001) 001(40) 120 023 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VDPPS, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+51845, 434},
    /*   1 : VDPPS xmmreg,xmmrm128,imm8 [r+vmi:     vex.nds.128.66.0f3a 40 /r ib      ] ND,AVX,SANDYBRIDGE */
        /* 260(003 001) 001(40) 110 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VDPPS, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51853, 434},
    /*   2 : VDPPS ymmreg,ymmreg*,ymmrm256,imm8 [rvmi:     vex.nds.256.66.0f3a 40 /r ib      ] AVX,SANDYBRIDGE */
        /* 261(003 005) 001(40) 120 023 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VDPPS, 4, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+51861, 434},
    /*   3 : VDPPS ymmreg,ymmrm256,imm8 [r+vmi:     vex.nds.256.66.0f3a 40 /r ib      ] ND,AVX,SANDYBRIDGE */
        /* 260(003 005) 001(40) 110 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VDPPS, 3, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51869, 434},
};

static const struct itemplate instrux_VEXTRACTF128[1] = {
    /*   0 : VEXTRACTF128 xmmrm128,ymmreg,imm8 [mri:      vex.256.66.0f3a.w0 19 /r ib       ] AVX,SANDYBRIDGE */
        /* 270(003 005) 001(19) 101 022 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VEXTRACTF128, 3, {RM_XMM|BITS128|RN_L16,YMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51877, 442},
};

static const struct itemplate instrux_VEXTRACTPS[4] = {
    /*   0 : VEXTRACTPS rm32,xmmreg,imm8 [mri:      vex.128.66.0f3a 17 /r ib          ] AVX,SANDYBRIDGE */
        /* 270(003 001) 001(17) 101 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VEXTRACTPS, 3, {RM_GPR|BITS32|RN_L16,XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51885, 434},
    /*   1 : VEXTRACTPS reg32,xmmreg,imm8 [mri:t1s:  evex.128.66.0f3a.wig 17 /r ib     ] AVX512,FUTURE */
        /* 250(f3 7d 08) 306 001(17) 101 022 : WIG,EVEX,PROT,AVX512,FUTURE */
        {I_VEXTRACTPS, 3, {REG_GPR|BITS32,XMMREG,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18663, 553},
    /*   2 : VEXTRACTPS reg64,xmmreg,imm8 [mri:t1s:  evex.128.66.0f3a.wig 17 /r ib     ] AVX512,FUTURE */
        /* 250(f3 7d 08) 306 001(17) 101 022 : WIG,EVEX,PROT,AVX512,FUTURE */
        {I_VEXTRACTPS, 3, {REG_GPR|BITS64,XMMREG,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18663, 553},
    /*   3 : VEXTRACTPS mem32,xmmreg,imm8 [mri:t1s:  evex.128.66.0f3a.wig 17 /r ib     ] AVX512,FUTURE */
        /* 250(f3 7d 08) 306 001(17) 101 022 : WIG,EVEX,PROT,AVX512,FUTURE */
        {I_VEXTRACTPS, 3, {MEMORY|BITS32,XMMREG,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18663, 553},
};

static const struct itemplate instrux_VHADDPD[4] = {
    /*   0 : VHADDPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f 7c /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(7c) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VHADDPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58979, 434},
    /*   1 : VHADDPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f 7c /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(7c) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VHADDPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+58986, 434},
    /*   2 : VHADDPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f 7c /r           ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(7c) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VHADDPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+58993, 434},
    /*   3 : VHADDPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f 7c /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(7c) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VHADDPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59000, 434},
};

static const struct itemplate instrux_VHADDPS[4] = {
    /*   0 : VHADDPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.f2.0f 7c /r           ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(7c) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VHADDPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59007, 434},
    /*   1 : VHADDPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.f2.0f 7c /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(7c) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VHADDPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59014, 434},
    /*   2 : VHADDPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.f2.0f 7c /r           ] AVX,SANDYBRIDGE */
        /* 261(001 007) 001(7c) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VHADDPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59021, 434},
    /*   3 : VHADDPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.f2.0f 7c /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 007) 001(7c) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VHADDPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59028, 434},
};

static const struct itemplate instrux_VHSUBPD[4] = {
    /*   0 : VHSUBPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f 7d /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(7d) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VHSUBPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59035, 434},
    /*   1 : VHSUBPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f 7d /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(7d) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VHSUBPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59042, 434},
    /*   2 : VHSUBPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f 7d /r           ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(7d) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VHSUBPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59049, 434},
    /*   3 : VHSUBPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f 7d /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(7d) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VHSUBPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59056, 434},
};

static const struct itemplate instrux_VHSUBPS[4] = {
    /*   0 : VHSUBPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.f2.0f 7d /r           ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(7d) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VHSUBPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59063, 434},
    /*   1 : VHSUBPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.f2.0f 7d /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(7d) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VHSUBPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59070, 434},
    /*   2 : VHSUBPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.f2.0f 7d /r           ] AVX,SANDYBRIDGE */
        /* 261(001 007) 001(7d) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VHSUBPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59077, 434},
    /*   3 : VHSUBPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.f2.0f 7d /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 007) 001(7d) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VHSUBPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59084, 434},
};

static const struct itemplate instrux_VINSERTF128[2] = {
    /*   0 : VINSERTF128 ymmreg,ymmreg*,xmmrm128,imm8 [rvmi:     vex.nds.256.66.0f3a.w0 18 /r ib   ] AVX,SANDYBRIDGE */
        /* 261(003 005) 001(18) 120 023 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VINSERTF128, 4, {YMMREG|RN_L16,YMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+51893, 442},
    /*   1 : VINSERTF128 ymmreg,xmmrm128,imm8 [r+vmi:     vex.nds.256.66.0f3a.w0 18 /r ib   ] ND,AVX,SANDYBRIDGE */
        /* 260(003 005) 001(18) 110 022 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VINSERTF128, 3, {YMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51901, 442},
};

static const struct itemplate instrux_VINSERTPS[4] = {
    /*   0 : VINSERTPS xmmreg,xmmreg*,xmmrm32,imm8 [rvmi:     vex.nds.128.66.0f3a 21 /r ib      ] AVX,SANDYBRIDGE */
        /* 261(003 001) 001(21) 120 023 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VINSERTPS, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+51909, 434},
    /*   1 : VINSERTPS xmmreg,xmmrm32,imm8 [r+vmi:     vex.nds.128.66.0f3a 21 /r ib      ] ND,AVX,SANDYBRIDGE */
        /* 260(003 001) 001(21) 110 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VINSERTPS, 3, {XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51917, 434},
    /*   2 : VINSERTPS xmmreg,xmmreg*,xmmrm32,imm8 [rvmi:t1s: evex.nds.128.66.0f3a.w0 21 /r ib  ] AVX512,FUTURE */
        /* 241(f3 7d 08) 306 001(21) 120 023 : EVEX,PROT,AVX512,FUTURE */
        {I_VINSERTPS, 4, {XMMREG,XMMREG,RM_XMM|BITS32,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+19433, 545},
    /*   3 : VINSERTPS xmmreg,xmmrm32,imm8 [r+vmi:t1s: evex.nds.128.66.0f3a.w0 21 /r ib  ] ND,AVX512,FUTURE */
        /* 240(f3 7d 08) 306 001(21) 110 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VINSERTPS, 3, {XMMREG,RM_XMM|BITS32,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+19443, 545},
};

static const struct itemplate instrux_VLDDQU[2] = {
    /*   0 : VLDDQU xmmreg,mem128 [rm:       vex.128.f2.0f f0 /r               ] AVX,SANDYBRIDGE */
        /* 270(001 003) 001(f0) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VLDDQU, 2, {XMMREG|RN_L16,MEMORY|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59091, 434},
    /*   1 : VLDDQU ymmreg,mem256 [rm:       vex.256.f2.0f f0 /r               ] AVX,SANDYBRIDGE */
        /* 270(001 007) 001(f0) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VLDDQU, 2, {YMMREG|RN_L16,MEMORY|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59098, 434},
};

static const struct itemplate instrux_VLDQQU[1] = {
    /*   0 : VLDQQU ymmreg,mem256 [rm:       vex.256.f2.0f f0 /r               ] AVX,SANDYBRIDGE */
        /* 270(001 007) 001(f0) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VLDQQU, 2, {YMMREG|RN_L16,MEMORY|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59098, 434},
};

static const struct itemplate instrux_VLDMXCSR[1] = {
    /*   0 : VLDMXCSR mem32 [m:        vex.lz.0f ae /2                   ] AVX,SANDYBRIDGE */
        /* 270(001 000) 001(ae) 202 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VLDMXCSR, 1, {MEMORY|BITS32|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+59105, 434},
};

static const struct itemplate instrux_VMASKMOVDQU[1] = {
    /*   0 : VMASKMOVDQU xmmreg,xmmreg [rm:       vex.128.66.0f f7 /r               ] AVX,SANDYBRIDGE */
        /* 270(001 001) 001(f7) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMASKMOVDQU, 2, {XMMREG|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59112, 434},
};

static const struct itemplate instrux_VMASKMOVPS[4] = {
    /*   0 : VMASKMOVPS xmmreg,xmmreg,mem128 [rvm:      vex.nds.128.66.0f38.w0 2c /r      ] AVX,SANDYBRIDGE */
        /* 261(002 001) 001(2c) 120 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VMASKMOVPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,MEMORY|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59119, 442},
    /*   1 : VMASKMOVPS ymmreg,ymmreg,mem256 [rvm:      vex.nds.256.66.0f38.w0 2c /r      ] AVX,SANDYBRIDGE */
        /* 261(002 005) 001(2c) 120 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VMASKMOVPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,MEMORY|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59126, 442},
    /*   2 : VMASKMOVPS mem128,xmmreg,xmmreg [mvr:      vex.nds.128.66.0f38.w0 2e /r      ] AR0-2,SO,AVX,SANDYBRIDGE */
        /* 261(002 001) 001(2e) 102 : AR0,AR1,AR2,SO,NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VMASKMOVPS, 3, {MEMORY|BITS128|RN_L16,XMMREG|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59133, 452},
    /*   3 : VMASKMOVPS mem256,ymmreg,ymmreg [mvr:      vex.nds.256.66.0f38.w0 2e /r      ] AR0-2,SY,AVX,SANDYBRIDGE */
        /* 261(002 005) 001(2e) 102 : AR0,AR1,AR2,SY,NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VMASKMOVPS, 3, {MEMORY|BITS256|RN_L16,YMMREG|RN_L16,YMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59140, 453},
};

static const struct itemplate instrux_VMASKMOVPD[4] = {
    /*   0 : VMASKMOVPD xmmreg,xmmreg,mem128 [rvm:      vex.nds.128.66.0f38.w0 2d /r      ] AVX,SANDYBRIDGE */
        /* 261(002 001) 001(2d) 120 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VMASKMOVPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,MEMORY|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59147, 442},
    /*   1 : VMASKMOVPD ymmreg,ymmreg,mem256 [rvm:      vex.nds.256.66.0f38.w0 2d /r      ] AVX,SANDYBRIDGE */
        /* 261(002 005) 001(2d) 120 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VMASKMOVPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,MEMORY|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59154, 442},
    /*   2 : VMASKMOVPD mem128,xmmreg,xmmreg [mvr:      vex.nds.128.66.0f38.w0 2f /r      ] AVX,SANDYBRIDGE */
        /* 261(002 001) 001(2f) 102 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VMASKMOVPD, 3, {MEMORY|BITS128|RN_L16,XMMREG|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59161, 442},
    /*   3 : VMASKMOVPD mem256,ymmreg,ymmreg [mvr:      vex.nds.256.66.0f38.w0 2f /r      ] AVX,SANDYBRIDGE */
        /* 261(002 005) 001(2f) 102 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VMASKMOVPD, 3, {MEMORY|BITS256|RN_L16,YMMREG|RN_L16,YMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59168, 442},
};

static const struct itemplate instrux_VMAXPD[10] = {
    /*   0 : VMAXPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f 5f /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(5f) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMAXPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59175, 434},
    /*   1 : VMAXPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f 5f /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(5f) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMAXPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59182, 434},
    /*   2 : VMAXPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f 5f /r           ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(5f) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMAXPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59189, 434},
    /*   3 : VMAXPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f 5f /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(5f) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMAXPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59196, 434},
    /*   4 : VMAXPD xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f.w1 5f /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(5f) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMAXPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+33714, 544},
    /*   5 : VMAXPD xmmreg|mask|z,xmmrm128|b64 [r+vm:fv:   evex.nds.128.66.0f.w1 5f /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 08) 301 001(5f) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMAXPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+33723, 544},
    /*   6 : VMAXPD ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f.w1 5f /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(5f) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMAXPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+33732, 544},
    /*   7 : VMAXPD ymmreg|mask|z,ymmrm256|b64 [r+vm:fv:   evex.nds.256.66.0f.w1 5f /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 28) 301 001(5f) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMAXPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+33741, 544},
    /*   8 : VMAXPD zmmreg|mask|z,zmmreg*,zmmrm512|b64|sae [rvm:fv:   evex.nds.512.66.0f.w1 5f /r       ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(5f) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VMAXPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|SAE,0,0}, nasm_bytecodes+33750, 545},
    /*   9 : VMAXPD zmmreg|mask|z,zmmrm512|b64|sae [r+vm:fv:   evex.nds.512.66.0f.w1 5f /r       ] ND,AVX512,FUTURE */
        /* 240(f1 fd 48) 301 001(5f) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VMAXPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+33759, 545},
};

static const struct itemplate instrux_VMAXPS[10] = {
    /*   0 : VMAXPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f 5f /r              ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(5f) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMAXPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59203, 434},
    /*   1 : VMAXPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f 5f /r              ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(5f) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMAXPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59210, 434},
    /*   2 : VMAXPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f 5f /r              ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(5f) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMAXPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59217, 434},
    /*   3 : VMAXPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f 5f /r              ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(5f) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMAXPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59224, 434},
    /*   4 : VMAXPS xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.nds.128.0f.w0 5f /r          ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(5f) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMAXPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+33768, 544},
    /*   5 : VMAXPS xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.nds.128.0f.w0 5f /r          ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7c 08) 301 001(5f) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMAXPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+33777, 544},
    /*   6 : VMAXPS ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.nds.256.0f.w0 5f /r          ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(5f) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMAXPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+33786, 544},
    /*   7 : VMAXPS ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.nds.256.0f.w0 5f /r          ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7c 28) 301 001(5f) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMAXPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+33795, 544},
    /*   8 : VMAXPS zmmreg|mask|z,zmmreg*,zmmrm512|b32|sae [rvm:fv:   evex.nds.512.0f.w0 5f /r          ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(5f) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VMAXPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|SAE,0,0}, nasm_bytecodes+33804, 545},
    /*   9 : VMAXPS zmmreg|mask|z,zmmrm512|b32|sae [r+vm:fv:   evex.nds.512.0f.w0 5f /r          ] ND,AVX512,FUTURE */
        /* 240(f1 7c 48) 301 001(5f) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VMAXPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+33813, 545},
};

static const struct itemplate instrux_VMAXSD[4] = {
    /*   0 : VMAXSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f 5f /r           ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(5f) 120 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMAXSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59231, 441},
    /*   1 : VMAXSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f 5f /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(5f) 110 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMAXSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59238, 441},
    /*   2 : VMAXSD xmmreg|mask|z,xmmreg*,xmmrm64|sae [rvm:t1s:  evex.nds.lig.f2.0f.w1 5f /r       ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(5f) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VMAXSD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+33822, 546},
    /*   3 : VMAXSD xmmreg|mask|z,xmmrm64|sae [r+vm:t1s:  evex.nds.lig.f2.0f.w1 5f /r       ] ND,AVX512,FUTURE */
        /* 240(f1 ff 08) 306 001(5f) 110 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VMAXSD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+33831, 546},
};

static const struct itemplate instrux_VMAXSS[4] = {
    /*   0 : VMAXSS xmmreg,xmmreg*,xmmrm32 [rvm:      vex.nds.lig.f3.0f 5f /r           ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(5f) 120 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMAXSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59245, 441},
    /*   1 : VMAXSS xmmreg,xmmrm32 [r+vm:      vex.nds.lig.f3.0f 5f /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(5f) 110 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMAXSS, 2, {XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59252, 441},
    /*   2 : VMAXSS xmmreg|mask|z,xmmreg*,xmmrm32|sae [rvm:t1s:  evex.nds.lig.f3.0f.w0 5f /r       ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(5f) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VMAXSS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+33840, 546},
    /*   3 : VMAXSS xmmreg|mask|z,xmmrm32|sae [r+vm:t1s:  evex.nds.lig.f3.0f.w0 5f /r       ] ND,AVX512,FUTURE */
        /* 240(f1 7e 08) 306 001(5f) 110 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VMAXSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+33849, 546},
};

static const struct itemplate instrux_VMINPD[10] = {
    /*   0 : VMINPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f 5d /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(5d) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMINPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59259, 434},
    /*   1 : VMINPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f 5d /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(5d) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMINPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59266, 434},
    /*   2 : VMINPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f 5d /r           ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(5d) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMINPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59273, 434},
    /*   3 : VMINPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f 5d /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(5d) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMINPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59280, 434},
    /*   4 : VMINPD xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f.w1 5d /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(5d) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMINPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+33858, 544},
    /*   5 : VMINPD xmmreg|mask|z,xmmrm128|b64 [r+vm:fv:   evex.nds.128.66.0f.w1 5d /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 08) 301 001(5d) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMINPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+33867, 544},
    /*   6 : VMINPD ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f.w1 5d /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(5d) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMINPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+33876, 544},
    /*   7 : VMINPD ymmreg|mask|z,ymmrm256|b64 [r+vm:fv:   evex.nds.256.66.0f.w1 5d /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 28) 301 001(5d) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMINPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+33885, 544},
    /*   8 : VMINPD zmmreg|mask|z,zmmreg*,zmmrm512|b64|sae [rvm:fv:   evex.nds.512.66.0f.w1 5d /r       ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(5d) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VMINPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|SAE,0,0}, nasm_bytecodes+33894, 545},
    /*   9 : VMINPD zmmreg|mask|z,zmmrm512|b64|sae [r+vm:fv:   evex.nds.512.66.0f.w1 5d /r       ] ND,AVX512,FUTURE */
        /* 240(f1 fd 48) 301 001(5d) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VMINPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+33903, 545},
};

static const struct itemplate instrux_VMINPS[10] = {
    /*   0 : VMINPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f 5d /r              ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(5d) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMINPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59287, 434},
    /*   1 : VMINPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f 5d /r              ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(5d) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMINPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59294, 434},
    /*   2 : VMINPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f 5d /r              ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(5d) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMINPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59301, 434},
    /*   3 : VMINPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f 5d /r              ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(5d) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMINPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59308, 434},
    /*   4 : VMINPS xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.nds.128.0f.w0 5d /r          ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(5d) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMINPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+33912, 544},
    /*   5 : VMINPS xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.nds.128.0f.w0 5d /r          ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7c 08) 301 001(5d) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMINPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+33921, 544},
    /*   6 : VMINPS ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.nds.256.0f.w0 5d /r          ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(5d) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMINPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+33930, 544},
    /*   7 : VMINPS ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.nds.256.0f.w0 5d /r          ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7c 28) 301 001(5d) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMINPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+33939, 544},
    /*   8 : VMINPS zmmreg|mask|z,zmmreg*,zmmrm512|b32|sae [rvm:fv:   evex.nds.512.0f.w0 5d /r          ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(5d) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VMINPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|SAE,0,0}, nasm_bytecodes+33948, 545},
    /*   9 : VMINPS zmmreg|mask|z,zmmrm512|b32|sae [r+vm:fv:   evex.nds.512.0f.w0 5d /r          ] ND,AVX512,FUTURE */
        /* 240(f1 7c 48) 301 001(5d) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VMINPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+33957, 545},
};

static const struct itemplate instrux_VMINSD[4] = {
    /*   0 : VMINSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f 5d /r           ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(5d) 120 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMINSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59315, 441},
    /*   1 : VMINSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f 5d /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(5d) 110 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMINSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59322, 441},
    /*   2 : VMINSD xmmreg|mask|z,xmmreg*,xmmrm64|sae [rvm:t1s:  evex.nds.lig.f2.0f.w1 5d /r       ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(5d) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VMINSD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+33966, 546},
    /*   3 : VMINSD xmmreg|mask|z,xmmrm64|sae [r+vm:t1s:  evex.nds.lig.f2.0f.w1 5d /r       ] ND,AVX512,FUTURE */
        /* 240(f1 ff 08) 306 001(5d) 110 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VMINSD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+33975, 546},
};

static const struct itemplate instrux_VMINSS[4] = {
    /*   0 : VMINSS xmmreg,xmmreg*,xmmrm32 [rvm:      vex.nds.lig.f3.0f 5d /r           ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(5d) 120 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMINSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59329, 441},
    /*   1 : VMINSS xmmreg,xmmrm32 [r+vm:      vex.nds.lig.f3.0f 5d /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(5d) 110 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMINSS, 2, {XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59336, 441},
    /*   2 : VMINSS xmmreg|mask|z,xmmreg*,xmmrm32|sae [rvm:t1s:  evex.nds.lig.f3.0f.w0 5d /r       ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(5d) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VMINSS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+33984, 546},
    /*   3 : VMINSS xmmreg|mask|z,xmmrm32|sae [r+vm:t1s:  evex.nds.lig.f3.0f.w0 5d /r       ] ND,AVX512,FUTURE */
        /* 240(f1 7e 08) 306 001(5d) 110 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VMINSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+33993, 546},
};

static const struct itemplate instrux_VMOVAPD[13] = {
    /*   0 : VMOVAPD xmmreg,xmmrm128 [rm:       vex.128.66.0f 28 /r               ] AVX,SANDYBRIDGE */
        /* 270(001 001) 001(28) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVAPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59343, 434},
    /*   1 : VMOVAPD xmmrm128,xmmreg [mr:       vex.128.66.0f 29 /r               ] AVX,SANDYBRIDGE */
        /* 270(001 001) 001(29) 101 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVAPD, 2, {RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59350, 434},
    /*   2 : VMOVAPD ymmreg,ymmrm256 [rm:       vex.256.66.0f 28 /r               ] AVX,SANDYBRIDGE */
        /* 270(001 005) 001(28) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVAPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59357, 434},
    /*   3 : VMOVAPD ymmrm256,ymmreg [mr:       vex.256.66.0f 29 /r               ] AVX,SANDYBRIDGE */
        /* 270(001 005) 001(29) 101 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVAPD, 2, {RM_YMM|BITS256|RN_L16,YMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59364, 434},
    /*   4 : VMOVAPD xmmreg|mask|z,xmmrm128 [rm:fvm:   evex.128.66.0f.w1 28 /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 fd 08) 303 001(28) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVAPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34002, 544},
    /*   5 : VMOVAPD ymmreg|mask|z,ymmrm256 [rm:fvm:   evex.256.66.0f.w1 28 /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 fd 28) 303 001(28) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVAPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34011, 544},
    /*   6 : VMOVAPD zmmreg|mask|z,zmmrm512 [rm:fvm:   evex.512.66.0f.w1 28 /r           ] AVX512,FUTURE */
        /* 250(f1 fd 48) 303 001(28) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVAPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34020, 545},
    /*   7 : VMOVAPD xmmreg|mask|z,xmmreg [mr:       evex.128.66.0f.w1 29 /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 fd 08) 300 001(29) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVAPD, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34029, 544},
    /*   8 : VMOVAPD ymmreg|mask|z,ymmreg [mr:       evex.256.66.0f.w1 29 /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 fd 28) 300 001(29) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVAPD, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34038, 544},
    /*   9 : VMOVAPD zmmreg|mask|z,zmmreg [mr:       evex.512.66.0f.w1 29 /r           ] AVX512,FUTURE */
        /* 250(f1 fd 48) 300 001(29) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVAPD, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34047, 545},
    /*  10 : VMOVAPD mem128|mask,xmmreg [mr:fvm:   evex.128.66.0f.w1 29 /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 fd 08) 303 001(29) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVAPD, 2, {MEMORY|BITS128,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+34056, 544},
    /*  11 : VMOVAPD mem256|mask,ymmreg [mr:fvm:   evex.256.66.0f.w1 29 /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 fd 28) 303 001(29) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVAPD, 2, {MEMORY|BITS256,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+34065, 544},
    /*  12 : VMOVAPD mem512|mask,zmmreg [mr:fvm:   evex.512.66.0f.w1 29 /r           ] AVX512,FUTURE */
        /* 250(f1 fd 48) 303 001(29) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVAPD, 2, {MEMORY|BITS512,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+34074, 545},
};

static const struct itemplate instrux_VMOVAPS[13] = {
    /*   0 : VMOVAPS xmmreg,xmmrm128 [rm:       vex.128.0f 28 /r                  ] AVX,SANDYBRIDGE */
        /* 270(001 000) 001(28) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVAPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59371, 434},
    /*   1 : VMOVAPS xmmrm128,xmmreg [mr:       vex.128.0f 29 /r                  ] AVX,SANDYBRIDGE */
        /* 270(001 000) 001(29) 101 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVAPS, 2, {RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59378, 434},
    /*   2 : VMOVAPS ymmreg,ymmrm256 [rm:       vex.256.0f 28 /r                  ] AVX,SANDYBRIDGE */
        /* 270(001 004) 001(28) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVAPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59385, 434},
    /*   3 : VMOVAPS ymmrm256,ymmreg [mr:       vex.256.0f 29 /r                  ] AVX,SANDYBRIDGE */
        /* 270(001 004) 001(29) 101 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVAPS, 2, {RM_YMM|BITS256|RN_L16,YMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59392, 434},
    /*   4 : VMOVAPS xmmreg|mask|z,xmmrm128 [rm:fvm:   evex.128.0f.w0 28 /r              ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7c 08) 303 001(28) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVAPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34083, 544},
    /*   5 : VMOVAPS ymmreg|mask|z,ymmrm256 [rm:fvm:   evex.256.0f.w0 28 /r              ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7c 28) 303 001(28) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVAPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34092, 544},
    /*   6 : VMOVAPS zmmreg|mask|z,zmmrm512 [rm:fvm:   evex.512.0f.w0 28 /r              ] AVX512,FUTURE */
        /* 250(f1 7c 48) 303 001(28) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVAPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34101, 545},
    /*   7 : VMOVAPS xmmreg|mask|z,xmmreg [mr:       evex.128.0f.w0 29 /r              ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7c 08) 300 001(29) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVAPS, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34110, 544},
    /*   8 : VMOVAPS ymmreg|mask|z,ymmreg [mr:       evex.256.0f.w0 29 /r              ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7c 28) 300 001(29) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVAPS, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34119, 544},
    /*   9 : VMOVAPS zmmreg|mask|z,zmmreg [mr:       evex.512.0f.w0 29 /r              ] AVX512,FUTURE */
        /* 250(f1 7c 48) 300 001(29) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVAPS, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34128, 545},
    /*  10 : VMOVAPS mem128|mask,xmmreg [mr:fvm:   evex.128.0f.w0 29 /r              ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7c 08) 303 001(29) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVAPS, 2, {MEMORY|BITS128,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+34137, 544},
    /*  11 : VMOVAPS mem256|mask,ymmreg [mr:fvm:   evex.256.0f.w0 29 /r              ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7c 28) 303 001(29) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVAPS, 2, {MEMORY|BITS256,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+34146, 544},
    /*  12 : VMOVAPS mem512|mask,zmmreg [mr:fvm:   evex.512.0f.w0 29 /r              ] AVX512,FUTURE */
        /* 250(f1 7c 48) 303 001(29) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVAPS, 2, {MEMORY|BITS512,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+34155, 545},
};

static const struct itemplate instrux_VMOVD[6] = {
    /*   0 : VMOVD xmmreg,rm32 [rm:       vex.128.66.0f.w0 6e /r            ] AVX,SANDYBRIDGE */
        /* 270(001 001) 001(6e) 110 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VMOVD, 2, {XMMREG|RN_L16,RM_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59399, 442},
    /*   1 : VMOVD rm32,xmmreg [mr:       vex.128.66.0f.w0 7e /r            ] AVX,SANDYBRIDGE */
        /* 270(001 001) 001(7e) 101 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VMOVD, 2, {RM_GPR|BITS32|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59406, 442},
    /*   2 : VMOVD xmmreg,rm32 [rm:t1s:   evex.128.66.0f.w0 6e /r           ] AVX512,FUTURE */
        /* 250(f1 7d 08) 306 001(6e) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVD, 2, {XMMREG,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+34164, 545},
    /*   3 : VMOVD rm32,xmmreg [mr:t1s:   evex.128.66.0f.w0 7e /r           ] AVX512,FUTURE */
        /* 250(f1 7d 08) 306 001(7e) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVD, 2, {RM_GPR|BITS32,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+34173, 545},
    /*   4 : VMOVD xmmreg,xmmrm32 [rm:t1s:   evex.128.f3.0f.w0 7e /r           ] AVX10_2,FUTURE */
        /* 250(f1 7e 08) 306 001(7e) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VMOVD, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+51057, 645},
    /*   5 : VMOVD xmmrm32,xmmreg [mr:t1s:   evex.128.66.0f.w0 d6 /r           ] AVX10_2,FUTURE */
        /* 250(f1 7d 08) 306 001(d6) 101 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VMOVD, 2, {RM_XMM|BITS32,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+51066, 645},
};

static const struct itemplate instrux_VMOVQ[8] = {
    /*   0 : VMOVQ xmmreg,xmmrm64 [rm:       vex.128.f3.0f 7e /r               ] AR0-1,SQ,AVX,SANDYBRIDGE */
        /* 270(001 002) 001(7e) 110 : AR0,AR1,SQ,NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVQ, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59413, 454},
    /*   1 : VMOVQ xmmrm64,xmmreg [mr:       vex.128.66.0f d6 /r               ] AR0-1,SQ,AVX,SANDYBRIDGE */
        /* 270(001 001) 001(d6) 101 : AR0,AR1,SQ,NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVQ, 2, {RM_XMM|BITS64|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59420, 454},
    /*   2 : VMOVQ xmmreg,rm64 [rm:       vex.128.66.0f.w1 6e /r            ] AR0-1,SQ,LONG,PROT,AVX,X86_64,SANDYBRIDGE */
        /* 270(001 201) 001(6e) 110 : AR0,AR1,SQ,NOAPX,LONG,VEX,PROT,AVX,SANDYBRIDGE */
        {I_VMOVQ, 2, {XMMREG|RN_L16,RM_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59427, 455},
    /*   3 : VMOVQ rm64,xmmreg [mr:       vex.128.66.0f.w1 7e /r            ] AR0-1,SQ,LONG,PROT,AVX,X86_64,SANDYBRIDGE */
        /* 270(001 201) 001(7e) 101 : AR0,AR1,SQ,NOAPX,LONG,VEX,PROT,AVX,SANDYBRIDGE */
        {I_VMOVQ, 2, {RM_GPR|BITS64|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59434, 455},
    /*   4 : VMOVQ xmmreg,rm64 [rm:t1s:   evex.128.66.0f.w1 6e /r           ] AVX512,FUTURE */
        /* 250(f1 fd 08) 306 001(6e) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVQ, 2, {XMMREG,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+34785, 545},
    /*   5 : VMOVQ rm64,xmmreg [mr:t1s:   evex.128.66.0f.w1 7e /r           ] AVX512,FUTURE */
        /* 250(f1 fd 08) 306 001(7e) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVQ, 2, {RM_GPR|BITS64,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+34794, 545},
    /*   6 : VMOVQ xmmreg,xmmrm64 [rm:t1s:   evex.128.f3.0f.w1 7e /r           ] AVX512,FUTURE */
        /* 250(f1 fe 08) 306 001(7e) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVQ, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+34803, 545},
    /*   7 : VMOVQ xmmrm64,xmmreg [mr:t1s:   evex.128.66.0f.w1 d6 /r           ] AVX512,FUTURE */
        /* 250(f1 fd 08) 306 001(d6) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVQ, 2, {RM_XMM|BITS64,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+34812, 545},
};

static const struct itemplate instrux_VMOVDDUP[5] = {
    /*   0 : VMOVDDUP xmmreg,xmmrm64 [rm:       vex.128.f2.0f 12 /r               ] AVX,SANDYBRIDGE */
        /* 270(001 003) 001(12) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVDDUP, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59441, 434},
    /*   1 : VMOVDDUP ymmreg,ymmrm256 [rm:       vex.256.f2.0f 12 /r               ] AVX,SANDYBRIDGE */
        /* 270(001 007) 001(12) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVDDUP, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59448, 434},
    /*   2 : VMOVDDUP xmmreg|mask|z,xmmrm64 [rm:dup:   evex.128.f2.0f.w1 12 /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 ff 08) 320 001(12) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVDDUP, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34182, 544},
    /*   3 : VMOVDDUP ymmreg|mask|z,ymmrm256 [rm:dup:   evex.256.f2.0f.w1 12 /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 ff 28) 320 001(12) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVDDUP, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34191, 544},
    /*   4 : VMOVDDUP zmmreg|mask|z,zmmrm512 [rm:dup:   evex.512.f2.0f.w1 12 /r           ] AVX512,FUTURE */
        /* 250(f1 ff 48) 320 001(12) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVDDUP, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34200, 545},
};

static const struct itemplate instrux_VMOVDQA[4] = {
    /*   0 : VMOVDQA xmmreg,xmmrm128 [rm:       vex.128.66.0f 6f /r               ] AVX,SANDYBRIDGE */
        /* 270(001 001) 001(6f) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVDQA, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59455, 434},
    /*   1 : VMOVDQA xmmrm128,xmmreg [mr:       vex.128.66.0f 7f /r               ] AVX,SANDYBRIDGE */
        /* 270(001 001) 001(7f) 101 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVDQA, 2, {RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59462, 434},
    /*   2 : VMOVDQA ymmreg,ymmrm256 [rm:       vex.256.66.0f 6f /r               ] AVX,SANDYBRIDGE */
        /* 270(001 005) 001(6f) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVDQA, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59469, 434},
    /*   3 : VMOVDQA ymmrm256,ymmreg [mr:       vex.256.66.0f 7f /r               ] AVX,SANDYBRIDGE */
        /* 270(001 005) 001(7f) 101 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVDQA, 2, {RM_YMM|BITS256|RN_L16,YMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59476, 434},
};

static const struct itemplate instrux_VMOVQQA[2] = {
    /*   0 : VMOVQQA ymmreg,ymmrm256 [rm:       vex.256.66.0f 6f /r               ] AVX,SANDYBRIDGE */
        /* 270(001 005) 001(6f) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVQQA, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59469, 434},
    /*   1 : VMOVQQA ymmrm256,ymmreg [mr:       vex.256.66.0f 7f /r               ] AVX,SANDYBRIDGE */
        /* 270(001 005) 001(7f) 101 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVQQA, 2, {RM_YMM|BITS256|RN_L16,YMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59476, 434},
};

static const struct itemplate instrux_VMOVDQU[4] = {
    /*   0 : VMOVDQU xmmreg,xmmrm128 [rm:       vex.128.f3.0f 6f /r               ] AVX,SANDYBRIDGE */
        /* 270(001 002) 001(6f) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVDQU, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59483, 434},
    /*   1 : VMOVDQU xmmrm128,xmmreg [mr:       vex.128.f3.0f 7f /r               ] AVX,SANDYBRIDGE */
        /* 270(001 002) 001(7f) 101 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVDQU, 2, {RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59490, 434},
    /*   2 : VMOVDQU ymmreg,ymmrm256 [rm:       vex.256.f3.0f 6f /r               ] AVX,SANDYBRIDGE */
        /* 270(001 006) 001(6f) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVDQU, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59497, 434},
    /*   3 : VMOVDQU ymmrm256,ymmreg [mr:       vex.256.f3.0f 7f /r               ] AVX,SANDYBRIDGE */
        /* 270(001 006) 001(7f) 101 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVDQU, 2, {RM_YMM|BITS256|RN_L16,YMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59504, 434},
};

static const struct itemplate instrux_VMOVQQU[2] = {
    /*   0 : VMOVQQU ymmreg,ymmrm256 [rm:       vex.256.f3.0f 6f /r               ] AVX,SANDYBRIDGE */
        /* 270(001 006) 001(6f) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVQQU, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59497, 434},
    /*   1 : VMOVQQU ymmrm256,ymmreg [mr:       vex.256.f3.0f 7f /r               ] AVX,SANDYBRIDGE */
        /* 270(001 006) 001(7f) 101 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVQQU, 2, {RM_YMM|BITS256|RN_L16,YMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59504, 434},
};

static const struct itemplate instrux_VMOVHLPS[4] = {
    /*   0 : VMOVHLPS xmmreg,xmmreg*,xmmreg [rvm:      vex.nds.128.0f 12 /r              ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(12) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVHLPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59511, 434},
    /*   1 : VMOVHLPS xmmreg,xmmreg [r+vm:      vex.nds.128.0f 12 /r              ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(12) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVHLPS, 2, {XMMREG|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59518, 434},
    /*   2 : VMOVHLPS xmmreg,xmmreg*,xmmreg [rvm:      evex.nds.128.0f.w0 12 /r          ] AVX512,FUTURE */
        /* 241(f1 7c 08) 300 001(12) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVHLPS, 3, {XMMREG,XMMREG,XMMREG,0,0}, NO_DECORATOR, nasm_bytecodes+34533, 545},
    /*   3 : VMOVHLPS xmmreg,xmmreg [r+vm:      evex.nds.128.0f.w0 12 /r          ] ND,AVX512,FUTURE */
        /* 240(f1 7c 08) 300 001(12) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVHLPS, 2, {XMMREG,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+34542, 545},
};

static const struct itemplate instrux_VMOVHPD[6] = {
    /*   0 : VMOVHPD xmmreg,xmmreg*,mem64 [rvm:      vex.nds.128.66.0f 16 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(16) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVHPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,MEMORY|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59525, 434},
    /*   1 : VMOVHPD xmmreg,mem64 [r+vm:      vex.nds.128.66.0f 16 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(16) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVHPD, 2, {XMMREG|RN_L16,MEMORY|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59532, 434},
    /*   2 : VMOVHPD mem64,xmmreg [mr:       vex.128.66.0f 17 /r               ] AVX,SANDYBRIDGE */
        /* 270(001 001) 001(17) 101 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVHPD, 2, {MEMORY|BITS64|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59539, 434},
    /*   3 : VMOVHPD xmmreg,xmmreg*,mem64 [rvm:t1s:  evex.nds.128.66.0f.w1 16 /r       ] AVX512,FUTURE */
        /* 241(f1 fd 08) 306 001(16) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVHPD, 3, {XMMREG,XMMREG,MEMORY|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+34551, 545},
    /*   4 : VMOVHPD xmmreg,mem64 [r+vm:t1s:  evex.nds.128.66.0f.w1 16 /r       ] ND,AVX512,FUTURE */
        /* 240(f1 fd 08) 306 001(16) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVHPD, 2, {XMMREG,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+34560, 545},
    /*   5 : VMOVHPD mem64,xmmreg [mr:t1s:   evex.128.66.0f.w1 17 /r           ] AVX512,FUTURE */
        /* 250(f1 fd 08) 306 001(17) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVHPD, 2, {MEMORY|BITS64,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+34569, 545},
};

static const struct itemplate instrux_VMOVHPS[6] = {
    /*   0 : VMOVHPS xmmreg,xmmreg*,mem64 [rvm:      vex.nds.128.0f 16 /r              ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(16) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVHPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,MEMORY|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59546, 434},
    /*   1 : VMOVHPS xmmreg,mem64 [r+vm:      vex.nds.128.0f 16 /r              ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(16) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVHPS, 2, {XMMREG|RN_L16,MEMORY|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59553, 434},
    /*   2 : VMOVHPS mem64,xmmreg [mr:       vex.128.0f 17 /r                  ] AVX,SANDYBRIDGE */
        /* 270(001 000) 001(17) 101 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVHPS, 2, {MEMORY|BITS64|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59560, 434},
    /*   3 : VMOVHPS xmmreg,xmmreg*,mem64 [rvm:t2:   evex.nds.128.0f.w0 16 /r          ] AVX512,FUTURE */
        /* 241(f1 7c 08) 311 001(16) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVHPS, 3, {XMMREG,XMMREG,MEMORY|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+34578, 545},
    /*   4 : VMOVHPS xmmreg,mem64 [r+vm:t2:   evex.nds.128.0f.w0 16 /r          ] ND,AVX512,FUTURE */
        /* 240(f1 7c 08) 311 001(16) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVHPS, 2, {XMMREG,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+34587, 545},
    /*   5 : VMOVHPS mem64,xmmreg [mr:t2:    evex.128.0f.w0 17 /r              ] AVX512,FUTURE */
        /* 250(f1 7c 08) 311 001(17) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVHPS, 2, {MEMORY|BITS64,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+34596, 545},
};

static const struct itemplate instrux_VMOVLHPS[4] = {
    /*   0 : VMOVLHPS xmmreg,xmmreg*,xmmreg [rvm:      vex.nds.128.0f 16 /r              ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(16) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVLHPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59546, 434},
    /*   1 : VMOVLHPS xmmreg,xmmreg [r+vm:      vex.nds.128.0f 16 /r              ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(16) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVLHPS, 2, {XMMREG|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59553, 434},
    /*   2 : VMOVLHPS xmmreg,xmmreg*,xmmreg [rvm:      evex.nds.128.0f.w0 16 /r          ] AVX512,FUTURE */
        /* 241(f1 7c 08) 300 001(16) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVLHPS, 3, {XMMREG,XMMREG,XMMREG,0,0}, NO_DECORATOR, nasm_bytecodes+34605, 545},
    /*   3 : VMOVLHPS xmmreg,xmmreg [r+vm:      evex.nds.128.0f.w0 16 /r          ] ND,AVX512,FUTURE */
        /* 240(f1 7c 08) 300 001(16) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVLHPS, 2, {XMMREG,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+34614, 545},
};

static const struct itemplate instrux_VMOVLPD[6] = {
    /*   0 : VMOVLPD xmmreg,xmmreg*,mem64 [rvm:      vex.nds.128.66.0f 12 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(12) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVLPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,MEMORY|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59567, 434},
    /*   1 : VMOVLPD xmmreg,mem64 [r+vm:      vex.nds.128.66.0f 12 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(12) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVLPD, 2, {XMMREG|RN_L16,MEMORY|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59574, 434},
    /*   2 : VMOVLPD mem64,xmmreg [mr:       vex.128.66.0f 13 /r               ] AVX,SANDYBRIDGE */
        /* 270(001 001) 001(13) 101 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVLPD, 2, {MEMORY|BITS64|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59581, 434},
    /*   3 : VMOVLPD xmmreg,xmmreg*,mem64 [rvm:t1s:  evex.nds.128.66.0f.w1 12 /r       ] AVX512,FUTURE */
        /* 241(f1 fd 08) 306 001(12) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVLPD, 3, {XMMREG,XMMREG,MEMORY|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+34623, 545},
    /*   4 : VMOVLPD xmmreg,mem64 [r+vm:t1s:  evex.nds.128.66.0f.w1 12 /r       ] ND,AVX512,FUTURE */
        /* 240(f1 fd 08) 306 001(12) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVLPD, 2, {XMMREG,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+34632, 545},
    /*   5 : VMOVLPD mem64,xmmreg [mr:t1s:   evex.128.66.0f.w1 13 /r           ] AVX512,FUTURE */
        /* 250(f1 fd 08) 306 001(13) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVLPD, 2, {MEMORY|BITS64,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+34641, 545},
};

static const struct itemplate instrux_VMOVLPS[6] = {
    /*   0 : VMOVLPS xmmreg,xmmreg*,mem64 [rvm:      vex.nds.128.0f 12 /r              ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(12) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVLPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,MEMORY|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59511, 434},
    /*   1 : VMOVLPS xmmreg,mem64 [r+vm:      vex.nds.128.0f 12 /r              ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(12) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVLPS, 2, {XMMREG|RN_L16,MEMORY|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59518, 434},
    /*   2 : VMOVLPS mem64,xmmreg [mr:       vex.128.0f 13 /r                  ] AVX,SANDYBRIDGE */
        /* 270(001 000) 001(13) 101 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVLPS, 2, {MEMORY|BITS64|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59588, 434},
    /*   3 : VMOVLPS xmmreg,xmmreg*,mem64 [rvm:t2:   evex.nds.128.0f.w0 12 /r          ] AVX512,FUTURE */
        /* 241(f1 7c 08) 311 001(12) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVLPS, 3, {XMMREG,XMMREG,MEMORY|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+34650, 545},
    /*   4 : VMOVLPS xmmreg,mem64 [r+vm:t2:   evex.nds.128.0f.w0 12 /r          ] ND,AVX512,FUTURE */
        /* 240(f1 7c 08) 311 001(12) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVLPS, 2, {XMMREG,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+34659, 545},
    /*   5 : VMOVLPS mem64,xmmreg [mr:t2:    evex.128.0f.w0 13 /r              ] AVX512,FUTURE */
        /* 250(f1 7c 08) 311 001(13) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVLPS, 2, {MEMORY|BITS64,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+34668, 545},
};

static const struct itemplate instrux_VMOVMSKPD[4] = {
    /*   0 : VMOVMSKPD reg64,xmmreg [rm:       vex.128.66.0f 50 /r               ] LONG,PROT,AVX,X86_64,SANDYBRIDGE */
        /* 270(001 001) 001(50) 110 : NOAPX,WIG,LONG,VEX,PROT,AVX,SANDYBRIDGE */
        {I_VMOVMSKPD, 2, {REG_GPR|BITS64|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59595, 456},
    /*   1 : VMOVMSKPD reg32,xmmreg [rm:       vex.128.66.0f 50 /r               ] AVX,SANDYBRIDGE */
        /* 270(001 001) 001(50) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVMSKPD, 2, {REG_GPR|BITS32|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59595, 434},
    /*   2 : VMOVMSKPD reg64,ymmreg [rm:       vex.256.66.0f 50 /r               ] LONG,PROT,AVX,X86_64,SANDYBRIDGE */
        /* 270(001 005) 001(50) 110 : NOAPX,WIG,LONG,VEX,PROT,AVX,SANDYBRIDGE */
        {I_VMOVMSKPD, 2, {REG_GPR|BITS64|RN_L16,YMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59602, 456},
    /*   3 : VMOVMSKPD reg32,ymmreg [rm:       vex.256.66.0f 50 /r               ] AVX,SANDYBRIDGE */
        /* 270(001 005) 001(50) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVMSKPD, 2, {REG_GPR|BITS32|RN_L16,YMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59602, 434},
};

static const struct itemplate instrux_VMOVMSKPS[4] = {
    /*   0 : VMOVMSKPS reg64,xmmreg [rm:       vex.128.0f 50 /r                  ] LONG,PROT,AVX,X86_64,SANDYBRIDGE */
        /* 270(001 000) 001(50) 110 : NOAPX,WIG,LONG,VEX,PROT,AVX,SANDYBRIDGE */
        {I_VMOVMSKPS, 2, {REG_GPR|BITS64|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59609, 456},
    /*   1 : VMOVMSKPS reg32,xmmreg [rm:       vex.128.0f 50 /r                  ] AVX,SANDYBRIDGE */
        /* 270(001 000) 001(50) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVMSKPS, 2, {REG_GPR|BITS32|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59609, 434},
    /*   2 : VMOVMSKPS reg64,ymmreg [rm:       vex.256.0f 50 /r                  ] LONG,PROT,AVX,X86_64,SANDYBRIDGE */
        /* 270(001 004) 001(50) 110 : NOAPX,WIG,LONG,VEX,PROT,AVX,SANDYBRIDGE */
        {I_VMOVMSKPS, 2, {REG_GPR|BITS64|RN_L16,YMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59616, 456},
    /*   3 : VMOVMSKPS reg32,ymmreg [rm:       vex.256.0f 50 /r                  ] AVX,SANDYBRIDGE */
        /* 270(001 004) 001(50) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVMSKPS, 2, {REG_GPR|BITS32|RN_L16,YMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59616, 434},
};

static const struct itemplate instrux_VMOVNTDQ[5] = {
    /*   0 : VMOVNTDQ mem128,xmmreg [mr:       vex.128.66.0f e7 /r               ] AVX,SANDYBRIDGE */
        /* 270(001 001) 001(e7) 101 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVNTDQ, 2, {MEMORY|BITS128|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59623, 434},
    /*   1 : VMOVNTDQ mem256,ymmreg [mr:       vex.256.66.0f e7 /r               ] AVX,SANDYBRIDGE */
        /* 270(001 005) 001(e7) 101 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVNTDQ, 2, {MEMORY|BITS256|RN_L16,YMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59630, 434},
    /*   2 : VMOVNTDQ mem128,xmmreg [mr:fvm:   evex.128.66.0f.w0 e7 /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7d 08) 303 001(e7) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVNTDQ, 2, {MEMORY|BITS128,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+34677, 544},
    /*   3 : VMOVNTDQ mem256,ymmreg [mr:fvm:   evex.256.66.0f.w0 e7 /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7d 28) 303 001(e7) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVNTDQ, 2, {MEMORY|BITS256,YMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+34686, 544},
    /*   4 : VMOVNTDQ mem512,zmmreg [mr:fvm:   evex.512.66.0f.w0 e7 /r           ] AVX512,FUTURE */
        /* 250(f1 7d 48) 303 001(e7) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVNTDQ, 2, {MEMORY|BITS512,ZMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+34695, 545},
};

static const struct itemplate instrux_VMOVNTQQ[1] = {
    /*   0 : VMOVNTQQ mem256,ymmreg [mr:       vex.256.66.0f e7 /r               ] AVX,SANDYBRIDGE */
        /* 270(001 005) 001(e7) 101 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVNTQQ, 2, {MEMORY|BITS256|RN_L16,YMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59630, 434},
};

static const struct itemplate instrux_VMOVNTDQA[5] = {
    /*   0 : VMOVNTDQA xmmreg,mem128 [rm:       vex.128.66.0f38 2a /r             ] AVX,SANDYBRIDGE */
        /* 270(002 001) 001(2a) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVNTDQA, 2, {XMMREG|RN_L16,MEMORY|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59637, 434},
    /*   1 : VMOVNTDQA ymmreg,mem256 [rm:       vex.256.66.0f38 2a /r             ] AVX2,FUTURE */
        /* 270(002 005) 001(2a) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VMOVNTDQA, 2, {YMMREG|RN_L16,MEMORY|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64341, 468},
    /*   2 : VMOVNTDQA xmmreg,mem128 [rm:fvm:   evex.128.66.0f38.w0 2a /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 08) 303 001(2a) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVNTDQA, 2, {XMMREG,MEMORY|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34704, 544},
    /*   3 : VMOVNTDQA ymmreg,mem256 [rm:fvm:   evex.256.66.0f38.w0 2a /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 28) 303 001(2a) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVNTDQA, 2, {YMMREG,MEMORY|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+34713, 544},
    /*   4 : VMOVNTDQA zmmreg,mem512 [rm:fvm:   evex.512.66.0f38.w0 2a /r         ] AVX512,FUTURE */
        /* 250(f2 7d 48) 303 001(2a) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVNTDQA, 2, {ZMMREG,MEMORY|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+34722, 545},
};

static const struct itemplate instrux_VMOVNTPD[5] = {
    /*   0 : VMOVNTPD mem128,xmmreg [mr:       vex.128.66.0f 2b /r               ] AVX,SANDYBRIDGE */
        /* 270(001 001) 001(2b) 101 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVNTPD, 2, {MEMORY|BITS128|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59644, 434},
    /*   1 : VMOVNTPD mem256,ymmreg [mr:       vex.256.66.0f 2b /r               ] AVX,SANDYBRIDGE */
        /* 270(001 005) 001(2b) 101 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVNTPD, 2, {MEMORY|BITS256|RN_L16,YMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59651, 434},
    /*   2 : VMOVNTPD mem128,xmmreg [mr:fvm:   evex.128.66.0f.w1 2b /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 fd 08) 303 001(2b) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVNTPD, 2, {MEMORY|BITS128,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+34731, 544},
    /*   3 : VMOVNTPD mem256,ymmreg [mr:fvm:   evex.256.66.0f.w1 2b /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 fd 28) 303 001(2b) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVNTPD, 2, {MEMORY|BITS256,YMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+34740, 544},
    /*   4 : VMOVNTPD mem512,zmmreg [mr:fvm:   evex.512.66.0f.w1 2b /r           ] AVX512,FUTURE */
        /* 250(f1 fd 48) 303 001(2b) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVNTPD, 2, {MEMORY|BITS512,ZMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+34749, 545},
};

static const struct itemplate instrux_VMOVNTPS[5] = {
    /*   0 : VMOVNTPS mem128,xmmreg [mr:       vex.128.0f 2b /r                  ] AVX,SANDYBRIDGE */
        /* 270(001 000) 001(2b) 101 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVNTPS, 2, {MEMORY|BITS128|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59658, 434},
    /*   1 : VMOVNTPS mem256,ymmreg [mr:       vex.256.0f 2b /r                  ] AVX,SANDYBRIDGE */
        /* 270(001 004) 001(2b) 101 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVNTPS, 2, {MEMORY|BITS256|RN_L16,YMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59665, 434},
    /*   2 : VMOVNTPS mem128,xmmreg [mr:fvm:   evex.128.0f.w0 2b /r              ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7c 08) 303 001(2b) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVNTPS, 2, {MEMORY|BITS128,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+34758, 544},
    /*   3 : VMOVNTPS mem256,ymmreg [mr:fvm:   evex.256.0f.w0 2b /r              ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7c 28) 303 001(2b) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVNTPS, 2, {MEMORY|BITS256,YMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+34767, 544},
    /*   4 : VMOVNTPS mem512,zmmreg [mr:fvm:   evex.512.0f.w0 2b /r              ] AVX512,FUTURE */
        /* 250(f1 7c 48) 303 001(2b) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVNTPS, 2, {MEMORY|BITS512,ZMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+34776, 545},
};

static const struct itemplate instrux_VMOVSD[12] = {
    /*   0 : VMOVSD xmmreg,xmmreg*,xmmreg [rvm:      vex.nds.lig.f2.0f 10 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(10) 120 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59672, 441},
    /*   1 : VMOVSD xmmreg,xmmreg [r+vm:      vex.nds.lig.f2.0f 10 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(10) 110 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVSD, 2, {XMMREG|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59679, 441},
    /*   2 : VMOVSD xmmreg,mem64 [rm:       vex.lig.f2.0f 10 /r               ] AVX,SANDYBRIDGE */
        /* 270(001 003) 001(10) 110 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVSD, 2, {XMMREG|RN_L16,MEMORY|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59686, 441},
    /*   3 : VMOVSD xmmreg,xmmreg*,xmmreg [mvr:      vex.nds.lig.f2.0f 11 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(11) 102 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59693, 441},
    /*   4 : VMOVSD xmmreg,xmmreg [m+vr:      vex.nds.lig.f2.0f 11 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(11) 101 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVSD, 2, {XMMREG|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59700, 441},
    /*   5 : VMOVSD mem64,xmmreg [mr:       vex.lig.f2.0f 11 /r               ] AVX,SANDYBRIDGE */
        /* 270(001 003) 001(11) 101 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVSD, 2, {MEMORY|BITS64|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59707, 441},
    /*   6 : VMOVSD xmmreg|mask|z,mem64 [rm:t1s:   evex.lig.f2.0f.w1 10 /r           ] AVX512,FUTURE */
        /* 250(f1 ff 08) 306 001(10) 110 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VMOVSD, 2, {XMMREG,MEMORY|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34821, 546},
    /*   7 : VMOVSD mem64|mask,xmmreg [mr:t1s:   evex.lig.f2.0f.w1 11 /r           ] AVX512,FUTURE */
        /* 250(f1 ff 08) 306 001(11) 101 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VMOVSD, 2, {MEMORY|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+34830, 546},
    /*   8 : VMOVSD xmmreg|mask|z,xmmreg*,xmmreg [rvm:      evex.nds.lig.f2.0f.w1 10 /r       ] AVX512,FUTURE */
        /* 241(f1 ff 08) 300 001(10) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VMOVSD, 3, {XMMREG,XMMREG,XMMREG,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34839, 546},
    /*   9 : VMOVSD xmmreg|mask|z,xmmreg [r+vm:      evex.nds.lig.f2.0f.w1 10 /r       ] ND,AVX512,FUTURE */
        /* 240(f1 ff 08) 300 001(10) 110 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VMOVSD, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34848, 546},
    /*  10 : VMOVSD xmmreg|mask|z,xmmreg*,xmmreg [mvr:      evex.nds.lig.f2.0f.w1 11 /r       ] AVX512,FUTURE */
        /* 241(f1 ff 08) 300 001(11) 102 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VMOVSD, 3, {XMMREG,XMMREG,XMMREG,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34857, 546},
    /*  11 : VMOVSD xmmreg|mask|z,xmmreg [m+vr:      evex.nds.lig.f2.0f.w1 11 /r       ] ND,AVX512,FUTURE */
        /* 240(f1 ff 08) 300 001(11) 101 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VMOVSD, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34866, 546},
};

static const struct itemplate instrux_VMOVSHDUP[5] = {
    /*   0 : VMOVSHDUP xmmreg,xmmrm128 [rm:       vex.128.f3.0f 16 /r               ] AVX,SANDYBRIDGE */
        /* 270(001 002) 001(16) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVSHDUP, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59714, 434},
    /*   1 : VMOVSHDUP ymmreg,ymmrm256 [rm:       vex.256.f3.0f 16 /r               ] AVX,SANDYBRIDGE */
        /* 270(001 006) 001(16) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVSHDUP, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59721, 434},
    /*   2 : VMOVSHDUP xmmreg|mask|z,xmmrm128 [rm:fvm:   evex.128.f3.0f.w0 16 /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7e 08) 303 001(16) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVSHDUP, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34875, 544},
    /*   3 : VMOVSHDUP ymmreg|mask|z,ymmrm256 [rm:fvm:   evex.256.f3.0f.w0 16 /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7e 28) 303 001(16) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVSHDUP, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34884, 544},
    /*   4 : VMOVSHDUP zmmreg|mask|z,zmmrm512 [rm:fvm:   evex.512.f3.0f.w0 16 /r           ] AVX512,FUTURE */
        /* 250(f1 7e 48) 303 001(16) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVSHDUP, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34893, 545},
};

static const struct itemplate instrux_VMOVSLDUP[5] = {
    /*   0 : VMOVSLDUP xmmreg,xmmrm128 [rm:       vex.128.f3.0f 12 /r               ] AVX,SANDYBRIDGE */
        /* 270(001 002) 001(12) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVSLDUP, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59728, 434},
    /*   1 : VMOVSLDUP ymmreg,ymmrm256 [rm:       vex.256.f3.0f 12 /r               ] AVX,SANDYBRIDGE */
        /* 270(001 006) 001(12) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVSLDUP, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59735, 434},
    /*   2 : VMOVSLDUP xmmreg|mask|z,xmmrm128 [rm:fvm:   evex.128.f3.0f.w0 12 /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7e 08) 303 001(12) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVSLDUP, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34902, 544},
    /*   3 : VMOVSLDUP ymmreg|mask|z,ymmrm256 [rm:fvm:   evex.256.f3.0f.w0 12 /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7e 28) 303 001(12) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVSLDUP, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34911, 544},
    /*   4 : VMOVSLDUP zmmreg|mask|z,zmmrm512 [rm:fvm:   evex.512.f3.0f.w0 12 /r           ] AVX512,FUTURE */
        /* 250(f1 7e 48) 303 001(12) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVSLDUP, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34920, 545},
};

static const struct itemplate instrux_VMOVSS[12] = {
    /*   0 : VMOVSS xmmreg,xmmreg*,xmmreg [rvm:      vex.nds.lig.f3.0f 10 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(10) 120 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59742, 441},
    /*   1 : VMOVSS xmmreg,xmmreg [r+vm:      vex.nds.lig.f3.0f 10 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(10) 110 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVSS, 2, {XMMREG|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59749, 441},
    /*   2 : VMOVSS xmmreg,mem32 [rm:       vex.lig.f3.0f 10 /r               ] AVX,SANDYBRIDGE */
        /* 270(001 002) 001(10) 110 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVSS, 2, {XMMREG|RN_L16,MEMORY|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59756, 441},
    /*   3 : VMOVSS xmmreg,xmmreg*,xmmreg [mvr:      vex.nds.lig.f3.0f 11 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(11) 102 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59763, 441},
    /*   4 : VMOVSS xmmreg,xmmreg [m+vr:      vex.nds.lig.f3.0f 11 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(11) 101 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVSS, 2, {XMMREG|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59770, 441},
    /*   5 : VMOVSS mem32,xmmreg [mr:       vex.lig.f3.0f 11 /r               ] AVX,SANDYBRIDGE */
        /* 270(001 002) 001(11) 101 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVSS, 2, {MEMORY|BITS32|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59777, 441},
    /*   6 : VMOVSS xmmreg|mask|z,mem32 [rm:t1s:   evex.lig.f3.0f.w0 10 /r           ] AVX512,FUTURE */
        /* 250(f1 7e 08) 306 001(10) 110 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VMOVSS, 2, {XMMREG,MEMORY|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34929, 546},
    /*   7 : VMOVSS mem32|mask,xmmreg [mr:t1s:   evex.lig.f3.0f.w0 11 /r           ] AVX512,FUTURE */
        /* 250(f1 7e 08) 306 001(11) 101 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VMOVSS, 2, {MEMORY|BITS32,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+34938, 546},
    /*   8 : VMOVSS xmmreg|mask|z,xmmreg*,xmmreg [rvm:      evex.nds.lig.f3.0f.w0 10 /r       ] AVX512,FUTURE */
        /* 241(f1 7e 08) 300 001(10) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VMOVSS, 3, {XMMREG,XMMREG,XMMREG,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34947, 546},
    /*   9 : VMOVSS xmmreg|mask|z,xmmreg [r+vm:      evex.nds.lig.f3.0f.w0 10 /r       ] ND,AVX512,FUTURE */
        /* 240(f1 7e 08) 300 001(10) 110 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VMOVSS, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34956, 546},
    /*  10 : VMOVSS xmmreg|mask|z,xmmreg*,xmmreg [mvr:      evex.nds.lig.f3.0f.w0 11 /r       ] AVX512,FUTURE */
        /* 241(f1 7e 08) 300 001(11) 102 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VMOVSS, 3, {XMMREG,XMMREG,XMMREG,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34965, 546},
    /*  11 : VMOVSS xmmreg|mask|z,xmmreg [m+vr:      evex.nds.lig.f3.0f.w0 11 /r       ] ND,AVX512,FUTURE */
        /* 240(f1 7e 08) 300 001(11) 101 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VMOVSS, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34974, 546},
};

static const struct itemplate instrux_VMOVUPD[13] = {
    /*   0 : VMOVUPD xmmreg,xmmrm128 [rm:       vex.128.66.0f 10 /r               ] AVX,SANDYBRIDGE */
        /* 270(001 001) 001(10) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVUPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59784, 434},
    /*   1 : VMOVUPD xmmrm128,xmmreg [mr:       vex.128.66.0f 11 /r               ] AVX,SANDYBRIDGE */
        /* 270(001 001) 001(11) 101 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVUPD, 2, {RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59791, 434},
    /*   2 : VMOVUPD ymmreg,ymmrm256 [rm:       vex.256.66.0f 10 /r               ] AVX,SANDYBRIDGE */
        /* 270(001 005) 001(10) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVUPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59798, 434},
    /*   3 : VMOVUPD ymmrm256,ymmreg [mr:       vex.256.66.0f 11 /r               ] AVX,SANDYBRIDGE */
        /* 270(001 005) 001(11) 101 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVUPD, 2, {RM_YMM|BITS256|RN_L16,YMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59805, 434},
    /*   4 : VMOVUPD xmmreg|mask|z,xmmrm128 [rm:fvm:   evex.128.66.0f.w1 10 /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 fd 08) 303 001(10) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVUPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34983, 544},
    /*   5 : VMOVUPD ymmreg|mask|z,ymmrm256 [rm:fvm:   evex.256.66.0f.w1 10 /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 fd 28) 303 001(10) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVUPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34992, 544},
    /*   6 : VMOVUPD zmmreg|mask|z,zmmrm512 [rm:fvm:   evex.512.66.0f.w1 10 /r           ] AVX512,FUTURE */
        /* 250(f1 fd 48) 303 001(10) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVUPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35001, 545},
    /*   7 : VMOVUPD xmmreg|mask|z,xmmreg [mr:       evex.128.66.0f.w1 11 /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 fd 08) 300 001(11) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVUPD, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35010, 544},
    /*   8 : VMOVUPD ymmreg|mask|z,ymmreg [mr:       evex.256.66.0f.w1 11 /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 fd 28) 300 001(11) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVUPD, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35019, 544},
    /*   9 : VMOVUPD zmmreg|mask|z,zmmreg [mr:       evex.512.66.0f.w1 11 /r           ] AVX512,FUTURE */
        /* 250(f1 fd 48) 300 001(11) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVUPD, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35028, 545},
    /*  10 : VMOVUPD mem128|mask,xmmreg [mr:fvm:   evex.128.66.0f.w1 11 /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 fd 08) 303 001(11) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVUPD, 2, {MEMORY|BITS128,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+35037, 544},
    /*  11 : VMOVUPD mem256|mask,ymmreg [mr:fvm:   evex.256.66.0f.w1 11 /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 fd 28) 303 001(11) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVUPD, 2, {MEMORY|BITS256,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+35046, 544},
    /*  12 : VMOVUPD mem512|mask,zmmreg [mr:fvm:   evex.512.66.0f.w1 11 /r           ] AVX512,FUTURE */
        /* 250(f1 fd 48) 303 001(11) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVUPD, 2, {MEMORY|BITS512,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+35055, 545},
};

static const struct itemplate instrux_VMOVUPS[13] = {
    /*   0 : VMOVUPS xmmreg,xmmrm128 [rm:       vex.128.0f 10 /r                  ] AVX,SANDYBRIDGE */
        /* 270(001 000) 001(10) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVUPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59812, 434},
    /*   1 : VMOVUPS xmmrm128,xmmreg [mr:       vex.128.0f 11 /r                  ] AVX,SANDYBRIDGE */
        /* 270(001 000) 001(11) 101 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVUPS, 2, {RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59819, 434},
    /*   2 : VMOVUPS ymmreg,ymmrm256 [rm:       vex.256.0f 10 /r                  ] AVX,SANDYBRIDGE */
        /* 270(001 004) 001(10) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVUPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59826, 434},
    /*   3 : VMOVUPS ymmrm256,ymmreg [mr:       vex.256.0f 11 /r                  ] AVX,SANDYBRIDGE */
        /* 270(001 004) 001(11) 101 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMOVUPS, 2, {RM_YMM|BITS256|RN_L16,YMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59833, 434},
    /*   4 : VMOVUPS xmmreg|mask|z,xmmrm128 [rm:fvm:   evex.128.0f.w0 10 /r              ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7c 08) 303 001(10) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVUPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35064, 544},
    /*   5 : VMOVUPS ymmreg|mask|z,ymmrm256 [rm:fvm:   evex.256.0f.w0 10 /r              ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7c 28) 303 001(10) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVUPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35073, 544},
    /*   6 : VMOVUPS zmmreg|mask|z,zmmrm512 [rm:fvm:   evex.512.0f.w0 10 /r              ] AVX512,FUTURE */
        /* 250(f1 7c 48) 303 001(10) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVUPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35082, 545},
    /*   7 : VMOVUPS xmmreg|mask|z,xmmreg [mr:       evex.128.0f.w0 11 /r              ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7c 08) 300 001(11) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVUPS, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35091, 544},
    /*   8 : VMOVUPS ymmreg|mask|z,ymmreg [mr:       evex.256.0f.w0 11 /r              ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7c 28) 300 001(11) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVUPS, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35100, 544},
    /*   9 : VMOVUPS zmmreg|mask|z,zmmreg [mr:       evex.512.0f.w0 11 /r              ] AVX512,FUTURE */
        /* 250(f1 7c 48) 300 001(11) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVUPS, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35109, 545},
    /*  10 : VMOVUPS mem128|mask,xmmreg [mr:fvm:   evex.128.0f.w0 11 /r              ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7c 08) 303 001(11) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVUPS, 2, {MEMORY|BITS128,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+35118, 544},
    /*  11 : VMOVUPS mem256|mask,ymmreg [mr:fvm:   evex.256.0f.w0 11 /r              ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7c 28) 303 001(11) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVUPS, 2, {MEMORY|BITS256,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+35127, 544},
    /*  12 : VMOVUPS mem512|mask,zmmreg [mr:fvm:   evex.512.0f.w0 11 /r              ] AVX512,FUTURE */
        /* 250(f1 7c 48) 303 001(11) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVUPS, 2, {MEMORY|BITS512,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+35136, 545},
};

static const struct itemplate instrux_VMPSADBW[7] = {
    /*   0 : VMPSADBW xmmreg,xmmreg*,xmmrm128,imm8 [rvmi:     vex.nds.128.66.0f3a 42 /r ib      ] AVX,SANDYBRIDGE */
        /* 261(003 001) 001(42) 120 023 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMPSADBW, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+51925, 434},
    /*   1 : VMPSADBW xmmreg,xmmrm128,imm8 [r+vmi:     vex.nds.128.66.0f3a 42 /r ib      ] ND,AVX,SANDYBRIDGE */
        /* 260(003 001) 001(42) 110 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMPSADBW, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51933, 434},
    /*   2 : VMPSADBW ymmreg,ymmreg*,ymmrm256,imm8 [rvmi:     vex.nds.256.66.0f3a 42 /r ib      ] AVX2,FUTURE */
        /* 261(003 005) 001(42) 120 023 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VMPSADBW, 4, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+54101, 468},
    /*   3 : VMPSADBW ymmreg,ymmrm256,imm8 [r+vmi:     vex.nds.256.66.0f3a 42 /r ib      ] ND,AVX2,FUTURE */
        /* 260(003 005) 001(42) 110 022 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VMPSADBW, 3, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54109, 468},
    /*   4 : VMPSADBW xmmreg|mask|z,xmmreg,xmmrm128,imm8 [rvmi:fvm: evex.128.f3.0f3a.w0 42 /r ib      ] AVX10_2,FUTURE */
        /* 241(f3 7e 08) 303 001(42) 120 023 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VMPSADBW, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23193, 645},
    /*   5 : VMPSADBW ymmreg|mask|z,ymmreg,ymmrm256,imm8 [rvmi:fvm: evex.256.f3.0f3a.w0 42 /r ib      ] AVX10_2,FUTURE */
        /* 241(f3 7e 28) 303 001(42) 120 023 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VMPSADBW, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23203, 645},
    /*   6 : VMPSADBW zmmreg|mask|z,zmmreg,zmmrm512,imm8 [rvmi:fvm: evex.512.f3.0f3a.w0 42 /r ib      ] AVX10_2,FUTURE */
        /* 241(f3 7e 48) 303 001(42) 120 023 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VMPSADBW, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23213, 645},
};

static const struct itemplate instrux_VMULPD[10] = {
    /*   0 : VMULPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f 59 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(59) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMULPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59840, 434},
    /*   1 : VMULPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f 59 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(59) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMULPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59847, 434},
    /*   2 : VMULPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f 59 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(59) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMULPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59854, 434},
    /*   3 : VMULPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f 59 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(59) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMULPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59861, 434},
    /*   4 : VMULPD xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f.w1 59 /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(59) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMULPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+35145, 544},
    /*   5 : VMULPD xmmreg|mask|z,xmmrm128|b64 [r+vm:fv:   evex.nds.128.66.0f.w1 59 /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 08) 301 001(59) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMULPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+35154, 544},
    /*   6 : VMULPD ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f.w1 59 /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(59) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMULPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+35163, 544},
    /*   7 : VMULPD ymmreg|mask|z,ymmrm256|b64 [r+vm:fv:   evex.nds.256.66.0f.w1 59 /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 28) 301 001(59) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMULPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+35172, 544},
    /*   8 : VMULPD zmmreg|mask|z,zmmreg*,zmmrm512|b64|er [rvm:fv:   evex.nds.512.66.0f.w1 59 /r       ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(59) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VMULPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+35181, 545},
    /*   9 : VMULPD zmmreg|mask|z,zmmrm512|b64|er [r+vm:fv:   evex.nds.512.66.0f.w1 59 /r       ] ND,AVX512,FUTURE */
        /* 240(f1 fd 48) 301 001(59) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VMULPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+35190, 545},
};

static const struct itemplate instrux_VMULPS[10] = {
    /*   0 : VMULPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f 59 /r              ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(59) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMULPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59868, 434},
    /*   1 : VMULPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f 59 /r              ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(59) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMULPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59875, 434},
    /*   2 : VMULPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f 59 /r              ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(59) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMULPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59882, 434},
    /*   3 : VMULPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f 59 /r              ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(59) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMULPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59889, 434},
    /*   4 : VMULPS xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.nds.128.0f.w0 59 /r          ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(59) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMULPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+35199, 544},
    /*   5 : VMULPS xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.nds.128.0f.w0 59 /r          ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7c 08) 301 001(59) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMULPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+35208, 544},
    /*   6 : VMULPS ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.nds.256.0f.w0 59 /r          ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(59) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMULPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+35217, 544},
    /*   7 : VMULPS ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.nds.256.0f.w0 59 /r          ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7c 28) 301 001(59) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMULPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+35226, 544},
    /*   8 : VMULPS zmmreg|mask|z,zmmreg*,zmmrm512|b32|er [rvm:fv:   evex.nds.512.0f.w0 59 /r          ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(59) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VMULPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+35235, 545},
    /*   9 : VMULPS zmmreg|mask|z,zmmrm512|b32|er [r+vm:fv:   evex.nds.512.0f.w0 59 /r          ] ND,AVX512,FUTURE */
        /* 240(f1 7c 48) 301 001(59) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VMULPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+35244, 545},
};

static const struct itemplate instrux_VMULSD[4] = {
    /*   0 : VMULSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f 59 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(59) 120 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMULSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59896, 441},
    /*   1 : VMULSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f 59 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(59) 110 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMULSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59903, 441},
    /*   2 : VMULSD xmmreg|mask|z,xmmreg*,xmmrm64|er [rvm:t1s:  evex.nds.lig.f2.0f.w1 59 /r       ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(59) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VMULSD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+35253, 546},
    /*   3 : VMULSD xmmreg|mask|z,xmmrm64|er [r+vm:t1s:  evex.nds.lig.f2.0f.w1 59 /r       ] ND,AVX512,FUTURE */
        /* 240(f1 ff 08) 306 001(59) 110 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VMULSD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+35262, 546},
};

static const struct itemplate instrux_VMULSS[4] = {
    /*   0 : VMULSS xmmreg,xmmreg*,xmmrm32 [rvm:      vex.nds.lig.f3.0f 59 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(59) 120 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMULSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59910, 441},
    /*   1 : VMULSS xmmreg,xmmrm32 [r+vm:      vex.nds.lig.f3.0f 59 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(59) 110 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VMULSS, 2, {XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59917, 441},
    /*   2 : VMULSS xmmreg|mask|z,xmmreg*,xmmrm32|er [rvm:t1s:  evex.nds.lig.f3.0f.w0 59 /r       ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(59) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VMULSS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+35271, 546},
    /*   3 : VMULSS xmmreg|mask|z,xmmrm32|er [r+vm:t1s:  evex.nds.lig.f3.0f.w0 59 /r       ] ND,AVX512,FUTURE */
        /* 240(f1 7e 08) 306 001(59) 110 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VMULSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+35280, 546},
};

static const struct itemplate instrux_VORPD[10] = {
    /*   0 : VORPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f 56 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(56) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VORPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59924, 434},
    /*   1 : VORPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f 56 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(56) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VORPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59931, 434},
    /*   2 : VORPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f 56 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(56) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VORPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59938, 434},
    /*   3 : VORPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f 56 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(56) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VORPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59945, 434},
    /*   4 : VORPD xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f.w1 56 /r       ] AVX512VL,AVX512DQ,FUTURE */
        /* 241(f1 fd 08) 301 001(56) 120 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VORPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+35289, 547},
    /*   5 : VORPD xmmreg|mask|z,xmmrm128|b64 [r+vm:fv:   evex.nds.128.66.0f.w1 56 /r       ] ND,AVX512VL,AVX512DQ,FUTURE */
        /* 240(f1 fd 08) 301 001(56) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VORPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+35298, 547},
    /*   6 : VORPD ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f.w1 56 /r       ] AVX512VL,AVX512DQ,FUTURE */
        /* 241(f1 fd 28) 301 001(56) 120 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VORPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+35307, 547},
    /*   7 : VORPD ymmreg|mask|z,ymmrm256|b64 [r+vm:fv:   evex.nds.256.66.0f.w1 56 /r       ] ND,AVX512VL,AVX512DQ,FUTURE */
        /* 240(f1 fd 28) 301 001(56) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VORPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+35316, 547},
    /*   8 : VORPD zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv:   evex.nds.512.66.0f.w1 56 /r       ] AVX512DQ,FUTURE */
        /* 241(f1 fd 48) 301 001(56) 120 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VORPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+35325, 548},
    /*   9 : VORPD zmmreg|mask|z,zmmrm512|b64 [r+vm:fv:   evex.nds.512.66.0f.w1 56 /r       ] ND,AVX512DQ,FUTURE */
        /* 240(f1 fd 48) 301 001(56) 110 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VORPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+35334, 548},
};

static const struct itemplate instrux_VORPS[10] = {
    /*   0 : VORPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f 56 /r              ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(56) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VORPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59952, 434},
    /*   1 : VORPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f 56 /r              ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(56) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VORPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59959, 434},
    /*   2 : VORPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f 56 /r              ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(56) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VORPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+59966, 434},
    /*   3 : VORPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f 56 /r              ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(56) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VORPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59973, 434},
    /*   4 : VORPS xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.nds.128.0f.w0 56 /r          ] AVX512VL,AVX512DQ,FUTURE */
        /* 241(f1 7c 08) 301 001(56) 120 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VORPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+35343, 547},
    /*   5 : VORPS xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.nds.128.0f.w0 56 /r          ] ND,AVX512VL,AVX512DQ,FUTURE */
        /* 240(f1 7c 08) 301 001(56) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VORPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+35352, 547},
    /*   6 : VORPS ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.nds.256.0f.w0 56 /r          ] AVX512VL,AVX512DQ,FUTURE */
        /* 241(f1 7c 28) 301 001(56) 120 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VORPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+35361, 547},
    /*   7 : VORPS ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.nds.256.0f.w0 56 /r          ] ND,AVX512VL,AVX512DQ,FUTURE */
        /* 240(f1 7c 28) 301 001(56) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VORPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+35370, 547},
    /*   8 : VORPS zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv:   evex.nds.512.0f.w0 56 /r          ] AVX512DQ,FUTURE */
        /* 241(f1 7c 48) 301 001(56) 120 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VORPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+35379, 548},
    /*   9 : VORPS zmmreg|mask|z,zmmrm512|b32 [r+vm:fv:   evex.nds.512.0f.w0 56 /r          ] ND,AVX512DQ,FUTURE */
        /* 240(f1 7c 48) 301 001(56) 110 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VORPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+35388, 548},
};

static const struct itemplate instrux_VPABSB[5] = {
    /*   0 : VPABSB xmmreg,xmmrm128 [rm:       vex.128.66.0f38 1c /r             ] AVX,SANDYBRIDGE */
        /* 270(002 001) 001(1c) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPABSB, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59980, 434},
    /*   1 : VPABSB ymmreg,ymmrm256 [rm:       vex.256.66.0f38 1c /r             ] AVX2,FUTURE */
        /* 270(002 005) 001(1c) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPABSB, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63081, 468},
    /*   2 : VPABSB xmmreg|mask|z,xmmrm128 [rm:fvm:   evex.128.66.0f38.wig 1c /r        ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7d 08) 303 001(1c) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPABSB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35397, 556},
    /*   3 : VPABSB ymmreg|mask|z,ymmrm256 [rm:fvm:   evex.256.66.0f38.wig 1c /r        ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7d 28) 303 001(1c) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPABSB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35406, 556},
    /*   4 : VPABSB zmmreg|mask|z,zmmrm512 [rm:fvm:   evex.512.66.0f38.wig 1c /r        ] AVX512BW,FUTURE */
        /* 250(f2 7d 48) 303 001(1c) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPABSB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35415, 557},
};

static const struct itemplate instrux_VPABSW[5] = {
    /*   0 : VPABSW xmmreg,xmmrm128 [rm:       vex.128.66.0f38 1d /r             ] AVX,SANDYBRIDGE */
        /* 270(002 001) 001(1d) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPABSW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59987, 434},
    /*   1 : VPABSW ymmreg,ymmrm256 [rm:       vex.256.66.0f38 1d /r             ] AVX2,FUTURE */
        /* 270(002 005) 001(1d) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPABSW, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63088, 468},
    /*   2 : VPABSW xmmreg|mask|z,xmmrm128 [rm:fvm:   evex.128.66.0f38.wig 1d /r        ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7d 08) 303 001(1d) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPABSW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35478, 556},
    /*   3 : VPABSW ymmreg|mask|z,ymmrm256 [rm:fvm:   evex.256.66.0f38.wig 1d /r        ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7d 28) 303 001(1d) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPABSW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35487, 556},
    /*   4 : VPABSW zmmreg|mask|z,zmmrm512 [rm:fvm:   evex.512.66.0f38.wig 1d /r        ] AVX512BW,FUTURE */
        /* 250(f2 7d 48) 303 001(1d) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPABSW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35496, 557},
};

static const struct itemplate instrux_VPABSD[5] = {
    /*   0 : VPABSD xmmreg,xmmrm128 [rm:       vex.128.66.0f38 1e /r             ] AVX,SANDYBRIDGE */
        /* 270(002 001) 001(1e) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPABSD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+59994, 434},
    /*   1 : VPABSD ymmreg,ymmrm256 [rm:       vex.256.66.0f38 1e /r             ] AVX2,FUTURE */
        /* 270(002 005) 001(1e) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPABSD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63095, 468},
    /*   2 : VPABSD xmmreg|mask|z,xmmrm128|b32 [rm:fv:    evex.128.66.0f38.w0 1e /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 08) 301 001(1e) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPABSD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+35424, 544},
    /*   3 : VPABSD ymmreg|mask|z,ymmrm256|b32 [rm:fv:    evex.256.66.0f38.w0 1e /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 28) 301 001(1e) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPABSD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+35433, 544},
    /*   4 : VPABSD zmmreg|mask|z,zmmrm512|b32 [rm:fv:    evex.512.66.0f38.w0 1e /r         ] AVX512,FUTURE */
        /* 250(f2 7d 48) 301 001(1e) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPABSD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+35442, 545},
};

static const struct itemplate instrux_VPACKSSWB[10] = {
    /*   0 : VPACKSSWB xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f 63 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(63) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPACKSSWB, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60001, 434},
    /*   1 : VPACKSSWB xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f 63 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(63) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPACKSSWB, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60008, 434},
    /*   2 : VPACKSSWB ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f 63 /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(63) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPACKSSWB, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63102, 468},
    /*   3 : VPACKSSWB ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f 63 /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(63) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPACKSSWB, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63109, 468},
    /*   4 : VPACKSSWB xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f.wig 63 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 08) 303 001(63) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPACKSSWB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35559, 556},
    /*   5 : VPACKSSWB xmmreg|mask|z,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f.wig 63 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 303 001(63) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPACKSSWB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35568, 556},
    /*   6 : VPACKSSWB ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f.wig 63 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 28) 303 001(63) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPACKSSWB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35577, 556},
    /*   7 : VPACKSSWB ymmreg|mask|z,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f.wig 63 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 303 001(63) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPACKSSWB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35586, 556},
    /*   8 : VPACKSSWB zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f.wig 63 /r      ] AVX512BW,FUTURE */
        /* 241(f1 7d 48) 303 001(63) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPACKSSWB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35595, 557},
    /*   9 : VPACKSSWB zmmreg|mask|z,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f.wig 63 /r      ] ND,AVX512BW,FUTURE */
        /* 240(f1 7d 48) 303 001(63) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPACKSSWB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35604, 557},
};

static const struct itemplate instrux_VPACKSSDW[10] = {
    /*   0 : VPACKSSDW xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f 6b /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(6b) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPACKSSDW, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60015, 434},
    /*   1 : VPACKSSDW xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f 6b /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(6b) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPACKSSDW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60022, 434},
    /*   2 : VPACKSSDW ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f 6b /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(6b) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPACKSSDW, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63116, 468},
    /*   3 : VPACKSSDW ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f 6b /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(6b) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPACKSSDW, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63123, 468},
    /*   4 : VPACKSSDW xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f.w0 6b /r       ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 08) 301 001(6b) 120 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPACKSSDW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+35505, 550},
    /*   5 : VPACKSSDW xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.nds.128.66.0f.w0 6b /r       ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 301 001(6b) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPACKSSDW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+35514, 550},
    /*   6 : VPACKSSDW ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f.w0 6b /r       ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 28) 301 001(6b) 120 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPACKSSDW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+35523, 550},
    /*   7 : VPACKSSDW ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.nds.256.66.0f.w0 6b /r       ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 301 001(6b) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPACKSSDW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+35532, 550},
    /*   8 : VPACKSSDW zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv:   evex.nds.512.66.0f.w0 6b /r       ] AVX512BW,FUTURE */
        /* 241(f1 7d 48) 301 001(6b) 120 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPACKSSDW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+35541, 551},
    /*   9 : VPACKSSDW zmmreg|mask|z,zmmrm512|b32 [r+vm:fv:   evex.nds.512.66.0f.w0 6b /r       ] ND,AVX512BW,FUTURE */
        /* 240(f1 7d 48) 301 001(6b) 110 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPACKSSDW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+35550, 551},
};

static const struct itemplate instrux_VPACKUSWB[10] = {
    /*   0 : VPACKUSWB xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f 67 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(67) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPACKUSWB, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60029, 434},
    /*   1 : VPACKUSWB xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f 67 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(67) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPACKUSWB, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60036, 434},
    /*   2 : VPACKUSWB ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f 67 /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(67) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPACKUSWB, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63144, 468},
    /*   3 : VPACKUSWB ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f 67 /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(67) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPACKUSWB, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63151, 468},
    /*   4 : VPACKUSWB xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f.wig 67 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 08) 303 001(67) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPACKUSWB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35667, 556},
    /*   5 : VPACKUSWB xmmreg|mask|z,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f.wig 67 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 303 001(67) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPACKUSWB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35676, 556},
    /*   6 : VPACKUSWB ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f.wig 67 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 28) 303 001(67) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPACKUSWB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35685, 556},
    /*   7 : VPACKUSWB ymmreg|mask|z,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f.wig 67 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 303 001(67) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPACKUSWB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35694, 556},
    /*   8 : VPACKUSWB zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f.wig 67 /r      ] AVX512BW,FUTURE */
        /* 241(f1 7d 48) 303 001(67) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPACKUSWB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35703, 557},
    /*   9 : VPACKUSWB zmmreg|mask|z,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f.wig 67 /r      ] ND,AVX512BW,FUTURE */
        /* 240(f1 7d 48) 303 001(67) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPACKUSWB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35712, 557},
};

static const struct itemplate instrux_VPACKUSDW[10] = {
    /*   0 : VPACKUSDW xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f38 2b /r         ] AVX,SANDYBRIDGE */
        /* 261(002 001) 001(2b) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPACKUSDW, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60043, 434},
    /*   1 : VPACKUSDW xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f38 2b /r         ] ND,AVX,SANDYBRIDGE */
        /* 260(002 001) 001(2b) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPACKUSDW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60050, 434},
    /*   2 : VPACKUSDW ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f38 2b /r         ] AVX2,FUTURE */
        /* 261(002 005) 001(2b) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPACKUSDW, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63130, 468},
    /*   3 : VPACKUSDW ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f38 2b /r         ] ND,AVX2,FUTURE */
        /* 260(002 005) 001(2b) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPACKUSDW, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63137, 468},
    /*   4 : VPACKUSDW xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f38.w0 2b /r     ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f2 7d 08) 301 001(2b) 120 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPACKUSDW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+35613, 550},
    /*   5 : VPACKUSDW xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.nds.128.66.0f38.w0 2b /r     ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f2 7d 08) 301 001(2b) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPACKUSDW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+35622, 550},
    /*   6 : VPACKUSDW ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f38.w0 2b /r     ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f2 7d 28) 301 001(2b) 120 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPACKUSDW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+35631, 550},
    /*   7 : VPACKUSDW ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.nds.256.66.0f38.w0 2b /r     ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f2 7d 28) 301 001(2b) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPACKUSDW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+35640, 550},
    /*   8 : VPACKUSDW zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv:   evex.nds.512.66.0f38.w0 2b /r     ] AVX512BW,FUTURE */
        /* 241(f2 7d 48) 301 001(2b) 120 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPACKUSDW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+35649, 551},
    /*   9 : VPACKUSDW zmmreg|mask|z,zmmrm512|b32 [r+vm:fv:   evex.nds.512.66.0f38.w0 2b /r     ] ND,AVX512BW,FUTURE */
        /* 240(f2 7d 48) 301 001(2b) 110 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPACKUSDW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+35658, 551},
};

static const struct itemplate instrux_VPADDB[10] = {
    /*   0 : VPADDB xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f fc /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(fc) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPADDB, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60057, 434},
    /*   1 : VPADDB xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f fc /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(fc) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPADDB, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60064, 434},
    /*   2 : VPADDB ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f fc /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(fc) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPADDB, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63158, 468},
    /*   3 : VPADDB ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f fc /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(fc) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPADDB, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63165, 468},
    /*   4 : VPADDB xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f.wig fc /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 08) 303 001(fc) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPADDB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35721, 556},
    /*   5 : VPADDB xmmreg|mask|z,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f.wig fc /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 303 001(fc) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPADDB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35730, 556},
    /*   6 : VPADDB ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f.wig fc /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 28) 303 001(fc) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPADDB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35739, 556},
    /*   7 : VPADDB ymmreg|mask|z,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f.wig fc /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 303 001(fc) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPADDB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35748, 556},
    /*   8 : VPADDB zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f.wig fc /r      ] AVX512BW,FUTURE */
        /* 241(f1 7d 48) 303 001(fc) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPADDB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35757, 557},
    /*   9 : VPADDB zmmreg|mask|z,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f.wig fc /r      ] ND,AVX512BW,FUTURE */
        /* 240(f1 7d 48) 303 001(fc) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPADDB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35766, 557},
};

static const struct itemplate instrux_VPADDW[10] = {
    /*   0 : VPADDW xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f fd /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(fd) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPADDW, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60071, 434},
    /*   1 : VPADDW xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f fd /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(fd) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPADDW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60078, 434},
    /*   2 : VPADDW ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f fd /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(fd) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPADDW, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63172, 468},
    /*   3 : VPADDW ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f fd /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(fd) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPADDW, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63179, 468},
    /*   4 : VPADDW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f.wig fd /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 08) 303 001(fd) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPADDW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36099, 556},
    /*   5 : VPADDW xmmreg|mask|z,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f.wig fd /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 303 001(fd) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPADDW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36108, 556},
    /*   6 : VPADDW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f.wig fd /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 28) 303 001(fd) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPADDW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36117, 556},
    /*   7 : VPADDW ymmreg|mask|z,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f.wig fd /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 303 001(fd) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPADDW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36126, 556},
    /*   8 : VPADDW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f.wig fd /r      ] AVX512BW,FUTURE */
        /* 241(f1 7d 48) 303 001(fd) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPADDW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36135, 557},
    /*   9 : VPADDW zmmreg|mask|z,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f.wig fd /r      ] ND,AVX512BW,FUTURE */
        /* 240(f1 7d 48) 303 001(fd) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPADDW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36144, 557},
};

static const struct itemplate instrux_VPADDD[10] = {
    /*   0 : VPADDD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f fe /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(fe) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPADDD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60085, 434},
    /*   1 : VPADDD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f fe /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(fe) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPADDD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60092, 434},
    /*   2 : VPADDD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f fe /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(fe) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPADDD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63186, 468},
    /*   3 : VPADDD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f fe /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(fe) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPADDD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63193, 468},
    /*   4 : VPADDD xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f.w0 fe /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7d 08) 301 001(fe) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPADDD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+35775, 544},
    /*   5 : VPADDD xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.nds.128.66.0f.w0 fe /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 08) 301 001(fe) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPADDD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+35784, 544},
    /*   6 : VPADDD ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f.w0 fe /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7d 28) 301 001(fe) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPADDD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+35793, 544},
    /*   7 : VPADDD ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.nds.256.66.0f.w0 fe /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 28) 301 001(fe) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPADDD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+35802, 544},
    /*   8 : VPADDD zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv:   evex.nds.512.66.0f.w0 fe /r       ] AVX512,FUTURE */
        /* 241(f1 7d 48) 301 001(fe) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPADDD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+35811, 545},
    /*   9 : VPADDD zmmreg|mask|z,zmmrm512|b32 [r+vm:fv:   evex.nds.512.66.0f.w0 fe /r       ] ND,AVX512,FUTURE */
        /* 240(f1 7d 48) 301 001(fe) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPADDD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+35820, 545},
};

static const struct itemplate instrux_VPADDQ[10] = {
    /*   0 : VPADDQ xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f d4 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(d4) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPADDQ, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60099, 434},
    /*   1 : VPADDQ xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f d4 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(d4) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPADDQ, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60106, 434},
    /*   2 : VPADDQ ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f d4 /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(d4) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPADDQ, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63200, 468},
    /*   3 : VPADDQ ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f d4 /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(d4) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPADDQ, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63207, 468},
    /*   4 : VPADDQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f.w1 d4 /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(d4) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPADDQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+35829, 544},
    /*   5 : VPADDQ xmmreg|mask|z,xmmrm128|b64 [r+vm:fv:   evex.nds.128.66.0f.w1 d4 /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 08) 301 001(d4) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPADDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+35838, 544},
    /*   6 : VPADDQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f.w1 d4 /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(d4) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPADDQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+35847, 544},
    /*   7 : VPADDQ ymmreg|mask|z,ymmrm256|b64 [r+vm:fv:   evex.nds.256.66.0f.w1 d4 /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 28) 301 001(d4) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPADDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+35856, 544},
    /*   8 : VPADDQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv:   evex.nds.512.66.0f.w1 d4 /r       ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(d4) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPADDQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+35865, 545},
    /*   9 : VPADDQ zmmreg|mask|z,zmmrm512|b64 [r+vm:fv:   evex.nds.512.66.0f.w1 d4 /r       ] ND,AVX512,FUTURE */
        /* 240(f1 fd 48) 301 001(d4) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPADDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+35874, 545},
};

static const struct itemplate instrux_VPADDSB[10] = {
    /*   0 : VPADDSB xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f ec /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(ec) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPADDSB, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60113, 434},
    /*   1 : VPADDSB xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f ec /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(ec) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPADDSB, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60120, 434},
    /*   2 : VPADDSB ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f ec /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(ec) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPADDSB, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63214, 468},
    /*   3 : VPADDSB ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f ec /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(ec) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPADDSB, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63221, 468},
    /*   4 : VPADDSB xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f.wig ec /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 08) 303 001(ec) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPADDSB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35883, 556},
    /*   5 : VPADDSB xmmreg|mask|z,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f.wig ec /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 303 001(ec) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPADDSB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35892, 556},
    /*   6 : VPADDSB ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f.wig ec /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 28) 303 001(ec) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPADDSB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35901, 556},
    /*   7 : VPADDSB ymmreg|mask|z,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f.wig ec /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 303 001(ec) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPADDSB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35910, 556},
    /*   8 : VPADDSB zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f.wig ec /r      ] AVX512BW,FUTURE */
        /* 241(f1 7d 48) 303 001(ec) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPADDSB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35919, 557},
    /*   9 : VPADDSB zmmreg|mask|z,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f.wig ec /r      ] ND,AVX512BW,FUTURE */
        /* 240(f1 7d 48) 303 001(ec) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPADDSB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35928, 557},
};

static const struct itemplate instrux_VPADDSW[10] = {
    /*   0 : VPADDSW xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f ed /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(ed) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPADDSW, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60127, 434},
    /*   1 : VPADDSW xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f ed /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(ed) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPADDSW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60134, 434},
    /*   2 : VPADDSW ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f ed /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(ed) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPADDSW, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63228, 468},
    /*   3 : VPADDSW ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f ed /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(ed) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPADDSW, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63235, 468},
    /*   4 : VPADDSW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f.wig ed /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 08) 303 001(ed) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPADDSW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35937, 556},
    /*   5 : VPADDSW xmmreg|mask|z,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f.wig ed /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 303 001(ed) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPADDSW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35946, 556},
    /*   6 : VPADDSW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f.wig ed /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 28) 303 001(ed) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPADDSW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35955, 556},
    /*   7 : VPADDSW ymmreg|mask|z,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f.wig ed /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 303 001(ed) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPADDSW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35964, 556},
    /*   8 : VPADDSW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f.wig ed /r      ] AVX512BW,FUTURE */
        /* 241(f1 7d 48) 303 001(ed) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPADDSW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35973, 557},
    /*   9 : VPADDSW zmmreg|mask|z,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f.wig ed /r      ] ND,AVX512BW,FUTURE */
        /* 240(f1 7d 48) 303 001(ed) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPADDSW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35982, 557},
};

static const struct itemplate instrux_VPADDUSB[10] = {
    /*   0 : VPADDUSB xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f dc /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(dc) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPADDUSB, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60141, 434},
    /*   1 : VPADDUSB xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f dc /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(dc) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPADDUSB, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60148, 434},
    /*   2 : VPADDUSB ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f dc /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(dc) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPADDUSB, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63242, 468},
    /*   3 : VPADDUSB ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f dc /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(dc) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPADDUSB, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63249, 468},
    /*   4 : VPADDUSB xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f.wig dc /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 08) 303 001(dc) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPADDUSB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+35991, 556},
    /*   5 : VPADDUSB xmmreg|mask|z,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f.wig dc /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 303 001(dc) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPADDUSB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36000, 556},
    /*   6 : VPADDUSB ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f.wig dc /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 28) 303 001(dc) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPADDUSB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36009, 556},
    /*   7 : VPADDUSB ymmreg|mask|z,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f.wig dc /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 303 001(dc) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPADDUSB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36018, 556},
    /*   8 : VPADDUSB zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f.wig dc /r      ] AVX512BW,FUTURE */
        /* 241(f1 7d 48) 303 001(dc) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPADDUSB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36027, 557},
    /*   9 : VPADDUSB zmmreg|mask|z,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f.wig dc /r      ] ND,AVX512BW,FUTURE */
        /* 240(f1 7d 48) 303 001(dc) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPADDUSB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36036, 557},
};

static const struct itemplate instrux_VPADDUSW[10] = {
    /*   0 : VPADDUSW xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f dd /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(dd) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPADDUSW, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60155, 434},
    /*   1 : VPADDUSW xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f dd /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(dd) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPADDUSW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60162, 434},
    /*   2 : VPADDUSW ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f dd /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(dd) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPADDUSW, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63256, 468},
    /*   3 : VPADDUSW ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f dd /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(dd) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPADDUSW, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63263, 468},
    /*   4 : VPADDUSW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f.wig dd /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 08) 303 001(dd) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPADDUSW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36045, 556},
    /*   5 : VPADDUSW xmmreg|mask|z,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f.wig dd /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 303 001(dd) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPADDUSW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36054, 556},
    /*   6 : VPADDUSW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f.wig dd /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 28) 303 001(dd) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPADDUSW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36063, 556},
    /*   7 : VPADDUSW ymmreg|mask|z,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f.wig dd /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 303 001(dd) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPADDUSW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36072, 556},
    /*   8 : VPADDUSW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f.wig dd /r      ] AVX512BW,FUTURE */
        /* 241(f1 7d 48) 303 001(dd) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPADDUSW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36081, 557},
    /*   9 : VPADDUSW zmmreg|mask|z,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f.wig dd /r      ] ND,AVX512BW,FUTURE */
        /* 240(f1 7d 48) 303 001(dd) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPADDUSW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36090, 557},
};

static const struct itemplate instrux_VPALIGNR[10] = {
    /*   0 : VPALIGNR xmmreg,xmmreg*,xmmrm128,imm8 [rvmi:     vex.nds.128.66.0f3a 0f /r ib      ] AVX,SANDYBRIDGE */
        /* 261(003 001) 001(0f) 120 023 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPALIGNR, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+51941, 434},
    /*   1 : VPALIGNR xmmreg,xmmrm128,imm8 [r+vmi:     vex.nds.128.66.0f3a 0f /r ib      ] ND,AVX,SANDYBRIDGE */
        /* 260(003 001) 001(0f) 110 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPALIGNR, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51949, 434},
    /*   2 : VPALIGNR ymmreg,ymmreg*,ymmrm256,imm8 [rvmi:     vex.nds.256.66.0f3a 0f /r ib      ] AVX2,FUTURE */
        /* 261(003 005) 001(0f) 120 023 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPALIGNR, 4, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+54117, 468},
    /*   3 : VPALIGNR ymmreg,ymmrm256,imm8 [r+vmi:     vex.nds.256.66.0f3a 0f /r ib      ] ND,AVX2,FUTURE */
        /* 260(003 005) 001(0f) 110 022 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPALIGNR, 3, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54125, 468},
    /*   4 : VPALIGNR xmmreg|mask|z,xmmreg*,xmmrm128,imm8 [rvmi:fvm: evex.nds.128.66.0f3a.wig 0f /r ib ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 08) 303 001(0f) 120 023 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPALIGNR, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19453, 556},
    /*   5 : VPALIGNR xmmreg|mask|z,xmmrm128,imm8 [r+vmi:fvm: evex.nds.128.66.0f3a.wig 0f /r ib ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f3 7d 08) 303 001(0f) 110 022 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPALIGNR, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19463, 556},
    /*   6 : VPALIGNR ymmreg|mask|z,ymmreg*,ymmrm256,imm8 [rvmi:fvm: evex.nds.256.66.0f3a.wig 0f /r ib ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 28) 303 001(0f) 120 023 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPALIGNR, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19473, 556},
    /*   7 : VPALIGNR ymmreg|mask|z,ymmrm256,imm8 [r+vmi:fvm: evex.nds.256.66.0f3a.wig 0f /r ib ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f3 7d 28) 303 001(0f) 110 022 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPALIGNR, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19483, 556},
    /*   8 : VPALIGNR zmmreg|mask|z,zmmreg*,zmmrm512,imm8 [rvmi:fvm: evex.nds.512.66.0f3a.wig 0f /r ib ] AVX512BW,FUTURE */
        /* 241(f3 7d 48) 303 001(0f) 120 023 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPALIGNR, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19493, 557},
    /*   9 : VPALIGNR zmmreg|mask|z,zmmrm512,imm8 [r+vmi:fvm: evex.nds.512.66.0f3a.wig 0f /r ib ] ND,AVX512BW,FUTURE */
        /* 240(f3 7d 48) 303 001(0f) 110 022 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPALIGNR, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19503, 557},
};

static const struct itemplate instrux_VPAND[4] = {
    /*   0 : VPAND xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f db /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(db) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPAND, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60169, 434},
    /*   1 : VPAND xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f db /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(db) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPAND, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60176, 434},
    /*   2 : VPAND ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f db /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(db) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPAND, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63270, 468},
    /*   3 : VPAND ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f db /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(db) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPAND, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63277, 468},
};

static const struct itemplate instrux_VPANDN[4] = {
    /*   0 : VPANDN xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f df /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(df) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPANDN, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60183, 434},
    /*   1 : VPANDN xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f df /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(df) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPANDN, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60190, 434},
    /*   2 : VPANDN ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f df /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(df) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPANDN, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63284, 468},
    /*   3 : VPANDN ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f df /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(df) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPANDN, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63291, 468},
};

static const struct itemplate instrux_VPAVGB[10] = {
    /*   0 : VPAVGB xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f e0 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(e0) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPAVGB, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60197, 434},
    /*   1 : VPAVGB xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f e0 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(e0) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPAVGB, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60204, 434},
    /*   2 : VPAVGB ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f e0 /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(e0) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPAVGB, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63298, 468},
    /*   3 : VPAVGB ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f e0 /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(e0) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPAVGB, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63305, 468},
    /*   4 : VPAVGB xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f.wig e0 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 08) 303 001(e0) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPAVGB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36369, 556},
    /*   5 : VPAVGB xmmreg|mask|z,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f.wig e0 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 303 001(e0) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPAVGB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36378, 556},
    /*   6 : VPAVGB ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f.wig e0 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 28) 303 001(e0) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPAVGB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36387, 556},
    /*   7 : VPAVGB ymmreg|mask|z,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f.wig e0 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 303 001(e0) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPAVGB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36396, 556},
    /*   8 : VPAVGB zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f.wig e0 /r      ] AVX512BW,FUTURE */
        /* 241(f1 7d 48) 303 001(e0) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPAVGB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36405, 557},
    /*   9 : VPAVGB zmmreg|mask|z,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f.wig e0 /r      ] ND,AVX512BW,FUTURE */
        /* 240(f1 7d 48) 303 001(e0) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPAVGB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36414, 557},
};

static const struct itemplate instrux_VPAVGW[10] = {
    /*   0 : VPAVGW xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f e3 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(e3) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPAVGW, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60211, 434},
    /*   1 : VPAVGW xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f e3 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(e3) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPAVGW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60218, 434},
    /*   2 : VPAVGW ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f e3 /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(e3) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPAVGW, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63312, 468},
    /*   3 : VPAVGW ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f e3 /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(e3) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPAVGW, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63319, 468},
    /*   4 : VPAVGW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f.wig e3 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 08) 303 001(e3) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPAVGW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36423, 556},
    /*   5 : VPAVGW xmmreg|mask|z,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f.wig e3 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 303 001(e3) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPAVGW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36432, 556},
    /*   6 : VPAVGW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f.wig e3 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 28) 303 001(e3) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPAVGW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36441, 556},
    /*   7 : VPAVGW ymmreg|mask|z,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f.wig e3 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 303 001(e3) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPAVGW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36450, 556},
    /*   8 : VPAVGW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f.wig e3 /r      ] AVX512BW,FUTURE */
        /* 241(f1 7d 48) 303 001(e3) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPAVGW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36459, 557},
    /*   9 : VPAVGW zmmreg|mask|z,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f.wig e3 /r      ] ND,AVX512BW,FUTURE */
        /* 240(f1 7d 48) 303 001(e3) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPAVGW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36468, 557},
};

static const struct itemplate instrux_VPBLENDVB[4] = {
    /*   0 : VPBLENDVB xmmreg,xmmreg*,xmmrm128,xmmreg [rvms:     vex.nds.128.66.0f3a.w0 4c /r /is4 ] AVX,SANDYBRIDGE */
        /* 261(003 001) 001(4c) 120 177 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VPBLENDVB, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+51957, 442},
    /*   1 : VPBLENDVB xmmreg,xmmrm128,xmmreg [r+vms:     vex.nds.128.66.0f3a.w0 4c /r /is4 ] ND,AVX,SANDYBRIDGE */
        /* 260(003 001) 001(4c) 110 176 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VPBLENDVB, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+51965, 442},
    /*   2 : VPBLENDVB ymmreg,ymmreg*,ymmrm256,ymmreg [rvms:     vex.nds.256.66.0f3a 4c /r /is4    ] AVX2,FUTURE */
        /* 261(003 005) 001(4c) 120 177 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPBLENDVB, 4, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,YMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+54133, 468},
    /*   3 : VPBLENDVB ymmreg,ymmrm256,ymmreg [r+vms:     vex.nds.256.66.0f3a 4c /r /is4    ] ND,AVX2,FUTURE */
        /* 260(003 005) 001(4c) 110 176 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPBLENDVB, 3, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,YMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+54141, 468},
};

static const struct itemplate instrux_VPBLENDW[4] = {
    /*   0 : VPBLENDW xmmreg,xmmreg*,xmmrm128,imm8 [rvmi:     vex.nds.128.66.0f3a 0e /r ib      ] AVX,SANDYBRIDGE */
        /* 261(003 001) 001(0e) 120 023 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPBLENDW, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+51973, 434},
    /*   1 : VPBLENDW xmmreg,xmmrm128,imm8 [r+vmi:     vex.nds.128.66.0f3a 0e /r ib      ] ND,AVX,SANDYBRIDGE */
        /* 260(003 001) 001(0e) 110 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPBLENDW, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51981, 434},
    /*   2 : VPBLENDW ymmreg,ymmreg*,ymmrm256,imm8 [rvmi:     vex.nds.256.66.0f3a 0e /r ib      ] AVX2,FUTURE */
        /* 261(003 005) 001(0e) 120 023 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPBLENDW, 4, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+54149, 468},
    /*   3 : VPBLENDW ymmreg,ymmrm256,imm8 [r+vmi:     vex.nds.256.66.0f3a 0e /r ib      ] ND,AVX2,FUTURE */
        /* 260(003 005) 001(0e) 110 022 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPBLENDW, 3, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54157, 468},
};

static const struct itemplate instrux_VPCMPESTRI[1] = {
    /*   0 : VPCMPESTRI xmmreg,xmmrm128,imm8 [rmi:      vex.128.66.0f3a 61 /r ib          ] AVX,SANDYBRIDGE */
        /* 270(003 001) 001(61) 110 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPCMPESTRI, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51989, 434},
};

static const struct itemplate instrux_VPCMPESTRM[1] = {
    /*   0 : VPCMPESTRM xmmreg,xmmrm128,imm8 [rmi:      vex.128.66.0f3a 60 /r ib          ] AVX,SANDYBRIDGE */
        /* 270(003 001) 001(60) 110 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPCMPESTRM, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+51997, 434},
};

static const struct itemplate instrux_VPCMPISTRI[1] = {
    /*   0 : VPCMPISTRI xmmreg,xmmrm128,imm8 [rmi:      vex.128.66.0f3a 63 /r ib          ] AVX,SANDYBRIDGE */
        /* 270(003 001) 001(63) 110 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPCMPISTRI, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52005, 434},
};

static const struct itemplate instrux_VPCMPISTRM[1] = {
    /*   0 : VPCMPISTRM xmmreg,xmmrm128,imm8 [rmi:      vex.128.66.0f3a 62 /r ib          ] AVX,SANDYBRIDGE */
        /* 270(003 001) 001(62) 110 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPCMPISTRM, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52013, 434},
};

static const struct itemplate instrux_VPCMPEQB[10] = {
    /*   0 : VPCMPEQB xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f 74 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(74) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPCMPEQB, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60225, 434},
    /*   1 : VPCMPEQB xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f 74 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(74) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPCMPEQB, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60232, 434},
    /*   2 : VPCMPEQB ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f 74 /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(74) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPCMPEQB, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63326, 468},
    /*   3 : VPCMPEQB ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f 74 /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(74) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPCMPEQB, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63333, 468},
    /*   4 : VPCMPEQB kreg|mask,xmmreg,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f.wig 74 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 08) 303 001(74) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPEQB, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+36909, 556},
    /*   5 : VPCMPEQB kreg|mask,ymmreg,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f.wig 74 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 28) 303 001(74) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPEQB, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+36918, 556},
    /*   6 : VPCMPEQB kreg|mask,zmmreg,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f.wig 74 /r      ] AVX512BW,FUTURE */
        /* 241(f1 7d 48) 303 001(74) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPEQB, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+36927, 557},
    /*   7 : VPCMPEQB kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w0 3f /r 00  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 08) 303 001(3f) 120 001(00) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPEQB, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+7559, 550},
    /*   8 : VPCMPEQB kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w0 3f /r 00  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 28) 303 001(3f) 120 001(00) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPEQB, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+7570, 550},
    /*   9 : VPCMPEQB kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w0 3f /r 00  ] AVX512BW,FUTURE */
        /* 241(f3 7d 48) 303 001(3f) 120 001(00) : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPEQB, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+7581, 551},
};

static const struct itemplate instrux_VPCMPEQW[10] = {
    /*   0 : VPCMPEQW xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f 75 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(75) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPCMPEQW, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60239, 434},
    /*   1 : VPCMPEQW xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f 75 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(75) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPCMPEQW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60246, 434},
    /*   2 : VPCMPEQW ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f 75 /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(75) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPCMPEQW, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63340, 468},
    /*   3 : VPCMPEQW ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f 75 /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(75) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPCMPEQW, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63347, 468},
    /*   4 : VPCMPEQW kreg|mask,xmmreg,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f.wig 75 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 08) 303 001(75) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPEQW, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+36990, 556},
    /*   5 : VPCMPEQW kreg|mask,ymmreg,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f.wig 75 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 28) 303 001(75) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPEQW, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+36999, 556},
    /*   6 : VPCMPEQW kreg|mask,zmmreg,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f.wig 75 /r      ] AVX512BW,FUTURE */
        /* 241(f1 7d 48) 303 001(75) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPEQW, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+37008, 557},
    /*   7 : VPCMPEQW kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w1 3f /r 00  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 fd 08) 303 001(3f) 120 001(00) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPEQW, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+7790, 550},
    /*   8 : VPCMPEQW kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w1 3f /r 00  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 fd 28) 303 001(3f) 120 001(00) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPEQW, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+7801, 550},
    /*   9 : VPCMPEQW kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w1 3f /r 00  ] AVX512BW,FUTURE */
        /* 241(f3 fd 48) 303 001(3f) 120 001(00) : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPEQW, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+7812, 551},
};

static const struct itemplate instrux_VPCMPEQD[10] = {
    /*   0 : VPCMPEQD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f 76 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(76) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPCMPEQD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60253, 434},
    /*   1 : VPCMPEQD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f 76 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(76) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPCMPEQD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60260, 434},
    /*   2 : VPCMPEQD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f 76 /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(76) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPCMPEQD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63354, 468},
    /*   3 : VPCMPEQD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f 76 /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(76) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPCMPEQD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63361, 468},
    /*   4 : VPCMPEQD kreg|mask,xmmreg,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f.w0 76 /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7d 08) 301 001(76) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPEQD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+36936, 544},
    /*   5 : VPCMPEQD kreg|mask,ymmreg,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f.w0 76 /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7d 28) 301 001(76) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPEQD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+36945, 544},
    /*   6 : VPCMPEQD kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv:   evex.nds.512.66.0f.w0 76 /r       ] AVX512,FUTURE */
        /* 241(f1 7d 48) 301 001(76) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPEQD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+36954, 545},
    /*   7 : VPCMPEQD kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.66.0f3a.w0 1f /r 00  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 08) 301 001(1f) 120 001(00) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPEQD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+7592, 544},
    /*   8 : VPCMPEQD kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.66.0f3a.w0 1f /r 00  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 28) 301 001(1f) 120 001(00) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPEQD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+7603, 544},
    /*   9 : VPCMPEQD kreg|mask,zmmreg,zmmrm512|b32 [rvmi:fv:  evex.nds.512.66.0f3a.w0 1f /r 00  ] AVX512,FUTURE */
        /* 241(f3 7d 48) 301 001(1f) 120 001(00) : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPEQD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+7614, 545},
};

static const struct itemplate instrux_VPCMPEQQ[10] = {
    /*   0 : VPCMPEQQ xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f38 29 /r         ] AVX,SANDYBRIDGE */
        /* 261(002 001) 001(29) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPCMPEQQ, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60267, 434},
    /*   1 : VPCMPEQQ xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f38 29 /r         ] ND,AVX,SANDYBRIDGE */
        /* 260(002 001) 001(29) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPCMPEQQ, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60274, 434},
    /*   2 : VPCMPEQQ ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f38 29 /r         ] AVX2,FUTURE */
        /* 261(002 005) 001(29) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPCMPEQQ, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63368, 468},
    /*   3 : VPCMPEQQ ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f38 29 /r         ] ND,AVX2,FUTURE */
        /* 260(002 005) 001(29) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPCMPEQQ, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63375, 468},
    /*   4 : VPCMPEQQ kreg|mask,xmmreg,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 29 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 08) 301 001(29) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPEQQ, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+36963, 544},
    /*   5 : VPCMPEQQ kreg|mask,ymmreg,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 29 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 28) 301 001(29) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPEQQ, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+36972, 544},
    /*   6 : VPCMPEQQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv:   evex.nds.512.66.0f38.w1 29 /r     ] AVX512,FUTURE */
        /* 241(f2 fd 48) 301 001(29) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPEQQ, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+36981, 545},
    /*   7 : VPCMPEQQ kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f3a.w1 1f /r 00  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 08) 301 001(1f) 120 001(00) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPEQQ, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+7625, 544},
    /*   8 : VPCMPEQQ kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f3a.w1 1f /r 00  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 28) 301 001(1f) 120 001(00) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPEQQ, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+7636, 544},
    /*   9 : VPCMPEQQ kreg|mask,zmmreg,zmmrm512|b64 [rvmi:fv:  evex.nds.512.66.0f3a.w1 1f /r 00  ] AVX512,FUTURE */
        /* 241(f3 fd 48) 301 001(1f) 120 001(00) : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPEQQ, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+7647, 545},
};

static const struct itemplate instrux_VPCMPGTB[10] = {
    /*   0 : VPCMPGTB xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f 64 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(64) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPCMPGTB, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60281, 434},
    /*   1 : VPCMPGTB xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f 64 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(64) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPCMPGTB, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60288, 434},
    /*   2 : VPCMPGTB ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f 64 /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(64) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPCMPGTB, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63382, 468},
    /*   3 : VPCMPGTB ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f 64 /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(64) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPCMPGTB, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63389, 468},
    /*   4 : VPCMPGTB kreg|mask,xmmreg,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f.wig 64 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 08) 303 001(64) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPGTB, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+37017, 556},
    /*   5 : VPCMPGTB kreg|mask,ymmreg,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f.wig 64 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 28) 303 001(64) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPGTB, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+37026, 556},
    /*   6 : VPCMPGTB kreg|mask,zmmreg,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f.wig 64 /r      ] AVX512BW,FUTURE */
        /* 241(f1 7d 48) 303 001(64) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPGTB, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+37035, 557},
    /*   7 : VPCMPGTB kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w0 3f /r 06  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 08) 303 001(3f) 120 001(06) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPGTB, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8087, 550},
    /*   8 : VPCMPGTB kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w0 3f /r 06  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 28) 303 001(3f) 120 001(06) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPGTB, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8098, 550},
    /*   9 : VPCMPGTB kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w0 3f /r 06  ] AVX512BW,FUTURE */
        /* 241(f3 7d 48) 303 001(3f) 120 001(06) : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPGTB, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8109, 551},
};

static const struct itemplate instrux_VPCMPGTW[10] = {
    /*   0 : VPCMPGTW xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f 65 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(65) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPCMPGTW, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60295, 434},
    /*   1 : VPCMPGTW xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f 65 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(65) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPCMPGTW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60302, 434},
    /*   2 : VPCMPGTW ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f 65 /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(65) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPCMPGTW, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63396, 468},
    /*   3 : VPCMPGTW ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f 65 /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(65) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPCMPGTW, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63403, 468},
    /*   4 : VPCMPGTW kreg|mask,xmmreg,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f.wig 65 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 08) 303 001(65) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPGTW, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+37098, 556},
    /*   5 : VPCMPGTW kreg|mask,ymmreg,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f.wig 65 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 28) 303 001(65) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPGTW, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+37107, 556},
    /*   6 : VPCMPGTW kreg|mask,zmmreg,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f.wig 65 /r      ] AVX512BW,FUTURE */
        /* 241(f1 7d 48) 303 001(65) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPGTW, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+37116, 557},
    /*   7 : VPCMPGTW kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w1 3f /r 06  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 fd 08) 303 001(3f) 120 001(06) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPGTW, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8318, 550},
    /*   8 : VPCMPGTW kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w1 3f /r 06  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 fd 28) 303 001(3f) 120 001(06) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPGTW, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8329, 550},
    /*   9 : VPCMPGTW kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w1 3f /r 06  ] AVX512BW,FUTURE */
        /* 241(f3 fd 48) 303 001(3f) 120 001(06) : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPGTW, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8340, 551},
};

static const struct itemplate instrux_VPCMPGTD[10] = {
    /*   0 : VPCMPGTD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f 66 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(66) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPCMPGTD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60309, 434},
    /*   1 : VPCMPGTD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f 66 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(66) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPCMPGTD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60316, 434},
    /*   2 : VPCMPGTD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f 66 /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(66) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPCMPGTD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63410, 468},
    /*   3 : VPCMPGTD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f 66 /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(66) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPCMPGTD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63417, 468},
    /*   4 : VPCMPGTD kreg|mask,xmmreg,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f.w0 66 /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7d 08) 301 001(66) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPGTD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+37044, 544},
    /*   5 : VPCMPGTD kreg|mask,ymmreg,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f.w0 66 /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7d 28) 301 001(66) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPGTD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+37053, 544},
    /*   6 : VPCMPGTD kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv:   evex.nds.512.66.0f.w0 66 /r       ] AVX512,FUTURE */
        /* 241(f1 7d 48) 301 001(66) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPGTD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+37062, 545},
    /*   7 : VPCMPGTD kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.66.0f3a.w0 1f /r 06  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 08) 301 001(1f) 120 001(06) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPGTD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+8120, 544},
    /*   8 : VPCMPGTD kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.66.0f3a.w0 1f /r 06  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 28) 301 001(1f) 120 001(06) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPGTD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+8131, 544},
    /*   9 : VPCMPGTD kreg|mask,zmmreg,zmmrm512|b32 [rvmi:fv:  evex.nds.512.66.0f3a.w0 1f /r 06  ] AVX512,FUTURE */
        /* 241(f3 7d 48) 301 001(1f) 120 001(06) : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPGTD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+8142, 545},
};

static const struct itemplate instrux_VPCMPGTQ[10] = {
    /*   0 : VPCMPGTQ xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f38 37 /r         ] AVX,SANDYBRIDGE */
        /* 261(002 001) 001(37) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPCMPGTQ, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60323, 434},
    /*   1 : VPCMPGTQ xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f38 37 /r         ] ND,AVX,SANDYBRIDGE */
        /* 260(002 001) 001(37) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPCMPGTQ, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60330, 434},
    /*   2 : VPCMPGTQ ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f38 37 /r         ] AVX2,FUTURE */
        /* 261(002 005) 001(37) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPCMPGTQ, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63424, 468},
    /*   3 : VPCMPGTQ ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f38 37 /r         ] ND,AVX2,FUTURE */
        /* 260(002 005) 001(37) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPCMPGTQ, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63431, 468},
    /*   4 : VPCMPGTQ kreg|mask,xmmreg,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 37 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 08) 301 001(37) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPGTQ, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+37071, 544},
    /*   5 : VPCMPGTQ kreg|mask,ymmreg,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 37 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 28) 301 001(37) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPGTQ, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+37080, 544},
    /*   6 : VPCMPGTQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv:   evex.nds.512.66.0f38.w1 37 /r     ] AVX512,FUTURE */
        /* 241(f2 fd 48) 301 001(37) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPGTQ, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+37089, 545},
    /*   7 : VPCMPGTQ kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f3a.w1 1f /r 06  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 08) 301 001(1f) 120 001(06) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPGTQ, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+8153, 544},
    /*   8 : VPCMPGTQ kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f3a.w1 1f /r 06  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 28) 301 001(1f) 120 001(06) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPGTQ, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+8164, 544},
    /*   9 : VPCMPGTQ kreg|mask,zmmreg,zmmrm512|b64 [rvmi:fv:  evex.nds.512.66.0f3a.w1 1f /r 06  ] AVX512,FUTURE */
        /* 241(f3 fd 48) 301 001(1f) 120 001(06) : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPGTQ, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+8175, 545},
};

static const struct itemplate instrux_VPERMILPD[15] = {
    /*   0 : VPERMILPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f38.w0 0d /r      ] AVX,SANDYBRIDGE */
        /* 261(002 001) 001(0d) 120 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VPERMILPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60337, 442},
    /*   1 : VPERMILPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f38.w0 0d /r      ] ND,AVX,SANDYBRIDGE */
        /* 260(002 001) 001(0d) 110 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VPERMILPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60344, 442},
    /*   2 : VPERMILPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f38.w0 0d /r      ] AVX,SANDYBRIDGE */
        /* 261(002 005) 001(0d) 120 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VPERMILPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60351, 442},
    /*   3 : VPERMILPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f38.w0 0d /r      ] ND,AVX,SANDYBRIDGE */
        /* 260(002 005) 001(0d) 110 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VPERMILPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60358, 442},
    /*   4 : VPERMILPD xmmreg,xmmrm128,imm8 [rmi:      vex.128.66.0f3a.w0 05 /r ib       ] AVX,SANDYBRIDGE */
        /* 270(003 001) 001(05) 110 022 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VPERMILPD, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52021, 442},
    /*   5 : VPERMILPD ymmreg,ymmrm256,imm8 [rmi:      vex.256.66.0f3a.w0 05 /r ib       ] AVX,SANDYBRIDGE */
        /* 270(003 005) 001(05) 110 022 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VPERMILPD, 3, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52029, 442},
    /*   6 : VPERMILPD xmmreg|mask|z,xmmrm128|b64,imm8 [rmi:fv:   evex.128.66.0f3a.w1 05 /r ib      ] AVX512,AVX512VL,FUTURE */
        /* 250(f3 fd 08) 301 001(05) 110 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPERMILPD, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+19753, 544},
    /*   7 : VPERMILPD ymmreg|mask|z,ymmrm256|b64,imm8 [rmi:fv:   evex.256.66.0f3a.w1 05 /r ib      ] AVX512,AVX512VL,FUTURE */
        /* 250(f3 fd 28) 301 001(05) 110 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPERMILPD, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+19763, 544},
    /*   8 : VPERMILPD zmmreg|mask|z,zmmrm512|b64,imm8 [rmi:fv:   evex.512.66.0f3a.w1 05 /r ib      ] AVX512,FUTURE */
        /* 250(f3 fd 48) 301 001(05) 110 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VPERMILPD, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+19773, 545},
    /*   9 : VPERMILPD xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 0d /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 08) 301 001(0d) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPERMILPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+37539, 544},
    /*  10 : VPERMILPD xmmreg|mask|z,xmmrm128|b64 [r+vm:fv:   evex.nds.128.66.0f38.w1 0d /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 fd 08) 301 001(0d) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPERMILPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+37548, 544},
    /*  11 : VPERMILPD ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 0d /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 28) 301 001(0d) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPERMILPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+37557, 544},
    /*  12 : VPERMILPD ymmreg|mask|z,ymmrm256|b64 [r+vm:fv:   evex.nds.256.66.0f38.w1 0d /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 fd 28) 301 001(0d) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPERMILPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+37566, 544},
    /*  13 : VPERMILPD zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv:   evex.nds.512.66.0f38.w1 0d /r     ] AVX512,FUTURE */
        /* 241(f2 fd 48) 301 001(0d) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPERMILPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+37575, 545},
    /*  14 : VPERMILPD zmmreg|mask|z,zmmrm512|b64 [r+vm:fv:   evex.nds.512.66.0f38.w1 0d /r     ] ND,AVX512,FUTURE */
        /* 240(f2 fd 48) 301 001(0d) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPERMILPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+37584, 545},
};

static const struct itemplate instrux_VPERMILPS[15] = {
    /*   0 : VPERMILPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f38.w0 0c /r      ] AVX,SANDYBRIDGE */
        /* 261(002 001) 001(0c) 120 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VPERMILPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60365, 442},
    /*   1 : VPERMILPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f38.w0 0c /r      ] ND,AVX,SANDYBRIDGE */
        /* 260(002 001) 001(0c) 110 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VPERMILPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60372, 442},
    /*   2 : VPERMILPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f38.w0 0c /r      ] AVX,SANDYBRIDGE */
        /* 261(002 005) 001(0c) 120 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VPERMILPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60379, 442},
    /*   3 : VPERMILPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f38.w0 0c /r      ] ND,AVX,SANDYBRIDGE */
        /* 260(002 005) 001(0c) 110 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VPERMILPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60386, 442},
    /*   4 : VPERMILPS xmmreg,xmmrm128,imm8 [rmi:      vex.128.66.0f3a.w0 04 /r ib       ] AVX,SANDYBRIDGE */
        /* 270(003 001) 001(04) 110 022 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VPERMILPS, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52037, 442},
    /*   5 : VPERMILPS ymmreg,ymmrm256,imm8 [rmi:      vex.256.66.0f3a.w0 04 /r ib       ] AVX,SANDYBRIDGE */
        /* 270(003 005) 001(04) 110 022 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VPERMILPS, 3, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52045, 442},
    /*   6 : VPERMILPS xmmreg|mask|z,xmmrm128|b32,imm8 [rmi:fv:   evex.128.66.0f3a.w0 04 /r ib      ] AVX512,AVX512VL,FUTURE */
        /* 250(f3 7d 08) 301 001(04) 110 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPERMILPS, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+19783, 544},
    /*   7 : VPERMILPS ymmreg|mask|z,ymmrm256|b32,imm8 [rmi:fv:   evex.256.66.0f3a.w0 04 /r ib      ] AVX512,AVX512VL,FUTURE */
        /* 250(f3 7d 28) 301 001(04) 110 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPERMILPS, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+19793, 544},
    /*   8 : VPERMILPS zmmreg|mask|z,zmmrm512|b32,imm8 [rmi:fv:   evex.512.66.0f3a.w0 04 /r ib      ] AVX512,FUTURE */
        /* 250(f3 7d 48) 301 001(04) 110 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VPERMILPS, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+19803, 545},
    /*   9 : VPERMILPS xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f38.w0 0c /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 08) 301 001(0c) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPERMILPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+37593, 544},
    /*  10 : VPERMILPS xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.nds.128.66.0f38.w0 0c /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 7d 08) 301 001(0c) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPERMILPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+37602, 544},
    /*  11 : VPERMILPS ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f38.w0 0c /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 28) 301 001(0c) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPERMILPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+37611, 544},
    /*  12 : VPERMILPS ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.nds.256.66.0f38.w0 0c /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 7d 28) 301 001(0c) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPERMILPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+37620, 544},
    /*  13 : VPERMILPS zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv:   evex.nds.512.66.0f38.w0 0c /r     ] AVX512,FUTURE */
        /* 241(f2 7d 48) 301 001(0c) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPERMILPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+37629, 545},
    /*  14 : VPERMILPS zmmreg|mask|z,zmmrm512|b32 [r+vm:fv:   evex.nds.512.66.0f38.w0 0c /r     ] ND,AVX512,FUTURE */
        /* 240(f2 7d 48) 301 001(0c) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPERMILPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+37638, 545},
};

static const struct itemplate instrux_VPERM2F128[2] = {
    /*   0 : VPERM2F128 ymmreg,ymmreg*,ymmrm256,imm8 [rvmi:     vex.nds.256.66.0f3a.w0 06 /r ib   ] AVX,SANDYBRIDGE */
        /* 261(003 005) 001(06) 120 023 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VPERM2F128, 4, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+52053, 442},
    /*   1 : VPERM2F128 ymmreg,ymmrm256,imm8 [r+vmi:     vex.nds.256.66.0f3a.w0 06 /r ib   ] ND,AVX,SANDYBRIDGE */
        /* 260(003 005) 001(06) 110 022 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VPERM2F128, 3, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52061, 442},
};

static const struct itemplate instrux_VPEXTRB[8] = {
    /*   0 : VPEXTRB reg64,xmmreg,imm8 [mri:      vex.128.66.0f3a.w0 14 /r ib       ] LONG,PROT,AVX,X86_64,SANDYBRIDGE */
        /* 270(003 001) 001(14) 101 022 : NOAPX,LONG,VEX,PROT,AVX,SANDYBRIDGE */
        {I_VPEXTRB, 3, {REG_GPR|BITS64|RN_L16,XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52069, 457},
    /*   1 : VPEXTRB reg32,xmmreg,imm8 [mri:      vex.128.66.0f3a.w0 14 /r ib       ] AVX,SANDYBRIDGE */
        /* 270(003 001) 001(14) 101 022 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VPEXTRB, 3, {REG_GPR|BITS32|RN_L16,XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52069, 442},
    /*   2 : VPEXTRB mem8,xmmreg,imm8 [mri:      vex.128.66.0f3a.w0 14 /r ib       ] AVX,SANDYBRIDGE */
        /* 270(003 001) 001(14) 101 022 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VPEXTRB, 3, {MEMORY|BITS8|RN_L16,XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52069, 442},
    /*   3 : VPEXTRB reg8,xmmreg,imm8 [mri:t1s8: evex.128.66.0f3a.wig 14 /r ib     ] AVX512BW,FUTURE */
        /* 250(f3 7d 08) 304 001(14) 101 022 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPEXTRB, 3, {REG_GPR|BITS8,XMMREG,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+19853, 557},
    /*   4 : VPEXTRB reg16,xmmreg,imm8 [mri:t1s8: evex.128.66.0f3a.wig 14 /r ib     ] AVX512BW,FUTURE */
        /* 250(f3 7d 08) 304 001(14) 101 022 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPEXTRB, 3, {REG_GPR|BITS16,XMMREG,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+19853, 557},
    /*   5 : VPEXTRB reg32,xmmreg,imm8 [mri:t1s8: evex.128.66.0f3a.wig 14 /r ib     ] AVX512BW,FUTURE */
        /* 250(f3 7d 08) 304 001(14) 101 022 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPEXTRB, 3, {REG_GPR|BITS32,XMMREG,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+19853, 557},
    /*   6 : VPEXTRB reg64,xmmreg,imm8 [mri:t1s8: evex.128.66.0f3a.wig 14 /r ib     ] AVX512BW,FUTURE */
        /* 250(f3 7d 08) 304 001(14) 101 022 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPEXTRB, 3, {REG_GPR|BITS64,XMMREG,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+19853, 557},
    /*   7 : VPEXTRB mem8,xmmreg,imm8 [mri:t1s8: evex.128.66.0f3a.wig 14 /r ib     ] AVX512BW,FUTURE */
        /* 250(f3 7d 08) 304 001(14) 101 022 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPEXTRB, 3, {MEMORY|BITS8,XMMREG,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+19853, 557},
};

static const struct itemplate instrux_VPEXTRW[12] = {
    /*   0 : VPEXTRW reg64,xmmreg,imm8 [rmi:      vex.128.66.0f.w0 c5 /r ib         ] LONG,PROT,AVX,X86_64,SANDYBRIDGE */
        /* 270(001 001) 001(c5) 110 022 : NOAPX,LONG,VEX,PROT,AVX,SANDYBRIDGE */
        {I_VPEXTRW, 3, {REG_GPR|BITS64|RN_L16,XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52077, 457},
    /*   1 : VPEXTRW reg32,xmmreg,imm8 [rmi:      vex.128.66.0f.w0 c5 /r ib         ] AVX,SANDYBRIDGE */
        /* 270(001 001) 001(c5) 110 022 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VPEXTRW, 3, {REG_GPR|BITS32|RN_L16,XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52077, 442},
    /*   2 : VPEXTRW reg64,xmmreg,imm8 [mri:      vex.128.66.0f3a.w0 15 /r ib       ] LONG,PROT,AVX,X86_64,SANDYBRIDGE */
        /* 270(003 001) 001(15) 101 022 : NOAPX,LONG,VEX,PROT,AVX,SANDYBRIDGE */
        {I_VPEXTRW, 3, {REG_GPR|BITS64|RN_L16,XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52085, 457},
    /*   3 : VPEXTRW reg32,xmmreg,imm8 [mri:      vex.128.66.0f3a.w0 15 /r ib       ] AVX,SANDYBRIDGE */
        /* 270(003 001) 001(15) 101 022 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VPEXTRW, 3, {REG_GPR|BITS32|RN_L16,XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52085, 442},
    /*   4 : VPEXTRW mem16,xmmreg,imm8 [mri:      vex.128.66.0f3a.w0 15 /r ib       ] AVX,SANDYBRIDGE */
        /* 270(003 001) 001(15) 101 022 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VPEXTRW, 3, {MEMORY|BITS16|RN_L16,XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52085, 442},
    /*   5 : VPEXTRW reg16,xmmreg,imm8 [mri:t1s16:evex.128.66.0f3a.wig 15 /r ib     ] AVX512BW,FUTURE */
        /* 250(f3 7d 08) 305 001(15) 101 022 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPEXTRW, 3, {REG_GPR|BITS16,XMMREG,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+19883, 557},
    /*   6 : VPEXTRW reg32,xmmreg,imm8 [mri:t1s16:evex.128.66.0f3a.wig 15 /r ib     ] AVX512BW,FUTURE */
        /* 250(f3 7d 08) 305 001(15) 101 022 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPEXTRW, 3, {REG_GPR|BITS32,XMMREG,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+19883, 557},
    /*   7 : VPEXTRW reg64,xmmreg,imm8 [mri:t1s16:evex.128.66.0f3a.wig 15 /r ib     ] AVX512BW,FUTURE */
        /* 250(f3 7d 08) 305 001(15) 101 022 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPEXTRW, 3, {REG_GPR|BITS64,XMMREG,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+19883, 557},
    /*   8 : VPEXTRW mem16,xmmreg,imm8 [mri:t1s16:evex.128.66.0f3a.wig 15 /r ib     ] AVX512BW,FUTURE */
        /* 250(f3 7d 08) 305 001(15) 101 022 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPEXTRW, 3, {MEMORY|BITS16,XMMREG,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+19883, 557},
    /*   9 : VPEXTRW reg16,xmmreg,imm8 [rmi:      evex.128.66.0f.wig c5 /r ib       ] AVX512BW,FUTURE */
        /* 250(f1 7d 08) 300 001(c5) 110 022 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPEXTRW, 3, {REG_GPR|BITS16,XMMREG,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+19893, 557},
    /*  10 : VPEXTRW reg32,xmmreg,imm8 [rmi:      evex.128.66.0f.wig c5 /r ib       ] AVX512BW,FUTURE */
        /* 250(f1 7d 08) 300 001(c5) 110 022 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPEXTRW, 3, {REG_GPR|BITS32,XMMREG,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+19893, 557},
    /*  11 : VPEXTRW reg64,xmmreg,imm8 [rmi:      evex.128.66.0f.wig c5 /r ib       ] AVX512BW,FUTURE */
        /* 250(f1 7d 08) 300 001(c5) 110 022 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPEXTRW, 3, {REG_GPR|BITS64,XMMREG,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+19893, 557},
};

static const struct itemplate instrux_VPEXTRD[3] = {
    /*   0 : VPEXTRD reg64,xmmreg,imm8 [mri:      vex.128.66.0f3a.w0 16 /r ib       ] LONG,PROT,AVX,X86_64,SANDYBRIDGE */
        /* 270(003 001) 001(16) 101 022 : NOAPX,LONG,VEX,PROT,AVX,SANDYBRIDGE */
        {I_VPEXTRD, 3, {REG_GPR|BITS64|RN_L16,XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52093, 457},
    /*   1 : VPEXTRD rm32,xmmreg,imm8 [mri:      vex.128.66.0f3a.w0 16 /r ib       ] AVX,SANDYBRIDGE */
        /* 270(003 001) 001(16) 101 022 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VPEXTRD, 3, {RM_GPR|BITS32|RN_L16,XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52093, 442},
    /*   2 : VPEXTRD rm32,xmmreg,imm8 [mri:t1s:  evex.128.66.0f3a.w0 16 /r ib      ] AVX512DQ,FUTURE */
        /* 250(f3 7d 08) 306 001(16) 101 022 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VPEXTRD, 3, {RM_GPR|BITS32,XMMREG,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+19863, 548},
};

static const struct itemplate instrux_VPEXTRQ[2] = {
    /*   0 : VPEXTRQ rm64,xmmreg,imm8 [mri:      vex.128.66.0f3a.w1 16 /r ib       ] LONG,PROT,AVX,X86_64,SANDYBRIDGE */
        /* 270(003 201) 001(16) 101 022 : NOAPX,LONG,VEX,PROT,AVX,SANDYBRIDGE */
        {I_VPEXTRQ, 3, {RM_GPR|BITS64|RN_L16,XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52101, 457},
    /*   1 : VPEXTRQ rm64,xmmreg,imm8 [mri:t1s:  evex.128.66.0f3a.w1 16 /r ib      ] AVX512DQ,FUTURE */
        /* 250(f3 fd 08) 306 001(16) 101 022 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VPEXTRQ, 3, {RM_GPR|BITS64,XMMREG,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+19873, 548},
};

static const struct itemplate instrux_VPHADDW[4] = {
    /*   0 : VPHADDW xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f38 01 /r         ] AVX,SANDYBRIDGE */
        /* 261(002 001) 001(01) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPHADDW, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60393, 434},
    /*   1 : VPHADDW xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f38 01 /r         ] ND,AVX,SANDYBRIDGE */
        /* 260(002 001) 001(01) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPHADDW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60400, 434},
    /*   2 : VPHADDW ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f38 01 /r         ] AVX2,FUTURE */
        /* 261(002 005) 001(01) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPHADDW, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63438, 468},
    /*   3 : VPHADDW ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f38 01 /r         ] ND,AVX2,FUTURE */
        /* 260(002 005) 001(01) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPHADDW, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63445, 468},
};

static const struct itemplate instrux_VPHADDD[4] = {
    /*   0 : VPHADDD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f38 02 /r         ] AVX,SANDYBRIDGE */
        /* 261(002 001) 001(02) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPHADDD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60407, 434},
    /*   1 : VPHADDD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f38 02 /r         ] ND,AVX,SANDYBRIDGE */
        /* 260(002 001) 001(02) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPHADDD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60414, 434},
    /*   2 : VPHADDD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f38 02 /r         ] AVX2,FUTURE */
        /* 261(002 005) 001(02) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPHADDD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63452, 468},
    /*   3 : VPHADDD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f38 02 /r         ] ND,AVX2,FUTURE */
        /* 260(002 005) 001(02) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPHADDD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63459, 468},
};

static const struct itemplate instrux_VPHADDSW[4] = {
    /*   0 : VPHADDSW xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f38 03 /r         ] AVX,SANDYBRIDGE */
        /* 261(002 001) 001(03) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPHADDSW, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60421, 434},
    /*   1 : VPHADDSW xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f38 03 /r         ] ND,AVX,SANDYBRIDGE */
        /* 260(002 001) 001(03) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPHADDSW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60428, 434},
    /*   2 : VPHADDSW ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f38 03 /r         ] AVX2,FUTURE */
        /* 261(002 005) 001(03) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPHADDSW, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63466, 468},
    /*   3 : VPHADDSW ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f38 03 /r         ] ND,AVX2,FUTURE */
        /* 260(002 005) 001(03) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPHADDSW, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63473, 468},
};

static const struct itemplate instrux_VPHMINPOSUW[1] = {
    /*   0 : VPHMINPOSUW xmmreg,xmmrm128 [rm:       vex.128.66.0f38 41 /r             ] AVX,SANDYBRIDGE */
        /* 270(002 001) 001(41) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPHMINPOSUW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60435, 434},
};

static const struct itemplate instrux_VPHSUBW[4] = {
    /*   0 : VPHSUBW xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f38 05 /r         ] AVX,SANDYBRIDGE */
        /* 261(002 001) 001(05) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPHSUBW, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60442, 434},
    /*   1 : VPHSUBW xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f38 05 /r         ] ND,AVX,SANDYBRIDGE */
        /* 260(002 001) 001(05) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPHSUBW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60449, 434},
    /*   2 : VPHSUBW ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f38 05 /r         ] AVX2,FUTURE */
        /* 261(002 005) 001(05) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPHSUBW, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63480, 468},
    /*   3 : VPHSUBW ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f38 05 /r         ] ND,AVX2,FUTURE */
        /* 260(002 005) 001(05) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPHSUBW, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63487, 468},
};

static const struct itemplate instrux_VPHSUBD[4] = {
    /*   0 : VPHSUBD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f38 06 /r         ] AVX,SANDYBRIDGE */
        /* 261(002 001) 001(06) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPHSUBD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60456, 434},
    /*   1 : VPHSUBD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f38 06 /r         ] ND,AVX,SANDYBRIDGE */
        /* 260(002 001) 001(06) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPHSUBD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60463, 434},
    /*   2 : VPHSUBD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f38 06 /r         ] AVX2,FUTURE */
        /* 261(002 005) 001(06) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPHSUBD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63494, 468},
    /*   3 : VPHSUBD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f38 06 /r         ] ND,AVX2,FUTURE */
        /* 260(002 005) 001(06) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPHSUBD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63501, 468},
};

static const struct itemplate instrux_VPHSUBSW[4] = {
    /*   0 : VPHSUBSW xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f38 07 /r         ] AVX,SANDYBRIDGE */
        /* 261(002 001) 001(07) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPHSUBSW, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60470, 434},
    /*   1 : VPHSUBSW xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f38 07 /r         ] ND,AVX,SANDYBRIDGE */
        /* 260(002 001) 001(07) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPHSUBSW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60477, 434},
    /*   2 : VPHSUBSW ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f38 07 /r         ] AVX2,FUTURE */
        /* 261(002 005) 001(07) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPHSUBSW, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63508, 468},
    /*   3 : VPHSUBSW ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f38 07 /r         ] ND,AVX2,FUTURE */
        /* 260(002 005) 001(07) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPHSUBSW, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63515, 468},
};

static const struct itemplate instrux_VPINSRB[10] = {
    /*   0 : VPINSRB xmmreg,xmmreg*,mem8,imm8 [rvmi:     vex.nds.128.66.0f3a 20 /r ib      ] AVX,SANDYBRIDGE */
        /* 261(003 001) 001(20) 120 023 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPINSRB, 4, {XMMREG|RN_L16,XMMREG|RN_L16,MEMORY|BITS8|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+52109, 434},
    /*   1 : VPINSRB xmmreg,mem8,imm8 [r+vmi:     vex.nds.128.66.0f3a 20 /r ib      ] ND,AVX,SANDYBRIDGE */
        /* 260(003 001) 001(20) 110 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPINSRB, 3, {XMMREG|RN_L16,MEMORY|BITS8|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52117, 434},
    /*   2 : VPINSRB xmmreg,xmmreg*,rm8,imm8 [rvmi:     vex.nds.128.66.0f3a 20 /r ib      ] AVX,SANDYBRIDGE */
        /* 261(003 001) 001(20) 120 023 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPINSRB, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_GPR|BITS8|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+52109, 434},
    /*   3 : VPINSRB xmmreg,rm8,imm8 [r+vmi:     vex.nds.128.66.0f3a 20 /r ib      ] ND,AVX,SANDYBRIDGE */
        /* 260(003 001) 001(20) 110 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPINSRB, 3, {XMMREG|RN_L16,RM_GPR|BITS8|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52117, 434},
    /*   4 : VPINSRB xmmreg,xmmreg*,reg32,imm8 [rvmi:     vex.nds.128.66.0f3a 20 /r ib      ] AVX,SANDYBRIDGE */
        /* 261(003 001) 001(20) 120 023 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPINSRB, 4, {XMMREG|RN_L16,XMMREG|RN_L16,REG_GPR|BITS32|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+52109, 434},
    /*   5 : VPINSRB xmmreg,reg32,imm8 [r+vmi:     vex.nds.128.66.0f3a 20 /r ib      ] ND,AVX,SANDYBRIDGE */
        /* 260(003 001) 001(20) 110 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPINSRB, 3, {XMMREG|RN_L16,REG_GPR|BITS32|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52117, 434},
    /*   6 : VPINSRB xmmreg,xmmreg*,reg32,imm8 [rvmi:t1s8:evex.nds.128.66.0f3a.wig 20 /r ib ] AVX512BW,FUTURE */
        /* 241(f3 7d 08) 304 001(20) 120 023 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPINSRB, 4, {XMMREG,XMMREG,REG_GPR|BITS32,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+20023, 557},
    /*   7 : VPINSRB xmmreg,reg32,imm8 [r+vmi:t1s8:evex.nds.128.66.0f3a.wig 20 /r ib ] ND,AVX512BW,FUTURE */
        /* 240(f3 7d 08) 304 001(20) 110 022 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPINSRB, 3, {XMMREG,REG_GPR|BITS32,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+20033, 557},
    /*   8 : VPINSRB xmmreg,xmmreg*,mem8,imm8 [rvmi:t1s8:evex.nds.128.66.0f3a.wig 20 /r ib ] AVX512BW,FUTURE */
        /* 241(f3 7d 08) 304 001(20) 120 023 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPINSRB, 4, {XMMREG,XMMREG,MEMORY|BITS8,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+20023, 557},
    /*   9 : VPINSRB xmmreg,mem8,imm8 [r+vmi:t1s8:evex.nds.128.66.0f3a.wig 20 /r ib ] ND,AVX512BW,FUTURE */
        /* 240(f3 7d 08) 304 001(20) 110 022 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPINSRB, 3, {XMMREG,MEMORY|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+20033, 557},
};

static const struct itemplate instrux_VPINSRW[10] = {
    /*   0 : VPINSRW xmmreg,xmmreg*,mem16,imm8 [rvmi:     vex.nds.128.66.0f c4 /r ib        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c4) 120 023 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPINSRW, 4, {XMMREG|RN_L16,XMMREG|RN_L16,MEMORY|BITS16|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+52125, 434},
    /*   1 : VPINSRW xmmreg,mem16,imm8 [r+vmi:     vex.nds.128.66.0f c4 /r ib        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c4) 110 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPINSRW, 3, {XMMREG|RN_L16,MEMORY|BITS16|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52133, 434},
    /*   2 : VPINSRW xmmreg,xmmreg*,rm16,imm8 [rvmi:     vex.nds.128.66.0f c4 /r ib        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c4) 120 023 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPINSRW, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_GPR|BITS16|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+52125, 434},
    /*   3 : VPINSRW xmmreg,rm16,imm8 [r+vmi:     vex.nds.128.66.0f c4 /r ib        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c4) 110 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPINSRW, 3, {XMMREG|RN_L16,RM_GPR|BITS16|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52133, 434},
    /*   4 : VPINSRW xmmreg,xmmreg*,reg32,imm8 [rvmi:     vex.nds.128.66.0f c4 /r ib        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c4) 120 023 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPINSRW, 4, {XMMREG|RN_L16,XMMREG|RN_L16,REG_GPR|BITS32|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+52125, 434},
    /*   5 : VPINSRW xmmreg,reg32,imm8 [r+vmi:     vex.nds.128.66.0f c4 /r ib        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c4) 110 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPINSRW, 3, {XMMREG|RN_L16,REG_GPR|BITS32|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52133, 434},
    /*   6 : VPINSRW xmmreg,xmmreg*,reg32,imm8 [rvmi:t1s16:evex.nds.128.66.0f.wig c4 /r ib   ] AVX512BW,FUTURE */
        /* 241(f1 7d 08) 305 001(c4) 120 023 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPINSRW, 4, {XMMREG,XMMREG,REG_GPR|BITS32,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+20083, 557},
    /*   7 : VPINSRW xmmreg,reg32,imm8 [r+vmi:t1s16:evex.nds.128.66.0f.wig c4 /r ib   ] ND,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 305 001(c4) 110 022 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPINSRW, 3, {XMMREG,REG_GPR|BITS32,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+20093, 557},
    /*   8 : VPINSRW xmmreg,xmmreg*,mem16,imm8 [rvmi:t1s16:evex.nds.128.66.0f.wig c4 /r ib   ] AVX512BW,FUTURE */
        /* 241(f1 7d 08) 305 001(c4) 120 023 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPINSRW, 4, {XMMREG,XMMREG,MEMORY|BITS16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+20083, 557},
    /*   9 : VPINSRW xmmreg,mem16,imm8 [r+vmi:t1s16:evex.nds.128.66.0f.wig c4 /r ib   ] ND,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 305 001(c4) 110 022 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPINSRW, 3, {XMMREG,MEMORY|BITS16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+20093, 557},
};

static const struct itemplate instrux_VPINSRD[6] = {
    /*   0 : VPINSRD xmmreg,xmmreg*,mem32,imm8 [rvmi:     vex.nds.128.66.0f3a.w0 22 /r ib   ] AVX,SANDYBRIDGE */
        /* 261(003 001) 001(22) 120 023 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VPINSRD, 4, {XMMREG|RN_L16,XMMREG|RN_L16,MEMORY|BITS32|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+52141, 442},
    /*   1 : VPINSRD xmmreg,mem32,imm8 [r+vmi:     vex.nds.128.66.0f3a.w0 22 /r ib   ] ND,AVX,SANDYBRIDGE */
        /* 260(003 001) 001(22) 110 022 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VPINSRD, 3, {XMMREG|RN_L16,MEMORY|BITS32|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52149, 442},
    /*   2 : VPINSRD xmmreg,xmmreg*,rm32,imm8 [rvmi:     vex.nds.128.66.0f3a.w0 22 /r ib   ] AVX,SANDYBRIDGE */
        /* 261(003 001) 001(22) 120 023 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VPINSRD, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_GPR|BITS32|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+52141, 442},
    /*   3 : VPINSRD xmmreg,rm32,imm8 [r+vmi:     vex.nds.128.66.0f3a.w0 22 /r ib   ] ND,AVX,SANDYBRIDGE */
        /* 260(003 001) 001(22) 110 022 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VPINSRD, 3, {XMMREG|RN_L16,RM_GPR|BITS32|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52149, 442},
    /*   4 : VPINSRD xmmreg,xmmreg*,rm32,imm8 [rvmi:t1s: evex.nds.128.66.0f3a.w0 22 /r ib  ] AVX512DQ,FUTURE */
        /* 241(f3 7d 08) 306 001(22) 120 023 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VPINSRD, 4, {XMMREG,XMMREG,RM_GPR|BITS32,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+20043, 548},
    /*   5 : VPINSRD xmmreg,rm32,imm8 [r+vmi:t1s: evex.nds.128.66.0f3a.w0 22 /r ib  ] ND,AVX512DQ,FUTURE */
        /* 240(f3 7d 08) 306 001(22) 110 022 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VPINSRD, 3, {XMMREG,RM_GPR|BITS32,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+20053, 548},
};

static const struct itemplate instrux_VPINSRQ[6] = {
    /*   0 : VPINSRQ xmmreg,xmmreg*,mem64,imm8 [rvmi:     vex.nds.128.66.0f3a.w1 22 /r ib   ] LONG,PROT,AVX,X86_64,SANDYBRIDGE */
        /* 261(003 201) 001(22) 120 023 : NOAPX,LONG,VEX,PROT,AVX,SANDYBRIDGE */
        {I_VPINSRQ, 4, {XMMREG|RN_L16,XMMREG|RN_L16,MEMORY|BITS64|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+52157, 457},
    /*   1 : VPINSRQ xmmreg,mem64,imm8 [r+vmi:     vex.nds.128.66.0f3a.w1 22 /r ib   ] ND,LONG,PROT,AVX,X86_64,SANDYBRIDGE */
        /* 260(003 201) 001(22) 110 022 : NOAPX,LONG,VEX,PROT,AVX,SANDYBRIDGE */
        {I_VPINSRQ, 3, {XMMREG|RN_L16,MEMORY|BITS64|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52165, 457},
    /*   2 : VPINSRQ xmmreg,xmmreg*,rm64,imm8 [rvmi:     vex.nds.128.66.0f3a.w1 22 /r ib   ] LONG,PROT,AVX,X86_64,SANDYBRIDGE */
        /* 261(003 201) 001(22) 120 023 : NOAPX,LONG,VEX,PROT,AVX,SANDYBRIDGE */
        {I_VPINSRQ, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_GPR|BITS64|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+52157, 457},
    /*   3 : VPINSRQ xmmreg,rm64,imm8 [r+vmi:     vex.nds.128.66.0f3a.w1 22 /r ib   ] ND,LONG,PROT,AVX,X86_64,SANDYBRIDGE */
        /* 260(003 201) 001(22) 110 022 : NOAPX,LONG,VEX,PROT,AVX,SANDYBRIDGE */
        {I_VPINSRQ, 3, {XMMREG|RN_L16,RM_GPR|BITS64|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52165, 457},
    /*   4 : VPINSRQ xmmreg,xmmreg*,rm64,imm8 [rvmi:t1s: evex.nds.128.66.0f3a.w1 22 /r ib  ] AVX512DQ,FUTURE */
        /* 241(f3 fd 08) 306 001(22) 120 023 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VPINSRQ, 4, {XMMREG,XMMREG,RM_GPR|BITS64,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+20063, 548},
    /*   5 : VPINSRQ xmmreg,rm64,imm8 [r+vmi:t1s: evex.nds.128.66.0f3a.w1 22 /r ib  ] ND,AVX512DQ,FUTURE */
        /* 240(f3 fd 08) 306 001(22) 110 022 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VPINSRQ, 3, {XMMREG,RM_GPR|BITS64,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+20073, 548},
};

static const struct itemplate instrux_VPMADDWD[10] = {
    /*   0 : VPMADDWD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f f5 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(f5) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMADDWD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60484, 434},
    /*   1 : VPMADDWD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f f5 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(f5) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMADDWD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60491, 434},
    /*   2 : VPMADDWD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f f5 /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(f5) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMADDWD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63536, 468},
    /*   3 : VPMADDWD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f f5 /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(f5) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMADDWD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63543, 468},
    /*   4 : VPMADDWD xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f.wig f5 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 08) 303 001(f5) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMADDWD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38187, 556},
    /*   5 : VPMADDWD xmmreg|mask|z,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f.wig f5 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 303 001(f5) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMADDWD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38196, 556},
    /*   6 : VPMADDWD ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f.wig f5 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 28) 303 001(f5) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMADDWD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38205, 556},
    /*   7 : VPMADDWD ymmreg|mask|z,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f.wig f5 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 303 001(f5) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMADDWD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38214, 556},
    /*   8 : VPMADDWD zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f.wig f5 /r      ] AVX512BW,FUTURE */
        /* 241(f1 7d 48) 303 001(f5) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPMADDWD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38223, 557},
    /*   9 : VPMADDWD zmmreg|mask|z,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f.wig f5 /r      ] ND,AVX512BW,FUTURE */
        /* 240(f1 7d 48) 303 001(f5) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPMADDWD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38232, 557},
};

static const struct itemplate instrux_VPMADDUBSW[10] = {
    /*   0 : VPMADDUBSW xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f38 04 /r         ] AVX,SANDYBRIDGE */
        /* 261(002 001) 001(04) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMADDUBSW, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60498, 434},
    /*   1 : VPMADDUBSW xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f38 04 /r         ] ND,AVX,SANDYBRIDGE */
        /* 260(002 001) 001(04) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMADDUBSW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60505, 434},
    /*   2 : VPMADDUBSW ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f38 04 /r         ] AVX2,FUTURE */
        /* 261(002 005) 001(04) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMADDUBSW, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63522, 468},
    /*   3 : VPMADDUBSW ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f38 04 /r         ] ND,AVX2,FUTURE */
        /* 260(002 005) 001(04) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMADDUBSW, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63529, 468},
    /*   4 : VPMADDUBSW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f38.wig 04 /r    ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f2 7d 08) 303 001(04) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMADDUBSW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38133, 556},
    /*   5 : VPMADDUBSW xmmreg|mask|z,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f38.wig 04 /r    ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f2 7d 08) 303 001(04) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMADDUBSW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38142, 556},
    /*   6 : VPMADDUBSW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f38.wig 04 /r    ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f2 7d 28) 303 001(04) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMADDUBSW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38151, 556},
    /*   7 : VPMADDUBSW ymmreg|mask|z,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f38.wig 04 /r    ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f2 7d 28) 303 001(04) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMADDUBSW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38160, 556},
    /*   8 : VPMADDUBSW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f38.wig 04 /r    ] AVX512BW,FUTURE */
        /* 241(f2 7d 48) 303 001(04) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPMADDUBSW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38169, 557},
    /*   9 : VPMADDUBSW zmmreg|mask|z,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f38.wig 04 /r    ] ND,AVX512BW,FUTURE */
        /* 240(f2 7d 48) 303 001(04) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPMADDUBSW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38178, 557},
};

static const struct itemplate instrux_VPMAXSB[10] = {
    /*   0 : VPMAXSB xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f38 3c /r         ] AVX,SANDYBRIDGE */
        /* 261(002 001) 001(3c) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMAXSB, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60512, 434},
    /*   1 : VPMAXSB xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f38 3c /r         ] ND,AVX,SANDYBRIDGE */
        /* 260(002 001) 001(3c) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMAXSB, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60519, 434},
    /*   2 : VPMAXSB ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f38 3c /r         ] AVX2,FUTURE */
        /* 261(002 005) 001(3c) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMAXSB, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63550, 468},
    /*   3 : VPMAXSB ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f38 3c /r         ] ND,AVX2,FUTURE */
        /* 260(002 005) 001(3c) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMAXSB, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63557, 468},
    /*   4 : VPMAXSB xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f38.wig 3c /r    ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f2 7d 08) 303 001(3c) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMAXSB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38241, 556},
    /*   5 : VPMAXSB xmmreg|mask|z,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f38.wig 3c /r    ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f2 7d 08) 303 001(3c) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMAXSB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38250, 556},
    /*   6 : VPMAXSB ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f38.wig 3c /r    ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f2 7d 28) 303 001(3c) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMAXSB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38259, 556},
    /*   7 : VPMAXSB ymmreg|mask|z,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f38.wig 3c /r    ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f2 7d 28) 303 001(3c) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMAXSB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38268, 556},
    /*   8 : VPMAXSB zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f38.wig 3c /r    ] AVX512BW,FUTURE */
        /* 241(f2 7d 48) 303 001(3c) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPMAXSB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38277, 557},
    /*   9 : VPMAXSB zmmreg|mask|z,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f38.wig 3c /r    ] ND,AVX512BW,FUTURE */
        /* 240(f2 7d 48) 303 001(3c) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPMAXSB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38286, 557},
};

static const struct itemplate instrux_VPMAXSW[10] = {
    /*   0 : VPMAXSW xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f ee /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(ee) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMAXSW, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60526, 434},
    /*   1 : VPMAXSW xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f ee /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(ee) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMAXSW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60533, 434},
    /*   2 : VPMAXSW ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f ee /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(ee) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMAXSW, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63564, 468},
    /*   3 : VPMAXSW ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f ee /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(ee) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMAXSW, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63571, 468},
    /*   4 : VPMAXSW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f.wig ee /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 08) 303 001(ee) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMAXSW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38403, 556},
    /*   5 : VPMAXSW xmmreg|mask|z,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f.wig ee /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 303 001(ee) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMAXSW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38412, 556},
    /*   6 : VPMAXSW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f.wig ee /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 28) 303 001(ee) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMAXSW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38421, 556},
    /*   7 : VPMAXSW ymmreg|mask|z,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f.wig ee /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 303 001(ee) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMAXSW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38430, 556},
    /*   8 : VPMAXSW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f.wig ee /r      ] AVX512BW,FUTURE */
        /* 241(f1 7d 48) 303 001(ee) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPMAXSW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38439, 557},
    /*   9 : VPMAXSW zmmreg|mask|z,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f.wig ee /r      ] ND,AVX512BW,FUTURE */
        /* 240(f1 7d 48) 303 001(ee) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPMAXSW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38448, 557},
};

static const struct itemplate instrux_VPMAXSD[10] = {
    /*   0 : VPMAXSD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f38 3d /r         ] AVX,SANDYBRIDGE */
        /* 261(002 001) 001(3d) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMAXSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60540, 434},
    /*   1 : VPMAXSD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f38 3d /r         ] ND,AVX,SANDYBRIDGE */
        /* 260(002 001) 001(3d) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMAXSD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60547, 434},
    /*   2 : VPMAXSD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f38 3d /r         ] AVX2,FUTURE */
        /* 261(002 005) 001(3d) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMAXSD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63578, 468},
    /*   3 : VPMAXSD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f38 3d /r         ] ND,AVX2,FUTURE */
        /* 260(002 005) 001(3d) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMAXSD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63585, 468},
    /*   4 : VPMAXSD xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f38.w0 3d /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 08) 301 001(3d) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMAXSD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+38295, 544},
    /*   5 : VPMAXSD xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.nds.128.66.0f38.w0 3d /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 7d 08) 301 001(3d) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMAXSD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+38304, 544},
    /*   6 : VPMAXSD ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f38.w0 3d /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 28) 301 001(3d) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMAXSD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+38313, 544},
    /*   7 : VPMAXSD ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.nds.256.66.0f38.w0 3d /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 7d 28) 301 001(3d) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMAXSD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+38322, 544},
    /*   8 : VPMAXSD zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv:   evex.nds.512.66.0f38.w0 3d /r     ] AVX512,FUTURE */
        /* 241(f2 7d 48) 301 001(3d) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMAXSD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+38331, 545},
    /*   9 : VPMAXSD zmmreg|mask|z,zmmrm512|b32 [r+vm:fv:   evex.nds.512.66.0f38.w0 3d /r     ] ND,AVX512,FUTURE */
        /* 240(f2 7d 48) 301 001(3d) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMAXSD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+38340, 545},
};

static const struct itemplate instrux_VPMAXUB[10] = {
    /*   0 : VPMAXUB xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f de /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(de) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMAXUB, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60554, 434},
    /*   1 : VPMAXUB xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f de /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(de) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMAXUB, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60561, 434},
    /*   2 : VPMAXUB ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f de /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(de) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMAXUB, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63592, 468},
    /*   3 : VPMAXUB ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f de /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(de) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMAXUB, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63599, 468},
    /*   4 : VPMAXUB xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f.wig de /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 08) 303 001(de) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMAXUB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38457, 556},
    /*   5 : VPMAXUB xmmreg|mask|z,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f.wig de /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 303 001(de) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMAXUB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38466, 556},
    /*   6 : VPMAXUB ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f.wig de /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 28) 303 001(de) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMAXUB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38475, 556},
    /*   7 : VPMAXUB ymmreg|mask|z,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f.wig de /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 303 001(de) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMAXUB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38484, 556},
    /*   8 : VPMAXUB zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f.wig de /r      ] AVX512BW,FUTURE */
        /* 241(f1 7d 48) 303 001(de) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPMAXUB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38493, 557},
    /*   9 : VPMAXUB zmmreg|mask|z,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f.wig de /r      ] ND,AVX512BW,FUTURE */
        /* 240(f1 7d 48) 303 001(de) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPMAXUB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38502, 557},
};

static const struct itemplate instrux_VPMAXUW[10] = {
    /*   0 : VPMAXUW xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f38 3e /r         ] AVX,SANDYBRIDGE */
        /* 261(002 001) 001(3e) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMAXUW, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60568, 434},
    /*   1 : VPMAXUW xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f38 3e /r         ] ND,AVX,SANDYBRIDGE */
        /* 260(002 001) 001(3e) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMAXUW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60575, 434},
    /*   2 : VPMAXUW ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f38 3e /r         ] AVX2,FUTURE */
        /* 261(002 005) 001(3e) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMAXUW, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63606, 468},
    /*   3 : VPMAXUW ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f38 3e /r         ] ND,AVX2,FUTURE */
        /* 260(002 005) 001(3e) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMAXUW, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63613, 468},
    /*   4 : VPMAXUW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f38.wig 3e /r    ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f2 7d 08) 303 001(3e) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMAXUW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38619, 556},
    /*   5 : VPMAXUW xmmreg|mask|z,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f38.wig 3e /r    ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f2 7d 08) 303 001(3e) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMAXUW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38628, 556},
    /*   6 : VPMAXUW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f38.wig 3e /r    ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f2 7d 28) 303 001(3e) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMAXUW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38637, 556},
    /*   7 : VPMAXUW ymmreg|mask|z,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f38.wig 3e /r    ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f2 7d 28) 303 001(3e) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMAXUW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38646, 556},
    /*   8 : VPMAXUW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f38.wig 3e /r    ] AVX512BW,FUTURE */
        /* 241(f2 7d 48) 303 001(3e) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPMAXUW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38655, 557},
    /*   9 : VPMAXUW zmmreg|mask|z,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f38.wig 3e /r    ] ND,AVX512BW,FUTURE */
        /* 240(f2 7d 48) 303 001(3e) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPMAXUW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38664, 557},
};

static const struct itemplate instrux_VPMAXUD[10] = {
    /*   0 : VPMAXUD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f38 3f /r         ] AVX,SANDYBRIDGE */
        /* 261(002 001) 001(3f) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMAXUD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60582, 434},
    /*   1 : VPMAXUD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f38 3f /r         ] ND,AVX,SANDYBRIDGE */
        /* 260(002 001) 001(3f) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMAXUD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60589, 434},
    /*   2 : VPMAXUD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f38 3f /r         ] AVX2,FUTURE */
        /* 261(002 005) 001(3f) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMAXUD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63620, 468},
    /*   3 : VPMAXUD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f38 3f /r         ] ND,AVX2,FUTURE */
        /* 260(002 005) 001(3f) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMAXUD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63627, 468},
    /*   4 : VPMAXUD xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f38.w0 3f /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 08) 301 001(3f) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMAXUD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+38511, 544},
    /*   5 : VPMAXUD xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.nds.128.66.0f38.w0 3f /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 7d 08) 301 001(3f) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMAXUD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+38520, 544},
    /*   6 : VPMAXUD ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f38.w0 3f /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 28) 301 001(3f) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMAXUD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+38529, 544},
    /*   7 : VPMAXUD ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.nds.256.66.0f38.w0 3f /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 7d 28) 301 001(3f) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMAXUD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+38538, 544},
    /*   8 : VPMAXUD zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv:   evex.nds.512.66.0f38.w0 3f /r     ] AVX512,FUTURE */
        /* 241(f2 7d 48) 301 001(3f) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMAXUD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+38547, 545},
    /*   9 : VPMAXUD zmmreg|mask|z,zmmrm512|b32 [r+vm:fv:   evex.nds.512.66.0f38.w0 3f /r     ] ND,AVX512,FUTURE */
        /* 240(f2 7d 48) 301 001(3f) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMAXUD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+38556, 545},
};

static const struct itemplate instrux_VPMINSB[10] = {
    /*   0 : VPMINSB xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f38 38 /r         ] AVX,SANDYBRIDGE */
        /* 261(002 001) 001(38) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMINSB, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60596, 434},
    /*   1 : VPMINSB xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f38 38 /r         ] ND,AVX,SANDYBRIDGE */
        /* 260(002 001) 001(38) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMINSB, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60603, 434},
    /*   2 : VPMINSB ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f38 38 /r         ] AVX2,FUTURE */
        /* 261(002 005) 001(38) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMINSB, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63634, 468},
    /*   3 : VPMINSB ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f38 38 /r         ] ND,AVX2,FUTURE */
        /* 260(002 005) 001(38) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMINSB, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63641, 468},
    /*   4 : VPMINSB xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f38.wig 38 /r    ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f2 7d 08) 303 001(38) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMINSB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38673, 556},
    /*   5 : VPMINSB xmmreg|mask|z,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f38.wig 38 /r    ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f2 7d 08) 303 001(38) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMINSB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38682, 556},
    /*   6 : VPMINSB ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f38.wig 38 /r    ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f2 7d 28) 303 001(38) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMINSB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38691, 556},
    /*   7 : VPMINSB ymmreg|mask|z,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f38.wig 38 /r    ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f2 7d 28) 303 001(38) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMINSB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38700, 556},
    /*   8 : VPMINSB zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f38.wig 38 /r    ] AVX512BW,FUTURE */
        /* 241(f2 7d 48) 303 001(38) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPMINSB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38709, 557},
    /*   9 : VPMINSB zmmreg|mask|z,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f38.wig 38 /r    ] ND,AVX512BW,FUTURE */
        /* 240(f2 7d 48) 303 001(38) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPMINSB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38718, 557},
};

static const struct itemplate instrux_VPMINSW[10] = {
    /*   0 : VPMINSW xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f ea /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(ea) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMINSW, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60610, 434},
    /*   1 : VPMINSW xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f ea /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(ea) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMINSW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60617, 434},
    /*   2 : VPMINSW ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f ea /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(ea) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMINSW, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63648, 468},
    /*   3 : VPMINSW ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f ea /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(ea) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMINSW, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63655, 468},
    /*   4 : VPMINSW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f.wig ea /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 08) 303 001(ea) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMINSW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38835, 556},
    /*   5 : VPMINSW xmmreg|mask|z,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f.wig ea /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 303 001(ea) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMINSW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38844, 556},
    /*   6 : VPMINSW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f.wig ea /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 28) 303 001(ea) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMINSW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38853, 556},
    /*   7 : VPMINSW ymmreg|mask|z,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f.wig ea /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 303 001(ea) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMINSW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38862, 556},
    /*   8 : VPMINSW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f.wig ea /r      ] AVX512BW,FUTURE */
        /* 241(f1 7d 48) 303 001(ea) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPMINSW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38871, 557},
    /*   9 : VPMINSW zmmreg|mask|z,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f.wig ea /r      ] ND,AVX512BW,FUTURE */
        /* 240(f1 7d 48) 303 001(ea) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPMINSW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38880, 557},
};

static const struct itemplate instrux_VPMINSD[10] = {
    /*   0 : VPMINSD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f38 39 /r         ] AVX,SANDYBRIDGE */
        /* 261(002 001) 001(39) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMINSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60624, 434},
    /*   1 : VPMINSD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f38 39 /r         ] ND,AVX,SANDYBRIDGE */
        /* 260(002 001) 001(39) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMINSD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60631, 434},
    /*   2 : VPMINSD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f38 39 /r         ] AVX2,FUTURE */
        /* 261(002 005) 001(39) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMINSD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63662, 468},
    /*   3 : VPMINSD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f38 39 /r         ] ND,AVX2,FUTURE */
        /* 260(002 005) 001(39) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMINSD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63669, 468},
    /*   4 : VPMINSD xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f38.w0 39 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 08) 301 001(39) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMINSD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+38727, 544},
    /*   5 : VPMINSD xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.nds.128.66.0f38.w0 39 /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 7d 08) 301 001(39) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMINSD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+38736, 544},
    /*   6 : VPMINSD ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f38.w0 39 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 28) 301 001(39) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMINSD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+38745, 544},
    /*   7 : VPMINSD ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.nds.256.66.0f38.w0 39 /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 7d 28) 301 001(39) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMINSD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+38754, 544},
    /*   8 : VPMINSD zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv:   evex.nds.512.66.0f38.w0 39 /r     ] AVX512,FUTURE */
        /* 241(f2 7d 48) 301 001(39) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMINSD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+38763, 545},
    /*   9 : VPMINSD zmmreg|mask|z,zmmrm512|b32 [r+vm:fv:   evex.nds.512.66.0f38.w0 39 /r     ] ND,AVX512,FUTURE */
        /* 240(f2 7d 48) 301 001(39) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMINSD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+38772, 545},
};

static const struct itemplate instrux_VPMINUB[10] = {
    /*   0 : VPMINUB xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f da /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(da) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMINUB, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60638, 434},
    /*   1 : VPMINUB xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f da /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(da) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMINUB, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60645, 434},
    /*   2 : VPMINUB ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f da /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(da) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMINUB, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63676, 468},
    /*   3 : VPMINUB ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f da /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(da) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMINUB, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63683, 468},
    /*   4 : VPMINUB xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f.wig da /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 08) 303 001(da) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMINUB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38889, 556},
    /*   5 : VPMINUB xmmreg|mask|z,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f.wig da /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 303 001(da) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMINUB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38898, 556},
    /*   6 : VPMINUB ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f.wig da /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 28) 303 001(da) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMINUB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38907, 556},
    /*   7 : VPMINUB ymmreg|mask|z,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f.wig da /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 303 001(da) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMINUB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38916, 556},
    /*   8 : VPMINUB zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f.wig da /r      ] AVX512BW,FUTURE */
        /* 241(f1 7d 48) 303 001(da) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPMINUB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38925, 557},
    /*   9 : VPMINUB zmmreg|mask|z,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f.wig da /r      ] ND,AVX512BW,FUTURE */
        /* 240(f1 7d 48) 303 001(da) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPMINUB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38934, 557},
};

static const struct itemplate instrux_VPMINUW[10] = {
    /*   0 : VPMINUW xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f38 3a /r         ] AVX,SANDYBRIDGE */
        /* 261(002 001) 001(3a) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMINUW, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60652, 434},
    /*   1 : VPMINUW xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f38 3a /r         ] ND,AVX,SANDYBRIDGE */
        /* 260(002 001) 001(3a) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMINUW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60659, 434},
    /*   2 : VPMINUW ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f38 3a /r         ] AVX2,FUTURE */
        /* 261(002 005) 001(3a) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMINUW, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63690, 468},
    /*   3 : VPMINUW ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f38 3a /r         ] ND,AVX2,FUTURE */
        /* 260(002 005) 001(3a) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMINUW, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63697, 468},
    /*   4 : VPMINUW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f38.wig 3a /r    ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f2 7d 08) 303 001(3a) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMINUW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39051, 556},
    /*   5 : VPMINUW xmmreg|mask|z,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f38.wig 3a /r    ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f2 7d 08) 303 001(3a) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMINUW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39060, 556},
    /*   6 : VPMINUW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f38.wig 3a /r    ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f2 7d 28) 303 001(3a) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMINUW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39069, 556},
    /*   7 : VPMINUW ymmreg|mask|z,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f38.wig 3a /r    ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f2 7d 28) 303 001(3a) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMINUW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39078, 556},
    /*   8 : VPMINUW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f38.wig 3a /r    ] AVX512BW,FUTURE */
        /* 241(f2 7d 48) 303 001(3a) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPMINUW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39087, 557},
    /*   9 : VPMINUW zmmreg|mask|z,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f38.wig 3a /r    ] ND,AVX512BW,FUTURE */
        /* 240(f2 7d 48) 303 001(3a) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPMINUW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39096, 557},
};

static const struct itemplate instrux_VPMINUD[10] = {
    /*   0 : VPMINUD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f38 3b /r         ] AVX,SANDYBRIDGE */
        /* 261(002 001) 001(3b) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMINUD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60666, 434},
    /*   1 : VPMINUD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f38 3b /r         ] ND,AVX,SANDYBRIDGE */
        /* 260(002 001) 001(3b) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMINUD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60673, 434},
    /*   2 : VPMINUD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f38 3b /r         ] AVX2,FUTURE */
        /* 261(002 005) 001(3b) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMINUD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63704, 468},
    /*   3 : VPMINUD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f38 3b /r         ] ND,AVX2,FUTURE */
        /* 260(002 005) 001(3b) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMINUD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63711, 468},
    /*   4 : VPMINUD xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f38.w0 3b /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 08) 301 001(3b) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMINUD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+38943, 544},
    /*   5 : VPMINUD xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.nds.128.66.0f38.w0 3b /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 7d 08) 301 001(3b) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMINUD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+38952, 544},
    /*   6 : VPMINUD ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f38.w0 3b /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 28) 301 001(3b) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMINUD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+38961, 544},
    /*   7 : VPMINUD ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.nds.256.66.0f38.w0 3b /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 7d 28) 301 001(3b) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMINUD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+38970, 544},
    /*   8 : VPMINUD zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv:   evex.nds.512.66.0f38.w0 3b /r     ] AVX512,FUTURE */
        /* 241(f2 7d 48) 301 001(3b) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMINUD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+38979, 545},
    /*   9 : VPMINUD zmmreg|mask|z,zmmrm512|b32 [r+vm:fv:   evex.nds.512.66.0f38.w0 3b /r     ] ND,AVX512,FUTURE */
        /* 240(f2 7d 48) 301 001(3b) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMINUD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+38988, 545},
};

static const struct itemplate instrux_VPMOVMSKB[4] = {
    /*   0 : VPMOVMSKB reg64,xmmreg [rm:       vex.128.66.0f d7 /r               ] LONG,PROT,AVX,X86_64,SANDYBRIDGE */
        /* 270(001 001) 001(d7) 110 : NOAPX,WIG,LONG,VEX,PROT,AVX,SANDYBRIDGE */
        {I_VPMOVMSKB, 2, {REG_GPR|BITS64|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60680, 456},
    /*   1 : VPMOVMSKB reg32,xmmreg [rm:       vex.128.66.0f d7 /r               ] AVX,SANDYBRIDGE */
        /* 270(001 001) 001(d7) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMOVMSKB, 2, {REG_GPR|BITS32|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60680, 434},
    /*   2 : VPMOVMSKB reg32,ymmreg [rm:       vex.256.66.0f d7 /r               ] AVX2,FUTURE */
        /* 270(001 005) 001(d7) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMOVMSKB, 2, {REG_GPR|BITS32|RN_L16,YMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63718, 468},
    /*   3 : VPMOVMSKB reg64,ymmreg [rm:       vex.256.66.0f d7 /r               ] AVX2,FUTURE */
        /* 270(001 005) 001(d7) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMOVMSKB, 2, {REG_GPR|BITS64|RN_L16,YMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63718, 468},
};

static const struct itemplate instrux_VPMOVSXBW[5] = {
    /*   0 : VPMOVSXBW xmmreg,xmmrm64 [rm:       vex.128.66.0f38 20 /r             ] AVX,SANDYBRIDGE */
        /* 270(002 001) 001(20) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMOVSXBW, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60687, 434},
    /*   1 : VPMOVSXBW ymmreg,xmmrm128 [rm:       vex.256.66.0f38 20 /r             ] AVX2,FUTURE */
        /* 270(002 005) 001(20) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMOVSXBW, 2, {YMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63725, 468},
    /*   2 : VPMOVSXBW xmmreg|mask|z,xmmrm64 [rm:hvm:   evex.128.66.0f38.wig 20 /r        ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7d 08) 314 001(20) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMOVSXBW, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39942, 556},
    /*   3 : VPMOVSXBW ymmreg|mask|z,xmmrm128 [rm:hvm:   evex.256.66.0f38.wig 20 /r        ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7d 28) 314 001(20) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMOVSXBW, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39951, 556},
    /*   4 : VPMOVSXBW zmmreg|mask|z,ymmrm256 [rm:hvm:   evex.512.66.0f38.wig 20 /r        ] AVX512BW,FUTURE */
        /* 250(f2 7d 48) 314 001(20) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPMOVSXBW, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39960, 557},
};

static const struct itemplate instrux_VPMOVSXBD[6] = {
    /*   0 : VPMOVSXBD xmmreg,xmmrm32 [rm:       vex.128.66.0f38 21 /r             ] AVX,SANDYBRIDGE */
        /* 270(002 001) 001(21) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMOVSXBD, 2, {XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60694, 434},
    /*   1 : VPMOVSXBD ymmreg,mem64 [rm:       vex.256.66.0f38 21 /r             ] AVX2,FUTURE */
        /* 270(002 005) 001(21) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMOVSXBD, 2, {YMMREG|RN_L16,MEMORY|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63732, 468},
    /*   2 : VPMOVSXBD ymmreg,xmmreg [rm:       vex.256.66.0f38 21 /r             ] AVX2,FUTURE */
        /* 270(002 005) 001(21) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMOVSXBD, 2, {YMMREG|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63732, 468},
    /*   3 : VPMOVSXBD xmmreg|mask|z,xmmrm32 [rm:qvm:   evex.128.66.0f38.wig 21 /r        ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 08) 315 001(21) 110 : WIG,EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVSXBD, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39888, 564},
    /*   4 : VPMOVSXBD ymmreg|mask|z,xmmrm64 [rm:qvm:   evex.256.66.0f38.wig 21 /r        ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 28) 315 001(21) 110 : WIG,EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVSXBD, 2, {YMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39897, 564},
    /*   5 : VPMOVSXBD zmmreg|mask|z,xmmrm128 [rm:qvm:   evex.512.66.0f38.wig 21 /r        ] AVX512,FUTURE */
        /* 250(f2 7d 48) 315 001(21) 110 : WIG,EVEX,PROT,AVX512,FUTURE */
        {I_VPMOVSXBD, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39906, 553},
};

static const struct itemplate instrux_VPMOVSXBQ[6] = {
    /*   0 : VPMOVSXBQ xmmreg,xmmrm16 [rm:       vex.128.66.0f38 22 /r             ] AVX,SANDYBRIDGE */
        /* 270(002 001) 001(22) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMOVSXBQ, 2, {XMMREG|RN_L16,RM_XMM|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60701, 434},
    /*   1 : VPMOVSXBQ ymmreg,mem32 [rm:       vex.256.66.0f38 22 /r             ] AVX2,FUTURE */
        /* 270(002 005) 001(22) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMOVSXBQ, 2, {YMMREG|RN_L16,MEMORY|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63739, 468},
    /*   2 : VPMOVSXBQ ymmreg,xmmreg [rm:       vex.256.66.0f38 22 /r             ] AVX2,FUTURE */
        /* 270(002 005) 001(22) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMOVSXBQ, 2, {YMMREG|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63739, 468},
    /*   3 : VPMOVSXBQ xmmreg|mask|z,xmmrm16 [rm:ovm:   evex.128.66.0f38.wig 22 /r        ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 08) 316 001(22) 110 : WIG,EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVSXBQ, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39915, 564},
    /*   4 : VPMOVSXBQ ymmreg|mask|z,xmmrm32 [rm:ovm:   evex.256.66.0f38.wig 22 /r        ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 28) 316 001(22) 110 : WIG,EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVSXBQ, 2, {YMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39924, 564},
    /*   5 : VPMOVSXBQ zmmreg|mask|z,xmmrm64 [rm:ovm:   evex.512.66.0f38.wig 22 /r        ] AVX512,FUTURE */
        /* 250(f2 7d 48) 316 001(22) 110 : WIG,EVEX,PROT,AVX512,FUTURE */
        {I_VPMOVSXBQ, 2, {ZMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39933, 553},
};

static const struct itemplate instrux_VPMOVSXWD[5] = {
    /*   0 : VPMOVSXWD xmmreg,xmmrm64 [rm:       vex.128.66.0f38 23 /r             ] AVX,SANDYBRIDGE */
        /* 270(002 001) 001(23) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMOVSXWD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60708, 434},
    /*   1 : VPMOVSXWD ymmreg,xmmrm128 [rm:       vex.256.66.0f38 23 /r             ] AVX2,FUTURE */
        /* 270(002 005) 001(23) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMOVSXWD, 2, {YMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63746, 468},
    /*   2 : VPMOVSXWD xmmreg|mask|z,xmmrm64 [rm:hvm:   evex.128.66.0f38.wig 23 /r        ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 08) 314 001(23) 110 : WIG,EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVSXWD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39996, 564},
    /*   3 : VPMOVSXWD ymmreg|mask|z,xmmrm128 [rm:hvm:   evex.256.66.0f38.wig 23 /r        ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 28) 314 001(23) 110 : WIG,EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVSXWD, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40005, 564},
    /*   4 : VPMOVSXWD zmmreg|mask|z,ymmrm256 [rm:hvm:   evex.512.66.0f38.wig 23 /r        ] AVX512,FUTURE */
        /* 250(f2 7d 48) 314 001(23) 110 : WIG,EVEX,PROT,AVX512,FUTURE */
        {I_VPMOVSXWD, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40014, 553},
};

static const struct itemplate instrux_VPMOVSXWQ[6] = {
    /*   0 : VPMOVSXWQ xmmreg,xmmrm32 [rm:       vex.128.66.0f38 24 /r             ] AVX,SANDYBRIDGE */
        /* 270(002 001) 001(24) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMOVSXWQ, 2, {XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60715, 434},
    /*   1 : VPMOVSXWQ ymmreg,mem64 [rm:       vex.256.66.0f38 24 /r             ] AVX2,FUTURE */
        /* 270(002 005) 001(24) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMOVSXWQ, 2, {YMMREG|RN_L16,MEMORY|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63753, 468},
    /*   2 : VPMOVSXWQ ymmreg,xmmreg [rm:       vex.256.66.0f38 24 /r             ] AVX2,FUTURE */
        /* 270(002 005) 001(24) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMOVSXWQ, 2, {YMMREG|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63753, 468},
    /*   3 : VPMOVSXWQ xmmreg|mask|z,xmmrm32 [rm:qvm:   evex.128.66.0f38.wig 24 /r        ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 08) 315 001(24) 110 : WIG,EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVSXWQ, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40023, 564},
    /*   4 : VPMOVSXWQ ymmreg|mask|z,xmmrm64 [rm:qvm:   evex.256.66.0f38.wig 24 /r        ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 28) 315 001(24) 110 : WIG,EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVSXWQ, 2, {YMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40032, 564},
    /*   5 : VPMOVSXWQ zmmreg|mask|z,xmmrm128 [rm:qvm:   evex.512.66.0f38.wig 24 /r        ] AVX512,FUTURE */
        /* 250(f2 7d 48) 315 001(24) 110 : WIG,EVEX,PROT,AVX512,FUTURE */
        {I_VPMOVSXWQ, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40041, 553},
};

static const struct itemplate instrux_VPMOVSXDQ[5] = {
    /*   0 : VPMOVSXDQ xmmreg,xmmrm64 [rm:       vex.128.66.0f38 25 /r             ] AVX,SANDYBRIDGE */
        /* 270(002 001) 001(25) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMOVSXDQ, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60722, 434},
    /*   1 : VPMOVSXDQ ymmreg,xmmrm128 [rm:       vex.256.66.0f38 25 /r             ] AVX2,FUTURE */
        /* 270(002 005) 001(25) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMOVSXDQ, 2, {YMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63760, 468},
    /*   2 : VPMOVSXDQ xmmreg|mask|z,xmmrm64 [rm:hvm:   evex.128.66.0f38.w0 25 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 08) 314 001(25) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVSXDQ, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39969, 544},
    /*   3 : VPMOVSXDQ ymmreg|mask|z,xmmrm128 [rm:hvm:   evex.256.66.0f38.w0 25 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 28) 314 001(25) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVSXDQ, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39978, 544},
    /*   4 : VPMOVSXDQ zmmreg|mask|z,ymmrm256 [rm:hvm:   evex.512.66.0f38.w0 25 /r         ] AVX512,FUTURE */
        /* 250(f2 7d 48) 314 001(25) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMOVSXDQ, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39987, 545},
};

static const struct itemplate instrux_VPMOVZXBW[5] = {
    /*   0 : VPMOVZXBW xmmreg,xmmrm64 [rm:       vex.128.66.0f38 30 /r             ] AVX,SANDYBRIDGE */
        /* 270(002 001) 001(30) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMOVZXBW, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60729, 434},
    /*   1 : VPMOVZXBW ymmreg,xmmrm128 [rm:       vex.256.66.0f38 30 /r             ] AVX2,FUTURE */
        /* 270(002 005) 001(30) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMOVZXBW, 2, {YMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63767, 468},
    /*   2 : VPMOVZXBW xmmreg|mask|z,xmmrm64 [rm:hvm:   evex.128.66.0f38.wig 30 /r        ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7d 08) 314 001(30) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMOVZXBW, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40509, 556},
    /*   3 : VPMOVZXBW ymmreg|mask|z,xmmrm128 [rm:hvm:   evex.256.66.0f38.wig 30 /r        ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7d 28) 314 001(30) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMOVZXBW, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40518, 556},
    /*   4 : VPMOVZXBW zmmreg|mask|z,ymmrm256 [rm:hvm:   evex.512.66.0f38.wig 30 /r        ] AVX512BW,FUTURE */
        /* 250(f2 7d 48) 314 001(30) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPMOVZXBW, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40527, 557},
};

static const struct itemplate instrux_VPMOVZXBD[6] = {
    /*   0 : VPMOVZXBD xmmreg,xmmrm32 [rm:       vex.128.66.0f38 31 /r             ] AVX,SANDYBRIDGE */
        /* 270(002 001) 001(31) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMOVZXBD, 2, {XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60736, 434},
    /*   1 : VPMOVZXBD ymmreg,mem64 [rm:       vex.256.66.0f38 31 /r             ] AVX2,FUTURE */
        /* 270(002 005) 001(31) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMOVZXBD, 2, {YMMREG|RN_L16,MEMORY|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63774, 468},
    /*   2 : VPMOVZXBD ymmreg,xmmreg [rm:       vex.256.66.0f38 31 /r             ] AVX2,FUTURE */
        /* 270(002 005) 001(31) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMOVZXBD, 2, {YMMREG|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63774, 468},
    /*   3 : VPMOVZXBD xmmreg|mask|z,xmmrm32 [rm:qvm:   evex.128.66.0f38.wig 31 /r        ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 08) 315 001(31) 110 : WIG,EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVZXBD, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40455, 564},
    /*   4 : VPMOVZXBD ymmreg|mask|z,xmmrm64 [rm:qvm:   evex.256.66.0f38.wig 31 /r        ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 28) 315 001(31) 110 : WIG,EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVZXBD, 2, {YMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40464, 564},
    /*   5 : VPMOVZXBD zmmreg|mask|z,xmmrm128 [rm:qvm:   evex.512.66.0f38.wig 31 /r        ] AVX512,FUTURE */
        /* 250(f2 7d 48) 315 001(31) 110 : WIG,EVEX,PROT,AVX512,FUTURE */
        {I_VPMOVZXBD, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40473, 553},
};

static const struct itemplate instrux_VPMOVZXBQ[6] = {
    /*   0 : VPMOVZXBQ xmmreg,xmmrm16 [rm:       vex.128.66.0f38 32 /r             ] AVX,SANDYBRIDGE */
        /* 270(002 001) 001(32) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMOVZXBQ, 2, {XMMREG|RN_L16,RM_XMM|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60743, 434},
    /*   1 : VPMOVZXBQ ymmreg,mem32 [rm:       vex.256.66.0f38 32 /r             ] AVX2,FUTURE */
        /* 270(002 005) 001(32) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMOVZXBQ, 2, {YMMREG|RN_L16,MEMORY|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63781, 468},
    /*   2 : VPMOVZXBQ ymmreg,xmmreg [rm:       vex.256.66.0f38 32 /r             ] AVX2,FUTURE */
        /* 270(002 005) 001(32) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMOVZXBQ, 2, {YMMREG|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63781, 468},
    /*   3 : VPMOVZXBQ xmmreg|mask|z,xmmrm16 [rm:ovm:   evex.128.66.0f38.wig 32 /r        ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 08) 316 001(32) 110 : WIG,EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVZXBQ, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40482, 564},
    /*   4 : VPMOVZXBQ ymmreg|mask|z,xmmrm32 [rm:ovm:   evex.256.66.0f38.wig 32 /r        ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 28) 316 001(32) 110 : WIG,EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVZXBQ, 2, {YMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40491, 564},
    /*   5 : VPMOVZXBQ zmmreg|mask|z,xmmrm64 [rm:ovm:   evex.512.66.0f38.wig 32 /r        ] AVX512,FUTURE */
        /* 250(f2 7d 48) 316 001(32) 110 : WIG,EVEX,PROT,AVX512,FUTURE */
        {I_VPMOVZXBQ, 2, {ZMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40500, 553},
};

static const struct itemplate instrux_VPMOVZXWD[5] = {
    /*   0 : VPMOVZXWD xmmreg,xmmrm64 [rm:       vex.128.66.0f38 33 /r             ] AVX,SANDYBRIDGE */
        /* 270(002 001) 001(33) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMOVZXWD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60750, 434},
    /*   1 : VPMOVZXWD ymmreg,xmmrm128 [rm:       vex.256.66.0f38 33 /r             ] AVX2,FUTURE */
        /* 270(002 005) 001(33) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMOVZXWD, 2, {YMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63788, 468},
    /*   2 : VPMOVZXWD xmmreg|mask|z,xmmrm64 [rm:hvm:   evex.128.66.0f38.wig 33 /r        ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 08) 314 001(33) 110 : WIG,EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVZXWD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40563, 564},
    /*   3 : VPMOVZXWD ymmreg|mask|z,xmmrm128 [rm:hvm:   evex.256.66.0f38.wig 33 /r        ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 28) 314 001(33) 110 : WIG,EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVZXWD, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40572, 564},
    /*   4 : VPMOVZXWD zmmreg|mask|z,ymmrm256 [rm:hvm:   evex.512.66.0f38.wig 33 /r        ] AVX512,FUTURE */
        /* 250(f2 7d 48) 314 001(33) 110 : WIG,EVEX,PROT,AVX512,FUTURE */
        {I_VPMOVZXWD, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40581, 553},
};

static const struct itemplate instrux_VPMOVZXWQ[6] = {
    /*   0 : VPMOVZXWQ xmmreg,xmmrm32 [rm:       vex.128.66.0f38 34 /r             ] AVX,SANDYBRIDGE */
        /* 270(002 001) 001(34) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMOVZXWQ, 2, {XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60757, 434},
    /*   1 : VPMOVZXWQ ymmreg,mem64 [rm:       vex.256.66.0f38 34 /r             ] AVX2,FUTURE */
        /* 270(002 005) 001(34) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMOVZXWQ, 2, {YMMREG|RN_L16,MEMORY|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63795, 468},
    /*   2 : VPMOVZXWQ ymmreg,xmmreg [rm:       vex.256.66.0f38 34 /r             ] AVX2,FUTURE */
        /* 270(002 005) 001(34) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMOVZXWQ, 2, {YMMREG|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63795, 468},
    /*   3 : VPMOVZXWQ xmmreg|mask|z,xmmrm32 [rm:qvm:   evex.128.66.0f38.wig 34 /r        ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 08) 315 001(34) 110 : WIG,EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVZXWQ, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40590, 564},
    /*   4 : VPMOVZXWQ ymmreg|mask|z,xmmrm64 [rm:qvm:   evex.256.66.0f38.wig 34 /r        ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 28) 315 001(34) 110 : WIG,EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVZXWQ, 2, {YMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40599, 564},
    /*   5 : VPMOVZXWQ zmmreg|mask|z,xmmrm128 [rm:qvm:   evex.512.66.0f38.wig 34 /r        ] AVX512,FUTURE */
        /* 250(f2 7d 48) 315 001(34) 110 : WIG,EVEX,PROT,AVX512,FUTURE */
        {I_VPMOVZXWQ, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40608, 553},
};

static const struct itemplate instrux_VPMOVZXDQ[5] = {
    /*   0 : VPMOVZXDQ xmmreg,xmmrm64 [rm:       vex.128.66.0f38 35 /r             ] AVX,SANDYBRIDGE */
        /* 270(002 001) 001(35) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMOVZXDQ, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60764, 434},
    /*   1 : VPMOVZXDQ ymmreg,xmmrm128 [rm:       vex.256.66.0f38 35 /r             ] AVX2,FUTURE */
        /* 270(002 005) 001(35) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMOVZXDQ, 2, {YMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63802, 468},
    /*   2 : VPMOVZXDQ xmmreg|mask|z,xmmrm64 [rm:hvm:   evex.128.66.0f38.w0 35 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 08) 314 001(35) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVZXDQ, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40536, 544},
    /*   3 : VPMOVZXDQ ymmreg|mask|z,xmmrm128 [rm:hvm:   evex.256.66.0f38.w0 35 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 28) 314 001(35) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVZXDQ, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40545, 544},
    /*   4 : VPMOVZXDQ zmmreg|mask|z,ymmrm256 [rm:hvm:   evex.512.66.0f38.w0 35 /r         ] AVX512,FUTURE */
        /* 250(f2 7d 48) 314 001(35) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMOVZXDQ, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40554, 545},
};

static const struct itemplate instrux_VPMULHUW[10] = {
    /*   0 : VPMULHUW xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f e4 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(e4) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMULHUW, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60771, 434},
    /*   1 : VPMULHUW xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f e4 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(e4) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMULHUW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60778, 434},
    /*   2 : VPMULHUW ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f e4 /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(e4) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMULHUW, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63837, 468},
    /*   3 : VPMULHUW ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f e4 /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(e4) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMULHUW, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63844, 468},
    /*   4 : VPMULHUW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f.wig e4 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 08) 303 001(e4) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMULHUW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40725, 556},
    /*   5 : VPMULHUW xmmreg|mask|z,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f.wig e4 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 303 001(e4) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMULHUW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40734, 556},
    /*   6 : VPMULHUW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f.wig e4 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 28) 303 001(e4) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMULHUW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40743, 556},
    /*   7 : VPMULHUW ymmreg|mask|z,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f.wig e4 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 303 001(e4) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMULHUW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40752, 556},
    /*   8 : VPMULHUW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f.wig e4 /r      ] AVX512BW,FUTURE */
        /* 241(f1 7d 48) 303 001(e4) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPMULHUW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40761, 557},
    /*   9 : VPMULHUW zmmreg|mask|z,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f.wig e4 /r      ] ND,AVX512BW,FUTURE */
        /* 240(f1 7d 48) 303 001(e4) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPMULHUW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40770, 557},
};

static const struct itemplate instrux_VPMULHRSW[10] = {
    /*   0 : VPMULHRSW xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f38 0b /r         ] AVX,SANDYBRIDGE */
        /* 261(002 001) 001(0b) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMULHRSW, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60785, 434},
    /*   1 : VPMULHRSW xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f38 0b /r         ] ND,AVX,SANDYBRIDGE */
        /* 260(002 001) 001(0b) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMULHRSW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60792, 434},
    /*   2 : VPMULHRSW ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f38 0b /r         ] AVX2,FUTURE */
        /* 261(002 005) 001(0b) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMULHRSW, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63823, 468},
    /*   3 : VPMULHRSW ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f38 0b /r         ] ND,AVX2,FUTURE */
        /* 260(002 005) 001(0b) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMULHRSW, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63830, 468},
    /*   4 : VPMULHRSW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f38.wig 0b /r    ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f2 7d 08) 303 001(0b) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMULHRSW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40671, 556},
    /*   5 : VPMULHRSW xmmreg|mask|z,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f38.wig 0b /r    ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f2 7d 08) 303 001(0b) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMULHRSW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40680, 556},
    /*   6 : VPMULHRSW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f38.wig 0b /r    ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f2 7d 28) 303 001(0b) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMULHRSW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40689, 556},
    /*   7 : VPMULHRSW ymmreg|mask|z,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f38.wig 0b /r    ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f2 7d 28) 303 001(0b) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMULHRSW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40698, 556},
    /*   8 : VPMULHRSW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f38.wig 0b /r    ] AVX512BW,FUTURE */
        /* 241(f2 7d 48) 303 001(0b) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPMULHRSW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40707, 557},
    /*   9 : VPMULHRSW zmmreg|mask|z,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f38.wig 0b /r    ] ND,AVX512BW,FUTURE */
        /* 240(f2 7d 48) 303 001(0b) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPMULHRSW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40716, 557},
};

static const struct itemplate instrux_VPMULHW[10] = {
    /*   0 : VPMULHW xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f e5 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(e5) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMULHW, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60799, 434},
    /*   1 : VPMULHW xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f e5 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(e5) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMULHW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60806, 434},
    /*   2 : VPMULHW ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f e5 /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(e5) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMULHW, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63851, 468},
    /*   3 : VPMULHW ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f e5 /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(e5) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMULHW, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63858, 468},
    /*   4 : VPMULHW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f.wig e5 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 08) 303 001(e5) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMULHW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40779, 556},
    /*   5 : VPMULHW xmmreg|mask|z,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f.wig e5 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 303 001(e5) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMULHW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40788, 556},
    /*   6 : VPMULHW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f.wig e5 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 28) 303 001(e5) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMULHW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40797, 556},
    /*   7 : VPMULHW ymmreg|mask|z,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f.wig e5 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 303 001(e5) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMULHW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40806, 556},
    /*   8 : VPMULHW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f.wig e5 /r      ] AVX512BW,FUTURE */
        /* 241(f1 7d 48) 303 001(e5) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPMULHW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40815, 557},
    /*   9 : VPMULHW zmmreg|mask|z,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f.wig e5 /r      ] ND,AVX512BW,FUTURE */
        /* 240(f1 7d 48) 303 001(e5) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPMULHW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40824, 557},
};

static const struct itemplate instrux_VPMULLW[10] = {
    /*   0 : VPMULLW xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f d5 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(d5) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMULLW, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60813, 434},
    /*   1 : VPMULLW xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f d5 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(d5) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMULLW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60820, 434},
    /*   2 : VPMULLW ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f d5 /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(d5) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMULLW, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63865, 468},
    /*   3 : VPMULLW ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f d5 /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(d5) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMULLW, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63872, 468},
    /*   4 : VPMULLW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f.wig d5 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 08) 303 001(d5) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMULLW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40941, 556},
    /*   5 : VPMULLW xmmreg|mask|z,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f.wig d5 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 303 001(d5) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMULLW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40950, 556},
    /*   6 : VPMULLW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f.wig d5 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 28) 303 001(d5) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMULLW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40959, 556},
    /*   7 : VPMULLW ymmreg|mask|z,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f.wig d5 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 303 001(d5) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMULLW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40968, 556},
    /*   8 : VPMULLW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f.wig d5 /r      ] AVX512BW,FUTURE */
        /* 241(f1 7d 48) 303 001(d5) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPMULLW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40977, 557},
    /*   9 : VPMULLW zmmreg|mask|z,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f.wig d5 /r      ] ND,AVX512BW,FUTURE */
        /* 240(f1 7d 48) 303 001(d5) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPMULLW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40986, 557},
};

static const struct itemplate instrux_VPMULLD[10] = {
    /*   0 : VPMULLD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f38 40 /r         ] AVX,SANDYBRIDGE */
        /* 261(002 001) 001(40) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMULLD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60827, 434},
    /*   1 : VPMULLD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f38 40 /r         ] ND,AVX,SANDYBRIDGE */
        /* 260(002 001) 001(40) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMULLD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60834, 434},
    /*   2 : VPMULLD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f38 40 /r         ] AVX2,FUTURE */
        /* 261(002 005) 001(40) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMULLD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63879, 468},
    /*   3 : VPMULLD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f38 40 /r         ] ND,AVX2,FUTURE */
        /* 260(002 005) 001(40) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMULLD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63886, 468},
    /*   4 : VPMULLD xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f38.w0 40 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 08) 301 001(40) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMULLD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+40833, 544},
    /*   5 : VPMULLD xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.nds.128.66.0f38.w0 40 /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 7d 08) 301 001(40) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMULLD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+40842, 544},
    /*   6 : VPMULLD ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f38.w0 40 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 28) 301 001(40) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMULLD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+40851, 544},
    /*   7 : VPMULLD ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.nds.256.66.0f38.w0 40 /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 7d 28) 301 001(40) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMULLD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+40860, 544},
    /*   8 : VPMULLD zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv:   evex.nds.512.66.0f38.w0 40 /r     ] AVX512,FUTURE */
        /* 241(f2 7d 48) 301 001(40) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMULLD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+40869, 545},
    /*   9 : VPMULLD zmmreg|mask|z,zmmrm512|b32 [r+vm:fv:   evex.nds.512.66.0f38.w0 40 /r     ] ND,AVX512,FUTURE */
        /* 240(f2 7d 48) 301 001(40) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMULLD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+40878, 545},
};

static const struct itemplate instrux_VPMULUDQ[10] = {
    /*   0 : VPMULUDQ xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f f4 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(f4) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMULUDQ, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60841, 434},
    /*   1 : VPMULUDQ xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f f4 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(f4) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMULUDQ, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60848, 434},
    /*   2 : VPMULUDQ ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f f4 /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(f4) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMULUDQ, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63893, 468},
    /*   3 : VPMULUDQ ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f f4 /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(f4) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMULUDQ, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63900, 468},
    /*   4 : VPMULUDQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f.w1 f4 /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(f4) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMULUDQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+41049, 544},
    /*   5 : VPMULUDQ xmmreg|mask|z,xmmrm128|b64 [r+vm:fv:   evex.nds.128.66.0f.w1 f4 /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 08) 301 001(f4) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMULUDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+41058, 544},
    /*   6 : VPMULUDQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f.w1 f4 /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(f4) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMULUDQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+41067, 544},
    /*   7 : VPMULUDQ ymmreg|mask|z,ymmrm256|b64 [r+vm:fv:   evex.nds.256.66.0f.w1 f4 /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 28) 301 001(f4) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMULUDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+41076, 544},
    /*   8 : VPMULUDQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv:   evex.nds.512.66.0f.w1 f4 /r       ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(f4) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMULUDQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+41085, 545},
    /*   9 : VPMULUDQ zmmreg|mask|z,zmmrm512|b64 [r+vm:fv:   evex.nds.512.66.0f.w1 f4 /r       ] ND,AVX512,FUTURE */
        /* 240(f1 fd 48) 301 001(f4) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMULUDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+41094, 545},
};

static const struct itemplate instrux_VPMULDQ[10] = {
    /*   0 : VPMULDQ xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f38 28 /r         ] AVX,SANDYBRIDGE */
        /* 261(002 001) 001(28) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMULDQ, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60855, 434},
    /*   1 : VPMULDQ xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f38 28 /r         ] ND,AVX,SANDYBRIDGE */
        /* 260(002 001) 001(28) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPMULDQ, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60862, 434},
    /*   2 : VPMULDQ ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f38 28 /r         ] AVX2,FUTURE */
        /* 261(002 005) 001(28) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMULDQ, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63809, 468},
    /*   3 : VPMULDQ ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f38 28 /r         ] ND,AVX2,FUTURE */
        /* 260(002 005) 001(28) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPMULDQ, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63816, 468},
    /*   4 : VPMULDQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 28 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 08) 301 001(28) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMULDQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+40617, 544},
    /*   5 : VPMULDQ xmmreg|mask|z,xmmrm128|b64 [r+vm:fv:   evex.nds.128.66.0f38.w1 28 /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 fd 08) 301 001(28) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMULDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+40626, 544},
    /*   6 : VPMULDQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 28 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 28) 301 001(28) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMULDQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+40635, 544},
    /*   7 : VPMULDQ ymmreg|mask|z,ymmrm256|b64 [r+vm:fv:   evex.nds.256.66.0f38.w1 28 /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 fd 28) 301 001(28) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMULDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+40644, 544},
    /*   8 : VPMULDQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv:   evex.nds.512.66.0f38.w1 28 /r     ] AVX512,FUTURE */
        /* 241(f2 fd 48) 301 001(28) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMULDQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+40653, 545},
    /*   9 : VPMULDQ zmmreg|mask|z,zmmrm512|b64 [r+vm:fv:   evex.nds.512.66.0f38.w1 28 /r     ] ND,AVX512,FUTURE */
        /* 240(f2 fd 48) 301 001(28) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMULDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+40662, 545},
};

static const struct itemplate instrux_VPOR[4] = {
    /*   0 : VPOR xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f eb /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(eb) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPOR, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60869, 434},
    /*   1 : VPOR xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f eb /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(eb) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPOR, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60876, 434},
    /*   2 : VPOR ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f eb /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(eb) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPOR, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63907, 468},
    /*   3 : VPOR ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f eb /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(eb) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPOR, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63914, 468},
};

static const struct itemplate instrux_VPSADBW[10] = {
    /*   0 : VPSADBW xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f f6 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(f6) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSADBW, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60883, 434},
    /*   1 : VPSADBW xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f f6 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(f6) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSADBW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60890, 434},
    /*   2 : VPSADBW ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f f6 /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(f6) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSADBW, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63921, 468},
    /*   3 : VPSADBW ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f f6 /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(f6) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSADBW, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63928, 468},
    /*   4 : VPSADBW xmmreg,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f.wig f6 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 08) 303 001(f6) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSADBW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+41427, 556},
    /*   5 : VPSADBW xmmreg,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f.wig f6 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 303 001(f6) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSADBW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+41436, 556},
    /*   6 : VPSADBW ymmreg,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f.wig f6 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 28) 303 001(f6) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSADBW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+41445, 556},
    /*   7 : VPSADBW ymmreg,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f.wig f6 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 303 001(f6) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSADBW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+41454, 556},
    /*   8 : VPSADBW zmmreg,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f.wig f6 /r      ] AVX512BW,FUTURE */
        /* 241(f1 7d 48) 303 001(f6) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPSADBW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, NO_DECORATOR, nasm_bytecodes+41463, 557},
    /*   9 : VPSADBW zmmreg,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f.wig f6 /r      ] ND,AVX512BW,FUTURE */
        /* 240(f1 7d 48) 303 001(f6) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPSADBW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+41472, 557},
};

static const struct itemplate instrux_VPSHUFB[10] = {
    /*   0 : VPSHUFB xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f38 00 /r         ] AVX,SANDYBRIDGE */
        /* 261(002 001) 001(00) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSHUFB, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60897, 434},
    /*   1 : VPSHUFB xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f38 00 /r         ] ND,AVX,SANDYBRIDGE */
        /* 260(002 001) 001(00) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSHUFB, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60904, 434},
    /*   2 : VPSHUFB ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f38 00 /r         ] AVX2,FUTURE */
        /* 261(002 005) 001(00) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSHUFB, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63935, 468},
    /*   3 : VPSHUFB ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f38 00 /r         ] ND,AVX2,FUTURE */
        /* 260(002 005) 001(00) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSHUFB, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63942, 468},
    /*   4 : VPSHUFB xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f38.wig 00 /r    ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f2 7d 08) 303 001(00) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSHUFB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41481, 556},
    /*   5 : VPSHUFB xmmreg|mask|z,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f38.wig 00 /r    ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f2 7d 08) 303 001(00) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSHUFB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41490, 556},
    /*   6 : VPSHUFB ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f38.wig 00 /r    ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f2 7d 28) 303 001(00) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSHUFB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41499, 556},
    /*   7 : VPSHUFB ymmreg|mask|z,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f38.wig 00 /r    ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f2 7d 28) 303 001(00) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSHUFB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41508, 556},
    /*   8 : VPSHUFB zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f38.wig 00 /r    ] AVX512BW,FUTURE */
        /* 241(f2 7d 48) 303 001(00) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPSHUFB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41517, 557},
    /*   9 : VPSHUFB zmmreg|mask|z,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f38.wig 00 /r    ] ND,AVX512BW,FUTURE */
        /* 240(f2 7d 48) 303 001(00) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPSHUFB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41526, 557},
};

static const struct itemplate instrux_VPSHUFD[5] = {
    /*   0 : VPSHUFD xmmreg,xmmrm128,imm8 [rmi:      vex.128.66.0f 70 /r ib            ] AVX,SANDYBRIDGE */
        /* 270(001 001) 001(70) 110 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSHUFD, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52173, 434},
    /*   1 : VPSHUFD ymmreg,ymmrm256,imm8 [rmi:      vex.256.66.0f 70 /r ib            ] AVX2,FUTURE */
        /* 270(001 005) 001(70) 110 022 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSHUFD, 3, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54165, 468},
    /*   2 : VPSHUFD xmmreg|mask|z,xmmrm128|b32,imm8 [rmi:fv:   evex.128.66.0f.w0 70 /r ib        ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7d 08) 301 001(70) 110 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSHUFD, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20463, 544},
    /*   3 : VPSHUFD ymmreg|mask|z,ymmrm256|b32,imm8 [rmi:fv:   evex.256.66.0f.w0 70 /r ib        ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7d 28) 301 001(70) 110 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSHUFD, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20473, 544},
    /*   4 : VPSHUFD zmmreg|mask|z,zmmrm512|b32,imm8 [rmi:fv:   evex.512.66.0f.w0 70 /r ib        ] AVX512,FUTURE */
        /* 250(f1 7d 48) 301 001(70) 110 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSHUFD, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20483, 545},
};

static const struct itemplate instrux_VPSHUFHW[5] = {
    /*   0 : VPSHUFHW xmmreg,xmmrm128,imm8 [rmi:      vex.128.f3.0f 70 /r ib            ] AVX,SANDYBRIDGE */
        /* 270(001 002) 001(70) 110 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSHUFHW, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52181, 434},
    /*   1 : VPSHUFHW ymmreg,ymmrm256,imm8 [rmi:      vex.256.f3.0f 70 /r ib            ] AVX2,FUTURE */
        /* 270(001 006) 001(70) 110 022 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSHUFHW, 3, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54173, 468},
    /*   2 : VPSHUFHW xmmreg|mask|z,xmmrm128,imm8 [rmi:fvm:  evex.128.f3.0f.wig 70 /r ib       ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f1 7e 08) 303 001(70) 110 022 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSHUFHW, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20493, 556},
    /*   3 : VPSHUFHW ymmreg|mask|z,ymmrm256,imm8 [rmi:fvm:  evex.256.f3.0f.wig 70 /r ib       ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f1 7e 28) 303 001(70) 110 022 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSHUFHW, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20503, 556},
    /*   4 : VPSHUFHW zmmreg|mask|z,zmmrm512,imm8 [rmi:fvm:  evex.512.f3.0f.wig 70 /r ib       ] AVX512BW,FUTURE */
        /* 250(f1 7e 48) 303 001(70) 110 022 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPSHUFHW, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20513, 557},
};

static const struct itemplate instrux_VPSHUFLW[5] = {
    /*   0 : VPSHUFLW xmmreg,xmmrm128,imm8 [rmi:      vex.128.f2.0f 70 /r ib            ] AVX,SANDYBRIDGE */
        /* 270(001 003) 001(70) 110 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSHUFLW, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52189, 434},
    /*   1 : VPSHUFLW ymmreg,ymmrm256,imm8 [rmi:      vex.256.f2.0f 70 /r ib            ] AVX2,FUTURE */
        /* 270(001 007) 001(70) 110 022 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSHUFLW, 3, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54181, 468},
    /*   2 : VPSHUFLW xmmreg|mask|z,xmmrm128,imm8 [rmi:fvm:  evex.128.f2.0f.wig 70 /r ib       ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f1 7f 08) 303 001(70) 110 022 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSHUFLW, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20523, 556},
    /*   3 : VPSHUFLW ymmreg|mask|z,ymmrm256,imm8 [rmi:fvm:  evex.256.f2.0f.wig 70 /r ib       ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f1 7f 28) 303 001(70) 110 022 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSHUFLW, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20533, 556},
    /*   4 : VPSHUFLW zmmreg|mask|z,zmmrm512,imm8 [rmi:fvm:  evex.512.f2.0f.wig 70 /r ib       ] AVX512BW,FUTURE */
        /* 250(f1 7f 48) 303 001(70) 110 022 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPSHUFLW, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20543, 557},
};

static const struct itemplate instrux_VPSIGNB[4] = {
    /*   0 : VPSIGNB xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f38 08 /r         ] AVX,SANDYBRIDGE */
        /* 261(002 001) 001(08) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSIGNB, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60911, 434},
    /*   1 : VPSIGNB xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f38 08 /r         ] ND,AVX,SANDYBRIDGE */
        /* 260(002 001) 001(08) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSIGNB, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60918, 434},
    /*   2 : VPSIGNB ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f38 08 /r         ] AVX2,FUTURE */
        /* 261(002 005) 001(08) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSIGNB, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63949, 468},
    /*   3 : VPSIGNB ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f38 08 /r         ] ND,AVX2,FUTURE */
        /* 260(002 005) 001(08) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSIGNB, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63956, 468},
};

static const struct itemplate instrux_VPSIGNW[4] = {
    /*   0 : VPSIGNW xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f38 09 /r         ] AVX,SANDYBRIDGE */
        /* 261(002 001) 001(09) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSIGNW, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60925, 434},
    /*   1 : VPSIGNW xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f38 09 /r         ] ND,AVX,SANDYBRIDGE */
        /* 260(002 001) 001(09) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSIGNW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60932, 434},
    /*   2 : VPSIGNW ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f38 09 /r         ] AVX2,FUTURE */
        /* 261(002 005) 001(09) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSIGNW, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63963, 468},
    /*   3 : VPSIGNW ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f38 09 /r         ] ND,AVX2,FUTURE */
        /* 260(002 005) 001(09) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSIGNW, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63970, 468},
};

static const struct itemplate instrux_VPSIGND[4] = {
    /*   0 : VPSIGND xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f38 0a /r         ] AVX,SANDYBRIDGE */
        /* 261(002 001) 001(0a) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSIGND, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60939, 434},
    /*   1 : VPSIGND xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f38 0a /r         ] ND,AVX,SANDYBRIDGE */
        /* 260(002 001) 001(0a) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSIGND, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60946, 434},
    /*   2 : VPSIGND ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f38 0a /r         ] AVX2,FUTURE */
        /* 261(002 005) 001(0a) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSIGND, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63977, 468},
    /*   3 : VPSIGND ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f38 0a /r         ] ND,AVX2,FUTURE */
        /* 260(002 005) 001(0a) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSIGND, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63984, 468},
};

static const struct itemplate instrux_VPSLLDQ[10] = {
    /*   0 : VPSLLDQ xmmreg,xmmreg*,imm8 [vmi:      vex.ndd.128.66.0f 73 /7 ib        ] AVX,SANDYBRIDGE */
        /* 260(001 001) 001(73) 217 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSLLDQ, 3, {XMMREG|RN_L16,XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52197, 434},
    /*   1 : VPSLLDQ xmmreg,imm8 [v+mi:      vex.ndd.128.66.0f 73 /7 ib        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(73) 207 021 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSLLDQ, 2, {XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+52205, 434},
    /*   2 : VPSLLDQ ymmreg,ymmreg*,imm8 [vmi:      vex.ndd.256.66.0f 73 /7 ib        ] AVX2,FUTURE */
        /* 260(001 005) 001(73) 217 022 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSLLDQ, 3, {YMMREG|RN_L16,YMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54189, 468},
    /*   3 : VPSLLDQ ymmreg,imm8 [v+mi:      vex.ndd.256.66.0f 73 /7 ib        ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(73) 207 021 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSLLDQ, 2, {YMMREG|RN_L16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+54197, 468},
    /*   4 : VPSLLDQ xmmreg,xmmrm128*,imm8 [vmi:fvm:  evex.nds.128.66.0f.wig 73 /7 ib   ] AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 303 001(73) 217 022 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSLLDQ, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+20613, 556},
    /*   5 : VPSLLDQ xmmreg,imm8 [v+mi:fvm:  evex.nds.128.66.0f.wig 73 /7 ib   ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 303 001(73) 207 021 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSLLDQ, 2, {XMMREG,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+20623, 556},
    /*   6 : VPSLLDQ ymmreg,ymmrm256*,imm8 [vmi:fvm:  evex.nds.256.66.0f.wig 73 /7 ib   ] AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 303 001(73) 217 022 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSLLDQ, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+20633, 556},
    /*   7 : VPSLLDQ ymmreg,imm8 [v+mi:fvm:  evex.nds.256.66.0f.wig 73 /7 ib   ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 303 001(73) 207 021 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSLLDQ, 2, {YMMREG,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+20643, 556},
    /*   8 : VPSLLDQ zmmreg,zmmrm512*,imm8 [vmi:fvm:  evex.nds.512.66.0f.wig 73 /7 ib   ] AVX512BW,FUTURE */
        /* 240(f1 7d 48) 303 001(73) 217 022 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPSLLDQ, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+20653, 557},
    /*   9 : VPSLLDQ zmmreg,imm8 [v+mi:fvm:  evex.nds.512.66.0f.wig 73 /7 ib   ] ND,AVX512BW,FUTURE */
        /* 240(f1 7d 48) 303 001(73) 207 021 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPSLLDQ, 2, {ZMMREG,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+20663, 557},
};

static const struct itemplate instrux_VPSRLDQ[10] = {
    /*   0 : VPSRLDQ xmmreg,xmmreg*,imm8 [vmi:      vex.ndd.128.66.0f 73 /3 ib        ] AVX,SANDYBRIDGE */
        /* 260(001 001) 001(73) 213 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSRLDQ, 3, {XMMREG|RN_L16,XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52213, 434},
    /*   1 : VPSRLDQ xmmreg,imm8 [v+mi:      vex.ndd.128.66.0f 73 /3 ib        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(73) 203 021 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSRLDQ, 2, {XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+52221, 434},
    /*   2 : VPSRLDQ ymmreg,ymmreg*,imm8 [vmi:      vex.ndd.256.66.0f 73 /3 ib        ] AVX2,FUTURE */
        /* 260(001 005) 001(73) 213 022 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSRLDQ, 3, {YMMREG|RN_L16,YMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54285, 468},
    /*   3 : VPSRLDQ ymmreg,imm8 [v+mi:      vex.ndd.256.66.0f 73 /3 ib        ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(73) 203 021 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSRLDQ, 2, {YMMREG|RN_L16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+54293, 468},
    /*   4 : VPSRLDQ xmmreg,xmmrm128*,imm8 [vmi:fvm:  evex.nds.128.66.0f.wig 73 /3 ib   ] AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 303 001(73) 213 022 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSRLDQ, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+21033, 556},
    /*   5 : VPSRLDQ xmmreg,imm8 [v+mi:fvm:  evex.nds.128.66.0f.wig 73 /3 ib   ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 303 001(73) 203 021 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSRLDQ, 2, {XMMREG,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+21043, 556},
    /*   6 : VPSRLDQ ymmreg,ymmrm256*,imm8 [vmi:fvm:  evex.nds.256.66.0f.wig 73 /3 ib   ] AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 303 001(73) 213 022 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSRLDQ, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+21053, 556},
    /*   7 : VPSRLDQ ymmreg,imm8 [v+mi:fvm:  evex.nds.256.66.0f.wig 73 /3 ib   ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 303 001(73) 203 021 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSRLDQ, 2, {YMMREG,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+21063, 556},
    /*   8 : VPSRLDQ zmmreg,zmmrm512*,imm8 [vmi:fvm:  evex.nds.512.66.0f.wig 73 /3 ib   ] AVX512BW,FUTURE */
        /* 240(f1 7d 48) 303 001(73) 213 022 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPSRLDQ, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+21073, 557},
    /*   9 : VPSRLDQ zmmreg,imm8 [v+mi:fvm:  evex.nds.512.66.0f.wig 73 /3 ib   ] ND,AVX512BW,FUTURE */
        /* 240(f1 7d 48) 303 001(73) 203 021 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPSRLDQ, 2, {ZMMREG,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+21083, 557},
};

static const struct itemplate instrux_VPSLLW[20] = {
    /*   0 : VPSLLW xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f f1 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(f1) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSLLW, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60953, 434},
    /*   1 : VPSLLW xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f f1 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(f1) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSLLW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60960, 434},
    /*   2 : VPSLLW xmmreg,xmmreg*,imm8 [vmi:      vex.ndd.128.66.0f 71 /6 ib        ] AVX,SANDYBRIDGE */
        /* 260(001 001) 001(71) 216 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSLLW, 3, {XMMREG|RN_L16,XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52229, 434},
    /*   3 : VPSLLW xmmreg,imm8 [v+mi:      vex.ndd.128.66.0f 71 /6 ib        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(71) 206 021 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSLLW, 2, {XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+52237, 434},
    /*   4 : VPSLLW ymmreg,ymmreg*,xmmrm128 [rvm:      vex.nds.256.66.0f f1 /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(f1) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSLLW, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63991, 468},
    /*   5 : VPSLLW ymmreg,xmmrm128 [r+vm:      vex.nds.256.66.0f f1 /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(f1) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSLLW, 2, {YMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63998, 468},
    /*   6 : VPSLLW ymmreg,ymmreg*,imm8 [vmi:      vex.ndd.256.66.0f 71 /6 ib        ] AVX2,FUTURE */
        /* 260(001 005) 001(71) 216 022 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSLLW, 3, {YMMREG|RN_L16,YMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54205, 468},
    /*   7 : VPSLLW ymmreg,imm8 [v+mi:      vex.ndd.256.66.0f 71 /6 ib        ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(71) 206 021 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSLLW, 2, {YMMREG|RN_L16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+54213, 468},
    /*   8 : VPSLLW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:m128: evex.nds.128.66.0f.wig f1 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 08) 317 001(f1) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSLLW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41805, 556},
    /*   9 : VPSLLW xmmreg|mask|z,xmmrm128 [r+vm:m128: evex.nds.128.66.0f.wig f1 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 317 001(f1) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSLLW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41814, 556},
    /*  10 : VPSLLW ymmreg|mask|z,ymmreg*,xmmrm128 [rvm:m128: evex.nds.256.66.0f.wig f1 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 28) 317 001(f1) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSLLW, 3, {YMMREG,YMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41823, 556},
    /*  11 : VPSLLW ymmreg|mask|z,xmmrm128 [r+vm:m128: evex.nds.256.66.0f.wig f1 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 317 001(f1) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSLLW, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41832, 556},
    /*  12 : VPSLLW zmmreg|mask|z,zmmreg*,xmmrm128 [rvm:m128: evex.nds.512.66.0f.wig f1 /r      ] AVX512BW,FUTURE */
        /* 241(f1 7d 48) 317 001(f1) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPSLLW, 3, {ZMMREG,ZMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41841, 557},
    /*  13 : VPSLLW zmmreg|mask|z,xmmrm128 [r+vm:m128: evex.nds.512.66.0f.wig f1 /r      ] ND,AVX512BW,FUTURE */
        /* 240(f1 7d 48) 317 001(f1) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPSLLW, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41850, 557},
    /*  14 : VPSLLW xmmreg|mask|z,xmmrm128*,imm8 [vmi:fvm:  evex.nds.128.66.0f.wig 71 /6 ib   ] AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 303 001(71) 216 022 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSLLW, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20733, 556},
    /*  15 : VPSLLW xmmreg|mask|z,imm8 [v+mi:fvm:  evex.nds.128.66.0f.wig 71 /6 ib   ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 303 001(71) 206 021 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSLLW, 2, {XMMREG,IMM_NORMAL|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20743, 556},
    /*  16 : VPSLLW ymmreg|mask|z,ymmrm256*,imm8 [vmi:fvm:  evex.nds.256.66.0f.wig 71 /6 ib   ] AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 303 001(71) 216 022 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSLLW, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20753, 556},
    /*  17 : VPSLLW ymmreg|mask|z,imm8 [v+mi:fvm:  evex.nds.256.66.0f.wig 71 /6 ib   ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 303 001(71) 206 021 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSLLW, 2, {YMMREG,IMM_NORMAL|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20763, 556},
    /*  18 : VPSLLW zmmreg|mask|z,zmmrm512*,imm8 [vmi:fvm:  evex.nds.512.66.0f.wig 71 /6 ib   ] AVX512BW,FUTURE */
        /* 240(f1 7d 48) 303 001(71) 216 022 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPSLLW, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20773, 557},
    /*  19 : VPSLLW zmmreg|mask|z,imm8 [v+mi:fvm:  evex.nds.512.66.0f.wig 71 /6 ib   ] ND,AVX512BW,FUTURE */
        /* 240(f1 7d 48) 303 001(71) 206 021 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPSLLW, 2, {ZMMREG,IMM_NORMAL|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20783, 557},
};

static const struct itemplate instrux_VPSLLD[20] = {
    /*   0 : VPSLLD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f f2 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(f2) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSLLD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60967, 434},
    /*   1 : VPSLLD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f f2 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(f2) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSLLD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60974, 434},
    /*   2 : VPSLLD xmmreg,xmmreg*,imm8 [vmi:      vex.ndd.128.66.0f 72 /6 ib        ] AVX,SANDYBRIDGE */
        /* 260(001 001) 001(72) 216 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSLLD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52245, 434},
    /*   3 : VPSLLD xmmreg,imm8 [v+mi:      vex.ndd.128.66.0f 72 /6 ib        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(72) 206 021 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSLLD, 2, {XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+52253, 434},
    /*   4 : VPSLLD ymmreg,ymmreg*,xmmrm128 [rvm:      vex.nds.256.66.0f f2 /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(f2) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSLLD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64005, 468},
    /*   5 : VPSLLD ymmreg,xmmrm128 [r+vm:      vex.nds.256.66.0f f2 /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(f2) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSLLD, 2, {YMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64012, 468},
    /*   6 : VPSLLD ymmreg,ymmreg*,imm8 [vmi:      vex.ndd.256.66.0f 72 /6 ib        ] AVX2,FUTURE */
        /* 260(001 005) 001(72) 216 022 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSLLD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54221, 468},
    /*   7 : VPSLLD ymmreg,imm8 [v+mi:      vex.ndd.256.66.0f 72 /6 ib        ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(72) 206 021 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSLLD, 2, {YMMREG|RN_L16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+54229, 468},
    /*   8 : VPSLLD xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:m128: evex.nds.128.66.0f.w0 f2 /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7d 08) 317 001(f2) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSLLD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41535, 544},
    /*   9 : VPSLLD xmmreg|mask|z,xmmrm128 [r+vm:m128: evex.nds.128.66.0f.w0 f2 /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 08) 317 001(f2) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSLLD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41544, 544},
    /*  10 : VPSLLD ymmreg|mask|z,ymmreg*,xmmrm128 [rvm:m128: evex.nds.256.66.0f.w0 f2 /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7d 28) 317 001(f2) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSLLD, 3, {YMMREG,YMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41553, 544},
    /*  11 : VPSLLD ymmreg|mask|z,xmmrm128 [r+vm:m128: evex.nds.256.66.0f.w0 f2 /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 28) 317 001(f2) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSLLD, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41562, 544},
    /*  12 : VPSLLD zmmreg|mask|z,zmmreg*,xmmrm128 [rvm:m128: evex.nds.512.66.0f.w0 f2 /r       ] AVX512,FUTURE */
        /* 241(f1 7d 48) 317 001(f2) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSLLD, 3, {ZMMREG,ZMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41571, 545},
    /*  13 : VPSLLD zmmreg|mask|z,xmmrm128 [r+vm:m128: evex.nds.512.66.0f.w0 f2 /r       ] ND,AVX512,FUTURE */
        /* 240(f1 7d 48) 317 001(f2) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSLLD, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41580, 545},
    /*  14 : VPSLLD xmmreg|mask|z,xmmrm128|b32*,imm8 [vmi:fv:   evex.nds.128.66.0f.w0 72 /6 ib    ] AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 08) 301 001(72) 216 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSLLD, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20553, 544},
    /*  15 : VPSLLD xmmreg|mask|z,imm8 [v+mi:fv:   evex.nds.128.66.0f.w0 72 /6 ib    ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 08) 301 001(72) 206 021 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSLLD, 2, {XMMREG,IMM_NORMAL|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20563, 544},
    /*  16 : VPSLLD ymmreg|mask|z,ymmrm256|b32*,imm8 [vmi:fv:   evex.nds.256.66.0f.w0 72 /6 ib    ] AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 28) 301 001(72) 216 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSLLD, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20573, 544},
    /*  17 : VPSLLD ymmreg|mask|z,imm8 [v+mi:fv:   evex.nds.256.66.0f.w0 72 /6 ib    ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 28) 301 001(72) 206 021 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSLLD, 2, {YMMREG,IMM_NORMAL|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20583, 544},
    /*  18 : VPSLLD zmmreg|mask|z,zmmrm512|b32*,imm8 [vmi:fv:   evex.nds.512.66.0f.w0 72 /6 ib    ] AVX512,FUTURE */
        /* 240(f1 7d 48) 301 001(72) 216 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSLLD, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20593, 545},
    /*  19 : VPSLLD zmmreg|mask|z,imm8 [v+mi:fv:   evex.nds.512.66.0f.w0 72 /6 ib    ] ND,AVX512,FUTURE */
        /* 240(f1 7d 48) 301 001(72) 206 021 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSLLD, 2, {ZMMREG,IMM_NORMAL|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20603, 545},
};

static const struct itemplate instrux_VPSLLQ[20] = {
    /*   0 : VPSLLQ xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f f3 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(f3) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSLLQ, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60981, 434},
    /*   1 : VPSLLQ xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f f3 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(f3) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSLLQ, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+60988, 434},
    /*   2 : VPSLLQ xmmreg,xmmreg*,imm8 [vmi:      vex.ndd.128.66.0f 73 /6 ib        ] AVX,SANDYBRIDGE */
        /* 260(001 001) 001(73) 216 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSLLQ, 3, {XMMREG|RN_L16,XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52261, 434},
    /*   3 : VPSLLQ xmmreg,imm8 [v+mi:      vex.ndd.128.66.0f 73 /6 ib        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(73) 206 021 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSLLQ, 2, {XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+52269, 434},
    /*   4 : VPSLLQ ymmreg,ymmreg*,xmmrm128 [rvm:      vex.nds.256.66.0f f3 /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(f3) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSLLQ, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64019, 468},
    /*   5 : VPSLLQ ymmreg,xmmrm128 [r+vm:      vex.nds.256.66.0f f3 /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(f3) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSLLQ, 2, {YMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64026, 468},
    /*   6 : VPSLLQ ymmreg,ymmreg*,imm8 [vmi:      vex.ndd.256.66.0f 73 /6 ib        ] AVX2,FUTURE */
        /* 260(001 005) 001(73) 216 022 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSLLQ, 3, {YMMREG|RN_L16,YMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54237, 468},
    /*   7 : VPSLLQ ymmreg,imm8 [v+mi:      vex.ndd.256.66.0f 73 /6 ib        ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(73) 206 021 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSLLQ, 2, {YMMREG|RN_L16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+54245, 468},
    /*   8 : VPSLLQ xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:m128: evex.nds.128.66.0f.w1 f3 /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 317 001(f3) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSLLQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41589, 544},
    /*   9 : VPSLLQ xmmreg|mask|z,xmmrm128 [r+vm:m128: evex.nds.128.66.0f.w1 f3 /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 08) 317 001(f3) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSLLQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41598, 544},
    /*  10 : VPSLLQ ymmreg|mask|z,ymmreg*,xmmrm128 [rvm:m128: evex.nds.256.66.0f.w1 f3 /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 317 001(f3) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSLLQ, 3, {YMMREG,YMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41607, 544},
    /*  11 : VPSLLQ ymmreg|mask|z,xmmrm128 [r+vm:m128: evex.nds.256.66.0f.w1 f3 /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 28) 317 001(f3) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSLLQ, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41616, 544},
    /*  12 : VPSLLQ zmmreg|mask|z,zmmreg*,xmmrm128 [rvm:m128: evex.nds.512.66.0f.w1 f3 /r       ] AVX512,FUTURE */
        /* 241(f1 fd 48) 317 001(f3) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSLLQ, 3, {ZMMREG,ZMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41625, 545},
    /*  13 : VPSLLQ zmmreg|mask|z,xmmrm128 [r+vm:m128: evex.nds.512.66.0f.w1 f3 /r       ] ND,AVX512,FUTURE */
        /* 240(f1 fd 48) 317 001(f3) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSLLQ, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41634, 545},
    /*  14 : VPSLLQ xmmreg|mask|z,xmmrm128|b64*,imm8 [vmi:fv:   evex.nds.128.66.0f.w1 73 /6 ib    ] AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 08) 301 001(73) 216 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSLLQ, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+20673, 544},
    /*  15 : VPSLLQ xmmreg|mask|z,imm8 [v+mi:fv:   evex.nds.128.66.0f.w1 73 /6 ib    ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 08) 301 001(73) 206 021 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSLLQ, 2, {XMMREG,IMM_NORMAL|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20683, 544},
    /*  16 : VPSLLQ ymmreg|mask|z,ymmrm256|b64*,imm8 [vmi:fv:   evex.nds.256.66.0f.w1 73 /6 ib    ] AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 28) 301 001(73) 216 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSLLQ, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+20693, 544},
    /*  17 : VPSLLQ ymmreg|mask|z,imm8 [v+mi:fv:   evex.nds.256.66.0f.w1 73 /6 ib    ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 28) 301 001(73) 206 021 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSLLQ, 2, {YMMREG,IMM_NORMAL|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20703, 544},
    /*  18 : VPSLLQ zmmreg|mask|z,zmmrm512|b64*,imm8 [vmi:fv:   evex.nds.512.66.0f.w1 73 /6 ib    ] AVX512,FUTURE */
        /* 240(f1 fd 48) 301 001(73) 216 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSLLQ, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+20713, 545},
    /*  19 : VPSLLQ zmmreg|mask|z,imm8 [v+mi:fv:   evex.nds.512.66.0f.w1 73 /6 ib    ] ND,AVX512,FUTURE */
        /* 240(f1 fd 48) 301 001(73) 206 021 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSLLQ, 2, {ZMMREG,IMM_NORMAL|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20723, 545},
};

static const struct itemplate instrux_VPSRAW[20] = {
    /*   0 : VPSRAW xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f e1 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(e1) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSRAW, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+60995, 434},
    /*   1 : VPSRAW xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f e1 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(e1) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSRAW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61002, 434},
    /*   2 : VPSRAW xmmreg,xmmreg*,imm8 [vmi:      vex.ndd.128.66.0f 71 /4 ib        ] AVX,SANDYBRIDGE */
        /* 260(001 001) 001(71) 214 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSRAW, 3, {XMMREG|RN_L16,XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52277, 434},
    /*   3 : VPSRAW xmmreg,imm8 [v+mi:      vex.ndd.128.66.0f 71 /4 ib        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(71) 204 021 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSRAW, 2, {XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+52285, 434},
    /*   4 : VPSRAW ymmreg,ymmreg*,xmmrm128 [rvm:      vex.nds.256.66.0f e1 /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(e1) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSRAW, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64033, 468},
    /*   5 : VPSRAW ymmreg,xmmrm128 [r+vm:      vex.nds.256.66.0f e1 /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(e1) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSRAW, 2, {YMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64040, 468},
    /*   6 : VPSRAW ymmreg,ymmreg*,imm8 [vmi:      vex.ndd.256.66.0f 71 /4 ib        ] AVX2,FUTURE */
        /* 260(001 005) 001(71) 214 022 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSRAW, 3, {YMMREG|RN_L16,YMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54253, 468},
    /*   7 : VPSRAW ymmreg,imm8 [v+mi:      vex.ndd.256.66.0f 71 /4 ib        ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(71) 204 021 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSRAW, 2, {YMMREG|RN_L16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+54261, 468},
    /*   8 : VPSRAW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:m128: evex.nds.128.66.0f.wig e1 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 08) 317 001(e1) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSRAW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42129, 556},
    /*   9 : VPSRAW xmmreg|mask|z,xmmrm128 [r+vm:m128: evex.nds.128.66.0f.wig e1 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 317 001(e1) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSRAW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42138, 556},
    /*  10 : VPSRAW ymmreg|mask|z,ymmreg*,xmmrm128 [rvm:m128: evex.nds.256.66.0f.wig e1 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 28) 317 001(e1) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSRAW, 3, {YMMREG,YMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42147, 556},
    /*  11 : VPSRAW ymmreg|mask|z,xmmrm128 [r+vm:m128: evex.nds.256.66.0f.wig e1 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 317 001(e1) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSRAW, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42156, 556},
    /*  12 : VPSRAW zmmreg|mask|z,zmmreg*,xmmrm128 [rvm:m128: evex.nds.512.66.0f.wig e1 /r      ] AVX512BW,FUTURE */
        /* 241(f1 7d 48) 317 001(e1) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPSRAW, 3, {ZMMREG,ZMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42165, 557},
    /*  13 : VPSRAW zmmreg|mask|z,xmmrm128 [r+vm:m128: evex.nds.512.66.0f.wig e1 /r      ] ND,AVX512BW,FUTURE */
        /* 240(f1 7d 48) 317 001(e1) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPSRAW, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42174, 557},
    /*  14 : VPSRAW xmmreg|mask|z,xmmrm128*,imm8 [vmi:fvm:  evex.nds.128.66.0f.wig 71 /4 ib   ] AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 303 001(71) 214 022 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSRAW, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20913, 556},
    /*  15 : VPSRAW xmmreg|mask|z,imm8 [v+mi:fvm:  evex.nds.128.66.0f.wig 71 /4 ib   ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 303 001(71) 204 021 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSRAW, 2, {XMMREG,IMM_NORMAL|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20923, 556},
    /*  16 : VPSRAW ymmreg|mask|z,ymmrm256*,imm8 [vmi:fvm:  evex.nds.256.66.0f.wig 71 /4 ib   ] AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 303 001(71) 214 022 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSRAW, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20933, 556},
    /*  17 : VPSRAW ymmreg|mask|z,imm8 [v+mi:fvm:  evex.nds.256.66.0f.wig 71 /4 ib   ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 303 001(71) 204 021 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSRAW, 2, {YMMREG,IMM_NORMAL|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20943, 556},
    /*  18 : VPSRAW zmmreg|mask|z,zmmrm512*,imm8 [vmi:fvm:  evex.nds.512.66.0f.wig 71 /4 ib   ] AVX512BW,FUTURE */
        /* 240(f1 7d 48) 303 001(71) 214 022 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPSRAW, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20953, 557},
    /*  19 : VPSRAW zmmreg|mask|z,imm8 [v+mi:fvm:  evex.nds.512.66.0f.wig 71 /4 ib   ] ND,AVX512BW,FUTURE */
        /* 240(f1 7d 48) 303 001(71) 204 021 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPSRAW, 2, {ZMMREG,IMM_NORMAL|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20963, 557},
};

static const struct itemplate instrux_VPSRAD[20] = {
    /*   0 : VPSRAD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f e2 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(e2) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSRAD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61009, 434},
    /*   1 : VPSRAD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f e2 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(e2) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSRAD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61016, 434},
    /*   2 : VPSRAD xmmreg,xmmreg*,imm8 [vmi:      vex.ndd.128.66.0f 72 /4 ib        ] AVX,SANDYBRIDGE */
        /* 260(001 001) 001(72) 214 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSRAD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52293, 434},
    /*   3 : VPSRAD xmmreg,imm8 [v+mi:      vex.ndd.128.66.0f 72 /4 ib        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(72) 204 021 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSRAD, 2, {XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+52301, 434},
    /*   4 : VPSRAD ymmreg,ymmreg*,xmmrm128 [rvm:      vex.nds.256.66.0f e2 /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(e2) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSRAD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64047, 468},
    /*   5 : VPSRAD ymmreg,xmmrm128 [r+vm:      vex.nds.256.66.0f e2 /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(e2) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSRAD, 2, {YMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64054, 468},
    /*   6 : VPSRAD ymmreg,ymmreg*,imm8 [vmi:      vex.ndd.256.66.0f 72 /4 ib        ] AVX2,FUTURE */
        /* 260(001 005) 001(72) 214 022 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSRAD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54269, 468},
    /*   7 : VPSRAD ymmreg,imm8 [v+mi:      vex.ndd.256.66.0f 72 /4 ib        ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(72) 204 021 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSRAD, 2, {YMMREG|RN_L16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+54277, 468},
    /*   8 : VPSRAD xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:m128: evex.nds.128.66.0f.w0 e2 /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7d 08) 317 001(e2) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRAD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41859, 544},
    /*   9 : VPSRAD xmmreg|mask|z,xmmrm128 [r+vm:m128: evex.nds.128.66.0f.w0 e2 /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 08) 317 001(e2) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRAD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41868, 544},
    /*  10 : VPSRAD ymmreg|mask|z,ymmreg*,xmmrm128 [rvm:m128: evex.nds.256.66.0f.w0 e2 /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7d 28) 317 001(e2) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRAD, 3, {YMMREG,YMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41877, 544},
    /*  11 : VPSRAD ymmreg|mask|z,xmmrm128 [r+vm:m128: evex.nds.256.66.0f.w0 e2 /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 28) 317 001(e2) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRAD, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41886, 544},
    /*  12 : VPSRAD zmmreg|mask|z,zmmreg*,xmmrm128 [rvm:m128: evex.nds.512.66.0f.w0 e2 /r       ] AVX512,FUTURE */
        /* 241(f1 7d 48) 317 001(e2) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSRAD, 3, {ZMMREG,ZMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41895, 545},
    /*  13 : VPSRAD zmmreg|mask|z,xmmrm128 [r+vm:m128: evex.nds.512.66.0f.w0 e2 /r       ] ND,AVX512,FUTURE */
        /* 240(f1 7d 48) 317 001(e2) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSRAD, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41904, 545},
    /*  14 : VPSRAD xmmreg|mask|z,xmmrm128|b32*,imm8 [vmi:fv:   evex.nds.128.66.0f.w0 72 /4 ib    ] AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 08) 301 001(72) 214 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRAD, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20793, 544},
    /*  15 : VPSRAD xmmreg|mask|z,imm8 [v+mi:fv:   evex.nds.128.66.0f.w0 72 /4 ib    ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 08) 301 001(72) 204 021 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRAD, 2, {XMMREG,IMM_NORMAL|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20803, 544},
    /*  16 : VPSRAD ymmreg|mask|z,ymmrm256|b32*,imm8 [vmi:fv:   evex.nds.256.66.0f.w0 72 /4 ib    ] AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 28) 301 001(72) 214 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRAD, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20813, 544},
    /*  17 : VPSRAD ymmreg|mask|z,imm8 [v+mi:fv:   evex.nds.256.66.0f.w0 72 /4 ib    ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 28) 301 001(72) 204 021 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRAD, 2, {YMMREG,IMM_NORMAL|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20823, 544},
    /*  18 : VPSRAD zmmreg|mask|z,zmmrm512|b32*,imm8 [vmi:fv:   evex.nds.512.66.0f.w0 72 /4 ib    ] AVX512,FUTURE */
        /* 240(f1 7d 48) 301 001(72) 214 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSRAD, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20833, 545},
    /*  19 : VPSRAD zmmreg|mask|z,imm8 [v+mi:fv:   evex.nds.512.66.0f.w0 72 /4 ib    ] ND,AVX512,FUTURE */
        /* 240(f1 7d 48) 301 001(72) 204 021 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSRAD, 2, {ZMMREG,IMM_NORMAL|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20843, 545},
};

static const struct itemplate instrux_VPSRLW[20] = {
    /*   0 : VPSRLW xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f d1 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(d1) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSRLW, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61023, 434},
    /*   1 : VPSRLW xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f d1 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(d1) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSRLW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61030, 434},
    /*   2 : VPSRLW xmmreg,xmmreg*,imm8 [vmi:      vex.ndd.128.66.0f 71 /2 ib        ] AVX,SANDYBRIDGE */
        /* 260(001 001) 001(71) 212 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSRLW, 3, {XMMREG|RN_L16,XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52309, 434},
    /*   3 : VPSRLW xmmreg,imm8 [v+mi:      vex.ndd.128.66.0f 71 /2 ib        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(71) 202 021 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSRLW, 2, {XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+52317, 434},
    /*   4 : VPSRLW ymmreg,ymmreg*,xmmrm128 [rvm:      vex.nds.256.66.0f d1 /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(d1) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSRLW, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64061, 468},
    /*   5 : VPSRLW ymmreg,xmmrm128 [r+vm:      vex.nds.256.66.0f d1 /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(d1) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSRLW, 2, {YMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64068, 468},
    /*   6 : VPSRLW ymmreg,ymmreg*,imm8 [vmi:      vex.ndd.256.66.0f 71 /2 ib        ] AVX2,FUTURE */
        /* 260(001 005) 001(71) 212 022 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSRLW, 3, {YMMREG|RN_L16,YMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54301, 468},
    /*   7 : VPSRLW ymmreg,imm8 [v+mi:      vex.ndd.256.66.0f 71 /2 ib        ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(71) 202 021 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSRLW, 2, {YMMREG|RN_L16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+54309, 468},
    /*   8 : VPSRLW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:m128: evex.nds.128.66.0f.wig d1 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 08) 317 001(d1) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSRLW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42453, 556},
    /*   9 : VPSRLW xmmreg|mask|z,xmmrm128 [r+vm:m128: evex.nds.128.66.0f.wig d1 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 317 001(d1) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSRLW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42462, 556},
    /*  10 : VPSRLW ymmreg|mask|z,ymmreg*,xmmrm128 [rvm:m128: evex.nds.256.66.0f.wig d1 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 28) 317 001(d1) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSRLW, 3, {YMMREG,YMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42471, 556},
    /*  11 : VPSRLW ymmreg|mask|z,xmmrm128 [r+vm:m128: evex.nds.256.66.0f.wig d1 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 317 001(d1) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSRLW, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42480, 556},
    /*  12 : VPSRLW zmmreg|mask|z,zmmreg*,xmmrm128 [rvm:m128: evex.nds.512.66.0f.wig d1 /r      ] AVX512BW,FUTURE */
        /* 241(f1 7d 48) 317 001(d1) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPSRLW, 3, {ZMMREG,ZMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42489, 557},
    /*  13 : VPSRLW zmmreg|mask|z,xmmrm128 [r+vm:m128: evex.nds.512.66.0f.wig d1 /r      ] ND,AVX512BW,FUTURE */
        /* 240(f1 7d 48) 317 001(d1) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPSRLW, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42498, 557},
    /*  14 : VPSRLW xmmreg|mask|z,xmmrm128*,imm8 [vmi:fvm:  evex.nds.128.66.0f.wig 71 /2 ib   ] AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 303 001(71) 212 022 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSRLW, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21153, 556},
    /*  15 : VPSRLW xmmreg|mask|z,imm8 [v+mi:fvm:  evex.nds.128.66.0f.wig 71 /2 ib   ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 303 001(71) 202 021 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSRLW, 2, {XMMREG,IMM_NORMAL|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21163, 556},
    /*  16 : VPSRLW ymmreg|mask|z,ymmrm256*,imm8 [vmi:fvm:  evex.nds.256.66.0f.wig 71 /2 ib   ] AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 303 001(71) 212 022 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSRLW, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21173, 556},
    /*  17 : VPSRLW ymmreg|mask|z,imm8 [v+mi:fvm:  evex.nds.256.66.0f.wig 71 /2 ib   ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 303 001(71) 202 021 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSRLW, 2, {YMMREG,IMM_NORMAL|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21183, 556},
    /*  18 : VPSRLW zmmreg|mask|z,zmmrm512*,imm8 [vmi:fvm:  evex.nds.512.66.0f.wig 71 /2 ib   ] AVX512BW,FUTURE */
        /* 240(f1 7d 48) 303 001(71) 212 022 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPSRLW, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21193, 557},
    /*  19 : VPSRLW zmmreg|mask|z,imm8 [v+mi:fvm:  evex.nds.512.66.0f.wig 71 /2 ib   ] ND,AVX512BW,FUTURE */
        /* 240(f1 7d 48) 303 001(71) 202 021 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPSRLW, 2, {ZMMREG,IMM_NORMAL|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21203, 557},
};

static const struct itemplate instrux_VPSRLD[20] = {
    /*   0 : VPSRLD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f d2 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(d2) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSRLD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61037, 434},
    /*   1 : VPSRLD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f d2 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(d2) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSRLD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61044, 434},
    /*   2 : VPSRLD xmmreg,xmmreg*,imm8 [vmi:      vex.ndd.128.66.0f 72 /2 ib        ] AVX,SANDYBRIDGE */
        /* 260(001 001) 001(72) 212 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSRLD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52325, 434},
    /*   3 : VPSRLD xmmreg,imm8 [v+mi:      vex.ndd.128.66.0f 72 /2 ib        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(72) 202 021 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSRLD, 2, {XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+52333, 434},
    /*   4 : VPSRLD ymmreg,ymmreg*,xmmrm128 [rvm:      vex.nds.256.66.0f d2 /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(d2) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSRLD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64075, 468},
    /*   5 : VPSRLD ymmreg,xmmrm128 [r+vm:      vex.nds.256.66.0f d2 /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(d2) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSRLD, 2, {YMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64082, 468},
    /*   6 : VPSRLD ymmreg,ymmreg*,imm8 [vmi:      vex.ndd.256.66.0f 72 /2 ib        ] AVX2,FUTURE */
        /* 260(001 005) 001(72) 212 022 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSRLD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54317, 468},
    /*   7 : VPSRLD ymmreg,imm8 [v+mi:      vex.ndd.256.66.0f 72 /2 ib        ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(72) 202 021 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSRLD, 2, {YMMREG|RN_L16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+54325, 468},
    /*   8 : VPSRLD xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:m128: evex.nds.128.66.0f.w0 d2 /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7d 08) 317 001(d2) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRLD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42183, 544},
    /*   9 : VPSRLD xmmreg|mask|z,xmmrm128 [r+vm:m128: evex.nds.128.66.0f.w0 d2 /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 08) 317 001(d2) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRLD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42192, 544},
    /*  10 : VPSRLD ymmreg|mask|z,ymmreg*,xmmrm128 [rvm:m128: evex.nds.256.66.0f.w0 d2 /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7d 28) 317 001(d2) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRLD, 3, {YMMREG,YMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42201, 544},
    /*  11 : VPSRLD ymmreg|mask|z,xmmrm128 [r+vm:m128: evex.nds.256.66.0f.w0 d2 /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 28) 317 001(d2) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRLD, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42210, 544},
    /*  12 : VPSRLD zmmreg|mask|z,zmmreg*,xmmrm128 [rvm:m128: evex.nds.512.66.0f.w0 d2 /r       ] AVX512,FUTURE */
        /* 241(f1 7d 48) 317 001(d2) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSRLD, 3, {ZMMREG,ZMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42219, 545},
    /*  13 : VPSRLD zmmreg|mask|z,xmmrm128 [r+vm:m128: evex.nds.512.66.0f.w0 d2 /r       ] ND,AVX512,FUTURE */
        /* 240(f1 7d 48) 317 001(d2) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSRLD, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42228, 545},
    /*  14 : VPSRLD xmmreg|mask|z,xmmrm128|b32*,imm8 [vmi:fv:   evex.nds.128.66.0f.w0 72 /2 ib    ] AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 08) 301 001(72) 212 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRLD, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20973, 544},
    /*  15 : VPSRLD xmmreg|mask|z,imm8 [v+mi:fv:   evex.nds.128.66.0f.w0 72 /2 ib    ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 08) 301 001(72) 202 021 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRLD, 2, {XMMREG,IMM_NORMAL|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20983, 544},
    /*  16 : VPSRLD ymmreg|mask|z,ymmrm256|b32*,imm8 [vmi:fv:   evex.nds.256.66.0f.w0 72 /2 ib    ] AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 28) 301 001(72) 212 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRLD, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20993, 544},
    /*  17 : VPSRLD ymmreg|mask|z,imm8 [v+mi:fv:   evex.nds.256.66.0f.w0 72 /2 ib    ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 28) 301 001(72) 202 021 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRLD, 2, {YMMREG,IMM_NORMAL|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21003, 544},
    /*  18 : VPSRLD zmmreg|mask|z,zmmrm512|b32*,imm8 [vmi:fv:   evex.nds.512.66.0f.w0 72 /2 ib    ] AVX512,FUTURE */
        /* 240(f1 7d 48) 301 001(72) 212 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSRLD, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+21013, 545},
    /*  19 : VPSRLD zmmreg|mask|z,imm8 [v+mi:fv:   evex.nds.512.66.0f.w0 72 /2 ib    ] ND,AVX512,FUTURE */
        /* 240(f1 7d 48) 301 001(72) 202 021 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSRLD, 2, {ZMMREG,IMM_NORMAL|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21023, 545},
};

static const struct itemplate instrux_VPSRLQ[20] = {
    /*   0 : VPSRLQ xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f d3 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(d3) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSRLQ, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61051, 434},
    /*   1 : VPSRLQ xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f d3 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(d3) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSRLQ, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61058, 434},
    /*   2 : VPSRLQ xmmreg,xmmreg*,imm8 [vmi:      vex.ndd.128.66.0f 73 /2 ib        ] AVX,SANDYBRIDGE */
        /* 260(001 001) 001(73) 212 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSRLQ, 3, {XMMREG|RN_L16,XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52341, 434},
    /*   3 : VPSRLQ xmmreg,imm8 [v+mi:      vex.ndd.128.66.0f 73 /2 ib        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(73) 202 021 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSRLQ, 2, {XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+52349, 434},
    /*   4 : VPSRLQ ymmreg,ymmreg*,xmmrm128 [rvm:      vex.nds.256.66.0f d3 /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(d3) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSRLQ, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64089, 468},
    /*   5 : VPSRLQ ymmreg,xmmrm128 [r+vm:      vex.nds.256.66.0f d3 /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(d3) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSRLQ, 2, {YMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64096, 468},
    /*   6 : VPSRLQ ymmreg,ymmreg*,imm8 [vmi:      vex.ndd.256.66.0f.wig 73 /2 ib    ] AVX2,FUTURE */
        /* 260(001 005) 001(73) 212 022 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSRLQ, 3, {YMMREG|RN_L16,YMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54333, 468},
    /*   7 : VPSRLQ ymmreg,imm8 [v+mi:      vex.ndd.256.66.0f.wig 73 /2 ib    ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(73) 202 021 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSRLQ, 2, {YMMREG|RN_L16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+54341, 468},
    /*   8 : VPSRLQ xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:m128: evex.nds.128.66.0f.w1 d3 /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 317 001(d3) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRLQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42237, 544},
    /*   9 : VPSRLQ xmmreg|mask|z,xmmrm128 [r+vm:m128: evex.nds.128.66.0f.w1 d3 /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 08) 317 001(d3) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRLQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42246, 544},
    /*  10 : VPSRLQ ymmreg|mask|z,ymmreg*,xmmrm128 [rvm:m128: evex.nds.256.66.0f.w1 d3 /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 317 001(d3) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRLQ, 3, {YMMREG,YMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42255, 544},
    /*  11 : VPSRLQ ymmreg|mask|z,xmmrm128 [r+vm:m128: evex.nds.256.66.0f.w1 d3 /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 28) 317 001(d3) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRLQ, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42264, 544},
    /*  12 : VPSRLQ zmmreg|mask|z,zmmreg*,xmmrm128 [rvm:m128: evex.nds.512.66.0f.w1 d3 /r       ] AVX512,FUTURE */
        /* 241(f1 fd 48) 317 001(d3) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSRLQ, 3, {ZMMREG,ZMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42273, 545},
    /*  13 : VPSRLQ zmmreg|mask|z,xmmrm128 [r+vm:m128: evex.nds.512.66.0f.w1 d3 /r       ] ND,AVX512,FUTURE */
        /* 240(f1 fd 48) 317 001(d3) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSRLQ, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42282, 545},
    /*  14 : VPSRLQ xmmreg|mask|z,xmmrm128|b64*,imm8 [vmi:fv:   evex.nds.128.66.0f.w1 73 /2 ib    ] AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 08) 301 001(73) 212 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRLQ, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+21093, 544},
    /*  15 : VPSRLQ xmmreg|mask|z,imm8 [v+mi:fv:   evex.nds.128.66.0f.w1 73 /2 ib    ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 08) 301 001(73) 202 021 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRLQ, 2, {XMMREG,IMM_NORMAL|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21103, 544},
    /*  16 : VPSRLQ ymmreg|mask|z,ymmrm256|b64*,imm8 [vmi:fv:   evex.nds.256.66.0f.w1 73 /2 ib    ] AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 28) 301 001(73) 212 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRLQ, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+21113, 544},
    /*  17 : VPSRLQ ymmreg|mask|z,imm8 [v+mi:fv:   evex.nds.256.66.0f.w1 73 /2 ib    ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 28) 301 001(73) 202 021 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRLQ, 2, {YMMREG,IMM_NORMAL|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21123, 544},
    /*  18 : VPSRLQ zmmreg|mask|z,zmmrm512|b64*,imm8 [vmi:fv:   evex.nds.512.66.0f.w1 73 /2 ib    ] AVX512,FUTURE */
        /* 240(f1 fd 48) 301 001(73) 212 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSRLQ, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+21133, 545},
    /*  19 : VPSRLQ zmmreg|mask|z,imm8 [v+mi:fv:   evex.nds.512.66.0f.w1 73 /2 ib    ] ND,AVX512,FUTURE */
        /* 240(f1 fd 48) 301 001(73) 202 021 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSRLQ, 2, {ZMMREG,IMM_NORMAL|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21143, 545},
};

static const struct itemplate instrux_VPTEST[2] = {
    /*   0 : VPTEST xmmreg,xmmrm128 [rm:       vex.128.66.0f38 17 /r             ] AVX,SANDYBRIDGE */
        /* 270(002 001) 001(17) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPTEST, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61065, 434},
    /*   1 : VPTEST ymmreg,ymmrm256 [rm:       vex.256.66.0f38 17 /r             ] AVX,SANDYBRIDGE */
        /* 270(002 005) 001(17) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPTEST, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61072, 434},
};

static const struct itemplate instrux_VPSUBB[10] = {
    /*   0 : VPSUBB xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f f8 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(f8) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSUBB, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61079, 434},
    /*   1 : VPSUBB xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f f8 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(f8) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSUBB, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61086, 434},
    /*   2 : VPSUBB ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f f8 /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(f8) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSUBB, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64103, 468},
    /*   3 : VPSUBB ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f f8 /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(f8) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSUBB, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64110, 468},
    /*   4 : VPSUBB xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f.wig f8 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 08) 303 001(f8) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSUBB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42507, 556},
    /*   5 : VPSUBB xmmreg|mask|z,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f.wig f8 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 303 001(f8) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSUBB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42516, 556},
    /*   6 : VPSUBB ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f.wig f8 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 28) 303 001(f8) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSUBB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42525, 556},
    /*   7 : VPSUBB ymmreg|mask|z,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f.wig f8 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 303 001(f8) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSUBB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42534, 556},
    /*   8 : VPSUBB zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f.wig f8 /r      ] AVX512BW,FUTURE */
        /* 241(f1 7d 48) 303 001(f8) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPSUBB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42543, 557},
    /*   9 : VPSUBB zmmreg|mask|z,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f.wig f8 /r      ] ND,AVX512BW,FUTURE */
        /* 240(f1 7d 48) 303 001(f8) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPSUBB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42552, 557},
};

static const struct itemplate instrux_VPSUBW[10] = {
    /*   0 : VPSUBW xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f f9 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(f9) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSUBW, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61093, 434},
    /*   1 : VPSUBW xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f f9 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(f9) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSUBW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61100, 434},
    /*   2 : VPSUBW ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f f9 /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(f9) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSUBW, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64117, 468},
    /*   3 : VPSUBW ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f f9 /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(f9) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSUBW, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64124, 468},
    /*   4 : VPSUBW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f.wig f9 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 08) 303 001(f9) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSUBW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42885, 556},
    /*   5 : VPSUBW xmmreg|mask|z,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f.wig f9 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 303 001(f9) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSUBW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42894, 556},
    /*   6 : VPSUBW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f.wig f9 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 28) 303 001(f9) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSUBW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42903, 556},
    /*   7 : VPSUBW ymmreg|mask|z,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f.wig f9 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 303 001(f9) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSUBW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42912, 556},
    /*   8 : VPSUBW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f.wig f9 /r      ] AVX512BW,FUTURE */
        /* 241(f1 7d 48) 303 001(f9) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPSUBW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42921, 557},
    /*   9 : VPSUBW zmmreg|mask|z,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f.wig f9 /r      ] ND,AVX512BW,FUTURE */
        /* 240(f1 7d 48) 303 001(f9) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPSUBW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42930, 557},
};

static const struct itemplate instrux_VPSUBD[10] = {
    /*   0 : VPSUBD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f fa /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(fa) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSUBD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61107, 434},
    /*   1 : VPSUBD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f fa /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(fa) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSUBD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61114, 434},
    /*   2 : VPSUBD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f fa /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(fa) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSUBD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64131, 468},
    /*   3 : VPSUBD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f fa /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(fa) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSUBD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64138, 468},
    /*   4 : VPSUBD xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f.w0 fa /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7d 08) 301 001(fa) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSUBD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+42561, 544},
    /*   5 : VPSUBD xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.nds.128.66.0f.w0 fa /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 08) 301 001(fa) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSUBD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+42570, 544},
    /*   6 : VPSUBD ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f.w0 fa /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7d 28) 301 001(fa) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSUBD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+42579, 544},
    /*   7 : VPSUBD ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.nds.256.66.0f.w0 fa /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 28) 301 001(fa) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSUBD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+42588, 544},
    /*   8 : VPSUBD zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv:   evex.nds.512.66.0f.w0 fa /r       ] AVX512,FUTURE */
        /* 241(f1 7d 48) 301 001(fa) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSUBD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+42597, 545},
    /*   9 : VPSUBD zmmreg|mask|z,zmmrm512|b32 [r+vm:fv:   evex.nds.512.66.0f.w0 fa /r       ] ND,AVX512,FUTURE */
        /* 240(f1 7d 48) 301 001(fa) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSUBD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+42606, 545},
};

static const struct itemplate instrux_VPSUBQ[10] = {
    /*   0 : VPSUBQ xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f fb /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(fb) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSUBQ, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61121, 434},
    /*   1 : VPSUBQ xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f fb /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(fb) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSUBQ, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61128, 434},
    /*   2 : VPSUBQ ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f fb /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(fb) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSUBQ, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64145, 468},
    /*   3 : VPSUBQ ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f fb /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(fb) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSUBQ, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64152, 468},
    /*   4 : VPSUBQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f.w1 fb /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(fb) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSUBQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+42615, 544},
    /*   5 : VPSUBQ xmmreg|mask|z,xmmrm128|b64 [r+vm:fv:   evex.nds.128.66.0f.w1 fb /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 08) 301 001(fb) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSUBQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+42624, 544},
    /*   6 : VPSUBQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f.w1 fb /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(fb) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSUBQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+42633, 544},
    /*   7 : VPSUBQ ymmreg|mask|z,ymmrm256|b64 [r+vm:fv:   evex.nds.256.66.0f.w1 fb /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 28) 301 001(fb) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSUBQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+42642, 544},
    /*   8 : VPSUBQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv:   evex.nds.512.66.0f.w1 fb /r       ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(fb) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSUBQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+42651, 545},
    /*   9 : VPSUBQ zmmreg|mask|z,zmmrm512|b64 [r+vm:fv:   evex.nds.512.66.0f.w1 fb /r       ] ND,AVX512,FUTURE */
        /* 240(f1 fd 48) 301 001(fb) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSUBQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+42660, 545},
};

static const struct itemplate instrux_VPSUBSB[10] = {
    /*   0 : VPSUBSB xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f e8 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(e8) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSUBSB, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61135, 434},
    /*   1 : VPSUBSB xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f e8 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(e8) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSUBSB, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61142, 434},
    /*   2 : VPSUBSB ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f e8 /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(e8) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSUBSB, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64159, 468},
    /*   3 : VPSUBSB ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f e8 /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(e8) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSUBSB, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64166, 468},
    /*   4 : VPSUBSB xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f.wig e8 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 08) 303 001(e8) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSUBSB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42669, 556},
    /*   5 : VPSUBSB xmmreg|mask|z,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f.wig e8 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 303 001(e8) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSUBSB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42678, 556},
    /*   6 : VPSUBSB ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f.wig e8 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 28) 303 001(e8) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSUBSB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42687, 556},
    /*   7 : VPSUBSB ymmreg|mask|z,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f.wig e8 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 303 001(e8) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSUBSB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42696, 556},
    /*   8 : VPSUBSB zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f.wig e8 /r      ] AVX512BW,FUTURE */
        /* 241(f1 7d 48) 303 001(e8) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPSUBSB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42705, 557},
    /*   9 : VPSUBSB zmmreg|mask|z,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f.wig e8 /r      ] ND,AVX512BW,FUTURE */
        /* 240(f1 7d 48) 303 001(e8) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPSUBSB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42714, 557},
};

static const struct itemplate instrux_VPSUBSW[10] = {
    /*   0 : VPSUBSW xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f e9 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(e9) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSUBSW, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61149, 434},
    /*   1 : VPSUBSW xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f e9 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(e9) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSUBSW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61156, 434},
    /*   2 : VPSUBSW ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f e9 /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(e9) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSUBSW, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64173, 468},
    /*   3 : VPSUBSW ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f e9 /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(e9) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSUBSW, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64180, 468},
    /*   4 : VPSUBSW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f.wig e9 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 08) 303 001(e9) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSUBSW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42723, 556},
    /*   5 : VPSUBSW xmmreg|mask|z,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f.wig e9 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 303 001(e9) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSUBSW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42732, 556},
    /*   6 : VPSUBSW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f.wig e9 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 28) 303 001(e9) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSUBSW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42741, 556},
    /*   7 : VPSUBSW ymmreg|mask|z,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f.wig e9 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 303 001(e9) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSUBSW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42750, 556},
    /*   8 : VPSUBSW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f.wig e9 /r      ] AVX512BW,FUTURE */
        /* 241(f1 7d 48) 303 001(e9) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPSUBSW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42759, 557},
    /*   9 : VPSUBSW zmmreg|mask|z,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f.wig e9 /r      ] ND,AVX512BW,FUTURE */
        /* 240(f1 7d 48) 303 001(e9) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPSUBSW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42768, 557},
};

static const struct itemplate instrux_VPSUBUSB[10] = {
    /*   0 : VPSUBUSB xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f d8 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(d8) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSUBUSB, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61163, 434},
    /*   1 : VPSUBUSB xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f d8 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(d8) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSUBUSB, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61170, 434},
    /*   2 : VPSUBUSB ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f d8 /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(d8) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSUBUSB, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64187, 468},
    /*   3 : VPSUBUSB ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f d8 /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(d8) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSUBUSB, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64194, 468},
    /*   4 : VPSUBUSB xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f.wig d8 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 08) 303 001(d8) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSUBUSB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42777, 556},
    /*   5 : VPSUBUSB xmmreg|mask|z,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f.wig d8 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 303 001(d8) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSUBUSB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42786, 556},
    /*   6 : VPSUBUSB ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f.wig d8 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 28) 303 001(d8) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSUBUSB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42795, 556},
    /*   7 : VPSUBUSB ymmreg|mask|z,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f.wig d8 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 303 001(d8) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSUBUSB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42804, 556},
    /*   8 : VPSUBUSB zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f.wig d8 /r      ] AVX512BW,FUTURE */
        /* 241(f1 7d 48) 303 001(d8) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPSUBUSB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42813, 557},
    /*   9 : VPSUBUSB zmmreg|mask|z,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f.wig d8 /r      ] ND,AVX512BW,FUTURE */
        /* 240(f1 7d 48) 303 001(d8) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPSUBUSB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42822, 557},
};

static const struct itemplate instrux_VPSUBUSW[10] = {
    /*   0 : VPSUBUSW xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f d9 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(d9) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSUBUSW, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61177, 434},
    /*   1 : VPSUBUSW xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f d9 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(d9) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPSUBUSW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61184, 434},
    /*   2 : VPSUBUSW ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f d9 /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(d9) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSUBUSW, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64201, 468},
    /*   3 : VPSUBUSW ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f d9 /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(d9) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPSUBUSW, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64208, 468},
    /*   4 : VPSUBUSW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f.wig d9 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 08) 303 001(d9) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSUBUSW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42831, 556},
    /*   5 : VPSUBUSW xmmreg|mask|z,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f.wig d9 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 303 001(d9) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSUBUSW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42840, 556},
    /*   6 : VPSUBUSW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f.wig d9 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 28) 303 001(d9) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSUBUSW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42849, 556},
    /*   7 : VPSUBUSW ymmreg|mask|z,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f.wig d9 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 303 001(d9) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSUBUSW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42858, 556},
    /*   8 : VPSUBUSW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f.wig d9 /r      ] AVX512BW,FUTURE */
        /* 241(f1 7d 48) 303 001(d9) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPSUBUSW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42867, 557},
    /*   9 : VPSUBUSW zmmreg|mask|z,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f.wig d9 /r      ] ND,AVX512BW,FUTURE */
        /* 240(f1 7d 48) 303 001(d9) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPSUBUSW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42876, 557},
};

static const struct itemplate instrux_VPUNPCKHBW[10] = {
    /*   0 : VPUNPCKHBW xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f 68 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(68) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPUNPCKHBW, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61191, 434},
    /*   1 : VPUNPCKHBW xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f 68 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(68) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPUNPCKHBW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61198, 434},
    /*   2 : VPUNPCKHBW ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f 68 /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(68) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPUNPCKHBW, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64215, 468},
    /*   3 : VPUNPCKHBW ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f 68 /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(68) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPUNPCKHBW, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64222, 468},
    /*   4 : VPUNPCKHBW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f.wig 68 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 08) 303 001(68) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPUNPCKHBW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+43155, 556},
    /*   5 : VPUNPCKHBW xmmreg|mask|z,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f.wig 68 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 303 001(68) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPUNPCKHBW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+43164, 556},
    /*   6 : VPUNPCKHBW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f.wig 68 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 28) 303 001(68) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPUNPCKHBW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+43173, 556},
    /*   7 : VPUNPCKHBW ymmreg|mask|z,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f.wig 68 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 303 001(68) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPUNPCKHBW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+43182, 556},
    /*   8 : VPUNPCKHBW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f.wig 68 /r      ] AVX512BW,FUTURE */
        /* 241(f1 7d 48) 303 001(68) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPUNPCKHBW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+43191, 557},
    /*   9 : VPUNPCKHBW zmmreg|mask|z,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f.wig 68 /r      ] ND,AVX512BW,FUTURE */
        /* 240(f1 7d 48) 303 001(68) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPUNPCKHBW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+43200, 557},
};

static const struct itemplate instrux_VPUNPCKHWD[10] = {
    /*   0 : VPUNPCKHWD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f 69 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(69) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPUNPCKHWD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61205, 434},
    /*   1 : VPUNPCKHWD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f 69 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(69) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPUNPCKHWD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61212, 434},
    /*   2 : VPUNPCKHWD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f 69 /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(69) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPUNPCKHWD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64229, 468},
    /*   3 : VPUNPCKHWD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f 69 /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(69) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPUNPCKHWD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64236, 468},
    /*   4 : VPUNPCKHWD xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f.wig 69 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 08) 303 001(69) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPUNPCKHWD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+43317, 556},
    /*   5 : VPUNPCKHWD xmmreg|mask|z,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f.wig 69 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 303 001(69) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPUNPCKHWD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+43326, 556},
    /*   6 : VPUNPCKHWD ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f.wig 69 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 28) 303 001(69) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPUNPCKHWD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+43335, 556},
    /*   7 : VPUNPCKHWD ymmreg|mask|z,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f.wig 69 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 303 001(69) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPUNPCKHWD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+43344, 556},
    /*   8 : VPUNPCKHWD zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f.wig 69 /r      ] AVX512BW,FUTURE */
        /* 241(f1 7d 48) 303 001(69) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPUNPCKHWD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+43353, 557},
    /*   9 : VPUNPCKHWD zmmreg|mask|z,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f.wig 69 /r      ] ND,AVX512BW,FUTURE */
        /* 240(f1 7d 48) 303 001(69) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPUNPCKHWD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+43362, 557},
};

static const struct itemplate instrux_VPUNPCKHDQ[10] = {
    /*   0 : VPUNPCKHDQ xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f 6a /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(6a) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPUNPCKHDQ, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61219, 434},
    /*   1 : VPUNPCKHDQ xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f 6a /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(6a) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPUNPCKHDQ, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61226, 434},
    /*   2 : VPUNPCKHDQ ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f 6a /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(6a) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPUNPCKHDQ, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64243, 468},
    /*   3 : VPUNPCKHDQ ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f 6a /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(6a) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPUNPCKHDQ, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64250, 468},
    /*   4 : VPUNPCKHDQ xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f.w0 6a /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7d 08) 301 001(6a) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPUNPCKHDQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+43209, 544},
    /*   5 : VPUNPCKHDQ xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.nds.128.66.0f.w0 6a /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 08) 301 001(6a) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPUNPCKHDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+43218, 544},
    /*   6 : VPUNPCKHDQ ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f.w0 6a /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7d 28) 301 001(6a) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPUNPCKHDQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+43227, 544},
    /*   7 : VPUNPCKHDQ ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.nds.256.66.0f.w0 6a /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 28) 301 001(6a) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPUNPCKHDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+43236, 544},
    /*   8 : VPUNPCKHDQ zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv:   evex.nds.512.66.0f.w0 6a /r       ] AVX512,FUTURE */
        /* 241(f1 7d 48) 301 001(6a) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPUNPCKHDQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+43245, 545},
    /*   9 : VPUNPCKHDQ zmmreg|mask|z,zmmrm512|b32 [r+vm:fv:   evex.nds.512.66.0f.w0 6a /r       ] ND,AVX512,FUTURE */
        /* 240(f1 7d 48) 301 001(6a) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPUNPCKHDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+43254, 545},
};

static const struct itemplate instrux_VPUNPCKHQDQ[10] = {
    /*   0 : VPUNPCKHQDQ xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f 6d /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(6d) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPUNPCKHQDQ, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61233, 434},
    /*   1 : VPUNPCKHQDQ xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f 6d /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(6d) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPUNPCKHQDQ, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61240, 434},
    /*   2 : VPUNPCKHQDQ ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f 6d /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(6d) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPUNPCKHQDQ, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64257, 468},
    /*   3 : VPUNPCKHQDQ ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f 6d /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(6d) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPUNPCKHQDQ, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64264, 468},
    /*   4 : VPUNPCKHQDQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f.w1 6d /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(6d) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPUNPCKHQDQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+43263, 544},
    /*   5 : VPUNPCKHQDQ xmmreg|mask|z,xmmrm128|b64 [r+vm:fv:   evex.nds.128.66.0f.w1 6d /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 08) 301 001(6d) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPUNPCKHQDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+43272, 544},
    /*   6 : VPUNPCKHQDQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f.w1 6d /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(6d) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPUNPCKHQDQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+43281, 544},
    /*   7 : VPUNPCKHQDQ ymmreg|mask|z,ymmrm256|b64 [r+vm:fv:   evex.nds.256.66.0f.w1 6d /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 28) 301 001(6d) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPUNPCKHQDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+43290, 544},
    /*   8 : VPUNPCKHQDQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv:   evex.nds.512.66.0f.w1 6d /r       ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(6d) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPUNPCKHQDQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+43299, 545},
    /*   9 : VPUNPCKHQDQ zmmreg|mask|z,zmmrm512|b64 [r+vm:fv:   evex.nds.512.66.0f.w1 6d /r       ] ND,AVX512,FUTURE */
        /* 240(f1 fd 48) 301 001(6d) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPUNPCKHQDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+43308, 545},
};

static const struct itemplate instrux_VPUNPCKLBW[10] = {
    /*   0 : VPUNPCKLBW xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f 60 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(60) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPUNPCKLBW, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61247, 434},
    /*   1 : VPUNPCKLBW xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f 60 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(60) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPUNPCKLBW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61254, 434},
    /*   2 : VPUNPCKLBW ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f 60 /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(60) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPUNPCKLBW, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64271, 468},
    /*   3 : VPUNPCKLBW ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f 60 /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(60) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPUNPCKLBW, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64278, 468},
    /*   4 : VPUNPCKLBW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f.wig 60 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 08) 303 001(60) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPUNPCKLBW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+43371, 556},
    /*   5 : VPUNPCKLBW xmmreg|mask|z,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f.wig 60 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 303 001(60) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPUNPCKLBW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+43380, 556},
    /*   6 : VPUNPCKLBW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f.wig 60 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 28) 303 001(60) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPUNPCKLBW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+43389, 556},
    /*   7 : VPUNPCKLBW ymmreg|mask|z,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f.wig 60 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 303 001(60) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPUNPCKLBW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+43398, 556},
    /*   8 : VPUNPCKLBW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f.wig 60 /r      ] AVX512BW,FUTURE */
        /* 241(f1 7d 48) 303 001(60) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPUNPCKLBW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+43407, 557},
    /*   9 : VPUNPCKLBW zmmreg|mask|z,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f.wig 60 /r      ] ND,AVX512BW,FUTURE */
        /* 240(f1 7d 48) 303 001(60) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPUNPCKLBW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+43416, 557},
};

static const struct itemplate instrux_VPUNPCKLWD[10] = {
    /*   0 : VPUNPCKLWD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f 61 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(61) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPUNPCKLWD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61261, 434},
    /*   1 : VPUNPCKLWD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f 61 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(61) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPUNPCKLWD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61268, 434},
    /*   2 : VPUNPCKLWD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f 61 /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(61) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPUNPCKLWD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64285, 468},
    /*   3 : VPUNPCKLWD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f 61 /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(61) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPUNPCKLWD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64292, 468},
    /*   4 : VPUNPCKLWD xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f.wig 61 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 08) 303 001(61) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPUNPCKLWD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+43533, 556},
    /*   5 : VPUNPCKLWD xmmreg|mask|z,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f.wig 61 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 08) 303 001(61) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPUNPCKLWD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+43542, 556},
    /*   6 : VPUNPCKLWD ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f.wig 61 /r      ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f1 7d 28) 303 001(61) 120 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPUNPCKLWD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+43551, 556},
    /*   7 : VPUNPCKLWD ymmreg|mask|z,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f.wig 61 /r      ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f1 7d 28) 303 001(61) 110 : WIG,EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPUNPCKLWD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+43560, 556},
    /*   8 : VPUNPCKLWD zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f.wig 61 /r      ] AVX512BW,FUTURE */
        /* 241(f1 7d 48) 303 001(61) 120 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPUNPCKLWD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+43569, 557},
    /*   9 : VPUNPCKLWD zmmreg|mask|z,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f.wig 61 /r      ] ND,AVX512BW,FUTURE */
        /* 240(f1 7d 48) 303 001(61) 110 : WIG,EVEX,PROT,AVX512BW,FUTURE */
        {I_VPUNPCKLWD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+43578, 557},
};

static const struct itemplate instrux_VPUNPCKLDQ[10] = {
    /*   0 : VPUNPCKLDQ xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f 62 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(62) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPUNPCKLDQ, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61275, 434},
    /*   1 : VPUNPCKLDQ xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f 62 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(62) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPUNPCKLDQ, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61282, 434},
    /*   2 : VPUNPCKLDQ ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f 62 /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(62) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPUNPCKLDQ, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64299, 468},
    /*   3 : VPUNPCKLDQ ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f 62 /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(62) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPUNPCKLDQ, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64306, 468},
    /*   4 : VPUNPCKLDQ xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f.w0 62 /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7d 08) 301 001(62) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPUNPCKLDQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+43425, 544},
    /*   5 : VPUNPCKLDQ xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.nds.128.66.0f.w0 62 /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 08) 301 001(62) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPUNPCKLDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+43434, 544},
    /*   6 : VPUNPCKLDQ ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f.w0 62 /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7d 28) 301 001(62) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPUNPCKLDQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+43443, 544},
    /*   7 : VPUNPCKLDQ ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.nds.256.66.0f.w0 62 /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 28) 301 001(62) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPUNPCKLDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+43452, 544},
    /*   8 : VPUNPCKLDQ zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv:   evex.nds.512.66.0f.w0 62 /r       ] AVX512,FUTURE */
        /* 241(f1 7d 48) 301 001(62) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPUNPCKLDQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+43461, 545},
    /*   9 : VPUNPCKLDQ zmmreg|mask|z,zmmrm512|b32 [r+vm:fv:   evex.nds.512.66.0f.w0 62 /r       ] ND,AVX512,FUTURE */
        /* 240(f1 7d 48) 301 001(62) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPUNPCKLDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+43470, 545},
};

static const struct itemplate instrux_VPUNPCKLQDQ[10] = {
    /*   0 : VPUNPCKLQDQ xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f 6c /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(6c) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPUNPCKLQDQ, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61289, 434},
    /*   1 : VPUNPCKLQDQ xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f 6c /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(6c) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPUNPCKLQDQ, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61296, 434},
    /*   2 : VPUNPCKLQDQ ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f 6c /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(6c) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPUNPCKLQDQ, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64313, 468},
    /*   3 : VPUNPCKLQDQ ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f 6c /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(6c) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPUNPCKLQDQ, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64320, 468},
    /*   4 : VPUNPCKLQDQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f.w1 6c /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(6c) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPUNPCKLQDQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+43479, 544},
    /*   5 : VPUNPCKLQDQ xmmreg|mask|z,xmmrm128|b64 [r+vm:fv:   evex.nds.128.66.0f.w1 6c /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 08) 301 001(6c) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPUNPCKLQDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+43488, 544},
    /*   6 : VPUNPCKLQDQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f.w1 6c /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(6c) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPUNPCKLQDQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+43497, 544},
    /*   7 : VPUNPCKLQDQ ymmreg|mask|z,ymmrm256|b64 [r+vm:fv:   evex.nds.256.66.0f.w1 6c /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 28) 301 001(6c) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPUNPCKLQDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+43506, 544},
    /*   8 : VPUNPCKLQDQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv:   evex.nds.512.66.0f.w1 6c /r       ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(6c) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPUNPCKLQDQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+43515, 545},
    /*   9 : VPUNPCKLQDQ zmmreg|mask|z,zmmrm512|b64 [r+vm:fv:   evex.nds.512.66.0f.w1 6c /r       ] ND,AVX512,FUTURE */
        /* 240(f1 fd 48) 301 001(6c) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPUNPCKLQDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+43524, 545},
};

static const struct itemplate instrux_VPXOR[4] = {
    /*   0 : VPXOR xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f ef /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(ef) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPXOR, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61303, 434},
    /*   1 : VPXOR xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f ef /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(ef) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPXOR, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61310, 434},
    /*   2 : VPXOR ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f ef /r           ] AVX2,FUTURE */
        /* 261(001 005) 001(ef) 120 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPXOR, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64327, 468},
    /*   3 : VPXOR ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f ef /r           ] ND,AVX2,FUTURE */
        /* 260(001 005) 001(ef) 110 : NOAPX,WIG,VEX,AVX2,FUTURE */
        {I_VPXOR, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64334, 468},
};

static const struct itemplate instrux_VRCPPS[2] = {
    /*   0 : VRCPPS xmmreg,xmmrm128 [rm:       vex.128.0f 53 /r                  ] AVX,SANDYBRIDGE */
        /* 270(001 000) 001(53) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VRCPPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61317, 434},
    /*   1 : VRCPPS ymmreg,ymmrm256 [rm:       vex.256.0f 53 /r                  ] AVX,SANDYBRIDGE */
        /* 270(001 004) 001(53) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VRCPPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61324, 434},
};

static const struct itemplate instrux_VRCPSS[2] = {
    /*   0 : VRCPSS xmmreg,xmmreg*,xmmrm32 [rvm:      vex.nds.lig.f3.0f 53 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(53) 120 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VRCPSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61331, 441},
    /*   1 : VRCPSS xmmreg,xmmrm32 [r+vm:      vex.nds.lig.f3.0f 53 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(53) 110 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VRCPSS, 2, {XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61338, 441},
};

static const struct itemplate instrux_VRSQRTPS[2] = {
    /*   0 : VRSQRTPS xmmreg,xmmrm128 [rm:       vex.128.0f 52 /r                  ] AVX,SANDYBRIDGE */
        /* 270(001 000) 001(52) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VRSQRTPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61345, 434},
    /*   1 : VRSQRTPS ymmreg,ymmrm256 [rm:       vex.256.0f 52 /r                  ] AVX,SANDYBRIDGE */
        /* 270(001 004) 001(52) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VRSQRTPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61352, 434},
};

static const struct itemplate instrux_VRSQRTSS[2] = {
    /*   0 : VRSQRTSS xmmreg,xmmreg*,xmmrm32 [rvm:      vex.nds.lig.f3.0f 52 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(52) 120 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VRSQRTSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61359, 441},
    /*   1 : VRSQRTSS xmmreg,xmmrm32 [r+vm:      vex.nds.lig.f3.0f 52 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(52) 110 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VRSQRTSS, 2, {XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61366, 441},
};

static const struct itemplate instrux_VROUNDPD[2] = {
    /*   0 : VROUNDPD xmmreg,xmmrm128,imm8 [rmi:      vex.128.66.0f3a 09 /r ib          ] AVX,SANDYBRIDGE */
        /* 270(003 001) 001(09) 110 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VROUNDPD, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52357, 434},
    /*   1 : VROUNDPD ymmreg,ymmrm256,imm8 [rmi:      vex.256.66.0f3a 09 /r ib          ] AVX,SANDYBRIDGE */
        /* 270(003 005) 001(09) 110 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VROUNDPD, 3, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52365, 434},
};

static const struct itemplate instrux_VROUNDPS[2] = {
    /*   0 : VROUNDPS xmmreg,xmmrm128,imm8 [rmi:      vex.128.66.0f3a 08 /r ib          ] AVX,SANDYBRIDGE */
        /* 270(003 001) 001(08) 110 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VROUNDPS, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52373, 434},
    /*   1 : VROUNDPS ymmreg,ymmrm256,imm8 [rmi:      vex.256.66.0f3a 08 /r ib          ] AVX,SANDYBRIDGE */
        /* 270(003 005) 001(08) 110 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VROUNDPS, 3, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52381, 434},
};

static const struct itemplate instrux_VROUNDSD[2] = {
    /*   0 : VROUNDSD xmmreg,xmmreg*,xmmrm64,imm8 [rvmi:     vex.nds.128.66.0f3a 0b /r ib      ] AVX,SANDYBRIDGE */
        /* 261(003 001) 001(0b) 120 023 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VROUNDSD, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+52389, 434},
    /*   1 : VROUNDSD xmmreg,xmmrm64,imm8 [r+vmi:     vex.nds.128.66.0f3a 0b /r ib      ] ND,AVX,SANDYBRIDGE */
        /* 260(003 001) 001(0b) 110 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VROUNDSD, 3, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52397, 434},
};

static const struct itemplate instrux_VROUNDSS[2] = {
    /*   0 : VROUNDSS xmmreg,xmmreg*,xmmrm32,imm8 [rvmi:     vex.nds.128.66.0f3a 0a /r ib      ] AVX,SANDYBRIDGE */
        /* 261(003 001) 001(0a) 120 023 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VROUNDSS, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+52405, 434},
    /*   1 : VROUNDSS xmmreg,xmmrm32,imm8 [r+vmi:     vex.nds.128.66.0f3a 0a /r ib      ] ND,AVX,SANDYBRIDGE */
        /* 260(003 001) 001(0a) 110 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VROUNDSS, 3, {XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52413, 434},
};

static const struct itemplate instrux_VSHUFPD[10] = {
    /*   0 : VSHUFPD xmmreg,xmmreg*,xmmrm128,imm8 [rvmi:     vex.nds.128.66.0f c6 /r ib        ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(c6) 120 023 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VSHUFPD, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+52421, 434},
    /*   1 : VSHUFPD xmmreg,xmmrm128,imm8 [r+vmi:     vex.nds.128.66.0f c6 /r ib        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(c6) 110 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VSHUFPD, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52429, 434},
    /*   2 : VSHUFPD ymmreg,ymmreg*,ymmrm256,imm8 [rvmi:     vex.nds.256.66.0f c6 /r ib        ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(c6) 120 023 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VSHUFPD, 4, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+52437, 434},
    /*   3 : VSHUFPD ymmreg,ymmrm256,imm8 [r+vmi:     vex.nds.256.66.0f c6 /r ib        ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(c6) 110 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VSHUFPD, 3, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52445, 434},
    /*   4 : VSHUFPD xmmreg|mask|z,xmmreg*,xmmrm128|b64,imm8 [rvmi:fv:  evex.nds.128.66.0f.w1 c6 /r ib    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c6) 120 023 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSHUFPD, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22043, 544},
    /*   5 : VSHUFPD xmmreg|mask|z,xmmrm128|b64,imm8 [r+vmi:fv:  evex.nds.128.66.0f.w1 c6 /r ib    ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 08) 301 001(c6) 110 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSHUFPD, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+22053, 544},
    /*   6 : VSHUFPD ymmreg|mask|z,ymmreg*,ymmrm256|b64,imm8 [rvmi:fv:  evex.nds.256.66.0f.w1 c6 /r ib    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c6) 120 023 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSHUFPD, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22063, 544},
    /*   7 : VSHUFPD ymmreg|mask|z,ymmrm256|b64,imm8 [r+vmi:fv:  evex.nds.256.66.0f.w1 c6 /r ib    ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 28) 301 001(c6) 110 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSHUFPD, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+22073, 544},
    /*   8 : VSHUFPD zmmreg|mask|z,zmmreg*,zmmrm512|b64,imm8 [rvmi:fv:  evex.nds.512.66.0f.w1 c6 /r ib    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c6) 120 023 : EVEX,PROT,AVX512,FUTURE */
        {I_VSHUFPD, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22083, 545},
    /*   9 : VSHUFPD zmmreg|mask|z,zmmrm512|b64,imm8 [r+vmi:fv:  evex.nds.512.66.0f.w1 c6 /r ib    ] ND,AVX512,FUTURE */
        /* 240(f1 fd 48) 301 001(c6) 110 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VSHUFPD, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+22093, 545},
};

static const struct itemplate instrux_VSHUFPS[10] = {
    /*   0 : VSHUFPS xmmreg,xmmreg*,xmmrm128,imm8 [rvmi:     vex.nds.128.0f c6 /r ib           ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(c6) 120 023 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VSHUFPS, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+52453, 434},
    /*   1 : VSHUFPS xmmreg,xmmrm128,imm8 [r+vmi:     vex.nds.128.0f c6 /r ib           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(c6) 110 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VSHUFPS, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52461, 434},
    /*   2 : VSHUFPS ymmreg,ymmreg*,ymmrm256,imm8 [rvmi:     vex.nds.256.0f c6 /r ib           ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(c6) 120 023 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VSHUFPS, 4, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+52469, 434},
    /*   3 : VSHUFPS ymmreg,ymmrm256,imm8 [r+vmi:     vex.nds.256.0f c6 /r ib           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(c6) 110 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VSHUFPS, 3, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52477, 434},
    /*   4 : VSHUFPS xmmreg|mask|z,xmmreg*,xmmrm128|b32,imm8 [rvmi:fv:  evex.nds.128.0f.w0 c6 /r ib       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c6) 120 023 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSHUFPS, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22103, 544},
    /*   5 : VSHUFPS xmmreg|mask|z,xmmrm128|b32,imm8 [r+vmi:fv:  evex.nds.128.0f.w0 c6 /r ib       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7c 08) 301 001(c6) 110 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSHUFPS, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+22113, 544},
    /*   6 : VSHUFPS ymmreg|mask|z,ymmreg*,ymmrm256|b32,imm8 [rvmi:fv:  evex.nds.256.0f.w0 c6 /r ib       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c6) 120 023 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSHUFPS, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22123, 544},
    /*   7 : VSHUFPS ymmreg|mask|z,ymmrm256|b32,imm8 [r+vmi:fv:  evex.nds.256.0f.w0 c6 /r ib       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7c 28) 301 001(c6) 110 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSHUFPS, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+22133, 544},
    /*   8 : VSHUFPS zmmreg|mask|z,zmmreg*,zmmrm512|b32,imm8 [rvmi:fv:  evex.nds.512.0f.w0 c6 /r ib       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c6) 120 023 : EVEX,PROT,AVX512,FUTURE */
        {I_VSHUFPS, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22143, 545},
    /*   9 : VSHUFPS zmmreg|mask|z,zmmrm512|b32,imm8 [r+vmi:fv:  evex.nds.512.0f.w0 c6 /r ib       ] ND,AVX512,FUTURE */
        /* 240(f1 7c 48) 301 001(c6) 110 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VSHUFPS, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+22153, 545},
};

static const struct itemplate instrux_VSQRTPD[5] = {
    /*   0 : VSQRTPD xmmreg,xmmrm128 [rm:       vex.128.66.0f 51 /r               ] AVX,SANDYBRIDGE */
        /* 270(001 001) 001(51) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VSQRTPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61373, 434},
    /*   1 : VSQRTPD ymmreg,ymmrm256 [rm:       vex.256.66.0f 51 /r               ] AVX,SANDYBRIDGE */
        /* 270(001 005) 001(51) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VSQRTPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61380, 434},
    /*   2 : VSQRTPD xmmreg|mask|z,xmmrm128|b64 [rm:fv:    evex.128.66.0f.w1 51 /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 fd 08) 301 001(51) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSQRTPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+44127, 544},
    /*   3 : VSQRTPD ymmreg|mask|z,ymmrm256|b64 [rm:fv:    evex.256.66.0f.w1 51 /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 fd 28) 301 001(51) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSQRTPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+44136, 544},
    /*   4 : VSQRTPD zmmreg|mask|z,zmmrm512|b64|er [rm:fv:    evex.512.66.0f.w1 51 /r           ] AVX512,FUTURE */
        /* 250(f1 fd 48) 301 001(51) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VSQRTPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+44145, 545},
};

static const struct itemplate instrux_VSQRTPS[5] = {
    /*   0 : VSQRTPS xmmreg,xmmrm128 [rm:       vex.128.0f 51 /r                  ] AVX,SANDYBRIDGE */
        /* 270(001 000) 001(51) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VSQRTPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61387, 434},
    /*   1 : VSQRTPS ymmreg,ymmrm256 [rm:       vex.256.0f 51 /r                  ] AVX,SANDYBRIDGE */
        /* 270(001 004) 001(51) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VSQRTPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61394, 434},
    /*   2 : VSQRTPS xmmreg|mask|z,xmmrm128|b32 [rm:fv:    evex.128.0f.w0 51 /r              ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7c 08) 301 001(51) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSQRTPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+44154, 544},
    /*   3 : VSQRTPS ymmreg|mask|z,ymmrm256|b32 [rm:fv:    evex.256.0f.w0 51 /r              ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7c 28) 301 001(51) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSQRTPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+44163, 544},
    /*   4 : VSQRTPS zmmreg|mask|z,zmmrm512|b32|er [rm:fv:    evex.512.0f.w0 51 /r              ] AVX512,FUTURE */
        /* 250(f1 7c 48) 301 001(51) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VSQRTPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+44172, 545},
};

static const struct itemplate instrux_VSQRTSD[4] = {
    /*   0 : VSQRTSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f 51 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(51) 120 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VSQRTSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61401, 441},
    /*   1 : VSQRTSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f 51 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(51) 110 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VSQRTSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61408, 441},
    /*   2 : VSQRTSD xmmreg|mask|z,xmmreg*,xmmrm64|er [rvm:t1s:  evex.nds.lig.f2.0f.w1 51 /r       ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(51) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VSQRTSD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+44181, 546},
    /*   3 : VSQRTSD xmmreg|mask|z,xmmrm64|er [r+vm:t1s:  evex.nds.lig.f2.0f.w1 51 /r       ] ND,AVX512,FUTURE */
        /* 240(f1 ff 08) 306 001(51) 110 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VSQRTSD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+44190, 546},
};

static const struct itemplate instrux_VSQRTSS[4] = {
    /*   0 : VSQRTSS xmmreg,xmmreg*,xmmrm32 [rvm:      vex.nds.lig.f3.0f 51 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(51) 120 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VSQRTSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61415, 441},
    /*   1 : VSQRTSS xmmreg,xmmrm32 [r+vm:      vex.nds.lig.f3.0f 51 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(51) 110 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VSQRTSS, 2, {XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61422, 441},
    /*   2 : VSQRTSS xmmreg|mask|z,xmmreg*,xmmrm32|er [rvm:t1s:  evex.nds.lig.f3.0f.w0 51 /r       ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(51) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VSQRTSS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+44199, 546},
    /*   3 : VSQRTSS xmmreg|mask|z,xmmrm32|er [r+vm:t1s:  evex.nds.lig.f3.0f.w0 51 /r       ] ND,AVX512,FUTURE */
        /* 240(f1 7e 08) 306 001(51) 110 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VSQRTSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+44208, 546},
};

static const struct itemplate instrux_VSTMXCSR[1] = {
    /*   0 : VSTMXCSR mem32 [m:        vex.128.0f ae /3                  ] AVX,SANDYBRIDGE */
        /* 270(001 000) 001(ae) 203 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VSTMXCSR, 1, {MEMORY|BITS32|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+61429, 434},
};

static const struct itemplate instrux_VSUBPD[10] = {
    /*   0 : VSUBPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f 5c /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(5c) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VSUBPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61436, 434},
    /*   1 : VSUBPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f 5c /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(5c) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VSUBPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61443, 434},
    /*   2 : VSUBPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f 5c /r           ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(5c) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VSUBPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61450, 434},
    /*   3 : VSUBPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f 5c /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(5c) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VSUBPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61457, 434},
    /*   4 : VSUBPD xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f.w1 5c /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(5c) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSUBPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+44217, 544},
    /*   5 : VSUBPD xmmreg|mask|z,xmmrm128|b64 [r+vm:fv:   evex.nds.128.66.0f.w1 5c /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 08) 301 001(5c) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSUBPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+44226, 544},
    /*   6 : VSUBPD ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f.w1 5c /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(5c) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSUBPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+44235, 544},
    /*   7 : VSUBPD ymmreg|mask|z,ymmrm256|b64 [r+vm:fv:   evex.nds.256.66.0f.w1 5c /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 28) 301 001(5c) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSUBPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+44244, 544},
    /*   8 : VSUBPD zmmreg|mask|z,zmmreg*,zmmrm512|b64|er [rvm:fv:   evex.nds.512.66.0f.w1 5c /r       ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(5c) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VSUBPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+44253, 545},
    /*   9 : VSUBPD zmmreg|mask|z,zmmrm512|b64|er [r+vm:fv:   evex.nds.512.66.0f.w1 5c /r       ] ND,AVX512,FUTURE */
        /* 240(f1 fd 48) 301 001(5c) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VSUBPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+44262, 545},
};

static const struct itemplate instrux_VSUBPS[10] = {
    /*   0 : VSUBPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f 5c /r              ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(5c) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VSUBPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61464, 434},
    /*   1 : VSUBPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f 5c /r              ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(5c) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VSUBPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61471, 434},
    /*   2 : VSUBPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f 5c /r              ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(5c) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VSUBPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61478, 434},
    /*   3 : VSUBPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f 5c /r              ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(5c) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VSUBPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61485, 434},
    /*   4 : VSUBPS xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.nds.128.0f.w0 5c /r          ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(5c) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSUBPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+44271, 544},
    /*   5 : VSUBPS xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.nds.128.0f.w0 5c /r          ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7c 08) 301 001(5c) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSUBPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+44280, 544},
    /*   6 : VSUBPS ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.nds.256.0f.w0 5c /r          ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(5c) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSUBPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+44289, 544},
    /*   7 : VSUBPS ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.nds.256.0f.w0 5c /r          ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7c 28) 301 001(5c) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSUBPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+44298, 544},
    /*   8 : VSUBPS zmmreg|mask|z,zmmreg*,zmmrm512|b32|er [rvm:fv:   evex.nds.512.0f.w0 5c /r          ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(5c) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VSUBPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+44307, 545},
    /*   9 : VSUBPS zmmreg|mask|z,zmmrm512|b32|er [r+vm:fv:   evex.nds.512.0f.w0 5c /r          ] ND,AVX512,FUTURE */
        /* 240(f1 7c 48) 301 001(5c) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VSUBPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+44316, 545},
};

static const struct itemplate instrux_VSUBSD[4] = {
    /*   0 : VSUBSD xmmreg,xmmreg*,xmmrm64 [rvm:      vex.nds.lig.f2.0f 5c /r           ] AVX,SANDYBRIDGE */
        /* 261(001 003) 001(5c) 120 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VSUBSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61492, 441},
    /*   1 : VSUBSD xmmreg,xmmrm64 [r+vm:      vex.nds.lig.f2.0f 5c /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 003) 001(5c) 110 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VSUBSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61499, 441},
    /*   2 : VSUBSD xmmreg|mask|z,xmmreg*,xmmrm64|er [rvm:t1s:  evex.nds.lig.f2.0f.w1 5c /r       ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(5c) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VSUBSD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+44325, 546},
    /*   3 : VSUBSD xmmreg|mask|z,xmmrm64|er [r+vm:t1s:  evex.nds.lig.f2.0f.w1 5c /r       ] ND,AVX512,FUTURE */
        /* 240(f1 ff 08) 306 001(5c) 110 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VSUBSD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+44334, 546},
};

static const struct itemplate instrux_VSUBSS[4] = {
    /*   0 : VSUBSS xmmreg,xmmreg*,xmmrm32 [rvm:      vex.nds.lig.f3.0f 5c /r           ] AVX,SANDYBRIDGE */
        /* 261(001 002) 001(5c) 120 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VSUBSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61506, 441},
    /*   1 : VSUBSS xmmreg,xmmrm32 [r+vm:      vex.nds.lig.f3.0f 5c /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 002) 001(5c) 110 : NOAPX,LIG,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VSUBSS, 2, {XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61513, 441},
    /*   2 : VSUBSS xmmreg|mask|z,xmmreg*,xmmrm32|er [rvm:t1s:  evex.nds.lig.f3.0f.w0 5c /r       ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(5c) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VSUBSS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+44343, 546},
    /*   3 : VSUBSS xmmreg|mask|z,xmmrm32|er [r+vm:t1s:  evex.nds.lig.f3.0f.w0 5c /r       ] ND,AVX512,FUTURE */
        /* 240(f1 7e 08) 306 001(5c) 110 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VSUBSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+44352, 546},
};

static const struct itemplate instrux_VTESTPS[2] = {
    /*   0 : VTESTPS xmmreg,xmmrm128 [rm:       vex.128.66.0f38.w0 0e /r          ] FL,AVX,SANDYBRIDGE */
        /* 270(002 001) 001(0e) 110 : NOAPX,FL,VEX,AVX,SANDYBRIDGE */
        {I_VTESTPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61520, 458},
    /*   1 : VTESTPS ymmreg,ymmrm256 [rm:       vex.256.66.0f38.w0 0e /r          ] FL,AVX,SANDYBRIDGE */
        /* 270(002 005) 001(0e) 110 : NOAPX,FL,VEX,AVX,SANDYBRIDGE */
        {I_VTESTPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61527, 458},
};

static const struct itemplate instrux_VTESTPD[2] = {
    /*   0 : VTESTPD xmmreg,xmmrm128 [rm:       vex.128.66.0f38.w0 0f /r          ] AVX,SANDYBRIDGE */
        /* 270(002 001) 001(0f) 110 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VTESTPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61534, 442},
    /*   1 : VTESTPD ymmreg,ymmrm256 [rm:       vex.256.66.0f38.w0 0f /r          ] AVX,SANDYBRIDGE */
        /* 270(002 005) 001(0f) 110 : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VTESTPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61541, 442},
};

static const struct itemplate instrux_VUCOMISD[2] = {
    /*   0 : VUCOMISD xmmreg,xmmrm64 [rm:       vex.lig.66.0f 2e /r               ] FL,AVX,SANDYBRIDGE */
        /* 270(001 001) 001(2e) 110 : NOAPX,LIG,WIG,FL,VEX,AVX,SANDYBRIDGE */
        {I_VUCOMISD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61548, 443},
    /*   1 : VUCOMISD xmmreg,xmmrm64|sae [rm:t1s:   evex.lig.66.0f.w1 2e /r           ] FL,AVX512,FUTURE */
        /* 250(f1 fd 08) 306 001(2e) 110 : LIG,FL,EVEX,PROT,AVX512,FUTURE */
        {I_VUCOMISD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+44361, 549},
};

static const struct itemplate instrux_VUCOMISS[2] = {
    /*   0 : VUCOMISS xmmreg,xmmrm32 [rm:       vex.lig.0f 2e /r                  ] FL,AVX,SANDYBRIDGE */
        /* 270(001 000) 001(2e) 110 : NOAPX,LIG,WIG,FL,VEX,AVX,SANDYBRIDGE */
        {I_VUCOMISS, 2, {XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61555, 443},
    /*   1 : VUCOMISS xmmreg,xmmrm32|sae [rm:t1s:   evex.lig.0f.w0 2e /r              ] FL,AVX512,FUTURE */
        /* 250(f1 7c 08) 306 001(2e) 110 : LIG,FL,EVEX,PROT,AVX512,FUTURE */
        {I_VUCOMISS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+44370, 549},
};

static const struct itemplate instrux_VUNPCKHPD[10] = {
    /*   0 : VUNPCKHPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f 15 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(15) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VUNPCKHPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61562, 434},
    /*   1 : VUNPCKHPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f 15 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(15) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VUNPCKHPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61569, 434},
    /*   2 : VUNPCKHPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f 15 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(15) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VUNPCKHPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61576, 434},
    /*   3 : VUNPCKHPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f 15 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(15) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VUNPCKHPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61583, 434},
    /*   4 : VUNPCKHPD xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f.w1 15 /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(15) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VUNPCKHPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+44379, 544},
    /*   5 : VUNPCKHPD xmmreg|mask|z,xmmrm128|b64 [r+vm:fv:   evex.nds.128.66.0f.w1 15 /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 08) 301 001(15) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VUNPCKHPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+44388, 544},
    /*   6 : VUNPCKHPD ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f.w1 15 /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(15) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VUNPCKHPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+44397, 544},
    /*   7 : VUNPCKHPD ymmreg|mask|z,ymmrm256|b64 [r+vm:fv:   evex.nds.256.66.0f.w1 15 /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 28) 301 001(15) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VUNPCKHPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+44406, 544},
    /*   8 : VUNPCKHPD zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv:   evex.nds.512.66.0f.w1 15 /r       ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(15) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VUNPCKHPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+44415, 545},
    /*   9 : VUNPCKHPD zmmreg|mask|z,zmmrm512|b64 [r+vm:fv:   evex.nds.512.66.0f.w1 15 /r       ] ND,AVX512,FUTURE */
        /* 240(f1 fd 48) 301 001(15) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VUNPCKHPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+44424, 545},
};

static const struct itemplate instrux_VUNPCKHPS[10] = {
    /*   0 : VUNPCKHPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f 15 /r              ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(15) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VUNPCKHPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61590, 434},
    /*   1 : VUNPCKHPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f 15 /r              ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(15) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VUNPCKHPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61597, 434},
    /*   2 : VUNPCKHPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f 15 /r              ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(15) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VUNPCKHPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61604, 434},
    /*   3 : VUNPCKHPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f 15 /r              ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(15) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VUNPCKHPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61611, 434},
    /*   4 : VUNPCKHPS xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.nds.128.0f.w0 15 /r          ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(15) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VUNPCKHPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+44433, 544},
    /*   5 : VUNPCKHPS xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.nds.128.0f.w0 15 /r          ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7c 08) 301 001(15) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VUNPCKHPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+44442, 544},
    /*   6 : VUNPCKHPS ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.nds.256.0f.w0 15 /r          ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(15) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VUNPCKHPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+44451, 544},
    /*   7 : VUNPCKHPS ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.nds.256.0f.w0 15 /r          ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7c 28) 301 001(15) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VUNPCKHPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+44460, 544},
    /*   8 : VUNPCKHPS zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv:   evex.nds.512.0f.w0 15 /r          ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(15) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VUNPCKHPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+44469, 545},
    /*   9 : VUNPCKHPS zmmreg|mask|z,zmmrm512|b32 [r+vm:fv:   evex.nds.512.0f.w0 15 /r          ] ND,AVX512,FUTURE */
        /* 240(f1 7c 48) 301 001(15) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VUNPCKHPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+44478, 545},
};

static const struct itemplate instrux_VUNPCKLPD[10] = {
    /*   0 : VUNPCKLPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f 14 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(14) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VUNPCKLPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61618, 434},
    /*   1 : VUNPCKLPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f 14 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(14) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VUNPCKLPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61625, 434},
    /*   2 : VUNPCKLPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f 14 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(14) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VUNPCKLPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61632, 434},
    /*   3 : VUNPCKLPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f 14 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(14) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VUNPCKLPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61639, 434},
    /*   4 : VUNPCKLPD xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f.w1 14 /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(14) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VUNPCKLPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+44487, 544},
    /*   5 : VUNPCKLPD xmmreg|mask|z,xmmrm128|b64 [r+vm:fv:   evex.nds.128.66.0f.w1 14 /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 08) 301 001(14) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VUNPCKLPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+44496, 544},
    /*   6 : VUNPCKLPD ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f.w1 14 /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(14) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VUNPCKLPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+44505, 544},
    /*   7 : VUNPCKLPD ymmreg|mask|z,ymmrm256|b64 [r+vm:fv:   evex.nds.256.66.0f.w1 14 /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 28) 301 001(14) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VUNPCKLPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+44514, 544},
    /*   8 : VUNPCKLPD zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv:   evex.nds.512.66.0f.w1 14 /r       ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(14) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VUNPCKLPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+44523, 545},
    /*   9 : VUNPCKLPD zmmreg|mask|z,zmmrm512|b64 [r+vm:fv:   evex.nds.512.66.0f.w1 14 /r       ] ND,AVX512,FUTURE */
        /* 240(f1 fd 48) 301 001(14) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VUNPCKLPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+44532, 545},
};

static const struct itemplate instrux_VUNPCKLPS[10] = {
    /*   0 : VUNPCKLPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f 14 /r              ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(14) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VUNPCKLPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61646, 434},
    /*   1 : VUNPCKLPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f 14 /r              ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(14) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VUNPCKLPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61653, 434},
    /*   2 : VUNPCKLPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f 14 /r              ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(14) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VUNPCKLPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61660, 434},
    /*   3 : VUNPCKLPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f 14 /r              ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(14) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VUNPCKLPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61667, 434},
    /*   4 : VUNPCKLPS xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.nds.128.0f.w0 14 /r          ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(14) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VUNPCKLPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+44541, 544},
    /*   5 : VUNPCKLPS xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.nds.128.0f.w0 14 /r          ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7c 08) 301 001(14) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VUNPCKLPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+44550, 544},
    /*   6 : VUNPCKLPS ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.nds.256.0f.w0 14 /r          ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(14) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VUNPCKLPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+44559, 544},
    /*   7 : VUNPCKLPS ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.nds.256.0f.w0 14 /r          ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7c 28) 301 001(14) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VUNPCKLPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+44568, 544},
    /*   8 : VUNPCKLPS zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv:   evex.nds.512.0f.w0 14 /r          ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(14) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VUNPCKLPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+44577, 545},
    /*   9 : VUNPCKLPS zmmreg|mask|z,zmmrm512|b32 [r+vm:fv:   evex.nds.512.0f.w0 14 /r          ] ND,AVX512,FUTURE */
        /* 240(f1 7c 48) 301 001(14) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VUNPCKLPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+44586, 545},
};

static const struct itemplate instrux_VXORPD[10] = {
    /*   0 : VXORPD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f 57 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 001) 001(57) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VXORPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61674, 434},
    /*   1 : VXORPD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f 57 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 001) 001(57) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VXORPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61681, 434},
    /*   2 : VXORPD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f 57 /r           ] AVX,SANDYBRIDGE */
        /* 261(001 005) 001(57) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VXORPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61688, 434},
    /*   3 : VXORPD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f 57 /r           ] ND,AVX,SANDYBRIDGE */
        /* 260(001 005) 001(57) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VXORPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61695, 434},
    /*   4 : VXORPD xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f.w1 57 /r       ] AVX512VL,AVX512DQ,FUTURE */
        /* 241(f1 fd 08) 301 001(57) 120 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VXORPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+44595, 547},
    /*   5 : VXORPD xmmreg|mask|z,xmmrm128|b64 [r+vm:fv:   evex.nds.128.66.0f.w1 57 /r       ] ND,AVX512VL,AVX512DQ,FUTURE */
        /* 240(f1 fd 08) 301 001(57) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VXORPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+44604, 547},
    /*   6 : VXORPD ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f.w1 57 /r       ] AVX512VL,AVX512DQ,FUTURE */
        /* 241(f1 fd 28) 301 001(57) 120 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VXORPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+44613, 547},
    /*   7 : VXORPD ymmreg|mask|z,ymmrm256|b64 [r+vm:fv:   evex.nds.256.66.0f.w1 57 /r       ] ND,AVX512VL,AVX512DQ,FUTURE */
        /* 240(f1 fd 28) 301 001(57) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VXORPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+44622, 547},
    /*   8 : VXORPD zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv:   evex.nds.512.66.0f.w1 57 /r       ] AVX512DQ,FUTURE */
        /* 241(f1 fd 48) 301 001(57) 120 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VXORPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+44631, 548},
    /*   9 : VXORPD zmmreg|mask|z,zmmrm512|b64 [r+vm:fv:   evex.nds.512.66.0f.w1 57 /r       ] ND,AVX512DQ,FUTURE */
        /* 240(f1 fd 48) 301 001(57) 110 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VXORPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+44640, 548},
};

static const struct itemplate instrux_VXORPS[10] = {
    /*   0 : VXORPS xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.0f 57 /r              ] AVX,SANDYBRIDGE */
        /* 261(001 000) 001(57) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VXORPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61702, 434},
    /*   1 : VXORPS xmmreg,xmmrm128 [r+vm:      vex.nds.128.0f 57 /r              ] ND,AVX,SANDYBRIDGE */
        /* 260(001 000) 001(57) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VXORPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61709, 434},
    /*   2 : VXORPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.0f 57 /r              ] AVX,SANDYBRIDGE */
        /* 261(001 004) 001(57) 120 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VXORPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61716, 434},
    /*   3 : VXORPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.0f 57 /r              ] ND,AVX,SANDYBRIDGE */
        /* 260(001 004) 001(57) 110 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VXORPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+61723, 434},
    /*   4 : VXORPS xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.nds.128.0f.w0 57 /r          ] AVX512VL,AVX512DQ,FUTURE */
        /* 241(f1 7c 08) 301 001(57) 120 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VXORPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+44649, 547},
    /*   5 : VXORPS xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.nds.128.0f.w0 57 /r          ] ND,AVX512VL,AVX512DQ,FUTURE */
        /* 240(f1 7c 08) 301 001(57) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VXORPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+44658, 547},
    /*   6 : VXORPS ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.nds.256.0f.w0 57 /r          ] AVX512VL,AVX512DQ,FUTURE */
        /* 241(f1 7c 28) 301 001(57) 120 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VXORPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+44667, 547},
    /*   7 : VXORPS ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.nds.256.0f.w0 57 /r          ] ND,AVX512VL,AVX512DQ,FUTURE */
        /* 240(f1 7c 28) 301 001(57) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VXORPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+44676, 547},
    /*   8 : VXORPS zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv:   evex.nds.512.0f.w0 57 /r          ] AVX512DQ,FUTURE */
        /* 241(f1 7c 48) 301 001(57) 120 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VXORPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+44685, 548},
    /*   9 : VXORPS zmmreg|mask|z,zmmrm512|b32 [r+vm:fv:   evex.nds.512.0f.w0 57 /r          ] ND,AVX512DQ,FUTURE */
        /* 240(f1 7c 48) 301 001(57) 110 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VXORPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+44694, 548},
};

static const struct itemplate instrux_VZEROALL[1] = {
    /*   0 : VZEROALL void [          vex.256.0f.w0 77                  ] AVX,SANDYBRIDGE */
        /* 270(001 004) 001(77) : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VZEROALL, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+69812, 442},
};

static const struct itemplate instrux_VZEROUPPER[1] = {
    /*   0 : VZEROUPPER void [          vex.128.0f.w0 77                  ] AVX,SANDYBRIDGE */
        /* 270(001 000) 001(77) : NOAPX,VEX,AVX,SANDYBRIDGE */
        {I_VZEROUPPER, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+69818, 442},
};

static const struct itemplate instrux_PCLMULLQLQDQ[1] = {
    /*   0 : PCLMULLQLQDQ xmmreg,xmmrm128 [rm:       66 0f3a 44 /r 00                  ] SSE,WESTMERE */
        /* 361 357 001(44) 110 001(00) : NOAPX,SSE,WESTMERE */
        {I_PCLMULLQLQDQ, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+52485, 433},
};

static const struct itemplate instrux_PCLMULHQLQDQ[1] = {
    /*   0 : PCLMULHQLQDQ xmmreg,xmmrm128 [rm:       66 0f3a 44 /r 01                  ] SSE,WESTMERE */
        /* 361 357 001(44) 110 001(01) : NOAPX,SSE,WESTMERE */
        {I_PCLMULHQLQDQ, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+52493, 433},
};

static const struct itemplate instrux_PCLMULLQHQDQ[1] = {
    /*   0 : PCLMULLQHQDQ xmmreg,xmmrm128 [rm:       66 0f3a 44 /r 10                  ] SSE,WESTMERE */
        /* 361 357 001(44) 110 001(10) : NOAPX,SSE,WESTMERE */
        {I_PCLMULLQHQDQ, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+52501, 433},
};

static const struct itemplate instrux_PCLMULHQHQDQ[1] = {
    /*   0 : PCLMULHQHQDQ xmmreg,xmmrm128 [rm:       66 0f3a 44 /r 11                  ] SSE,WESTMERE */
        /* 361 357 001(44) 110 001(11) : NOAPX,SSE,WESTMERE */
        {I_PCLMULHQHQDQ, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+52509, 433},
};

static const struct itemplate instrux_PCLMULQDQ[1] = {
    /*   0 : PCLMULQDQ xmmreg,xmmrm128,imm8 [rmi:      66 0f3a 44 /r ib                  ] SSE,WESTMERE */
        /* 361 357 001(44) 110 022 : NOAPX,SSE,WESTMERE */
        {I_PCLMULQDQ, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+61730, 433},
};

static const struct itemplate instrux_VPCLMULLQLQDQ[10] = {
    /*   0 : VPCLMULLQLQDQ xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f3a 44 /r 00      ] AVX,SANDYBRIDGE */
        /* 261(003 001) 001(44) 120 001(00) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPCLMULLQLQDQ, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+29466, 434},
    /*   1 : VPCLMULLQLQDQ xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f3a 44 /r 00      ] ND,AVX,SANDYBRIDGE */
        /* 260(003 001) 001(44) 110 001(00) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPCLMULLQLQDQ, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29475, 434},
    /*   2 : VPCLMULLQLQDQ ymmreg,ymmreg*,ymmrm256 [rvm:fv:   vex.nds.256.66.0f3a.wig 44 /r 00  ] VPCLMULQDQ,FUTURE */
        /* 261(003 005) 001(44) 120 001(00) : NOAPX,WIG,VEX,VPCLMULQDQ,FUTURE */
        {I_VPCLMULLQLQDQ, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+29538, 459},
    /*   3 : VPCLMULLQLQDQ ymmreg,ymmrm256 [r+vm:fv:   vex.nds.256.66.0f3a.wig 44 /r 00  ] ND,VPCLMULQDQ,FUTURE */
        /* 260(003 005) 001(44) 110 001(00) : NOAPX,WIG,VEX,VPCLMULQDQ,FUTURE */
        {I_VPCLMULLQLQDQ, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29547, 459},
    /*   4 : VPCLMULLQLQDQ xmmreg,xmmreg*,xmmrm128 [rvm:fv:   evex.nds.128.66.0f3a.wig 44 /r 00 ] AVX512VL,VPCLMULQDQ,FUTURE */
        /* 241(f3 7d 08) 301 001(44) 120 001(00) : WIG,EVEX,PROT,AVX512VL,VPCLMULQDQ,FUTURE */
        {I_VPCLMULLQLQDQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4479, 460},
    /*   5 : VPCLMULLQLQDQ xmmreg,xmmrm128 [r+vm:fv:   evex.nds.128.66.0f3a.wig 44 /r 00 ] ND,AVX512VL,VPCLMULQDQ,FUTURE */
        /* 240(f3 7d 08) 301 001(44) 110 001(00) : WIG,EVEX,PROT,AVX512VL,VPCLMULQDQ,FUTURE */
        {I_VPCLMULLQLQDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4490, 460},
    /*   6 : VPCLMULLQLQDQ ymmreg,ymmreg*,ymmrm256 [rvm:fv:   evex.nds.256.66.0f3a.wig 44 /r 00 ] AVX512VL,VPCLMULQDQ,FUTURE */
        /* 241(f3 7d 28) 301 001(44) 120 001(00) : WIG,EVEX,PROT,AVX512VL,VPCLMULQDQ,FUTURE */
        {I_VPCLMULLQLQDQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4567, 460},
    /*   7 : VPCLMULLQLQDQ ymmreg,ymmrm256 [r+vm:fv:   evex.nds.256.66.0f3a.wig 44 /r 00 ] ND,AVX512VL,VPCLMULQDQ,FUTURE */
        /* 240(f3 7d 28) 301 001(44) 110 001(00) : WIG,EVEX,PROT,AVX512VL,VPCLMULQDQ,FUTURE */
        {I_VPCLMULLQLQDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4578, 460},
    /*   8 : VPCLMULLQLQDQ zmmreg,zmmreg*,zmmrm512 [rvm:fv:   evex.nds.512.66.0f3a.wig 44 /r 00 ] AVX512,VPCLMULQDQ,FUTURE */
        /* 241(f3 7d 48) 301 001(44) 120 001(00) : WIG,EVEX,PROT,AVX512,VPCLMULQDQ,FUTURE */
        {I_VPCLMULLQLQDQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, NO_DECORATOR, nasm_bytecodes+4655, 461},
    /*   9 : VPCLMULLQLQDQ zmmreg,zmmrm512 [r+vm:fv:   evex.nds.512.66.0f3a.wig 44 /r 00 ] ND,AVX512,VPCLMULQDQ,FUTURE */
        /* 240(f3 7d 48) 301 001(44) 110 001(00) : WIG,EVEX,PROT,AVX512,VPCLMULQDQ,FUTURE */
        {I_VPCLMULLQLQDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+4666, 461},
};

static const struct itemplate instrux_VPCLMULHQLQDQ[10] = {
    /*   0 : VPCLMULHQLQDQ xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f3a 44 /r 01      ] AVX,SANDYBRIDGE */
        /* 261(003 001) 001(44) 120 001(01) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPCLMULHQLQDQ, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+29484, 434},
    /*   1 : VPCLMULHQLQDQ xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f3a 44 /r 01      ] ND,AVX,SANDYBRIDGE */
        /* 260(003 001) 001(44) 110 001(01) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPCLMULHQLQDQ, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29493, 434},
    /*   2 : VPCLMULHQLQDQ ymmreg,ymmreg*,ymmrm256 [rvm:fv:   vex.nds.256.66.0f3a.wig 44 /r 01  ] VPCLMULQDQ,FUTURE */
        /* 261(003 005) 001(44) 120 001(01) : NOAPX,WIG,VEX,VPCLMULQDQ,FUTURE */
        {I_VPCLMULHQLQDQ, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+29556, 459},
    /*   3 : VPCLMULHQLQDQ ymmreg,ymmrm256 [r+vm:fv:   vex.nds.256.66.0f3a.wig 44 /r 01  ] ND,VPCLMULQDQ,FUTURE */
        /* 260(003 005) 001(44) 110 001(01) : NOAPX,WIG,VEX,VPCLMULQDQ,FUTURE */
        {I_VPCLMULHQLQDQ, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29565, 459},
    /*   4 : VPCLMULHQLQDQ xmmreg,xmmreg*,xmmrm128 [rvm:fv:   evex.nds.128.66.0f3a.wig 44 /r 01 ] AVX512VL,VPCLMULQDQ,FUTURE */
        /* 241(f3 7d 08) 301 001(44) 120 001(01) : WIG,EVEX,PROT,AVX512VL,VPCLMULQDQ,FUTURE */
        {I_VPCLMULHQLQDQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4501, 460},
    /*   5 : VPCLMULHQLQDQ xmmreg,xmmrm128 [r+vm:fv:   evex.nds.128.66.0f3a.wig 44 /r 01 ] ND,AVX512VL,VPCLMULQDQ,FUTURE */
        /* 240(f3 7d 08) 301 001(44) 110 001(01) : WIG,EVEX,PROT,AVX512VL,VPCLMULQDQ,FUTURE */
        {I_VPCLMULHQLQDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4512, 460},
    /*   6 : VPCLMULHQLQDQ ymmreg,ymmreg*,ymmrm256 [rvm:fv:   evex.nds.256.66.0f3a.wig 44 /r 01 ] AVX512VL,VPCLMULQDQ,FUTURE */
        /* 241(f3 7d 28) 301 001(44) 120 001(01) : WIG,EVEX,PROT,AVX512VL,VPCLMULQDQ,FUTURE */
        {I_VPCLMULHQLQDQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4589, 460},
    /*   7 : VPCLMULHQLQDQ ymmreg,ymmrm256 [r+vm:fv:   evex.nds.256.66.0f3a.wig 44 /r 01 ] ND,AVX512VL,VPCLMULQDQ,FUTURE */
        /* 240(f3 7d 28) 301 001(44) 110 001(01) : WIG,EVEX,PROT,AVX512VL,VPCLMULQDQ,FUTURE */
        {I_VPCLMULHQLQDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4600, 460},
    /*   8 : VPCLMULHQLQDQ zmmreg,zmmreg*,zmmrm512 [rvm:fv:   evex.nds.512.66.0f3a.wig 44 /r 01 ] AVX512,VPCLMULQDQ,FUTURE */
        /* 241(f3 7d 48) 301 001(44) 120 001(01) : WIG,EVEX,PROT,AVX512,VPCLMULQDQ,FUTURE */
        {I_VPCLMULHQLQDQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, NO_DECORATOR, nasm_bytecodes+4677, 461},
    /*   9 : VPCLMULHQLQDQ zmmreg,zmmrm512 [r+vm:fv:   evex.nds.512.66.0f3a.wig 44 /r 01 ] ND,AVX512,VPCLMULQDQ,FUTURE */
        /* 240(f3 7d 48) 301 001(44) 110 001(01) : WIG,EVEX,PROT,AVX512,VPCLMULQDQ,FUTURE */
        {I_VPCLMULHQLQDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+4688, 461},
};

static const struct itemplate instrux_VPCLMULLQHQDQ[10] = {
    /*   0 : VPCLMULLQHQDQ xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f3a 44 /r 10      ] AVX,SANDYBRIDGE */
        /* 261(003 001) 001(44) 120 001(10) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPCLMULLQHQDQ, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+29502, 434},
    /*   1 : VPCLMULLQHQDQ xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f3a 44 /r 10      ] ND,AVX,SANDYBRIDGE */
        /* 260(003 001) 001(44) 110 001(10) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPCLMULLQHQDQ, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29511, 434},
    /*   2 : VPCLMULLQHQDQ ymmreg,ymmreg*,ymmrm256 [rvm:fv:   vex.nds.256.66.0f3a.wig 44 /r 10  ] VPCLMULQDQ,FUTURE */
        /* 261(003 005) 001(44) 120 001(10) : NOAPX,WIG,VEX,VPCLMULQDQ,FUTURE */
        {I_VPCLMULLQHQDQ, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+29574, 459},
    /*   3 : VPCLMULLQHQDQ ymmreg,ymmrm256 [r+vm:fv:   vex.nds.256.66.0f3a.wig 44 /r 10  ] ND,VPCLMULQDQ,FUTURE */
        /* 260(003 005) 001(44) 110 001(10) : NOAPX,WIG,VEX,VPCLMULQDQ,FUTURE */
        {I_VPCLMULLQHQDQ, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29583, 459},
    /*   4 : VPCLMULLQHQDQ xmmreg,xmmreg*,xmmrm128 [rvm:fv:   evex.nds.128.66.0f3a.wig 44 /r 10 ] AVX512VL,VPCLMULQDQ,FUTURE */
        /* 241(f3 7d 08) 301 001(44) 120 001(10) : WIG,EVEX,PROT,AVX512VL,VPCLMULQDQ,FUTURE */
        {I_VPCLMULLQHQDQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4523, 460},
    /*   5 : VPCLMULLQHQDQ xmmreg,xmmrm128 [r+vm:fv:   evex.nds.128.66.0f3a.wig 44 /r 10 ] ND,AVX512VL,VPCLMULQDQ,FUTURE */
        /* 240(f3 7d 08) 301 001(44) 110 001(10) : WIG,EVEX,PROT,AVX512VL,VPCLMULQDQ,FUTURE */
        {I_VPCLMULLQHQDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4534, 460},
    /*   6 : VPCLMULLQHQDQ ymmreg,ymmreg*,ymmrm256 [rvm:fv:   evex.nds.256.66.0f3a.wig 44 /r 10 ] AVX512VL,VPCLMULQDQ,FUTURE */
        /* 241(f3 7d 28) 301 001(44) 120 001(10) : WIG,EVEX,PROT,AVX512VL,VPCLMULQDQ,FUTURE */
        {I_VPCLMULLQHQDQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4611, 460},
    /*   7 : VPCLMULLQHQDQ ymmreg,ymmrm256 [r+vm:fv:   evex.nds.256.66.0f3a.wig 44 /r 10 ] ND,AVX512VL,VPCLMULQDQ,FUTURE */
        /* 240(f3 7d 28) 301 001(44) 110 001(10) : WIG,EVEX,PROT,AVX512VL,VPCLMULQDQ,FUTURE */
        {I_VPCLMULLQHQDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4622, 460},
    /*   8 : VPCLMULLQHQDQ zmmreg,zmmreg*,zmmrm512 [rvm:fv:   evex.nds.512.66.0f3a.wig 44 /r 10 ] AVX512,VPCLMULQDQ,FUTURE */
        /* 241(f3 7d 48) 301 001(44) 120 001(10) : WIG,EVEX,PROT,AVX512,VPCLMULQDQ,FUTURE */
        {I_VPCLMULLQHQDQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, NO_DECORATOR, nasm_bytecodes+4699, 461},
    /*   9 : VPCLMULLQHQDQ zmmreg,zmmrm512 [r+vm:fv:   evex.nds.512.66.0f3a.wig 44 /r 10 ] ND,AVX512,VPCLMULQDQ,FUTURE */
        /* 240(f3 7d 48) 301 001(44) 110 001(10) : WIG,EVEX,PROT,AVX512,VPCLMULQDQ,FUTURE */
        {I_VPCLMULLQHQDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+4710, 461},
};

static const struct itemplate instrux_VPCLMULHQHQDQ[10] = {
    /*   0 : VPCLMULHQHQDQ xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f3a 44 /r 11      ] AVX,SANDYBRIDGE */
        /* 261(003 001) 001(44) 120 001(11) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPCLMULHQHQDQ, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+29520, 434},
    /*   1 : VPCLMULHQHQDQ xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f3a 44 /r 11      ] ND,AVX,SANDYBRIDGE */
        /* 260(003 001) 001(44) 110 001(11) : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPCLMULHQHQDQ, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29529, 434},
    /*   2 : VPCLMULHQHQDQ ymmreg,ymmreg*,ymmrm256 [rvm:fv:   vex.nds.256.66.0f3a.wig 44 /r 11  ] VPCLMULQDQ,FUTURE */
        /* 261(003 005) 001(44) 120 001(11) : NOAPX,WIG,VEX,VPCLMULQDQ,FUTURE */
        {I_VPCLMULHQHQDQ, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+29592, 459},
    /*   3 : VPCLMULHQHQDQ ymmreg,ymmrm256 [r+vm:fv:   vex.nds.256.66.0f3a.wig 44 /r 11  ] ND,VPCLMULQDQ,FUTURE */
        /* 260(003 005) 001(44) 110 001(11) : NOAPX,WIG,VEX,VPCLMULQDQ,FUTURE */
        {I_VPCLMULHQHQDQ, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29601, 459},
    /*   4 : VPCLMULHQHQDQ xmmreg,xmmreg*,xmmrm128 [rvm:fv:   evex.nds.128.66.0f3a.wig 44 /r 11 ] AVX512VL,VPCLMULQDQ,FUTURE */
        /* 241(f3 7d 08) 301 001(44) 120 001(11) : WIG,EVEX,PROT,AVX512VL,VPCLMULQDQ,FUTURE */
        {I_VPCLMULHQHQDQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4545, 460},
    /*   5 : VPCLMULHQHQDQ xmmreg,xmmrm128 [r+vm:fv:   evex.nds.128.66.0f3a.wig 44 /r 11 ] ND,AVX512VL,VPCLMULQDQ,FUTURE */
        /* 240(f3 7d 08) 301 001(44) 110 001(11) : WIG,EVEX,PROT,AVX512VL,VPCLMULQDQ,FUTURE */
        {I_VPCLMULHQHQDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4556, 460},
    /*   6 : VPCLMULHQHQDQ ymmreg,ymmreg*,ymmrm256 [rvm:fv:   evex.nds.256.66.0f3a.wig 44 /r 11 ] AVX512VL,VPCLMULQDQ,FUTURE */
        /* 241(f3 7d 28) 301 001(44) 120 001(11) : WIG,EVEX,PROT,AVX512VL,VPCLMULQDQ,FUTURE */
        {I_VPCLMULHQHQDQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4633, 460},
    /*   7 : VPCLMULHQHQDQ ymmreg,ymmrm256 [r+vm:fv:   evex.nds.256.66.0f3a.wig 44 /r 11 ] ND,AVX512VL,VPCLMULQDQ,FUTURE */
        /* 240(f3 7d 28) 301 001(44) 110 001(11) : WIG,EVEX,PROT,AVX512VL,VPCLMULQDQ,FUTURE */
        {I_VPCLMULHQHQDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4644, 460},
    /*   8 : VPCLMULHQHQDQ zmmreg,zmmreg*,zmmrm512 [rvm:fv:   evex.nds.512.66.0f3a.wig 44 /r 11 ] AVX512,VPCLMULQDQ,FUTURE */
        /* 241(f3 7d 48) 301 001(44) 120 001(11) : WIG,EVEX,PROT,AVX512,VPCLMULQDQ,FUTURE */
        {I_VPCLMULHQHQDQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, NO_DECORATOR, nasm_bytecodes+4721, 461},
    /*   9 : VPCLMULHQHQDQ zmmreg,zmmrm512 [r+vm:fv:   evex.nds.512.66.0f3a.wig 44 /r 11 ] ND,AVX512,VPCLMULQDQ,FUTURE */
        /* 240(f3 7d 48) 301 001(44) 110 001(11) : WIG,EVEX,PROT,AVX512,VPCLMULQDQ,FUTURE */
        {I_VPCLMULHQHQDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+4732, 461},
};

static const struct itemplate instrux_VPCLMULQDQ[10] = {
    /*   0 : VPCLMULQDQ xmmreg,xmmreg*,xmmrm128,imm8 [rvmi:     vex.nds.128.66.0f3a 44 /r ib      ] AVX,SANDYBRIDGE */
        /* 261(003 001) 001(44) 120 023 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPCLMULQDQ, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+52517, 434},
    /*   1 : VPCLMULQDQ xmmreg,xmmrm128,imm8 [r+vmi:     vex.nds.128.66.0f3a 44 /r ib      ] ND,AVX,SANDYBRIDGE */
        /* 260(003 001) 001(44) 110 022 : NOAPX,WIG,VEX,AVX,SANDYBRIDGE */
        {I_VPCLMULQDQ, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52525, 434},
    /*   2 : VPCLMULQDQ ymmreg,ymmreg*,ymmrm256,imm8 [rvmi:fv:  vex.nds.256.66.0f3a.wig 44 /r ib  ] VPCLMULQDQ,FUTURE */
        /* 261(003 005) 001(44) 120 023 : NOAPX,WIG,VEX,VPCLMULQDQ,FUTURE */
        {I_VPCLMULQDQ, 4, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+52533, 459},
    /*   3 : VPCLMULQDQ ymmreg,ymmrm256,imm8 [r+vmi:fv:  vex.nds.256.66.0f3a.wig 44 /r ib  ] ND,VPCLMULQDQ,FUTURE */
        /* 260(003 005) 001(44) 110 022 : NOAPX,WIG,VEX,VPCLMULQDQ,FUTURE */
        {I_VPCLMULQDQ, 3, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52541, 459},
    /*   4 : VPCLMULQDQ xmmreg,xmmreg*,xmmrm128,imm8 [rvmi:fv:  evex.nds.128.66.0f3a.wig 44 /r ib ] AVX512VL,VPCLMULQDQ,FUTURE */
        /* 241(f3 7d 08) 301 001(44) 120 023 : WIG,EVEX,PROT,AVX512VL,VPCLMULQDQ,FUTURE */
        {I_VPCLMULQDQ, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+17993, 460},
    /*   5 : VPCLMULQDQ xmmreg,xmmrm128,imm8 [r+vmi:fv:  evex.nds.128.66.0f3a.wig 44 /r ib ] ND,AVX512VL,VPCLMULQDQ,FUTURE */
        /* 240(f3 7d 08) 301 001(44) 110 022 : WIG,EVEX,PROT,AVX512VL,VPCLMULQDQ,FUTURE */
        {I_VPCLMULQDQ, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18003, 460},
    /*   6 : VPCLMULQDQ ymmreg,ymmreg*,ymmrm256,imm8 [rvmi:fv:  evex.nds.256.66.0f3a.wig 44 /r ib ] AVX512VL,VPCLMULQDQ,FUTURE */
        /* 241(f3 7d 28) 301 001(44) 120 023 : WIG,EVEX,PROT,AVX512VL,VPCLMULQDQ,FUTURE */
        {I_VPCLMULQDQ, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+18013, 460},
    /*   7 : VPCLMULQDQ ymmreg,ymmrm256,imm8 [r+vmi:fv:  evex.nds.256.66.0f3a.wig 44 /r ib ] ND,AVX512VL,VPCLMULQDQ,FUTURE */
        /* 240(f3 7d 28) 301 001(44) 110 022 : WIG,EVEX,PROT,AVX512VL,VPCLMULQDQ,FUTURE */
        {I_VPCLMULQDQ, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18023, 460},
    /*   8 : VPCLMULQDQ zmmreg,zmmreg*,zmmrm512,imm8 [rvmi:fv:  evex.nds.512.66.0f3a.wig 44 /r ib ] AVX512,VPCLMULQDQ,FUTURE */
        /* 241(f3 7d 48) 301 001(44) 120 023 : WIG,EVEX,PROT,AVX512,VPCLMULQDQ,FUTURE */
        {I_VPCLMULQDQ, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+18033, 461},
    /*   9 : VPCLMULQDQ zmmreg,zmmrm512,imm8 [r+vmi:fv:  evex.nds.512.66.0f3a.wig 44 /r ib ] ND,AVX512,VPCLMULQDQ,FUTURE */
        /* 240(f3 7d 48) 301 001(44) 110 022 : WIG,EVEX,PROT,AVX512,VPCLMULQDQ,FUTURE */
        {I_VPCLMULQDQ, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18043, 461},
};

static const struct itemplate instrux_VFMADD132PS[5] = {
    /*   0 : VFMADD132PS xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w0 98 /r      ] FMA,FUTURE */
        /* 261(002 001) 001(98) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADD132PS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61737, 462},
    /*   1 : VFMADD132PS ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w0 98 /r      ] FMA,FUTURE */
        /* 261(002 005) 001(98) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADD132PS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61744, 462},
    /*   2 : VFMADD132PS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f38.w0 98 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 08) 301 001(98) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMADD132PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+32481, 544},
    /*   3 : VFMADD132PS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f38.w0 98 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 28) 301 001(98) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMADD132PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+32490, 544},
    /*   4 : VFMADD132PS zmmreg|mask|z,zmmreg,zmmrm512|b32|er [rvm:fv:   evex.nds.512.66.0f38.w0 98 /r     ] AVX512,FUTURE */
        /* 241(f2 7d 48) 301 001(98) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VFMADD132PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+32499, 545},
};

static const struct itemplate instrux_VFMADD132PD[5] = {
    /*   0 : VFMADD132PD xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w1 98 /r      ] FMA,FUTURE */
        /* 261(002 201) 001(98) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADD132PD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61751, 462},
    /*   1 : VFMADD132PD ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w1 98 /r      ] FMA,FUTURE */
        /* 261(002 205) 001(98) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADD132PD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61758, 462},
    /*   2 : VFMADD132PD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 98 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 08) 301 001(98) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMADD132PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+32454, 544},
    /*   3 : VFMADD132PD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 98 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 28) 301 001(98) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMADD132PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+32463, 544},
    /*   4 : VFMADD132PD zmmreg|mask|z,zmmreg,zmmrm512|b64|er [rvm:fv:   evex.nds.512.66.0f38.w1 98 /r     ] AVX512,FUTURE */
        /* 241(f2 fd 48) 301 001(98) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VFMADD132PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+32472, 545},
};

static const struct itemplate instrux_VFMADD312PS[2] = {
    /*   0 : VFMADD312PS xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w0 98 /r      ] FMA,FUTURE */
        /* 261(002 001) 001(98) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADD312PS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61737, 462},
    /*   1 : VFMADD312PS ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w0 98 /r      ] FMA,FUTURE */
        /* 261(002 005) 001(98) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADD312PS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61744, 462},
};

static const struct itemplate instrux_VFMADD312PD[2] = {
    /*   0 : VFMADD312PD xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w1 98 /r      ] FMA,FUTURE */
        /* 261(002 201) 001(98) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADD312PD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61751, 462},
    /*   1 : VFMADD312PD ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w1 98 /r      ] FMA,FUTURE */
        /* 261(002 205) 001(98) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADD312PD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61758, 462},
};

static const struct itemplate instrux_VFMADD213PS[5] = {
    /*   0 : VFMADD213PS xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w0 a8 /r      ] FMA,FUTURE */
        /* 261(002 001) 001(a8) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADD213PS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61765, 462},
    /*   1 : VFMADD213PS ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w0 a8 /r      ] FMA,FUTURE */
        /* 261(002 005) 001(a8) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADD213PS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61772, 462},
    /*   2 : VFMADD213PS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f38.w0 a8 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 08) 301 001(a8) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMADD213PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+32553, 544},
    /*   3 : VFMADD213PS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f38.w0 a8 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 28) 301 001(a8) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMADD213PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+32562, 544},
    /*   4 : VFMADD213PS zmmreg|mask|z,zmmreg,zmmrm512|b32|er [rvm:fv:   evex.nds.512.66.0f38.w0 a8 /r     ] AVX512,FUTURE */
        /* 241(f2 7d 48) 301 001(a8) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VFMADD213PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+32571, 545},
};

static const struct itemplate instrux_VFMADD213PD[5] = {
    /*   0 : VFMADD213PD xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w1 a8 /r      ] FMA,FUTURE */
        /* 261(002 201) 001(a8) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADD213PD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61779, 462},
    /*   1 : VFMADD213PD ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w1 a8 /r      ] FMA,FUTURE */
        /* 261(002 205) 001(a8) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADD213PD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61786, 462},
    /*   2 : VFMADD213PD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 a8 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 08) 301 001(a8) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMADD213PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+32526, 544},
    /*   3 : VFMADD213PD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 a8 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 28) 301 001(a8) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMADD213PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+32535, 544},
    /*   4 : VFMADD213PD zmmreg|mask|z,zmmreg,zmmrm512|b64|er [rvm:fv:   evex.nds.512.66.0f38.w1 a8 /r     ] AVX512,FUTURE */
        /* 241(f2 fd 48) 301 001(a8) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VFMADD213PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+32544, 545},
};

static const struct itemplate instrux_VFMADD123PS[2] = {
    /*   0 : VFMADD123PS xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w0 a8 /r      ] FMA,FUTURE */
        /* 261(002 001) 001(a8) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADD123PS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61765, 462},
    /*   1 : VFMADD123PS ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w0 a8 /r      ] FMA,FUTURE */
        /* 261(002 005) 001(a8) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADD123PS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61772, 462},
};

static const struct itemplate instrux_VFMADD123PD[2] = {
    /*   0 : VFMADD123PD xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w1 a8 /r      ] FMA,FUTURE */
        /* 261(002 201) 001(a8) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADD123PD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61779, 462},
    /*   1 : VFMADD123PD ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w1 a8 /r      ] FMA,FUTURE */
        /* 261(002 205) 001(a8) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADD123PD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61786, 462},
};

static const struct itemplate instrux_VFMADD231PS[5] = {
    /*   0 : VFMADD231PS xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w0 b8 /r      ] FMA,FUTURE */
        /* 261(002 001) 001(b8) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADD231PS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61793, 462},
    /*   1 : VFMADD231PS ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w0 b8 /r      ] FMA,FUTURE */
        /* 261(002 005) 001(b8) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADD231PS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61800, 462},
    /*   2 : VFMADD231PS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f38.w0 b8 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 08) 301 001(b8) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMADD231PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+32625, 544},
    /*   3 : VFMADD231PS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f38.w0 b8 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 28) 301 001(b8) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMADD231PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+32634, 544},
    /*   4 : VFMADD231PS zmmreg|mask|z,zmmreg,zmmrm512|b32|er [rvm:fv:   evex.nds.512.66.0f38.w0 b8 /r     ] AVX512,FUTURE */
        /* 241(f2 7d 48) 301 001(b8) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VFMADD231PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+32643, 545},
};

static const struct itemplate instrux_VFMADD231PD[5] = {
    /*   0 : VFMADD231PD xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w1 b8 /r      ] FMA,FUTURE */
        /* 261(002 201) 001(b8) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADD231PD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61807, 462},
    /*   1 : VFMADD231PD ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w1 b8 /r      ] FMA,FUTURE */
        /* 261(002 205) 001(b8) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADD231PD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61814, 462},
    /*   2 : VFMADD231PD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 b8 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 08) 301 001(b8) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMADD231PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+32598, 544},
    /*   3 : VFMADD231PD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 b8 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 28) 301 001(b8) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMADD231PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+32607, 544},
    /*   4 : VFMADD231PD zmmreg|mask|z,zmmreg,zmmrm512|b64|er [rvm:fv:   evex.nds.512.66.0f38.w1 b8 /r     ] AVX512,FUTURE */
        /* 241(f2 fd 48) 301 001(b8) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VFMADD231PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+32616, 545},
};

static const struct itemplate instrux_VFMADD321PS[2] = {
    /*   0 : VFMADD321PS xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w0 b8 /r      ] FMA,FUTURE */
        /* 261(002 001) 001(b8) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADD321PS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61793, 462},
    /*   1 : VFMADD321PS ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w0 b8 /r      ] FMA,FUTURE */
        /* 261(002 005) 001(b8) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADD321PS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61800, 462},
};

static const struct itemplate instrux_VFMADD321PD[2] = {
    /*   0 : VFMADD321PD xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w1 b8 /r      ] FMA,FUTURE */
        /* 261(002 201) 001(b8) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADD321PD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61807, 462},
    /*   1 : VFMADD321PD ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w1 b8 /r      ] FMA,FUTURE */
        /* 261(002 205) 001(b8) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADD321PD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61814, 462},
};

static const struct itemplate instrux_VFMADDSUB132PS[5] = {
    /*   0 : VFMADDSUB132PS xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w0 96 /r      ] FMA,FUTURE */
        /* 261(002 001) 001(96) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADDSUB132PS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61821, 462},
    /*   1 : VFMADDSUB132PS ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w0 96 /r      ] FMA,FUTURE */
        /* 261(002 005) 001(96) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADDSUB132PS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61828, 462},
    /*   2 : VFMADDSUB132PS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f38.w0 96 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 08) 301 001(96) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMADDSUB132PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+32697, 544},
    /*   3 : VFMADDSUB132PS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f38.w0 96 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 28) 301 001(96) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMADDSUB132PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+32706, 544},
    /*   4 : VFMADDSUB132PS zmmreg|mask|z,zmmreg,zmmrm512|b32|er [rvm:fv:   evex.nds.512.66.0f38.w0 96 /r     ] AVX512,FUTURE */
        /* 241(f2 7d 48) 301 001(96) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VFMADDSUB132PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+32715, 545},
};

static const struct itemplate instrux_VFMADDSUB132PD[5] = {
    /*   0 : VFMADDSUB132PD xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w1 96 /r      ] FMA,FUTURE */
        /* 261(002 201) 001(96) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADDSUB132PD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61835, 462},
    /*   1 : VFMADDSUB132PD ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w1 96 /r      ] FMA,FUTURE */
        /* 261(002 205) 001(96) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADDSUB132PD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61842, 462},
    /*   2 : VFMADDSUB132PD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 96 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 08) 301 001(96) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMADDSUB132PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+32670, 544},
    /*   3 : VFMADDSUB132PD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 96 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 28) 301 001(96) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMADDSUB132PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+32679, 544},
    /*   4 : VFMADDSUB132PD zmmreg|mask|z,zmmreg,zmmrm512|b64|er [rvm:fv:   evex.nds.512.66.0f38.w1 96 /r     ] AVX512,FUTURE */
        /* 241(f2 fd 48) 301 001(96) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VFMADDSUB132PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+32688, 545},
};

static const struct itemplate instrux_VFMADDSUB312PS[2] = {
    /*   0 : VFMADDSUB312PS xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w0 96 /r      ] FMA,FUTURE */
        /* 261(002 001) 001(96) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADDSUB312PS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61821, 462},
    /*   1 : VFMADDSUB312PS ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w0 96 /r      ] FMA,FUTURE */
        /* 261(002 005) 001(96) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADDSUB312PS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61828, 462},
};

static const struct itemplate instrux_VFMADDSUB312PD[2] = {
    /*   0 : VFMADDSUB312PD xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w1 96 /r      ] FMA,FUTURE */
        /* 261(002 201) 001(96) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADDSUB312PD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61835, 462},
    /*   1 : VFMADDSUB312PD ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w1 96 /r      ] FMA,FUTURE */
        /* 261(002 205) 001(96) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADDSUB312PD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61842, 462},
};

static const struct itemplate instrux_VFMADDSUB213PS[5] = {
    /*   0 : VFMADDSUB213PS xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w0 a6 /r      ] FMA,FUTURE */
        /* 261(002 001) 001(a6) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADDSUB213PS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61849, 462},
    /*   1 : VFMADDSUB213PS ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w0 a6 /r      ] FMA,FUTURE */
        /* 261(002 005) 001(a6) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADDSUB213PS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61856, 462},
    /*   2 : VFMADDSUB213PS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f38.w0 a6 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 08) 301 001(a6) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMADDSUB213PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+32751, 544},
    /*   3 : VFMADDSUB213PS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f38.w0 a6 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 28) 301 001(a6) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMADDSUB213PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+32760, 544},
    /*   4 : VFMADDSUB213PS zmmreg|mask|z,zmmreg,zmmrm512|b32|er [rvm:fv:   evex.nds.512.66.0f38.w0 a6 /r     ] AVX512,FUTURE */
        /* 241(f2 7d 48) 301 001(a6) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VFMADDSUB213PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+32769, 545},
};

static const struct itemplate instrux_VFMADDSUB213PD[5] = {
    /*   0 : VFMADDSUB213PD xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w1 a6 /r      ] FMA,FUTURE */
        /* 261(002 201) 001(a6) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADDSUB213PD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61863, 462},
    /*   1 : VFMADDSUB213PD ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w1 a6 /r      ] FMA,FUTURE */
        /* 261(002 205) 001(a6) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADDSUB213PD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61870, 462},
    /*   2 : VFMADDSUB213PD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 a6 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 08) 301 001(a6) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMADDSUB213PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+32724, 544},
    /*   3 : VFMADDSUB213PD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 a6 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 28) 301 001(a6) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMADDSUB213PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+32733, 544},
    /*   4 : VFMADDSUB213PD zmmreg|mask|z,zmmreg,zmmrm512|b64|er [rvm:fv:   evex.nds.512.66.0f38.w1 a6 /r     ] AVX512,FUTURE */
        /* 241(f2 fd 48) 301 001(a6) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VFMADDSUB213PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+32742, 545},
};

static const struct itemplate instrux_VFMADDSUB123PS[2] = {
    /*   0 : VFMADDSUB123PS xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w0 a6 /r      ] FMA,FUTURE */
        /* 261(002 001) 001(a6) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADDSUB123PS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61849, 462},
    /*   1 : VFMADDSUB123PS ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w0 a6 /r      ] FMA,FUTURE */
        /* 261(002 005) 001(a6) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADDSUB123PS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61856, 462},
};

static const struct itemplate instrux_VFMADDSUB123PD[2] = {
    /*   0 : VFMADDSUB123PD xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w1 a6 /r      ] FMA,FUTURE */
        /* 261(002 201) 001(a6) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADDSUB123PD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61863, 462},
    /*   1 : VFMADDSUB123PD ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w1 a6 /r      ] FMA,FUTURE */
        /* 261(002 205) 001(a6) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADDSUB123PD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61870, 462},
};

static const struct itemplate instrux_VFMADDSUB231PS[5] = {
    /*   0 : VFMADDSUB231PS xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w0 b6 /r      ] FMA,FUTURE */
        /* 261(002 001) 001(b6) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADDSUB231PS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61877, 462},
    /*   1 : VFMADDSUB231PS ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w0 b6 /r      ] FMA,FUTURE */
        /* 261(002 005) 001(b6) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADDSUB231PS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61884, 462},
    /*   2 : VFMADDSUB231PS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f38.w0 b6 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 08) 301 001(b6) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMADDSUB231PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+32805, 544},
    /*   3 : VFMADDSUB231PS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f38.w0 b6 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 28) 301 001(b6) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMADDSUB231PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+32814, 544},
    /*   4 : VFMADDSUB231PS zmmreg|mask|z,zmmreg,zmmrm512|b32|er [rvm:fv:   evex.nds.512.66.0f38.w0 b6 /r     ] AVX512,FUTURE */
        /* 241(f2 7d 48) 301 001(b6) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VFMADDSUB231PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+32823, 545},
};

static const struct itemplate instrux_VFMADDSUB231PD[5] = {
    /*   0 : VFMADDSUB231PD xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w1 b6 /r      ] FMA,FUTURE */
        /* 261(002 201) 001(b6) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADDSUB231PD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61891, 462},
    /*   1 : VFMADDSUB231PD ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w1 b6 /r      ] FMA,FUTURE */
        /* 261(002 205) 001(b6) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADDSUB231PD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61898, 462},
    /*   2 : VFMADDSUB231PD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 b6 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 08) 301 001(b6) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMADDSUB231PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+32778, 544},
    /*   3 : VFMADDSUB231PD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 b6 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 28) 301 001(b6) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMADDSUB231PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+32787, 544},
    /*   4 : VFMADDSUB231PD zmmreg|mask|z,zmmreg,zmmrm512|b64|er [rvm:fv:   evex.nds.512.66.0f38.w1 b6 /r     ] AVX512,FUTURE */
        /* 241(f2 fd 48) 301 001(b6) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VFMADDSUB231PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+32796, 545},
};

static const struct itemplate instrux_VFMADDSUB321PS[2] = {
    /*   0 : VFMADDSUB321PS xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w0 b6 /r      ] FMA,FUTURE */
        /* 261(002 001) 001(b6) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADDSUB321PS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61877, 462},
    /*   1 : VFMADDSUB321PS ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w0 b6 /r      ] FMA,FUTURE */
        /* 261(002 005) 001(b6) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADDSUB321PS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61884, 462},
};

static const struct itemplate instrux_VFMADDSUB321PD[2] = {
    /*   0 : VFMADDSUB321PD xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w1 b6 /r      ] FMA,FUTURE */
        /* 261(002 201) 001(b6) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADDSUB321PD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61891, 462},
    /*   1 : VFMADDSUB321PD ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w1 b6 /r      ] FMA,FUTURE */
        /* 261(002 205) 001(b6) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADDSUB321PD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61898, 462},
};

static const struct itemplate instrux_VFMSUB132PS[5] = {
    /*   0 : VFMSUB132PS xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w0 9a /r      ] FMA,FUTURE */
        /* 261(002 001) 001(9a) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUB132PS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61905, 462},
    /*   1 : VFMSUB132PS ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w0 9a /r      ] FMA,FUTURE */
        /* 261(002 005) 001(9a) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUB132PS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61912, 462},
    /*   2 : VFMSUB132PS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f38.w0 9a /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 08) 301 001(9a) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMSUB132PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+32859, 544},
    /*   3 : VFMSUB132PS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f38.w0 9a /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 28) 301 001(9a) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMSUB132PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+32868, 544},
    /*   4 : VFMSUB132PS zmmreg|mask|z,zmmreg,zmmrm512|b32|er [rvm:fv:   evex.nds.512.66.0f38.w0 9a /r     ] AVX512,FUTURE */
        /* 241(f2 7d 48) 301 001(9a) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VFMSUB132PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+32877, 545},
};

static const struct itemplate instrux_VFMSUB132PD[5] = {
    /*   0 : VFMSUB132PD xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w1 9a /r      ] FMA,FUTURE */
        /* 261(002 201) 001(9a) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUB132PD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61919, 462},
    /*   1 : VFMSUB132PD ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w1 9a /r      ] FMA,FUTURE */
        /* 261(002 205) 001(9a) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUB132PD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61926, 462},
    /*   2 : VFMSUB132PD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 9a /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 08) 301 001(9a) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMSUB132PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+32832, 544},
    /*   3 : VFMSUB132PD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 9a /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 28) 301 001(9a) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMSUB132PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+32841, 544},
    /*   4 : VFMSUB132PD zmmreg|mask|z,zmmreg,zmmrm512|b64|er [rvm:fv:   evex.nds.512.66.0f38.w1 9a /r     ] AVX512,FUTURE */
        /* 241(f2 fd 48) 301 001(9a) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VFMSUB132PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+32850, 545},
};

static const struct itemplate instrux_VFMSUB312PS[2] = {
    /*   0 : VFMSUB312PS xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w0 9a /r      ] FMA,FUTURE */
        /* 261(002 001) 001(9a) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUB312PS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61905, 462},
    /*   1 : VFMSUB312PS ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w0 9a /r      ] FMA,FUTURE */
        /* 261(002 005) 001(9a) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUB312PS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61912, 462},
};

static const struct itemplate instrux_VFMSUB312PD[2] = {
    /*   0 : VFMSUB312PD xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w1 9a /r      ] FMA,FUTURE */
        /* 261(002 201) 001(9a) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUB312PD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61919, 462},
    /*   1 : VFMSUB312PD ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w1 9a /r      ] FMA,FUTURE */
        /* 261(002 205) 001(9a) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUB312PD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61926, 462},
};

static const struct itemplate instrux_VFMSUB213PS[5] = {
    /*   0 : VFMSUB213PS xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w0 aa /r      ] FMA,FUTURE */
        /* 261(002 001) 001(aa) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUB213PS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61933, 462},
    /*   1 : VFMSUB213PS ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w0 aa /r      ] FMA,FUTURE */
        /* 261(002 005) 001(aa) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUB213PS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61940, 462},
    /*   2 : VFMSUB213PS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f38.w0 aa /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 08) 301 001(aa) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMSUB213PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+32931, 544},
    /*   3 : VFMSUB213PS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f38.w0 aa /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 28) 301 001(aa) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMSUB213PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+32940, 544},
    /*   4 : VFMSUB213PS zmmreg|mask|z,zmmreg,zmmrm512|b32|er [rvm:fv:   evex.nds.512.66.0f38.w0 aa /r     ] AVX512,FUTURE */
        /* 241(f2 7d 48) 301 001(aa) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VFMSUB213PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+32949, 545},
};

static const struct itemplate instrux_VFMSUB213PD[5] = {
    /*   0 : VFMSUB213PD xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w1 aa /r      ] FMA,FUTURE */
        /* 261(002 201) 001(aa) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUB213PD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61947, 462},
    /*   1 : VFMSUB213PD ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w1 aa /r      ] FMA,FUTURE */
        /* 261(002 205) 001(aa) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUB213PD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61954, 462},
    /*   2 : VFMSUB213PD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 aa /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 08) 301 001(aa) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMSUB213PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+32904, 544},
    /*   3 : VFMSUB213PD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 aa /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 28) 301 001(aa) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMSUB213PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+32913, 544},
    /*   4 : VFMSUB213PD zmmreg|mask|z,zmmreg,zmmrm512|b64|er [rvm:fv:   evex.nds.512.66.0f38.w1 aa /r     ] AVX512,FUTURE */
        /* 241(f2 fd 48) 301 001(aa) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VFMSUB213PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+32922, 545},
};

static const struct itemplate instrux_VFMSUB123PS[2] = {
    /*   0 : VFMSUB123PS xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w0 aa /r      ] FMA,FUTURE */
        /* 261(002 001) 001(aa) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUB123PS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61933, 462},
    /*   1 : VFMSUB123PS ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w0 aa /r      ] FMA,FUTURE */
        /* 261(002 005) 001(aa) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUB123PS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61940, 462},
};

static const struct itemplate instrux_VFMSUB123PD[2] = {
    /*   0 : VFMSUB123PD xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w1 aa /r      ] FMA,FUTURE */
        /* 261(002 201) 001(aa) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUB123PD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61947, 462},
    /*   1 : VFMSUB123PD ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w1 aa /r      ] FMA,FUTURE */
        /* 261(002 205) 001(aa) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUB123PD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61954, 462},
};

static const struct itemplate instrux_VFMSUB231PS[5] = {
    /*   0 : VFMSUB231PS xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w0 ba /r      ] FMA,FUTURE */
        /* 261(002 001) 001(ba) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUB231PS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61961, 462},
    /*   1 : VFMSUB231PS ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w0 ba /r      ] FMA,FUTURE */
        /* 261(002 005) 001(ba) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUB231PS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61968, 462},
    /*   2 : VFMSUB231PS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f38.w0 ba /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 08) 301 001(ba) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMSUB231PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+33003, 544},
    /*   3 : VFMSUB231PS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f38.w0 ba /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 28) 301 001(ba) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMSUB231PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+33012, 544},
    /*   4 : VFMSUB231PS zmmreg|mask|z,zmmreg,zmmrm512|b32|er [rvm:fv:   evex.nds.512.66.0f38.w0 ba /r     ] AVX512,FUTURE */
        /* 241(f2 7d 48) 301 001(ba) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VFMSUB231PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+33021, 545},
};

static const struct itemplate instrux_VFMSUB231PD[5] = {
    /*   0 : VFMSUB231PD xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w1 ba /r      ] FMA,FUTURE */
        /* 261(002 201) 001(ba) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUB231PD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61975, 462},
    /*   1 : VFMSUB231PD ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w1 ba /r      ] FMA,FUTURE */
        /* 261(002 205) 001(ba) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUB231PD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61982, 462},
    /*   2 : VFMSUB231PD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 ba /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 08) 301 001(ba) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMSUB231PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+32976, 544},
    /*   3 : VFMSUB231PD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 ba /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 28) 301 001(ba) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMSUB231PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+32985, 544},
    /*   4 : VFMSUB231PD zmmreg|mask|z,zmmreg,zmmrm512|b64|er [rvm:fv:   evex.nds.512.66.0f38.w1 ba /r     ] AVX512,FUTURE */
        /* 241(f2 fd 48) 301 001(ba) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VFMSUB231PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+32994, 545},
};

static const struct itemplate instrux_VFMSUB321PS[2] = {
    /*   0 : VFMSUB321PS xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w0 ba /r      ] FMA,FUTURE */
        /* 261(002 001) 001(ba) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUB321PS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61961, 462},
    /*   1 : VFMSUB321PS ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w0 ba /r      ] FMA,FUTURE */
        /* 261(002 005) 001(ba) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUB321PS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61968, 462},
};

static const struct itemplate instrux_VFMSUB321PD[2] = {
    /*   0 : VFMSUB321PD xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w1 ba /r      ] FMA,FUTURE */
        /* 261(002 201) 001(ba) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUB321PD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61975, 462},
    /*   1 : VFMSUB321PD ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w1 ba /r      ] FMA,FUTURE */
        /* 261(002 205) 001(ba) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUB321PD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61982, 462},
};

static const struct itemplate instrux_VFMSUBADD132PS[5] = {
    /*   0 : VFMSUBADD132PS xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w0 97 /r      ] FMA,FUTURE */
        /* 261(002 001) 001(97) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUBADD132PS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61989, 462},
    /*   1 : VFMSUBADD132PS ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w0 97 /r      ] FMA,FUTURE */
        /* 261(002 005) 001(97) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUBADD132PS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61996, 462},
    /*   2 : VFMSUBADD132PS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f38.w0 97 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 08) 301 001(97) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMSUBADD132PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+33075, 544},
    /*   3 : VFMSUBADD132PS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f38.w0 97 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 28) 301 001(97) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMSUBADD132PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+33084, 544},
    /*   4 : VFMSUBADD132PS zmmreg|mask|z,zmmreg,zmmrm512|b32|er [rvm:fv:   evex.nds.512.66.0f38.w0 97 /r     ] AVX512,FUTURE */
        /* 241(f2 7d 48) 301 001(97) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VFMSUBADD132PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+33093, 545},
};

static const struct itemplate instrux_VFMSUBADD132PD[5] = {
    /*   0 : VFMSUBADD132PD xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w1 97 /r      ] FMA,FUTURE */
        /* 261(002 201) 001(97) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUBADD132PD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62003, 462},
    /*   1 : VFMSUBADD132PD ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w1 97 /r      ] FMA,FUTURE */
        /* 261(002 205) 001(97) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUBADD132PD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62010, 462},
    /*   2 : VFMSUBADD132PD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 97 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 08) 301 001(97) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMSUBADD132PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+33048, 544},
    /*   3 : VFMSUBADD132PD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 97 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 28) 301 001(97) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMSUBADD132PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+33057, 544},
    /*   4 : VFMSUBADD132PD zmmreg|mask|z,zmmreg,zmmrm512|b64|er [rvm:fv:   evex.nds.512.66.0f38.w1 97 /r     ] AVX512,FUTURE */
        /* 241(f2 fd 48) 301 001(97) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VFMSUBADD132PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+33066, 545},
};

static const struct itemplate instrux_VFMSUBADD312PS[2] = {
    /*   0 : VFMSUBADD312PS xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w0 97 /r      ] FMA,FUTURE */
        /* 261(002 001) 001(97) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUBADD312PS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61989, 462},
    /*   1 : VFMSUBADD312PS ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w0 97 /r      ] FMA,FUTURE */
        /* 261(002 005) 001(97) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUBADD312PS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+61996, 462},
};

static const struct itemplate instrux_VFMSUBADD312PD[2] = {
    /*   0 : VFMSUBADD312PD xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w1 97 /r      ] FMA,FUTURE */
        /* 261(002 201) 001(97) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUBADD312PD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62003, 462},
    /*   1 : VFMSUBADD312PD ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w1 97 /r      ] FMA,FUTURE */
        /* 261(002 205) 001(97) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUBADD312PD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62010, 462},
};

static const struct itemplate instrux_VFMSUBADD213PS[5] = {
    /*   0 : VFMSUBADD213PS xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w0 a7 /r      ] FMA,FUTURE */
        /* 261(002 001) 001(a7) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUBADD213PS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62017, 462},
    /*   1 : VFMSUBADD213PS ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w0 a7 /r      ] FMA,FUTURE */
        /* 261(002 005) 001(a7) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUBADD213PS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62024, 462},
    /*   2 : VFMSUBADD213PS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f38.w0 a7 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 08) 301 001(a7) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMSUBADD213PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+33129, 544},
    /*   3 : VFMSUBADD213PS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f38.w0 a7 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 28) 301 001(a7) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMSUBADD213PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+33138, 544},
    /*   4 : VFMSUBADD213PS zmmreg|mask|z,zmmreg,zmmrm512|b32|er [rvm:fv:   evex.nds.512.66.0f38.w0 a7 /r     ] AVX512,FUTURE */
        /* 241(f2 7d 48) 301 001(a7) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VFMSUBADD213PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+33147, 545},
};

static const struct itemplate instrux_VFMSUBADD213PD[5] = {
    /*   0 : VFMSUBADD213PD xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w1 a7 /r      ] FMA,FUTURE */
        /* 261(002 201) 001(a7) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUBADD213PD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62031, 462},
    /*   1 : VFMSUBADD213PD ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w1 a7 /r      ] FMA,FUTURE */
        /* 261(002 205) 001(a7) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUBADD213PD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62038, 462},
    /*   2 : VFMSUBADD213PD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 a7 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 08) 301 001(a7) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMSUBADD213PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+33102, 544},
    /*   3 : VFMSUBADD213PD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 a7 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 28) 301 001(a7) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMSUBADD213PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+33111, 544},
    /*   4 : VFMSUBADD213PD zmmreg|mask|z,zmmreg,zmmrm512|b64|er [rvm:fv:   evex.nds.512.66.0f38.w1 a7 /r     ] AVX512,FUTURE */
        /* 241(f2 fd 48) 301 001(a7) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VFMSUBADD213PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+33120, 545},
};

static const struct itemplate instrux_VFMSUBADD123PS[2] = {
    /*   0 : VFMSUBADD123PS xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w0 a7 /r      ] FMA,FUTURE */
        /* 261(002 001) 001(a7) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUBADD123PS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62017, 462},
    /*   1 : VFMSUBADD123PS ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w0 a7 /r      ] FMA,FUTURE */
        /* 261(002 005) 001(a7) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUBADD123PS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62024, 462},
};

static const struct itemplate instrux_VFMSUBADD123PD[2] = {
    /*   0 : VFMSUBADD123PD xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w1 a7 /r      ] FMA,FUTURE */
        /* 261(002 201) 001(a7) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUBADD123PD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62031, 462},
    /*   1 : VFMSUBADD123PD ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w1 a7 /r      ] FMA,FUTURE */
        /* 261(002 205) 001(a7) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUBADD123PD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62038, 462},
};

static const struct itemplate instrux_VFMSUBADD231PS[5] = {
    /*   0 : VFMSUBADD231PS xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w0 b7 /r      ] FMA,FUTURE */
        /* 261(002 001) 001(b7) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUBADD231PS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62045, 462},
    /*   1 : VFMSUBADD231PS ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w0 b7 /r      ] FMA,FUTURE */
        /* 261(002 005) 001(b7) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUBADD231PS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62052, 462},
    /*   2 : VFMSUBADD231PS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f38.w0 b7 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 08) 301 001(b7) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMSUBADD231PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+33183, 544},
    /*   3 : VFMSUBADD231PS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f38.w0 b7 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 28) 301 001(b7) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMSUBADD231PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+33192, 544},
    /*   4 : VFMSUBADD231PS zmmreg|mask|z,zmmreg,zmmrm512|b32|er [rvm:fv:   evex.nds.512.66.0f38.w0 b7 /r     ] AVX512,FUTURE */
        /* 241(f2 7d 48) 301 001(b7) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VFMSUBADD231PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+33201, 545},
};

static const struct itemplate instrux_VFMSUBADD231PD[5] = {
    /*   0 : VFMSUBADD231PD xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w1 b7 /r      ] FMA,FUTURE */
        /* 261(002 201) 001(b7) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUBADD231PD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62059, 462},
    /*   1 : VFMSUBADD231PD ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w1 b7 /r      ] FMA,FUTURE */
        /* 261(002 205) 001(b7) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUBADD231PD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62066, 462},
    /*   2 : VFMSUBADD231PD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 b7 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 08) 301 001(b7) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMSUBADD231PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+33156, 544},
    /*   3 : VFMSUBADD231PD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 b7 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 28) 301 001(b7) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFMSUBADD231PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+33165, 544},
    /*   4 : VFMSUBADD231PD zmmreg|mask|z,zmmreg,zmmrm512|b64|er [rvm:fv:   evex.nds.512.66.0f38.w1 b7 /r     ] AVX512,FUTURE */
        /* 241(f2 fd 48) 301 001(b7) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VFMSUBADD231PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+33174, 545},
};

static const struct itemplate instrux_VFMSUBADD321PS[2] = {
    /*   0 : VFMSUBADD321PS xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w0 b7 /r      ] FMA,FUTURE */
        /* 261(002 001) 001(b7) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUBADD321PS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62045, 462},
    /*   1 : VFMSUBADD321PS ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w0 b7 /r      ] FMA,FUTURE */
        /* 261(002 005) 001(b7) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUBADD321PS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62052, 462},
};

static const struct itemplate instrux_VFMSUBADD321PD[2] = {
    /*   0 : VFMSUBADD321PD xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w1 b7 /r      ] FMA,FUTURE */
        /* 261(002 201) 001(b7) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUBADD321PD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62059, 462},
    /*   1 : VFMSUBADD321PD ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w1 b7 /r      ] FMA,FUTURE */
        /* 261(002 205) 001(b7) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUBADD321PD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62066, 462},
};

static const struct itemplate instrux_VFNMADD132PS[5] = {
    /*   0 : VFNMADD132PS xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w0 9c /r      ] FMA,FUTURE */
        /* 261(002 001) 001(9c) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMADD132PS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62073, 462},
    /*   1 : VFNMADD132PS ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w0 9c /r      ] FMA,FUTURE */
        /* 261(002 005) 001(9c) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMADD132PS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62080, 462},
    /*   2 : VFNMADD132PS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f38.w0 9c /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 08) 301 001(9c) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFNMADD132PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+33237, 544},
    /*   3 : VFNMADD132PS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f38.w0 9c /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 28) 301 001(9c) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFNMADD132PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+33246, 544},
    /*   4 : VFNMADD132PS zmmreg|mask|z,zmmreg,zmmrm512|b32|er [rvm:fv:   evex.nds.512.66.0f38.w0 9c /r     ] AVX512,FUTURE */
        /* 241(f2 7d 48) 301 001(9c) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VFNMADD132PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+33255, 545},
};

static const struct itemplate instrux_VFNMADD132PD[5] = {
    /*   0 : VFNMADD132PD xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w1 9c /r      ] FMA,FUTURE */
        /* 261(002 201) 001(9c) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMADD132PD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62087, 462},
    /*   1 : VFNMADD132PD ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w1 9c /r      ] FMA,FUTURE */
        /* 261(002 205) 001(9c) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMADD132PD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62094, 462},
    /*   2 : VFNMADD132PD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 9c /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 08) 301 001(9c) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFNMADD132PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+33210, 544},
    /*   3 : VFNMADD132PD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 9c /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 28) 301 001(9c) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFNMADD132PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+33219, 544},
    /*   4 : VFNMADD132PD zmmreg|mask|z,zmmreg,zmmrm512|b64|er [rvm:fv:   evex.nds.512.66.0f38.w1 9c /r     ] AVX512,FUTURE */
        /* 241(f2 fd 48) 301 001(9c) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VFNMADD132PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+33228, 545},
};

static const struct itemplate instrux_VFNMADD312PS[2] = {
    /*   0 : VFNMADD312PS xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w0 9c /r      ] FMA,FUTURE */
        /* 261(002 001) 001(9c) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMADD312PS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62073, 462},
    /*   1 : VFNMADD312PS ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w0 9c /r      ] FMA,FUTURE */
        /* 261(002 005) 001(9c) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMADD312PS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62080, 462},
};

static const struct itemplate instrux_VFNMADD312PD[2] = {
    /*   0 : VFNMADD312PD xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w1 9c /r      ] FMA,FUTURE */
        /* 261(002 201) 001(9c) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMADD312PD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62087, 462},
    /*   1 : VFNMADD312PD ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w1 9c /r      ] FMA,FUTURE */
        /* 261(002 205) 001(9c) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMADD312PD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62094, 462},
};

static const struct itemplate instrux_VFNMADD213PS[5] = {
    /*   0 : VFNMADD213PS xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w0 ac /r      ] FMA,FUTURE */
        /* 261(002 001) 001(ac) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMADD213PS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62101, 462},
    /*   1 : VFNMADD213PS ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w0 ac /r      ] FMA,FUTURE */
        /* 261(002 005) 001(ac) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMADD213PS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62108, 462},
    /*   2 : VFNMADD213PS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f38.w0 ac /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 08) 301 001(ac) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFNMADD213PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+33309, 544},
    /*   3 : VFNMADD213PS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f38.w0 ac /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 28) 301 001(ac) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFNMADD213PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+33318, 544},
    /*   4 : VFNMADD213PS zmmreg|mask|z,zmmreg,zmmrm512|b32|er [rvm:fv:   evex.nds.512.66.0f38.w0 ac /r     ] AVX512,FUTURE */
        /* 241(f2 7d 48) 301 001(ac) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VFNMADD213PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+33327, 545},
};

static const struct itemplate instrux_VFNMADD213PD[5] = {
    /*   0 : VFNMADD213PD xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w1 ac /r      ] FMA,FUTURE */
        /* 261(002 201) 001(ac) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMADD213PD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62115, 462},
    /*   1 : VFNMADD213PD ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w1 ac /r      ] FMA,FUTURE */
        /* 261(002 205) 001(ac) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMADD213PD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62122, 462},
    /*   2 : VFNMADD213PD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 ac /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 08) 301 001(ac) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFNMADD213PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+33282, 544},
    /*   3 : VFNMADD213PD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 ac /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 28) 301 001(ac) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFNMADD213PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+33291, 544},
    /*   4 : VFNMADD213PD zmmreg|mask|z,zmmreg,zmmrm512|b64|er [rvm:fv:   evex.nds.512.66.0f38.w1 ac /r     ] AVX512,FUTURE */
        /* 241(f2 fd 48) 301 001(ac) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VFNMADD213PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+33300, 545},
};

static const struct itemplate instrux_VFNMADD123PS[2] = {
    /*   0 : VFNMADD123PS xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w0 ac /r      ] FMA,FUTURE */
        /* 261(002 001) 001(ac) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMADD123PS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62101, 462},
    /*   1 : VFNMADD123PS ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w0 ac /r      ] FMA,FUTURE */
        /* 261(002 005) 001(ac) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMADD123PS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62108, 462},
};

static const struct itemplate instrux_VFNMADD123PD[2] = {
    /*   0 : VFNMADD123PD xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w1 ac /r      ] FMA,FUTURE */
        /* 261(002 201) 001(ac) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMADD123PD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62115, 462},
    /*   1 : VFNMADD123PD ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w1 ac /r      ] FMA,FUTURE */
        /* 261(002 205) 001(ac) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMADD123PD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62122, 462},
};

static const struct itemplate instrux_VFNMADD231PS[5] = {
    /*   0 : VFNMADD231PS xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w0 bc /r      ] FMA,FUTURE */
        /* 261(002 001) 001(bc) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMADD231PS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62129, 462},
    /*   1 : VFNMADD231PS ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w0 bc /r      ] FMA,FUTURE */
        /* 261(002 005) 001(bc) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMADD231PS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62136, 462},
    /*   2 : VFNMADD231PS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f38.w0 bc /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 08) 301 001(bc) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFNMADD231PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+33381, 544},
    /*   3 : VFNMADD231PS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f38.w0 bc /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 28) 301 001(bc) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFNMADD231PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+33390, 544},
    /*   4 : VFNMADD231PS zmmreg|mask|z,zmmreg,zmmrm512|b32|er [rvm:fv:   evex.nds.512.66.0f38.w0 bc /r     ] AVX512,FUTURE */
        /* 241(f2 7d 48) 301 001(bc) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VFNMADD231PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+33399, 545},
};

static const struct itemplate instrux_VFNMADD231PD[5] = {
    /*   0 : VFNMADD231PD xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w1 bc /r      ] FMA,FUTURE */
        /* 261(002 201) 001(bc) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMADD231PD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62143, 462},
    /*   1 : VFNMADD231PD ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w1 bc /r      ] FMA,FUTURE */
        /* 261(002 205) 001(bc) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMADD231PD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62150, 462},
    /*   2 : VFNMADD231PD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 bc /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 08) 301 001(bc) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFNMADD231PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+33354, 544},
    /*   3 : VFNMADD231PD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 bc /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 28) 301 001(bc) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFNMADD231PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+33363, 544},
    /*   4 : VFNMADD231PD zmmreg|mask|z,zmmreg,zmmrm512|b64|er [rvm:fv:   evex.nds.512.66.0f38.w1 bc /r     ] AVX512,FUTURE */
        /* 241(f2 fd 48) 301 001(bc) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VFNMADD231PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+33372, 545},
};

static const struct itemplate instrux_VFNMADD321PS[2] = {
    /*   0 : VFNMADD321PS xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w0 bc /r      ] FMA,FUTURE */
        /* 261(002 001) 001(bc) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMADD321PS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62129, 462},
    /*   1 : VFNMADD321PS ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w0 bc /r      ] FMA,FUTURE */
        /* 261(002 005) 001(bc) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMADD321PS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62136, 462},
};

static const struct itemplate instrux_VFNMADD321PD[2] = {
    /*   0 : VFNMADD321PD xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w1 bc /r      ] FMA,FUTURE */
        /* 261(002 201) 001(bc) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMADD321PD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62143, 462},
    /*   1 : VFNMADD321PD ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w1 bc /r      ] FMA,FUTURE */
        /* 261(002 205) 001(bc) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMADD321PD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62150, 462},
};

static const struct itemplate instrux_VFNMSUB132PS[5] = {
    /*   0 : VFNMSUB132PS xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w0 9e /r      ] FMA,FUTURE */
        /* 261(002 001) 001(9e) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMSUB132PS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62157, 462},
    /*   1 : VFNMSUB132PS ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w0 9e /r      ] FMA,FUTURE */
        /* 261(002 005) 001(9e) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMSUB132PS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62164, 462},
    /*   2 : VFNMSUB132PS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f38.w0 9e /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 08) 301 001(9e) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFNMSUB132PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+33453, 544},
    /*   3 : VFNMSUB132PS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f38.w0 9e /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 28) 301 001(9e) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFNMSUB132PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+33462, 544},
    /*   4 : VFNMSUB132PS zmmreg|mask|z,zmmreg,zmmrm512|b32|er [rvm:fv:   evex.nds.512.66.0f38.w0 9e /r     ] AVX512,FUTURE */
        /* 241(f2 7d 48) 301 001(9e) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VFNMSUB132PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+33471, 545},
};

static const struct itemplate instrux_VFNMSUB132PD[5] = {
    /*   0 : VFNMSUB132PD xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w1 9e /r      ] FMA,FUTURE */
        /* 261(002 201) 001(9e) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMSUB132PD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62171, 462},
    /*   1 : VFNMSUB132PD ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w1 9e /r      ] FMA,FUTURE */
        /* 261(002 205) 001(9e) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMSUB132PD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62178, 462},
    /*   2 : VFNMSUB132PD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 9e /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 08) 301 001(9e) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFNMSUB132PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+33426, 544},
    /*   3 : VFNMSUB132PD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 9e /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 28) 301 001(9e) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFNMSUB132PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+33435, 544},
    /*   4 : VFNMSUB132PD zmmreg|mask|z,zmmreg,zmmrm512|b64|er [rvm:fv:   evex.nds.512.66.0f38.w1 9e /r     ] AVX512,FUTURE */
        /* 241(f2 fd 48) 301 001(9e) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VFNMSUB132PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+33444, 545},
};

static const struct itemplate instrux_VFNMSUB312PS[2] = {
    /*   0 : VFNMSUB312PS xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w0 9e /r      ] FMA,FUTURE */
        /* 261(002 001) 001(9e) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMSUB312PS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62157, 462},
    /*   1 : VFNMSUB312PS ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w0 9e /r      ] FMA,FUTURE */
        /* 261(002 005) 001(9e) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMSUB312PS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62164, 462},
};

static const struct itemplate instrux_VFNMSUB312PD[2] = {
    /*   0 : VFNMSUB312PD xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w1 9e /r      ] FMA,FUTURE */
        /* 261(002 201) 001(9e) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMSUB312PD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62171, 462},
    /*   1 : VFNMSUB312PD ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w1 9e /r      ] FMA,FUTURE */
        /* 261(002 205) 001(9e) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMSUB312PD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62178, 462},
};

static const struct itemplate instrux_VFNMSUB213PS[5] = {
    /*   0 : VFNMSUB213PS xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w0 ae /r      ] FMA,FUTURE */
        /* 261(002 001) 001(ae) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMSUB213PS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62185, 462},
    /*   1 : VFNMSUB213PS ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w0 ae /r      ] FMA,FUTURE */
        /* 261(002 005) 001(ae) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMSUB213PS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62192, 462},
    /*   2 : VFNMSUB213PS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f38.w0 ae /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 08) 301 001(ae) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFNMSUB213PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+33525, 544},
    /*   3 : VFNMSUB213PS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f38.w0 ae /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 28) 301 001(ae) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFNMSUB213PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+33534, 544},
    /*   4 : VFNMSUB213PS zmmreg|mask|z,zmmreg,zmmrm512|b32|er [rvm:fv:   evex.nds.512.66.0f38.w0 ae /r     ] AVX512,FUTURE */
        /* 241(f2 7d 48) 301 001(ae) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VFNMSUB213PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+33543, 545},
};

static const struct itemplate instrux_VFNMSUB213PD[5] = {
    /*   0 : VFNMSUB213PD xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w1 ae /r      ] FMA,FUTURE */
        /* 261(002 201) 001(ae) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMSUB213PD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62199, 462},
    /*   1 : VFNMSUB213PD ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w1 ae /r      ] FMA,FUTURE */
        /* 261(002 205) 001(ae) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMSUB213PD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62206, 462},
    /*   2 : VFNMSUB213PD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 ae /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 08) 301 001(ae) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFNMSUB213PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+33498, 544},
    /*   3 : VFNMSUB213PD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 ae /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 28) 301 001(ae) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFNMSUB213PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+33507, 544},
    /*   4 : VFNMSUB213PD zmmreg|mask|z,zmmreg,zmmrm512|b64|er [rvm:fv:   evex.nds.512.66.0f38.w1 ae /r     ] AVX512,FUTURE */
        /* 241(f2 fd 48) 301 001(ae) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VFNMSUB213PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+33516, 545},
};

static const struct itemplate instrux_VFNMSUB123PS[2] = {
    /*   0 : VFNMSUB123PS xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w0 ae /r      ] FMA,FUTURE */
        /* 261(002 001) 001(ae) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMSUB123PS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62185, 462},
    /*   1 : VFNMSUB123PS ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w0 ae /r      ] FMA,FUTURE */
        /* 261(002 005) 001(ae) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMSUB123PS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62192, 462},
};

static const struct itemplate instrux_VFNMSUB123PD[2] = {
    /*   0 : VFNMSUB123PD xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w1 ae /r      ] FMA,FUTURE */
        /* 261(002 201) 001(ae) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMSUB123PD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62199, 462},
    /*   1 : VFNMSUB123PD ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w1 ae /r      ] FMA,FUTURE */
        /* 261(002 205) 001(ae) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMSUB123PD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62206, 462},
};

static const struct itemplate instrux_VFNMSUB231PS[5] = {
    /*   0 : VFNMSUB231PS xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w0 be /r      ] FMA,FUTURE */
        /* 261(002 001) 001(be) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMSUB231PS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62213, 462},
    /*   1 : VFNMSUB231PS ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w0 be /r      ] FMA,FUTURE */
        /* 261(002 005) 001(be) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMSUB231PS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62220, 462},
    /*   2 : VFNMSUB231PS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f38.w0 be /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 08) 301 001(be) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFNMSUB231PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+33597, 544},
    /*   3 : VFNMSUB231PS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f38.w0 be /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 28) 301 001(be) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFNMSUB231PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+33606, 544},
    /*   4 : VFNMSUB231PS zmmreg|mask|z,zmmreg,zmmrm512|b32|er [rvm:fv:   evex.nds.512.66.0f38.w0 be /r     ] AVX512,FUTURE */
        /* 241(f2 7d 48) 301 001(be) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VFNMSUB231PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+33615, 545},
};

static const struct itemplate instrux_VFNMSUB231PD[5] = {
    /*   0 : VFNMSUB231PD xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w1 be /r      ] FMA,FUTURE */
        /* 261(002 201) 001(be) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMSUB231PD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62227, 462},
    /*   1 : VFNMSUB231PD ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w1 be /r      ] FMA,FUTURE */
        /* 261(002 205) 001(be) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMSUB231PD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62234, 462},
    /*   2 : VFNMSUB231PD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 be /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 08) 301 001(be) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFNMSUB231PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+33570, 544},
    /*   3 : VFNMSUB231PD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 be /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 28) 301 001(be) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFNMSUB231PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+33579, 544},
    /*   4 : VFNMSUB231PD zmmreg|mask|z,zmmreg,zmmrm512|b64|er [rvm:fv:   evex.nds.512.66.0f38.w1 be /r     ] AVX512,FUTURE */
        /* 241(f2 fd 48) 301 001(be) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VFNMSUB231PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+33588, 545},
};

static const struct itemplate instrux_VFNMSUB321PS[2] = {
    /*   0 : VFNMSUB321PS xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w0 be /r      ] FMA,FUTURE */
        /* 261(002 001) 001(be) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMSUB321PS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62213, 462},
    /*   1 : VFNMSUB321PS ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w0 be /r      ] FMA,FUTURE */
        /* 261(002 005) 001(be) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMSUB321PS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62220, 462},
};

static const struct itemplate instrux_VFNMSUB321PD[2] = {
    /*   0 : VFNMSUB321PD xmmreg,xmmreg,xmmrm128 [rvm:      vex.dds.128.66.0f38.w1 be /r      ] FMA,FUTURE */
        /* 261(002 201) 001(be) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMSUB321PD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62227, 462},
    /*   1 : VFNMSUB321PD ymmreg,ymmreg,ymmrm256 [rvm:      vex.dds.256.66.0f38.w1 be /r      ] FMA,FUTURE */
        /* 261(002 205) 001(be) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMSUB321PD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62234, 462},
};

static const struct itemplate instrux_VFMADD132SS[2] = {
    /*   0 : VFMADD132SS xmmreg,xmmreg,xmmrm32 [rvm:      vex.dds.128.66.0f38.w0 99 /r      ] FMA,FUTURE */
        /* 261(002 001) 001(99) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADD132SS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62241, 462},
    /*   1 : VFMADD132SS xmmreg|mask|z,xmmreg,xmmrm32|er [rvm:t1s:  evex.nds.lig.66.0f38.w0 99 /r     ] AVX512,FUTURE */
        /* 241(f2 7d 08) 306 001(99) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VFMADD132SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+32517, 546},
};

static const struct itemplate instrux_VFMADD132SD[2] = {
    /*   0 : VFMADD132SD xmmreg,xmmreg,xmmrm64 [rvm:      vex.dds.128.66.0f38.w1 99 /r      ] FMA,FUTURE */
        /* 261(002 201) 001(99) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADD132SD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62248, 462},
    /*   1 : VFMADD132SD xmmreg|mask|z,xmmreg,xmmrm64|er [rvm:t1s:  evex.nds.lig.66.0f38.w1 99 /r     ] AVX512,FUTURE */
        /* 241(f2 fd 08) 306 001(99) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VFMADD132SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+32508, 546},
};

static const struct itemplate instrux_VFMADD312SS[1] = {
    /*   0 : VFMADD312SS xmmreg,xmmreg,xmmrm32 [rvm:      vex.dds.128.66.0f38.w0 99 /r      ] FMA,FUTURE */
        /* 261(002 001) 001(99) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADD312SS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62241, 462},
};

static const struct itemplate instrux_VFMADD312SD[1] = {
    /*   0 : VFMADD312SD xmmreg,xmmreg,xmmrm64 [rvm:      vex.dds.128.66.0f38.w1 99 /r      ] FMA,FUTURE */
        /* 261(002 201) 001(99) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADD312SD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62248, 462},
};

static const struct itemplate instrux_VFMADD213SS[2] = {
    /*   0 : VFMADD213SS xmmreg,xmmreg,xmmrm32 [rvm:      vex.dds.128.66.0f38.w0 a9 /r      ] FMA,FUTURE */
        /* 261(002 001) 001(a9) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADD213SS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62255, 462},
    /*   1 : VFMADD213SS xmmreg|mask|z,xmmreg,xmmrm32|er [rvm:t1s:  evex.nds.lig.66.0f38.w0 a9 /r     ] AVX512,FUTURE */
        /* 241(f2 7d 08) 306 001(a9) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VFMADD213SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+32589, 546},
};

static const struct itemplate instrux_VFMADD213SD[2] = {
    /*   0 : VFMADD213SD xmmreg,xmmreg,xmmrm64 [rvm:      vex.dds.128.66.0f38.w1 a9 /r      ] FMA,FUTURE */
        /* 261(002 201) 001(a9) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADD213SD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62262, 462},
    /*   1 : VFMADD213SD xmmreg|mask|z,xmmreg,xmmrm64|er [rvm:t1s:  evex.nds.lig.66.0f38.w1 a9 /r     ] AVX512,FUTURE */
        /* 241(f2 fd 08) 306 001(a9) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VFMADD213SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+32580, 546},
};

static const struct itemplate instrux_VFMADD123SS[1] = {
    /*   0 : VFMADD123SS xmmreg,xmmreg,xmmrm32 [rvm:      vex.dds.128.66.0f38.w0 a9 /r      ] FMA,FUTURE */
        /* 261(002 001) 001(a9) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADD123SS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62255, 462},
};

static const struct itemplate instrux_VFMADD123SD[1] = {
    /*   0 : VFMADD123SD xmmreg,xmmreg,xmmrm64 [rvm:      vex.dds.128.66.0f38.w1 a9 /r      ] FMA,FUTURE */
        /* 261(002 201) 001(a9) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADD123SD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62262, 462},
};

static const struct itemplate instrux_VFMADD231SS[2] = {
    /*   0 : VFMADD231SS xmmreg,xmmreg,xmmrm32 [rvm:      vex.dds.128.66.0f38.w0 b9 /r      ] FMA,FUTURE */
        /* 261(002 001) 001(b9) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADD231SS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62269, 462},
    /*   1 : VFMADD231SS xmmreg|mask|z,xmmreg,xmmrm32|er [rvm:t1s:  evex.nds.lig.66.0f38.w0 b9 /r     ] AVX512,FUTURE */
        /* 241(f2 7d 08) 306 001(b9) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VFMADD231SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+32661, 546},
};

static const struct itemplate instrux_VFMADD231SD[2] = {
    /*   0 : VFMADD231SD xmmreg,xmmreg,xmmrm64 [rvm:      vex.dds.128.66.0f38.w1 b9 /r      ] FMA,FUTURE */
        /* 261(002 201) 001(b9) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADD231SD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62276, 462},
    /*   1 : VFMADD231SD xmmreg|mask|z,xmmreg,xmmrm64|er [rvm:t1s:  evex.nds.lig.66.0f38.w1 b9 /r     ] AVX512,FUTURE */
        /* 241(f2 fd 08) 306 001(b9) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VFMADD231SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+32652, 546},
};

static const struct itemplate instrux_VFMADD321SS[1] = {
    /*   0 : VFMADD321SS xmmreg,xmmreg,xmmrm32 [rvm:      vex.dds.128.66.0f38.w0 b9 /r      ] FMA,FUTURE */
        /* 261(002 001) 001(b9) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADD321SS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62269, 462},
};

static const struct itemplate instrux_VFMADD321SD[1] = {
    /*   0 : VFMADD321SD xmmreg,xmmreg,xmmrm64 [rvm:      vex.dds.128.66.0f38.w1 b9 /r      ] FMA,FUTURE */
        /* 261(002 201) 001(b9) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMADD321SD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62276, 462},
};

static const struct itemplate instrux_VFMSUB132SS[2] = {
    /*   0 : VFMSUB132SS xmmreg,xmmreg,xmmrm32 [rvm:      vex.dds.128.66.0f38.w0 9b /r      ] FMA,FUTURE */
        /* 261(002 001) 001(9b) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUB132SS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62283, 462},
    /*   1 : VFMSUB132SS xmmreg|mask|z,xmmreg,xmmrm32|er [rvm:t1s:  evex.nds.lig.66.0f38.w0 9b /r     ] AVX512,FUTURE */
        /* 241(f2 7d 08) 306 001(9b) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VFMSUB132SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+32895, 546},
};

static const struct itemplate instrux_VFMSUB132SD[2] = {
    /*   0 : VFMSUB132SD xmmreg,xmmreg,xmmrm64 [rvm:      vex.dds.128.66.0f38.w1 9b /r      ] FMA,FUTURE */
        /* 261(002 201) 001(9b) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUB132SD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62290, 462},
    /*   1 : VFMSUB132SD xmmreg|mask|z,xmmreg,xmmrm64|er [rvm:t1s:  evex.nds.lig.66.0f38.w1 9b /r     ] AVX512,FUTURE */
        /* 241(f2 fd 08) 306 001(9b) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VFMSUB132SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+32886, 546},
};

static const struct itemplate instrux_VFMSUB312SS[1] = {
    /*   0 : VFMSUB312SS xmmreg,xmmreg,xmmrm32 [rvm:      vex.dds.128.66.0f38.w0 9b /r      ] FMA,FUTURE */
        /* 261(002 001) 001(9b) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUB312SS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62283, 462},
};

static const struct itemplate instrux_VFMSUB312SD[1] = {
    /*   0 : VFMSUB312SD xmmreg,xmmreg,xmmrm64 [rvm:      vex.dds.128.66.0f38.w1 9b /r      ] FMA,FUTURE */
        /* 261(002 201) 001(9b) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUB312SD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62290, 462},
};

static const struct itemplate instrux_VFMSUB213SS[2] = {
    /*   0 : VFMSUB213SS xmmreg,xmmreg,xmmrm32 [rvm:      vex.dds.128.66.0f38.w0 ab /r      ] FMA,FUTURE */
        /* 261(002 001) 001(ab) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUB213SS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62297, 462},
    /*   1 : VFMSUB213SS xmmreg|mask|z,xmmreg,xmmrm32|er [rvm:t1s:  evex.nds.lig.66.0f38.w0 ab /r     ] AVX512,FUTURE */
        /* 241(f2 7d 08) 306 001(ab) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VFMSUB213SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+32967, 546},
};

static const struct itemplate instrux_VFMSUB213SD[2] = {
    /*   0 : VFMSUB213SD xmmreg,xmmreg,xmmrm64 [rvm:      vex.dds.128.66.0f38.w1 ab /r      ] FMA,FUTURE */
        /* 261(002 201) 001(ab) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUB213SD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62304, 462},
    /*   1 : VFMSUB213SD xmmreg|mask|z,xmmreg,xmmrm64|er [rvm:t1s:  evex.nds.lig.66.0f38.w1 ab /r     ] AVX512,FUTURE */
        /* 241(f2 fd 08) 306 001(ab) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VFMSUB213SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+32958, 546},
};

static const struct itemplate instrux_VFMSUB123SS[1] = {
    /*   0 : VFMSUB123SS xmmreg,xmmreg,xmmrm32 [rvm:      vex.dds.128.66.0f38.w0 ab /r      ] FMA,FUTURE */
        /* 261(002 001) 001(ab) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUB123SS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62297, 462},
};

static const struct itemplate instrux_VFMSUB123SD[1] = {
    /*   0 : VFMSUB123SD xmmreg,xmmreg,xmmrm64 [rvm:      vex.dds.128.66.0f38.w1 ab /r      ] FMA,FUTURE */
        /* 261(002 201) 001(ab) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUB123SD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62304, 462},
};

static const struct itemplate instrux_VFMSUB231SS[2] = {
    /*   0 : VFMSUB231SS xmmreg,xmmreg,xmmrm32 [rvm:      vex.dds.128.66.0f38.w0 bb /r      ] FMA,FUTURE */
        /* 261(002 001) 001(bb) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUB231SS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62311, 462},
    /*   1 : VFMSUB231SS xmmreg|mask|z,xmmreg,xmmrm32|er [rvm:t1s:  evex.nds.lig.66.0f38.w0 bb /r     ] AVX512,FUTURE */
        /* 241(f2 7d 08) 306 001(bb) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VFMSUB231SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+33039, 546},
};

static const struct itemplate instrux_VFMSUB231SD[2] = {
    /*   0 : VFMSUB231SD xmmreg,xmmreg,xmmrm64 [rvm:      vex.dds.128.66.0f38.w1 bb /r      ] FMA,FUTURE */
        /* 261(002 201) 001(bb) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUB231SD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62318, 462},
    /*   1 : VFMSUB231SD xmmreg|mask|z,xmmreg,xmmrm64|er [rvm:t1s:  evex.nds.lig.66.0f38.w1 bb /r     ] AVX512,FUTURE */
        /* 241(f2 fd 08) 306 001(bb) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VFMSUB231SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+33030, 546},
};

static const struct itemplate instrux_VFMSUB321SS[1] = {
    /*   0 : VFMSUB321SS xmmreg,xmmreg,xmmrm32 [rvm:      vex.dds.128.66.0f38.w0 bb /r      ] FMA,FUTURE */
        /* 261(002 001) 001(bb) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUB321SS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62311, 462},
};

static const struct itemplate instrux_VFMSUB321SD[1] = {
    /*   0 : VFMSUB321SD xmmreg,xmmreg,xmmrm64 [rvm:      vex.dds.128.66.0f38.w1 bb /r      ] FMA,FUTURE */
        /* 261(002 201) 001(bb) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFMSUB321SD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62318, 462},
};

static const struct itemplate instrux_VFNMADD132SS[2] = {
    /*   0 : VFNMADD132SS xmmreg,xmmreg,xmmrm32 [rvm:      vex.dds.128.66.0f38.w0 9d /r      ] FMA,FUTURE */
        /* 261(002 001) 001(9d) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMADD132SS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62325, 462},
    /*   1 : VFNMADD132SS xmmreg|mask|z,xmmreg,xmmrm32|er [rvm:t1s:  evex.nds.lig.66.0f38.w0 9d /r     ] AVX512,FUTURE */
        /* 241(f2 7d 08) 306 001(9d) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VFNMADD132SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+33273, 546},
};

static const struct itemplate instrux_VFNMADD132SD[2] = {
    /*   0 : VFNMADD132SD xmmreg,xmmreg,xmmrm64 [rvm:      vex.dds.128.66.0f38.w1 9d /r      ] FMA,FUTURE */
        /* 261(002 201) 001(9d) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMADD132SD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62332, 462},
    /*   1 : VFNMADD132SD xmmreg|mask|z,xmmreg,xmmrm64|er [rvm:t1s:  evex.nds.lig.66.0f38.w1 9d /r     ] AVX512,FUTURE */
        /* 241(f2 fd 08) 306 001(9d) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VFNMADD132SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+33264, 546},
};

static const struct itemplate instrux_VFNMADD312SS[1] = {
    /*   0 : VFNMADD312SS xmmreg,xmmreg,xmmrm32 [rvm:      vex.dds.128.66.0f38.w0 9d /r      ] FMA,FUTURE */
        /* 261(002 001) 001(9d) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMADD312SS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62325, 462},
};

static const struct itemplate instrux_VFNMADD312SD[1] = {
    /*   0 : VFNMADD312SD xmmreg,xmmreg,xmmrm64 [rvm:      vex.dds.128.66.0f38.w1 9d /r      ] FMA,FUTURE */
        /* 261(002 201) 001(9d) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMADD312SD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62332, 462},
};

static const struct itemplate instrux_VFNMADD213SS[2] = {
    /*   0 : VFNMADD213SS xmmreg,xmmreg,xmmrm32 [rvm:      vex.dds.128.66.0f38.w0 ad /r      ] FMA,FUTURE */
        /* 261(002 001) 001(ad) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMADD213SS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62339, 462},
    /*   1 : VFNMADD213SS xmmreg|mask|z,xmmreg,xmmrm32|er [rvm:t1s:  evex.nds.lig.66.0f38.w0 ad /r     ] AVX512,FUTURE */
        /* 241(f2 7d 08) 306 001(ad) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VFNMADD213SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+33345, 546},
};

static const struct itemplate instrux_VFNMADD213SD[2] = {
    /*   0 : VFNMADD213SD xmmreg,xmmreg,xmmrm64 [rvm:      vex.dds.128.66.0f38.w1 ad /r      ] FMA,FUTURE */
        /* 261(002 201) 001(ad) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMADD213SD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62346, 462},
    /*   1 : VFNMADD213SD xmmreg|mask|z,xmmreg,xmmrm64|er [rvm:t1s:  evex.nds.lig.66.0f38.w1 ad /r     ] AVX512,FUTURE */
        /* 241(f2 fd 08) 306 001(ad) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VFNMADD213SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+33336, 546},
};

static const struct itemplate instrux_VFNMADD123SS[1] = {
    /*   0 : VFNMADD123SS xmmreg,xmmreg,xmmrm32 [rvm:      vex.dds.128.66.0f38.w0 ad /r      ] FMA,FUTURE */
        /* 261(002 001) 001(ad) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMADD123SS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62339, 462},
};

static const struct itemplate instrux_VFNMADD123SD[1] = {
    /*   0 : VFNMADD123SD xmmreg,xmmreg,xmmrm64 [rvm:      vex.dds.128.66.0f38.w1 ad /r      ] FMA,FUTURE */
        /* 261(002 201) 001(ad) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMADD123SD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62346, 462},
};

static const struct itemplate instrux_VFNMADD231SS[2] = {
    /*   0 : VFNMADD231SS xmmreg,xmmreg,xmmrm32 [rvm:      vex.dds.128.66.0f38.w0 bd /r      ] FMA,FUTURE */
        /* 261(002 001) 001(bd) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMADD231SS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62353, 462},
    /*   1 : VFNMADD231SS xmmreg|mask|z,xmmreg,xmmrm32|er [rvm:t1s:  evex.nds.lig.66.0f38.w0 bd /r     ] AVX512,FUTURE */
        /* 241(f2 7d 08) 306 001(bd) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VFNMADD231SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+33417, 546},
};

static const struct itemplate instrux_VFNMADD231SD[2] = {
    /*   0 : VFNMADD231SD xmmreg,xmmreg,xmmrm64 [rvm:      vex.dds.128.66.0f38.w1 bd /r      ] FMA,FUTURE */
        /* 261(002 201) 001(bd) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMADD231SD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62360, 462},
    /*   1 : VFNMADD231SD xmmreg|mask|z,xmmreg,xmmrm64|er [rvm:t1s:  evex.nds.lig.66.0f38.w1 bd /r     ] AVX512,FUTURE */
        /* 241(f2 fd 08) 306 001(bd) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VFNMADD231SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+33408, 546},
};

static const struct itemplate instrux_VFNMADD321SS[1] = {
    /*   0 : VFNMADD321SS xmmreg,xmmreg,xmmrm32 [rvm:      vex.dds.128.66.0f38.w0 bd /r      ] FMA,FUTURE */
        /* 261(002 001) 001(bd) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMADD321SS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62353, 462},
};

static const struct itemplate instrux_VFNMADD321SD[1] = {
    /*   0 : VFNMADD321SD xmmreg,xmmreg,xmmrm64 [rvm:      vex.dds.128.66.0f38.w1 bd /r      ] FMA,FUTURE */
        /* 261(002 201) 001(bd) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMADD321SD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62360, 462},
};

static const struct itemplate instrux_VFNMSUB132SS[2] = {
    /*   0 : VFNMSUB132SS xmmreg,xmmreg,xmmrm32 [rvm:      vex.dds.128.66.0f38.w0 9f /r      ] FMA,FUTURE */
        /* 261(002 001) 001(9f) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMSUB132SS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62367, 462},
    /*   1 : VFNMSUB132SS xmmreg|mask|z,xmmreg,xmmrm32|er [rvm:t1s:  evex.nds.lig.66.0f38.w0 9f /r     ] AVX512,FUTURE */
        /* 241(f2 7d 08) 306 001(9f) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VFNMSUB132SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+33489, 546},
};

static const struct itemplate instrux_VFNMSUB132SD[2] = {
    /*   0 : VFNMSUB132SD xmmreg,xmmreg,xmmrm64 [rvm:      vex.dds.128.66.0f38.w1 9f /r      ] FMA,FUTURE */
        /* 261(002 201) 001(9f) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMSUB132SD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62374, 462},
    /*   1 : VFNMSUB132SD xmmreg|mask|z,xmmreg,xmmrm64|er [rvm:t1s:  evex.nds.lig.66.0f38.w1 9f /r     ] AVX512,FUTURE */
        /* 241(f2 fd 08) 306 001(9f) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VFNMSUB132SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+33480, 546},
};

static const struct itemplate instrux_VFNMSUB312SS[1] = {
    /*   0 : VFNMSUB312SS xmmreg,xmmreg,xmmrm32 [rvm:      vex.dds.128.66.0f38.w0 9f /r      ] FMA,FUTURE */
        /* 261(002 001) 001(9f) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMSUB312SS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62367, 462},
};

static const struct itemplate instrux_VFNMSUB312SD[1] = {
    /*   0 : VFNMSUB312SD xmmreg,xmmreg,xmmrm64 [rvm:      vex.dds.128.66.0f38.w1 9f /r      ] FMA,FUTURE */
        /* 261(002 201) 001(9f) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMSUB312SD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62374, 462},
};

static const struct itemplate instrux_VFNMSUB213SS[2] = {
    /*   0 : VFNMSUB213SS xmmreg,xmmreg,xmmrm32 [rvm:      vex.dds.128.66.0f38.w0 af /r      ] FMA,FUTURE */
        /* 261(002 001) 001(af) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMSUB213SS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62381, 462},
    /*   1 : VFNMSUB213SS xmmreg|mask|z,xmmreg,xmmrm32|er [rvm:t1s:  evex.nds.lig.66.0f38.w0 af /r     ] AVX512,FUTURE */
        /* 241(f2 7d 08) 306 001(af) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VFNMSUB213SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+33561, 546},
};

static const struct itemplate instrux_VFNMSUB213SD[2] = {
    /*   0 : VFNMSUB213SD xmmreg,xmmreg,xmmrm64 [rvm:      vex.dds.128.66.0f38.w1 af /r      ] FMA,FUTURE */
        /* 261(002 201) 001(af) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMSUB213SD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62388, 462},
    /*   1 : VFNMSUB213SD xmmreg|mask|z,xmmreg,xmmrm64|er [rvm:t1s:  evex.nds.lig.66.0f38.w1 af /r     ] AVX512,FUTURE */
        /* 241(f2 fd 08) 306 001(af) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VFNMSUB213SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+33552, 546},
};

static const struct itemplate instrux_VFNMSUB123SS[1] = {
    /*   0 : VFNMSUB123SS xmmreg,xmmreg,xmmrm32 [rvm:      vex.dds.128.66.0f38.w0 af /r      ] FMA,FUTURE */
        /* 261(002 001) 001(af) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMSUB123SS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62381, 462},
};

static const struct itemplate instrux_VFNMSUB123SD[1] = {
    /*   0 : VFNMSUB123SD xmmreg,xmmreg,xmmrm64 [rvm:      vex.dds.128.66.0f38.w1 af /r      ] FMA,FUTURE */
        /* 261(002 201) 001(af) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMSUB123SD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62388, 462},
};

static const struct itemplate instrux_VFNMSUB231SS[2] = {
    /*   0 : VFNMSUB231SS xmmreg,xmmreg,xmmrm32 [rvm:      vex.dds.128.66.0f38.w0 bf /r      ] FMA,FUTURE */
        /* 261(002 001) 001(bf) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMSUB231SS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62395, 462},
    /*   1 : VFNMSUB231SS xmmreg|mask|z,xmmreg,xmmrm32|er [rvm:t1s:  evex.nds.lig.66.0f38.w0 bf /r     ] AVX512,FUTURE */
        /* 241(f2 7d 08) 306 001(bf) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VFNMSUB231SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+33633, 546},
};

static const struct itemplate instrux_VFNMSUB231SD[2] = {
    /*   0 : VFNMSUB231SD xmmreg,xmmreg,xmmrm64 [rvm:      vex.dds.128.66.0f38.w1 bf /r      ] FMA,FUTURE */
        /* 261(002 201) 001(bf) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMSUB231SD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62402, 462},
    /*   1 : VFNMSUB231SD xmmreg|mask|z,xmmreg,xmmrm64|er [rvm:t1s:  evex.nds.lig.66.0f38.w1 bf /r     ] AVX512,FUTURE */
        /* 241(f2 fd 08) 306 001(bf) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VFNMSUB231SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+33624, 546},
};

static const struct itemplate instrux_VFNMSUB321SS[1] = {
    /*   0 : VFNMSUB321SS xmmreg,xmmreg,xmmrm32 [rvm:      vex.dds.128.66.0f38.w0 bf /r      ] FMA,FUTURE */
        /* 261(002 001) 001(bf) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMSUB321SS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62395, 462},
};

static const struct itemplate instrux_VFNMSUB321SD[1] = {
    /*   0 : VFNMSUB321SD xmmreg,xmmreg,xmmrm64 [rvm:      vex.dds.128.66.0f38.w1 bf /r      ] FMA,FUTURE */
        /* 261(002 201) 001(bf) 120 : NOAPX,VEX,FMA,FUTURE */
        {I_VFNMSUB321SD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62402, 462},
};

static const struct itemplate instrux_VCVTPH2PS[8] = {
    /*   0 : VCVTPH2PS ymmreg,xmmrm128 [rm:       vex.256.66.0f38.w0 13 /r          ] F16C,FUTURE */
        /* 270(002 005) 001(13) 110 : NOAPX,VEX,F16C,FUTURE */
        {I_VCVTPH2PS, 2, {YMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+62409, 463},
    /*   1 : VCVTPH2PS xmmreg,xmmrm64 [rm:       vex.128.66.0f38.w0 13 /r          ] F16C,FUTURE */
        /* 270(002 001) 001(13) 110 : NOAPX,VEX,F16C,FUTURE */
        {I_VCVTPH2PS, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+62416, 463},
    /*   2 : VCVTPH2PS xmmreg|mask|z,xmmrm64 [rm:hvm:   evex.128.66.0f38.w0 13 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 08) 314 001(13) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCVTPH2PS, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+31410, 544},
    /*   3 : VCVTPH2PS ymmreg|mask|z,xmmrm128 [rm:hvm:   evex.256.66.0f38.w0 13 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 28) 314 001(13) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCVTPH2PS, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+31419, 544},
    /*   4 : VCVTPH2PS zmmreg|mask|z,ymmrm256|sae [rm:hvm:   evex.512.66.0f38.w0 13 /r         ] AVX512,FUTURE */
        /* 250(f2 7d 48) 314 001(13) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VCVTPH2PS, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+31428, 545},
    /*   5 : VCVTPH2PS xmmreg|mask|z,xmmrm64 [rm:hvm:   evex.128.66.0f38.w0 13 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 08) 314 001(13) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCVTPH2PS, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+31410, 544},
    /*   6 : VCVTPH2PS ymmreg|mask|z,xmmrm128 [rm:hvm:   evex.256.66.0f38.w0 13 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 28) 314 001(13) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCVTPH2PS, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+31419, 544},
    /*   7 : VCVTPH2PS zmmreg|mask|z,ymmrm256|sae [rm:hvm:   evex.512.66.0f38.w0 13 /r         ] AVX512,FUTURE */
        /* 250(f2 7d 48) 314 001(13) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VCVTPH2PS, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+31428, 545},
};

static const struct itemplate instrux_VCVTPS2PH[14] = {
    /*   0 : VCVTPS2PH xmmrm128,ymmreg,imm8 [mri:      vex.256.66.0f3a.w0 1d /r ib       ] F16C,FUTURE */
        /* 270(003 005) 001(1d) 101 022 : NOAPX,VEX,F16C,FUTURE */
        {I_VCVTPS2PH, 3, {RM_XMM|BITS128|RN_L16,YMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52549, 463},
    /*   1 : VCVTPS2PH xmmrm64,xmmreg,imm8 [mri:      vex.128.66.0f3a.w0 1d /r ib       ] F16C,FUTURE */
        /* 270(003 001) 001(1d) 101 022 : NOAPX,VEX,F16C,FUTURE */
        {I_VCVTPS2PH, 3, {RM_XMM|BITS64|RN_L16,XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+52557, 463},
    /*   2 : VCVTPS2PH xmmreg|mask|z,xmmreg,imm8 [mri:hvm:  evex.128.66.0f3a.w0 1d /r ib      ] AVX512,AVX512VL,FUTURE */
        /* 250(f3 7d 08) 314 001(1d) 101 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCVTPS2PH, 3, {XMMREG,XMMREG,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18333, 544},
    /*   3 : VCVTPS2PH xmmreg|mask|z,ymmreg,imm8 [mri:hvm:  evex.256.66.0f3a.w0 1d /r ib      ] AVX512,AVX512VL,FUTURE */
        /* 250(f3 7d 28) 314 001(1d) 101 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCVTPS2PH, 3, {XMMREG,YMMREG,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18343, 544},
    /*   4 : VCVTPS2PH ymmreg|mask|z,zmmreg|sae,imm8 [mri:hvm:  evex.512.66.0f3a.w0 1d /r ib      ] AVX512,FUTURE */
        /* 250(f3 7d 48) 314 001(1d) 101 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VCVTPS2PH, 3, {YMMREG,ZMMREG,IMM_NORMAL|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+18353, 545},
    /*   5 : VCVTPS2PH mem64|mask,xmmreg,imm8 [mri:hvm:  evex.128.66.0f3a.w0 1d /r ib      ] AVX512,AVX512VL,FUTURE */
        /* 250(f3 7d 08) 314 001(1d) 101 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCVTPS2PH, 3, {MEMORY|BITS64,XMMREG,IMM_NORMAL|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+18333, 544},
    /*   6 : VCVTPS2PH mem128|mask,ymmreg,imm8 [mri:hvm:  evex.256.66.0f3a.w0 1d /r ib      ] AVX512,AVX512VL,FUTURE */
        /* 250(f3 7d 28) 314 001(1d) 101 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCVTPS2PH, 3, {MEMORY|BITS128,YMMREG,IMM_NORMAL|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+18343, 544},
    /*   7 : VCVTPS2PH mem256|mask,zmmreg|sae,imm8 [mri:hvm:  evex.512.66.0f3a.w0 1d /r ib      ] AVX512,FUTURE */
        /* 250(f3 7d 48) 314 001(1d) 101 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VCVTPS2PH, 3, {MEMORY|BITS256,ZMMREG,IMM_NORMAL|BITS8,0,0}, {MASK,SAE,0,0,0}, nasm_bytecodes+18353, 545},
    /*   8 : VCVTPS2PH xmmreg|mask|z,xmmreg,imm8 [mri:hvm:  evex.128.66.0f3a.w0 1d /r ib      ] AVX512,AVX512VL,FUTURE */
        /* 250(f3 7d 08) 314 001(1d) 101 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCVTPS2PH, 3, {XMMREG,XMMREG,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18333, 544},
    /*   9 : VCVTPS2PH mem64|mask,xmmreg,imm8 [mri:hvm:  evex.128.66.0f3a.w0 1d /r ib      ] AVX512,AVX512VL,FUTURE */
        /* 250(f3 7d 08) 314 001(1d) 101 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCVTPS2PH, 3, {MEMORY|BITS64,XMMREG,IMM_NORMAL|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+18333, 544},
    /*  10 : VCVTPS2PH xmmreg|mask|z,ymmreg,imm8 [mri:hvm:  evex.256.66.0f3a.w0 1d /r ib      ] AVX512,AVX512VL,FUTURE */
        /* 250(f3 7d 28) 314 001(1d) 101 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCVTPS2PH, 3, {XMMREG,YMMREG,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18343, 544},
    /*  11 : VCVTPS2PH mem128|mask,ymmreg,imm8 [mri:hvm:  evex.256.66.0f3a.w0 1d /r ib      ] AVX512,AVX512VL,FUTURE */
        /* 250(f3 7d 28) 314 001(1d) 101 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCVTPS2PH, 3, {MEMORY|BITS128,YMMREG,IMM_NORMAL|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+18343, 544},
    /*  12 : VCVTPS2PH ymmreg|mask|z,zmmreg|sae,imm8 [mri:hvm:  evex.512.66.0f3a.w0 1d /r ib      ] AVX512,FUTURE */
        /* 250(f3 7d 48) 314 001(1d) 101 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VCVTPS2PH, 3, {YMMREG,ZMMREG,IMM_NORMAL|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+18353, 545},
    /*  13 : VCVTPS2PH mem256|mask,zmmreg|sae,imm8 [mri:hvm:  evex.512.66.0f3a.w0 1d /r ib      ] AVX512,FUTURE */
        /* 250(f3 7d 48) 314 001(1d) 101 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VCVTPS2PH, 3, {MEMORY|BITS256,ZMMREG,IMM_NORMAL|BITS8,0,0}, {MASK,SAE,0,0,0}, nasm_bytecodes+18353, 545},
};

static const struct itemplate instrux_XSTORE[1] = {
    /*   0 : XSTORE void [          0f a7 c0                          ] PENT,CYRIX */
        /* 355 002(a7 c0) : PENT,CYRIX */
        {I_XSTORE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72363, 464},
};

static const struct itemplate instrux_XCRYPTECB[1] = {
    /*   0 : XCRYPTECB void [          f3 0f a7 c8                       ] PENT,CYRIX */
        /* 333 355 002(a7 c8) : PENT,CYRIX */
        {I_XCRYPTECB, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+69824, 464},
};

static const struct itemplate instrux_XCRYPTCBC[1] = {
    /*   0 : XCRYPTCBC void [          f3 0f a7 d0                       ] PENT,CYRIX */
        /* 333 355 002(a7 d0) : PENT,CYRIX */
        {I_XCRYPTCBC, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+69830, 464},
};

static const struct itemplate instrux_XCRYPTCTR[1] = {
    /*   0 : XCRYPTCTR void [          f3 0f a7 d8                       ] PENT,CYRIX */
        /* 333 355 002(a7 d8) : PENT,CYRIX */
        {I_XCRYPTCTR, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+69836, 464},
};

static const struct itemplate instrux_XCRYPTCFB[1] = {
    /*   0 : XCRYPTCFB void [          f3 0f a7 e0                       ] PENT,CYRIX */
        /* 333 355 002(a7 e0) : PENT,CYRIX */
        {I_XCRYPTCFB, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+69842, 464},
};

static const struct itemplate instrux_XCRYPTOFB[1] = {
    /*   0 : XCRYPTOFB void [          f3 0f a7 e8                       ] PENT,CYRIX */
        /* 333 355 002(a7 e8) : PENT,CYRIX */
        {I_XCRYPTOFB, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+69848, 464},
};

static const struct itemplate instrux_MONTMUL[1] = {
    /*   0 : MONTMUL void [          f3 0f a6 c0                       ] PENT,CYRIX */
        /* 333 355 002(a6 c0) : PENT,CYRIX */
        {I_MONTMUL, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+69854, 464},
};

static const struct itemplate instrux_XSHA1[1] = {
    /*   0 : XSHA1 void [          f3 0f a6 c8                       ] PENT,CYRIX */
        /* 333 355 002(a6 c8) : PENT,CYRIX */
        {I_XSHA1, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+69860, 464},
};

static const struct itemplate instrux_XSHA256[1] = {
    /*   0 : XSHA256 void [          f3 0f a6 d0                       ] PENT,CYRIX */
        /* 333 355 002(a6 d0) : PENT,CYRIX */
        {I_XSHA256, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+69866, 464},
};

static const struct itemplate instrux_LLWPCB[2] = {
    /*   0 : LLWPCB reg32 [m:        xop.m9.w0.l0.p0 12 /0             ] 386,AMD */
        /* 270(111 000) 001(12) 200 : NOAPX,VEX,386,AMD */
        {I_LLWPCB, 1, {REG_GPR|BITS32|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+62423, 465},
    /*   1 : LLWPCB reg64 [m:        xop.m9.w1.l0.p0 12 /0             ] LONG,PROT,X86_64,AMD */
        /* 270(111 200) 001(12) 200 : NOAPX,LONG,VEX,PROT,X86_64,AMD */
        {I_LLWPCB, 1, {REG_GPR|BITS64|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+62430, 466},
};

static const struct itemplate instrux_SLWPCB[2] = {
    /*   0 : SLWPCB reg32 [m:        xop.m9.w0.l0.p0 12 /1             ] 386,AMD */
        /* 270(111 000) 001(12) 201 : NOAPX,VEX,386,AMD */
        {I_SLWPCB, 1, {REG_GPR|BITS32|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+62437, 465},
    /*   1 : SLWPCB reg64 [m:        xop.m9.w1.l0.p0 12 /1             ] LONG,PROT,X86_64,AMD */
        /* 270(111 200) 001(12) 201 : NOAPX,LONG,VEX,PROT,X86_64,AMD */
        {I_SLWPCB, 1, {REG_GPR|BITS64|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+62444, 466},
};

static const struct itemplate instrux_LWPVAL[2] = {
    /*   0 : LWPVAL reg32,rm32,imm32 [vmi:      xop.m10.w0.ndd.l0.p0 12 /1 id     ] 386,AMD */
        /* 260(112 000) 001(12) 211 042 : NOAPX,VEX,386,AMD */
        {I_LWPVAL, 3, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+52565, 465},
    /*   1 : LWPVAL reg64,rm32,imm32 [vmi:      xop.m10.w1.ndd.l0.p0 12 /1 id     ] LONG,PROT,X86_64,AMD */
        /* 260(112 200) 001(12) 211 042 : NOAPX,LONG,VEX,PROT,X86_64,AMD */
        {I_LWPVAL, 3, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS32|RN_L16,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+52573, 466},
};

static const struct itemplate instrux_LWPINS[2] = {
    /*   0 : LWPINS reg32,rm32,imm32 [vmi:      xop.m10.w0.ndd.l0.p0 12 /0 id     ] 386,AMD */
        /* 260(112 000) 001(12) 210 042 : NOAPX,VEX,386,AMD */
        {I_LWPINS, 3, {REG_GPR|BITS32|RN_L16,RM_GPR|BITS32|RN_L16,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+52581, 465},
    /*   1 : LWPINS reg64,rm32,imm32 [vmi:      xop.m10.w1.ndd.l0.p0 12 /0 id     ] LONG,PROT,X86_64,AMD */
        /* 260(112 200) 001(12) 210 042 : NOAPX,LONG,VEX,PROT,X86_64,AMD */
        {I_LWPINS, 3, {REG_GPR|BITS64|RN_L16,RM_GPR|BITS32|RN_L16,IMM_NORMAL|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+52589, 466},
};

static const struct itemplate instrux_VFMADDPD[8] = {
    /*   0 : VFMADDPD xmmreg,xmmreg*,xmmrm128,xmmreg [rvms:     vex.m3.w0.nds.l0.p1 69 /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 001) 001(69) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMADDPD, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+52597, 467},
    /*   1 : VFMADDPD xmmreg,xmmrm128,xmmreg [r+vms:     vex.m3.w0.nds.l0.p1 69 /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 001) 001(69) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMADDPD, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+52605, 467},
    /*   2 : VFMADDPD ymmreg,ymmreg*,ymmrm256,ymmreg [rvms:     vex.m3.w0.nds.l1.p1 69 /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 005) 001(69) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMADDPD, 4, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,YMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+52613, 467},
    /*   3 : VFMADDPD ymmreg,ymmrm256,ymmreg [r+vms:     vex.m3.w0.nds.l1.p1 69 /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 005) 001(69) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMADDPD, 3, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,YMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+52621, 467},
    /*   4 : VFMADDPD xmmreg,xmmreg*,xmmreg,xmmrm128 [rvsm:     vex.m3.w1.nds.l0.p1 69 /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 201) 001(69) 130 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMADDPD, 4, {XMMREG|RN_L16,XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+52629, 467},
    /*   5 : VFMADDPD xmmreg,xmmreg,xmmrm128 [r+vsm:     vex.m3.w1.nds.l0.p1 69 /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 201) 001(69) 120 175 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMADDPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+52637, 467},
    /*   6 : VFMADDPD ymmreg,ymmreg*,ymmreg,ymmrm256 [rvsm:     vex.m3.w1.nds.l1.p1 69 /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 205) 001(69) 130 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMADDPD, 4, {YMMREG|RN_L16,YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+52645, 467},
    /*   7 : VFMADDPD ymmreg,ymmreg,ymmrm256 [r+vsm:     vex.m3.w1.nds.l1.p1 69 /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 205) 001(69) 120 175 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMADDPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+52653, 467},
};

static const struct itemplate instrux_VFMADDPS[8] = {
    /*   0 : VFMADDPS xmmreg,xmmreg*,xmmrm128,xmmreg [rvms:     vex.m3.w0.nds.l0.p1 68 /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 001) 001(68) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMADDPS, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+52661, 467},
    /*   1 : VFMADDPS xmmreg,xmmrm128,xmmreg [r+vms:     vex.m3.w0.nds.l0.p1 68 /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 001) 001(68) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMADDPS, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+52669, 467},
    /*   2 : VFMADDPS ymmreg,ymmreg*,ymmrm256,ymmreg [rvms:     vex.m3.w0.nds.l1.p1 68 /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 005) 001(68) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMADDPS, 4, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,YMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+52677, 467},
    /*   3 : VFMADDPS ymmreg,ymmrm256,ymmreg [r+vms:     vex.m3.w0.nds.l1.p1 68 /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 005) 001(68) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMADDPS, 3, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,YMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+52685, 467},
    /*   4 : VFMADDPS xmmreg,xmmreg*,xmmreg,xmmrm128 [rvsm:     vex.m3.w1.nds.l0.p1 68 /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 201) 001(68) 130 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMADDPS, 4, {XMMREG|RN_L16,XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+52693, 467},
    /*   5 : VFMADDPS xmmreg,xmmreg,xmmrm128 [r+vsm:     vex.m3.w1.nds.l0.p1 68 /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 201) 001(68) 120 175 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMADDPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+52701, 467},
    /*   6 : VFMADDPS ymmreg,ymmreg*,ymmreg,ymmrm256 [rvsm:     vex.m3.w1.nds.l1.p1 68 /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 205) 001(68) 130 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMADDPS, 4, {YMMREG|RN_L16,YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+52709, 467},
    /*   7 : VFMADDPS ymmreg,ymmreg,ymmrm256 [r+vsm:     vex.m3.w1.nds.l1.p1 68 /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 205) 001(68) 120 175 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMADDPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+52717, 467},
};

static const struct itemplate instrux_VFMADDSD[4] = {
    /*   0 : VFMADDSD xmmreg,xmmreg*,xmmrm64,xmmreg [rvms:     vex.m3.w0.nds.l0.p1 6b /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 001) 001(6b) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMADDSD, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,XMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+52725, 467},
    /*   1 : VFMADDSD xmmreg,xmmrm64,xmmreg [r+vms:     vex.m3.w0.nds.l0.p1 6b /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 001) 001(6b) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMADDSD, 3, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+52733, 467},
    /*   2 : VFMADDSD xmmreg,xmmreg*,xmmreg,xmmrm64 [rvsm:     vex.m3.w1.nds.l0.p1 6b /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 201) 001(6b) 130 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMADDSD, 4, {XMMREG|RN_L16,XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+52741, 467},
    /*   3 : VFMADDSD xmmreg,xmmreg,xmmrm64 [r+vsm:     vex.m3.w1.nds.l0.p1 6b /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 201) 001(6b) 120 175 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMADDSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+52749, 467},
};

static const struct itemplate instrux_VFMADDSS[4] = {
    /*   0 : VFMADDSS xmmreg,xmmreg*,xmmrm32,xmmreg [rvms:     vex.m3.w0.nds.l0.p1 6a /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 001) 001(6a) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMADDSS, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,XMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+52757, 467},
    /*   1 : VFMADDSS xmmreg,xmmrm32,xmmreg [r+vms:     vex.m3.w0.nds.l0.p1 6a /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 001) 001(6a) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMADDSS, 3, {XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+52765, 467},
    /*   2 : VFMADDSS xmmreg,xmmreg*,xmmreg,xmmrm32 [rvsm:     vex.m3.w1.nds.l0.p1 6a /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 201) 001(6a) 130 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMADDSS, 4, {XMMREG|RN_L16,XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+52773, 467},
    /*   3 : VFMADDSS xmmreg,xmmreg,xmmrm32 [r+vsm:     vex.m3.w1.nds.l0.p1 6a /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 201) 001(6a) 120 175 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMADDSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+52781, 467},
};

static const struct itemplate instrux_VFMADDSUBPD[8] = {
    /*   0 : VFMADDSUBPD xmmreg,xmmreg*,xmmrm128,xmmreg [rvms:     vex.m3.w0.nds.l0.p1 5d /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 001) 001(5d) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMADDSUBPD, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+52789, 467},
    /*   1 : VFMADDSUBPD xmmreg,xmmrm128,xmmreg [r+vms:     vex.m3.w0.nds.l0.p1 5d /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 001) 001(5d) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMADDSUBPD, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+52797, 467},
    /*   2 : VFMADDSUBPD ymmreg,ymmreg*,ymmrm256,ymmreg [rvms:     vex.m3.w0.nds.l1.p1 5d /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 005) 001(5d) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMADDSUBPD, 4, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,YMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+52805, 467},
    /*   3 : VFMADDSUBPD ymmreg,ymmrm256,ymmreg [r+vms:     vex.m3.w0.nds.l1.p1 5d /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 005) 001(5d) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMADDSUBPD, 3, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,YMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+52813, 467},
    /*   4 : VFMADDSUBPD xmmreg,xmmreg*,xmmreg,xmmrm128 [rvsm:     vex.m3.w1.nds.l0.p1 5d /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 201) 001(5d) 130 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMADDSUBPD, 4, {XMMREG|RN_L16,XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+52821, 467},
    /*   5 : VFMADDSUBPD xmmreg,xmmreg,xmmrm128 [r+vsm:     vex.m3.w1.nds.l0.p1 5d /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 201) 001(5d) 120 175 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMADDSUBPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+52829, 467},
    /*   6 : VFMADDSUBPD ymmreg,ymmreg*,ymmreg,ymmrm256 [rvsm:     vex.m3.w1.nds.l1.p1 5d /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 205) 001(5d) 130 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMADDSUBPD, 4, {YMMREG|RN_L16,YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+52837, 467},
    /*   7 : VFMADDSUBPD ymmreg,ymmreg,ymmrm256 [r+vsm:     vex.m3.w1.nds.l1.p1 5d /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 205) 001(5d) 120 175 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMADDSUBPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+52845, 467},
};

static const struct itemplate instrux_VFMADDSUBPS[8] = {
    /*   0 : VFMADDSUBPS xmmreg,xmmreg*,xmmrm128,xmmreg [rvms:     vex.m3.w0.nds.l0.p1 5c /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 001) 001(5c) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMADDSUBPS, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+52853, 467},
    /*   1 : VFMADDSUBPS xmmreg,xmmrm128,xmmreg [r+vms:     vex.m3.w0.nds.l0.p1 5c /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 001) 001(5c) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMADDSUBPS, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+52861, 467},
    /*   2 : VFMADDSUBPS ymmreg,ymmreg*,ymmrm256,ymmreg [rvms:     vex.m3.w0.nds.l1.p1 5c /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 005) 001(5c) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMADDSUBPS, 4, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,YMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+52869, 467},
    /*   3 : VFMADDSUBPS ymmreg,ymmrm256,ymmreg [r+vms:     vex.m3.w0.nds.l1.p1 5c /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 005) 001(5c) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMADDSUBPS, 3, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,YMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+52877, 467},
    /*   4 : VFMADDSUBPS xmmreg,xmmreg*,xmmreg,xmmrm128 [rvsm:     vex.m3.w1.nds.l0.p1 5c /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 201) 001(5c) 130 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMADDSUBPS, 4, {XMMREG|RN_L16,XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+52885, 467},
    /*   5 : VFMADDSUBPS xmmreg,xmmreg,xmmrm128 [r+vsm:     vex.m3.w1.nds.l0.p1 5c /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 201) 001(5c) 120 175 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMADDSUBPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+52893, 467},
    /*   6 : VFMADDSUBPS ymmreg,ymmreg*,ymmreg,ymmrm256 [rvsm:     vex.m3.w1.nds.l1.p1 5c /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 205) 001(5c) 130 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMADDSUBPS, 4, {YMMREG|RN_L16,YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+52901, 467},
    /*   7 : VFMADDSUBPS ymmreg,ymmreg,ymmrm256 [r+vsm:     vex.m3.w1.nds.l1.p1 5c /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 205) 001(5c) 120 175 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMADDSUBPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+52909, 467},
};

static const struct itemplate instrux_VFMSUBADDPD[8] = {
    /*   0 : VFMSUBADDPD xmmreg,xmmreg*,xmmrm128,xmmreg [rvms:     vex.m3.w0.nds.l0.p1 5f /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 001) 001(5f) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMSUBADDPD, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+52917, 467},
    /*   1 : VFMSUBADDPD xmmreg,xmmrm128,xmmreg [r+vms:     vex.m3.w0.nds.l0.p1 5f /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 001) 001(5f) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMSUBADDPD, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+52925, 467},
    /*   2 : VFMSUBADDPD ymmreg,ymmreg*,ymmrm256,ymmreg [rvms:     vex.m3.w0.nds.l1.p1 5f /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 005) 001(5f) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMSUBADDPD, 4, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,YMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+52933, 467},
    /*   3 : VFMSUBADDPD ymmreg,ymmrm256,ymmreg [r+vms:     vex.m3.w0.nds.l1.p1 5f /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 005) 001(5f) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMSUBADDPD, 3, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,YMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+52941, 467},
    /*   4 : VFMSUBADDPD xmmreg,xmmreg*,xmmreg,xmmrm128 [rvsm:     vex.m3.w1.nds.l0.p1 5f /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 201) 001(5f) 130 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMSUBADDPD, 4, {XMMREG|RN_L16,XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+52949, 467},
    /*   5 : VFMSUBADDPD xmmreg,xmmreg,xmmrm128 [r+vsm:     vex.m3.w1.nds.l0.p1 5f /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 201) 001(5f) 120 175 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMSUBADDPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+52957, 467},
    /*   6 : VFMSUBADDPD ymmreg,ymmreg*,ymmreg,ymmrm256 [rvsm:     vex.m3.w1.nds.l1.p1 5f /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 205) 001(5f) 130 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMSUBADDPD, 4, {YMMREG|RN_L16,YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+52965, 467},
    /*   7 : VFMSUBADDPD ymmreg,ymmreg,ymmrm256 [r+vsm:     vex.m3.w1.nds.l1.p1 5f /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 205) 001(5f) 120 175 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMSUBADDPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+52973, 467},
};

static const struct itemplate instrux_VFMSUBADDPS[8] = {
    /*   0 : VFMSUBADDPS xmmreg,xmmreg*,xmmrm128,xmmreg [rvms:     vex.m3.w0.nds.l0.p1 5e /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 001) 001(5e) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMSUBADDPS, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+52981, 467},
    /*   1 : VFMSUBADDPS xmmreg,xmmrm128,xmmreg [r+vms:     vex.m3.w0.nds.l0.p1 5e /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 001) 001(5e) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMSUBADDPS, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+52989, 467},
    /*   2 : VFMSUBADDPS ymmreg,ymmreg*,ymmrm256,ymmreg [rvms:     vex.m3.w0.nds.l1.p1 5e /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 005) 001(5e) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMSUBADDPS, 4, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,YMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+52997, 467},
    /*   3 : VFMSUBADDPS ymmreg,ymmrm256,ymmreg [r+vms:     vex.m3.w0.nds.l1.p1 5e /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 005) 001(5e) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMSUBADDPS, 3, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,YMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53005, 467},
    /*   4 : VFMSUBADDPS xmmreg,xmmreg*,xmmreg,xmmrm128 [rvsm:     vex.m3.w1.nds.l0.p1 5e /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 201) 001(5e) 130 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMSUBADDPS, 4, {XMMREG|RN_L16,XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53013, 467},
    /*   5 : VFMSUBADDPS xmmreg,xmmreg,xmmrm128 [r+vsm:     vex.m3.w1.nds.l0.p1 5e /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 201) 001(5e) 120 175 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMSUBADDPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53021, 467},
    /*   6 : VFMSUBADDPS ymmreg,ymmreg*,ymmreg,ymmrm256 [rvsm:     vex.m3.w1.nds.l1.p1 5e /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 205) 001(5e) 130 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMSUBADDPS, 4, {YMMREG|RN_L16,YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53029, 467},
    /*   7 : VFMSUBADDPS ymmreg,ymmreg,ymmrm256 [r+vsm:     vex.m3.w1.nds.l1.p1 5e /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 205) 001(5e) 120 175 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMSUBADDPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53037, 467},
};

static const struct itemplate instrux_VFMSUBPD[8] = {
    /*   0 : VFMSUBPD xmmreg,xmmreg*,xmmrm128,xmmreg [rvms:     vex.m3.w0.nds.l0.p1 6d /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 001) 001(6d) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMSUBPD, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53045, 467},
    /*   1 : VFMSUBPD xmmreg,xmmrm128,xmmreg [r+vms:     vex.m3.w0.nds.l0.p1 6d /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 001) 001(6d) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMSUBPD, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53053, 467},
    /*   2 : VFMSUBPD ymmreg,ymmreg*,ymmrm256,ymmreg [rvms:     vex.m3.w0.nds.l1.p1 6d /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 005) 001(6d) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMSUBPD, 4, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,YMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53061, 467},
    /*   3 : VFMSUBPD ymmreg,ymmrm256,ymmreg [r+vms:     vex.m3.w0.nds.l1.p1 6d /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 005) 001(6d) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMSUBPD, 3, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,YMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53069, 467},
    /*   4 : VFMSUBPD xmmreg,xmmreg*,xmmreg,xmmrm128 [rvsm:     vex.m3.w1.nds.l0.p1 6d /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 201) 001(6d) 130 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMSUBPD, 4, {XMMREG|RN_L16,XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53077, 467},
    /*   5 : VFMSUBPD xmmreg,xmmreg,xmmrm128 [r+vsm:     vex.m3.w1.nds.l0.p1 6d /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 201) 001(6d) 120 175 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMSUBPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53085, 467},
    /*   6 : VFMSUBPD ymmreg,ymmreg*,ymmreg,ymmrm256 [rvsm:     vex.m3.w1.nds.l1.p1 6d /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 205) 001(6d) 130 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMSUBPD, 4, {YMMREG|RN_L16,YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53093, 467},
    /*   7 : VFMSUBPD ymmreg,ymmreg,ymmrm256 [r+vsm:     vex.m3.w1.nds.l1.p1 6d /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 205) 001(6d) 120 175 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMSUBPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53101, 467},
};

static const struct itemplate instrux_VFMSUBPS[8] = {
    /*   0 : VFMSUBPS xmmreg,xmmreg*,xmmrm128,xmmreg [rvms:     vex.m3.w0.nds.l0.p1 6c /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 001) 001(6c) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMSUBPS, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53109, 467},
    /*   1 : VFMSUBPS xmmreg,xmmrm128,xmmreg [r+vms:     vex.m3.w0.nds.l0.p1 6c /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 001) 001(6c) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMSUBPS, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53117, 467},
    /*   2 : VFMSUBPS ymmreg,ymmreg*,ymmrm256,ymmreg [rvms:     vex.m3.w0.nds.l1.p1 6c /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 005) 001(6c) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMSUBPS, 4, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,YMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53125, 467},
    /*   3 : VFMSUBPS ymmreg,ymmrm256,ymmreg [r+vms:     vex.m3.w0.nds.l1.p1 6c /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 005) 001(6c) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMSUBPS, 3, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,YMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53133, 467},
    /*   4 : VFMSUBPS xmmreg,xmmreg*,xmmreg,xmmrm128 [rvsm:     vex.m3.w1.nds.l0.p1 6c /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 201) 001(6c) 130 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMSUBPS, 4, {XMMREG|RN_L16,XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53141, 467},
    /*   5 : VFMSUBPS xmmreg,xmmreg,xmmrm128 [r+vsm:     vex.m3.w1.nds.l0.p1 6c /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 201) 001(6c) 120 175 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMSUBPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53149, 467},
    /*   6 : VFMSUBPS ymmreg,ymmreg*,ymmreg,ymmrm256 [rvsm:     vex.m3.w1.nds.l1.p1 6c /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 205) 001(6c) 130 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMSUBPS, 4, {YMMREG|RN_L16,YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53157, 467},
    /*   7 : VFMSUBPS ymmreg,ymmreg,ymmrm256 [r+vsm:     vex.m3.w1.nds.l1.p1 6c /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 205) 001(6c) 120 175 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMSUBPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53165, 467},
};

static const struct itemplate instrux_VFMSUBSD[4] = {
    /*   0 : VFMSUBSD xmmreg,xmmreg*,xmmrm64,xmmreg [rvms:     vex.m3.w0.nds.l0.p1 6f /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 001) 001(6f) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMSUBSD, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,XMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53173, 467},
    /*   1 : VFMSUBSD xmmreg,xmmrm64,xmmreg [r+vms:     vex.m3.w0.nds.l0.p1 6f /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 001) 001(6f) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMSUBSD, 3, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53181, 467},
    /*   2 : VFMSUBSD xmmreg,xmmreg*,xmmreg,xmmrm64 [rvsm:     vex.m3.w1.nds.l0.p1 6f /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 201) 001(6f) 130 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMSUBSD, 4, {XMMREG|RN_L16,XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53189, 467},
    /*   3 : VFMSUBSD xmmreg,xmmreg,xmmrm64 [r+vsm:     vex.m3.w1.nds.l0.p1 6f /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 201) 001(6f) 120 175 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMSUBSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53197, 467},
};

static const struct itemplate instrux_VFMSUBSS[4] = {
    /*   0 : VFMSUBSS xmmreg,xmmreg*,xmmrm32,xmmreg [rvms:     vex.m3.w0.nds.l0.p1 6e /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 001) 001(6e) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMSUBSS, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,XMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53205, 467},
    /*   1 : VFMSUBSS xmmreg,xmmrm32,xmmreg [r+vms:     vex.m3.w0.nds.l0.p1 6e /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 001) 001(6e) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMSUBSS, 3, {XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53213, 467},
    /*   2 : VFMSUBSS xmmreg,xmmreg*,xmmreg,xmmrm32 [rvsm:     vex.m3.w1.nds.l0.p1 6e /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 201) 001(6e) 130 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMSUBSS, 4, {XMMREG|RN_L16,XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53221, 467},
    /*   3 : VFMSUBSS xmmreg,xmmreg,xmmrm32 [r+vsm:     vex.m3.w1.nds.l0.p1 6e /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 201) 001(6e) 120 175 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFMSUBSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53229, 467},
};

static const struct itemplate instrux_VFNMADDPD[8] = {
    /*   0 : VFNMADDPD xmmreg,xmmreg*,xmmrm128,xmmreg [rvms:     vex.m3.w0.nds.l0.p1 79 /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 001) 001(79) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMADDPD, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53237, 467},
    /*   1 : VFNMADDPD xmmreg,xmmrm128,xmmreg [r+vms:     vex.m3.w0.nds.l0.p1 79 /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 001) 001(79) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMADDPD, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53245, 467},
    /*   2 : VFNMADDPD ymmreg,ymmreg*,ymmrm256,ymmreg [rvms:     vex.m3.w0.nds.l1.p1 79 /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 005) 001(79) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMADDPD, 4, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,YMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53253, 467},
    /*   3 : VFNMADDPD ymmreg,ymmrm256,ymmreg [r+vms:     vex.m3.w0.nds.l1.p1 79 /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 005) 001(79) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMADDPD, 3, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,YMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53261, 467},
    /*   4 : VFNMADDPD xmmreg,xmmreg*,xmmreg,xmmrm128 [rvsm:     vex.m3.w1.nds.l0.p1 79 /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 201) 001(79) 130 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMADDPD, 4, {XMMREG|RN_L16,XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53269, 467},
    /*   5 : VFNMADDPD xmmreg,xmmreg,xmmrm128 [r+vsm:     vex.m3.w1.nds.l0.p1 79 /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 201) 001(79) 120 175 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMADDPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53277, 467},
    /*   6 : VFNMADDPD ymmreg,ymmreg*,ymmreg,ymmrm256 [rvsm:     vex.m3.w1.nds.l1.p1 79 /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 205) 001(79) 130 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMADDPD, 4, {YMMREG|RN_L16,YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53285, 467},
    /*   7 : VFNMADDPD ymmreg,ymmreg,ymmrm256 [r+vsm:     vex.m3.w1.nds.l1.p1 79 /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 205) 001(79) 120 175 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMADDPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53293, 467},
};

static const struct itemplate instrux_VFNMADDPS[8] = {
    /*   0 : VFNMADDPS xmmreg,xmmreg*,xmmrm128,xmmreg [rvms:     vex.m3.w0.nds.l0.p1 78 /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 001) 001(78) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMADDPS, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53301, 467},
    /*   1 : VFNMADDPS xmmreg,xmmrm128,xmmreg [r+vms:     vex.m3.w0.nds.l0.p1 78 /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 001) 001(78) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMADDPS, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53309, 467},
    /*   2 : VFNMADDPS ymmreg,ymmreg*,ymmrm256,ymmreg [rvms:     vex.m3.w0.nds.l1.p1 78 /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 005) 001(78) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMADDPS, 4, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,YMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53317, 467},
    /*   3 : VFNMADDPS ymmreg,ymmrm256,ymmreg [r+vms:     vex.m3.w0.nds.l1.p1 78 /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 005) 001(78) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMADDPS, 3, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,YMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53325, 467},
    /*   4 : VFNMADDPS xmmreg,xmmreg*,xmmreg,xmmrm128 [rvsm:     vex.m3.w1.nds.l0.p1 78 /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 201) 001(78) 130 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMADDPS, 4, {XMMREG|RN_L16,XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53333, 467},
    /*   5 : VFNMADDPS xmmreg,xmmreg,xmmrm128 [r+vsm:     vex.m3.w1.nds.l0.p1 78 /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 201) 001(78) 120 175 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMADDPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53341, 467},
    /*   6 : VFNMADDPS ymmreg,ymmreg*,ymmreg,ymmrm256 [rvsm:     vex.m3.w1.nds.l1.p1 78 /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 205) 001(78) 130 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMADDPS, 4, {YMMREG|RN_L16,YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53349, 467},
    /*   7 : VFNMADDPS ymmreg,ymmreg,ymmrm256 [r+vsm:     vex.m3.w1.nds.l1.p1 78 /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 205) 001(78) 120 175 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMADDPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53357, 467},
};

static const struct itemplate instrux_VFNMADDSD[4] = {
    /*   0 : VFNMADDSD xmmreg,xmmreg*,xmmrm64,xmmreg [rvms:     vex.m3.w0.nds.l0.p1 7b /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 001) 001(7b) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMADDSD, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,XMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53365, 467},
    /*   1 : VFNMADDSD xmmreg,xmmrm64,xmmreg [r+vms:     vex.m3.w0.nds.l0.p1 7b /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 001) 001(7b) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMADDSD, 3, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53373, 467},
    /*   2 : VFNMADDSD xmmreg,xmmreg*,xmmreg,xmmrm64 [rvsm:     vex.m3.w1.nds.l0.p1 7b /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 201) 001(7b) 130 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMADDSD, 4, {XMMREG|RN_L16,XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53381, 467},
    /*   3 : VFNMADDSD xmmreg,xmmreg,xmmrm64 [r+vsm:     vex.m3.w1.nds.l0.p1 7b /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 201) 001(7b) 120 175 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMADDSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53389, 467},
};

static const struct itemplate instrux_VFNMADDSS[4] = {
    /*   0 : VFNMADDSS xmmreg,xmmreg*,xmmrm32,xmmreg [rvms:     vex.m3.w0.nds.l0.p1 7a /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 001) 001(7a) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMADDSS, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,XMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53397, 467},
    /*   1 : VFNMADDSS xmmreg,xmmrm32,xmmreg [r+vms:     vex.m3.w0.nds.l0.p1 7a /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 001) 001(7a) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMADDSS, 3, {XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53405, 467},
    /*   2 : VFNMADDSS xmmreg,xmmreg*,xmmreg,xmmrm32 [rvsm:     vex.m3.w1.nds.l0.p1 7a /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 201) 001(7a) 130 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMADDSS, 4, {XMMREG|RN_L16,XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53413, 467},
    /*   3 : VFNMADDSS xmmreg,xmmreg,xmmrm32 [r+vsm:     vex.m3.w1.nds.l0.p1 7a /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 201) 001(7a) 120 175 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMADDSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53421, 467},
};

static const struct itemplate instrux_VFNMSUBPD[8] = {
    /*   0 : VFNMSUBPD xmmreg,xmmreg*,xmmrm128,xmmreg [rvms:     vex.m3.w0.nds.l0.p1 7d /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 001) 001(7d) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMSUBPD, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53429, 467},
    /*   1 : VFNMSUBPD xmmreg,xmmrm128,xmmreg [r+vms:     vex.m3.w0.nds.l0.p1 7d /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 001) 001(7d) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMSUBPD, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53437, 467},
    /*   2 : VFNMSUBPD ymmreg,ymmreg*,ymmrm256,ymmreg [rvms:     vex.m3.w0.nds.l1.p1 7d /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 005) 001(7d) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMSUBPD, 4, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,YMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53445, 467},
    /*   3 : VFNMSUBPD ymmreg,ymmrm256,ymmreg [r+vms:     vex.m3.w0.nds.l1.p1 7d /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 005) 001(7d) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMSUBPD, 3, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,YMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53453, 467},
    /*   4 : VFNMSUBPD xmmreg,xmmreg*,xmmreg,xmmrm128 [rvsm:     vex.m3.w1.nds.l0.p1 7d /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 201) 001(7d) 130 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMSUBPD, 4, {XMMREG|RN_L16,XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53461, 467},
    /*   5 : VFNMSUBPD xmmreg,xmmreg,xmmrm128 [r+vsm:     vex.m3.w1.nds.l0.p1 7d /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 201) 001(7d) 120 175 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMSUBPD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53469, 467},
    /*   6 : VFNMSUBPD ymmreg,ymmreg*,ymmreg,ymmrm256 [rvsm:     vex.m3.w1.nds.l1.p1 7d /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 205) 001(7d) 130 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMSUBPD, 4, {YMMREG|RN_L16,YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53477, 467},
    /*   7 : VFNMSUBPD ymmreg,ymmreg,ymmrm256 [r+vsm:     vex.m3.w1.nds.l1.p1 7d /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 205) 001(7d) 120 175 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMSUBPD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53485, 467},
};

static const struct itemplate instrux_VFNMSUBPS[8] = {
    /*   0 : VFNMSUBPS xmmreg,xmmreg*,xmmrm128,xmmreg [rvms:     vex.m3.w0.nds.l0.p1 7c /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 001) 001(7c) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMSUBPS, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53493, 467},
    /*   1 : VFNMSUBPS xmmreg,xmmrm128,xmmreg [r+vms:     vex.m3.w0.nds.l0.p1 7c /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 001) 001(7c) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMSUBPS, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53501, 467},
    /*   2 : VFNMSUBPS ymmreg,ymmreg*,ymmrm256,ymmreg [rvms:     vex.m3.w0.nds.l1.p1 7c /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 005) 001(7c) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMSUBPS, 4, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,YMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53509, 467},
    /*   3 : VFNMSUBPS ymmreg,ymmrm256,ymmreg [r+vms:     vex.m3.w0.nds.l1.p1 7c /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 005) 001(7c) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMSUBPS, 3, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,YMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53517, 467},
    /*   4 : VFNMSUBPS xmmreg,xmmreg*,xmmreg,xmmrm128 [rvsm:     vex.m3.w1.nds.l0.p1 7c /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 201) 001(7c) 130 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMSUBPS, 4, {XMMREG|RN_L16,XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53525, 467},
    /*   5 : VFNMSUBPS xmmreg,xmmreg,xmmrm128 [r+vsm:     vex.m3.w1.nds.l0.p1 7c /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 201) 001(7c) 120 175 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMSUBPS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53533, 467},
    /*   6 : VFNMSUBPS ymmreg,ymmreg*,ymmreg,ymmrm256 [rvsm:     vex.m3.w1.nds.l1.p1 7c /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 205) 001(7c) 130 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMSUBPS, 4, {YMMREG|RN_L16,YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53541, 467},
    /*   7 : VFNMSUBPS ymmreg,ymmreg,ymmrm256 [r+vsm:     vex.m3.w1.nds.l1.p1 7c /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 205) 001(7c) 120 175 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMSUBPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53549, 467},
};

static const struct itemplate instrux_VFNMSUBSD[4] = {
    /*   0 : VFNMSUBSD xmmreg,xmmreg*,xmmrm64,xmmreg [rvms:     vex.m3.w0.nds.l0.p1 7f /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 001) 001(7f) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMSUBSD, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,XMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53557, 467},
    /*   1 : VFNMSUBSD xmmreg,xmmrm64,xmmreg [r+vms:     vex.m3.w0.nds.l0.p1 7f /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 001) 001(7f) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMSUBSD, 3, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53565, 467},
    /*   2 : VFNMSUBSD xmmreg,xmmreg*,xmmreg,xmmrm64 [rvsm:     vex.m3.w1.nds.l0.p1 7f /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 201) 001(7f) 130 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMSUBSD, 4, {XMMREG|RN_L16,XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53573, 467},
    /*   3 : VFNMSUBSD xmmreg,xmmreg,xmmrm64 [r+vsm:     vex.m3.w1.nds.l0.p1 7f /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 201) 001(7f) 120 175 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMSUBSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53581, 467},
};

static const struct itemplate instrux_VFNMSUBSS[4] = {
    /*   0 : VFNMSUBSS xmmreg,xmmreg*,xmmrm32,xmmreg [rvms:     vex.m3.w0.nds.l0.p1 7e /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 001) 001(7e) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMSUBSS, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,XMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53589, 467},
    /*   1 : VFNMSUBSS xmmreg,xmmrm32,xmmreg [r+vms:     vex.m3.w0.nds.l0.p1 7e /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 001) 001(7e) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMSUBSS, 3, {XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53597, 467},
    /*   2 : VFNMSUBSS xmmreg,xmmreg*,xmmreg,xmmrm32 [rvsm:     vex.m3.w1.nds.l0.p1 7e /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(003 201) 001(7e) 130 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMSUBSS, 4, {XMMREG|RN_L16,XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53605, 467},
    /*   3 : VFNMSUBSS xmmreg,xmmreg,xmmrm32 [r+vsm:     vex.m3.w1.nds.l0.p1 7e /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(003 201) 001(7e) 120 175 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFNMSUBSS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53613, 467},
};

static const struct itemplate instrux_VFRCZPD[4] = {
    /*   0 : VFRCZPD xmmreg,xmmrm128* [rm:       xop.m9.w0.l0.p0 81 /r             ] SSE5,FUTURE,AMD */
        /* 270(111 000) 001(81) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFRCZPD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+62451, 467},
    /*   1 : VFRCZPD xmmreg [r+m:       xop.m9.w0.l0.p0 81 /r             ] ND,SSE5,FUTURE,AMD */
        /* 270(111 000) 001(81) 100 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFRCZPD, 1, {XMMREG|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+62458, 467},
    /*   2 : VFRCZPD ymmreg,ymmrm256* [rm:       xop.m9.w0.l1.p0 81 /r             ] SSE5,FUTURE,AMD */
        /* 270(111 004) 001(81) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFRCZPD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+62465, 467},
    /*   3 : VFRCZPD ymmreg [r+m:       xop.m9.w0.l1.p0 81 /r             ] ND,SSE5,FUTURE,AMD */
        /* 270(111 004) 001(81) 100 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFRCZPD, 1, {YMMREG|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+62472, 467},
};

static const struct itemplate instrux_VFRCZPS[4] = {
    /*   0 : VFRCZPS xmmreg,xmmrm128* [rm:       xop.m9.w0.l0.p0 80 /r             ] SSE5,FUTURE,AMD */
        /* 270(111 000) 001(80) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFRCZPS, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+62479, 467},
    /*   1 : VFRCZPS xmmreg [r+m:       xop.m9.w0.l0.p0 80 /r             ] ND,SSE5,FUTURE,AMD */
        /* 270(111 000) 001(80) 100 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFRCZPS, 1, {XMMREG|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+62486, 467},
    /*   2 : VFRCZPS ymmreg,ymmrm256* [rm:       xop.m9.w0.l1.p0 80 /r             ] SSE5,FUTURE,AMD */
        /* 270(111 004) 001(80) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFRCZPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+62493, 467},
    /*   3 : VFRCZPS ymmreg [r+m:       xop.m9.w0.l1.p0 80 /r             ] ND,SSE5,FUTURE,AMD */
        /* 270(111 004) 001(80) 100 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFRCZPS, 1, {YMMREG|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+62500, 467},
};

static const struct itemplate instrux_VFRCZSD[2] = {
    /*   0 : VFRCZSD xmmreg,xmmrm64* [rm:       xop.m9.w0.l0.p0 83 /r             ] SSE5,FUTURE,AMD */
        /* 270(111 000) 001(83) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFRCZSD, 2, {XMMREG|RN_L16,RM_XMM|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+62507, 467},
    /*   1 : VFRCZSD xmmreg [r+m:       xop.m9.w0.l0.p0 83 /r             ] ND,SSE5,FUTURE,AMD */
        /* 270(111 000) 001(83) 100 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFRCZSD, 1, {XMMREG|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+62514, 467},
};

static const struct itemplate instrux_VFRCZSS[2] = {
    /*   0 : VFRCZSS xmmreg,xmmrm32* [rm:       xop.m9.w0.l0.p0 82 /r             ] SSE5,FUTURE,AMD */
        /* 270(111 000) 001(82) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFRCZSS, 2, {XMMREG|RN_L16,RM_XMM|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+62521, 467},
    /*   1 : VFRCZSS xmmreg [r+m:       xop.m9.w0.l0.p0 82 /r             ] ND,SSE5,FUTURE,AMD */
        /* 270(111 000) 001(82) 100 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VFRCZSS, 1, {XMMREG|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+62528, 467},
};

static const struct itemplate instrux_VPCMOV[8] = {
    /*   0 : VPCMOV xmmreg,xmmreg*,xmmrm128,xmmreg [rvms:     xop.m8.w0.nds.l0.p0 a2 /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(110 000) 001(a2) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPCMOV, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53621, 467},
    /*   1 : VPCMOV xmmreg,xmmrm128,xmmreg [r+vms:     xop.m8.w0.nds.l0.p0 a2 /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(110 000) 001(a2) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPCMOV, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53629, 467},
    /*   2 : VPCMOV ymmreg,ymmreg*,ymmrm256,ymmreg [rvms:     xop.m8.w0.nds.l1.p0 a2 /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(110 004) 001(a2) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPCMOV, 4, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,YMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53637, 467},
    /*   3 : VPCMOV ymmreg,ymmrm256,ymmreg [r+vms:     xop.m8.w0.nds.l1.p0 a2 /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(110 004) 001(a2) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPCMOV, 3, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,YMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53645, 467},
    /*   4 : VPCMOV xmmreg,xmmreg*,xmmreg,xmmrm128 [rvsm:     xop.m8.w1.nds.l0.p0 a2 /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(110 200) 001(a2) 130 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPCMOV, 4, {XMMREG|RN_L16,XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53653, 467},
    /*   5 : VPCMOV xmmreg,xmmreg,xmmrm128 [r+vsm:     xop.m8.w1.nds.l0.p0 a2 /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(110 200) 001(a2) 120 175 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPCMOV, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53661, 467},
    /*   6 : VPCMOV ymmreg,ymmreg*,ymmreg,ymmrm256 [rvsm:     xop.m8.w1.nds.l1.p0 a2 /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(110 204) 001(a2) 130 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPCMOV, 4, {YMMREG|RN_L16,YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53669, 467},
    /*   7 : VPCMOV ymmreg,ymmreg,ymmrm256 [r+vsm:     xop.m8.w1.nds.l1.p0 a2 /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(110 204) 001(a2) 120 175 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPCMOV, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53677, 467},
};

static const struct itemplate instrux_VPCOMB[2] = {
    /*   0 : VPCOMB xmmreg,xmmreg*,xmmrm128,imm8 [rvmi:     xop.m8.w0.nds.l0.p0 cc /r ib      ] SSE5,FUTURE,AMD */
        /* 261(110 000) 001(cc) 120 023 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPCOMB, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+53685, 467},
    /*   1 : VPCOMB xmmreg,xmmrm128,imm8 [r+vmi:     xop.m8.w0.nds.l0.p0 cc /r ib      ] ND,SSE5,FUTURE,AMD */
        /* 260(110 000) 001(cc) 110 022 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPCOMB, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+53693, 467},
};

static const struct itemplate instrux_VPCOMD[2] = {
    /*   0 : VPCOMD xmmreg,xmmreg*,xmmrm128,imm8 [rvmi:     xop.m8.w0.nds.l0.p0 ce /r ib      ] SSE5,FUTURE,AMD */
        /* 261(110 000) 001(ce) 120 023 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPCOMD, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+53701, 467},
    /*   1 : VPCOMD xmmreg,xmmrm128,imm8 [r+vmi:     xop.m8.w0.nds.l0.p0 ce /r ib      ] ND,SSE5,FUTURE,AMD */
        /* 260(110 000) 001(ce) 110 022 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPCOMD, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+53709, 467},
};

static const struct itemplate instrux_VPCOMQ[2] = {
    /*   0 : VPCOMQ xmmreg,xmmreg*,xmmrm128,imm8 [rvmi:     xop.m8.w0.nds.l0.p0 cf /r ib      ] SSE5,FUTURE,AMD */
        /* 261(110 000) 001(cf) 120 023 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPCOMQ, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+53717, 467},
    /*   1 : VPCOMQ xmmreg,xmmrm128,imm8 [r+vmi:     xop.m8.w0.nds.l0.p0 cf /r ib      ] ND,SSE5,FUTURE,AMD */
        /* 260(110 000) 001(cf) 110 022 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPCOMQ, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+53725, 467},
};

static const struct itemplate instrux_VPCOMUB[2] = {
    /*   0 : VPCOMUB xmmreg,xmmreg*,xmmrm128,imm8 [rvmi:     xop.m8.w0.nds.l0.p0 ec /r ib      ] SSE5,FUTURE,AMD */
        /* 261(110 000) 001(ec) 120 023 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPCOMUB, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+53733, 467},
    /*   1 : VPCOMUB xmmreg,xmmrm128,imm8 [r+vmi:     xop.m8.w0.nds.l0.p0 ec /r ib      ] ND,SSE5,FUTURE,AMD */
        /* 260(110 000) 001(ec) 110 022 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPCOMUB, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+53741, 467},
};

static const struct itemplate instrux_VPCOMUD[2] = {
    /*   0 : VPCOMUD xmmreg,xmmreg*,xmmrm128,imm8 [rvmi:     xop.m8.w0.nds.l0.p0 ee /r ib      ] SSE5,FUTURE,AMD */
        /* 261(110 000) 001(ee) 120 023 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPCOMUD, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+53749, 467},
    /*   1 : VPCOMUD xmmreg,xmmrm128,imm8 [r+vmi:     xop.m8.w0.nds.l0.p0 ee /r ib      ] ND,SSE5,FUTURE,AMD */
        /* 260(110 000) 001(ee) 110 022 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPCOMUD, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+53757, 467},
};

static const struct itemplate instrux_VPCOMUQ[2] = {
    /*   0 : VPCOMUQ xmmreg,xmmreg*,xmmrm128,imm8 [rvmi:     xop.m8.w0.nds.l0.p0 ef /r ib      ] SSE5,FUTURE,AMD */
        /* 261(110 000) 001(ef) 120 023 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPCOMUQ, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+53765, 467},
    /*   1 : VPCOMUQ xmmreg,xmmrm128,imm8 [r+vmi:     xop.m8.w0.nds.l0.p0 ef /r ib      ] ND,SSE5,FUTURE,AMD */
        /* 260(110 000) 001(ef) 110 022 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPCOMUQ, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+53773, 467},
};

static const struct itemplate instrux_VPCOMUW[2] = {
    /*   0 : VPCOMUW xmmreg,xmmreg*,xmmrm128,imm8 [rvmi:     xop.m8.w0.nds.l0.p0 ed /r ib      ] SSE5,FUTURE,AMD */
        /* 261(110 000) 001(ed) 120 023 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPCOMUW, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+53781, 467},
    /*   1 : VPCOMUW xmmreg,xmmrm128,imm8 [r+vmi:     xop.m8.w0.nds.l0.p0 ed /r ib      ] ND,SSE5,FUTURE,AMD */
        /* 260(110 000) 001(ed) 110 022 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPCOMUW, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+53789, 467},
};

static const struct itemplate instrux_VPCOMW[2] = {
    /*   0 : VPCOMW xmmreg,xmmreg*,xmmrm128,imm8 [rvmi:     xop.m8.w0.nds.l0.p0 cd /r ib      ] SSE5,FUTURE,AMD */
        /* 261(110 000) 001(cd) 120 023 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPCOMW, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+53797, 467},
    /*   1 : VPCOMW xmmreg,xmmrm128,imm8 [r+vmi:     xop.m8.w0.nds.l0.p0 cd /r ib      ] ND,SSE5,FUTURE,AMD */
        /* 260(110 000) 001(cd) 110 022 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPCOMW, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+53805, 467},
};

static const struct itemplate instrux_VPHADDBD[2] = {
    /*   0 : VPHADDBD xmmreg,xmmrm128* [rm:       xop.m9.w0.l0.p0 c2 /r             ] SSE5,FUTURE,AMD */
        /* 270(111 000) 001(c2) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPHADDBD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+62535, 467},
    /*   1 : VPHADDBD xmmreg [r+m:       xop.m9.w0.l0.p0 c2 /r             ] ND,SSE5,FUTURE,AMD */
        /* 270(111 000) 001(c2) 100 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPHADDBD, 1, {XMMREG|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+62542, 467},
};

static const struct itemplate instrux_VPHADDBQ[2] = {
    /*   0 : VPHADDBQ xmmreg,xmmrm128* [rm:       xop.m9.w0.l0.p0 c3 /r             ] SSE5,FUTURE,AMD */
        /* 270(111 000) 001(c3) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPHADDBQ, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+62549, 467},
    /*   1 : VPHADDBQ xmmreg [r+m:       xop.m9.w0.l0.p0 c3 /r             ] ND,SSE5,FUTURE,AMD */
        /* 270(111 000) 001(c3) 100 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPHADDBQ, 1, {XMMREG|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+62556, 467},
};

static const struct itemplate instrux_VPHADDBW[2] = {
    /*   0 : VPHADDBW xmmreg,xmmrm128* [rm:       xop.m9.w0.l0.p0 c1 /r             ] SSE5,FUTURE,AMD */
        /* 270(111 000) 001(c1) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPHADDBW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+62563, 467},
    /*   1 : VPHADDBW xmmreg [r+m:       xop.m9.w0.l0.p0 c1 /r             ] ND,SSE5,FUTURE,AMD */
        /* 270(111 000) 001(c1) 100 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPHADDBW, 1, {XMMREG|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+62570, 467},
};

static const struct itemplate instrux_VPHADDDQ[2] = {
    /*   0 : VPHADDDQ xmmreg,xmmrm128* [rm:       xop.m9.w0.l0.p0 cb /r             ] SSE5,FUTURE,AMD */
        /* 270(111 000) 001(cb) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPHADDDQ, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+62577, 467},
    /*   1 : VPHADDDQ xmmreg [r+m:       xop.m9.w0.l0.p0 cb /r             ] ND,SSE5,FUTURE,AMD */
        /* 270(111 000) 001(cb) 100 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPHADDDQ, 1, {XMMREG|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+62584, 467},
};

static const struct itemplate instrux_VPHADDUBD[2] = {
    /*   0 : VPHADDUBD xmmreg,xmmrm128* [rm:       xop.m9.w0.l0.p0 d2 /r             ] SSE5,FUTURE,AMD */
        /* 270(111 000) 001(d2) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPHADDUBD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+62591, 467},
    /*   1 : VPHADDUBD xmmreg [r+m:       xop.m9.w0.l0.p0 d2 /r             ] ND,SSE5,FUTURE,AMD */
        /* 270(111 000) 001(d2) 100 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPHADDUBD, 1, {XMMREG|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+62598, 467},
};

static const struct itemplate instrux_VPHADDUBQ[2] = {
    /*   0 : VPHADDUBQ xmmreg,xmmrm128* [rm:       xop.m9.w0.l0.p0 d3 /r             ] SSE5,FUTURE,AMD */
        /* 270(111 000) 001(d3) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPHADDUBQ, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+62605, 467},
    /*   1 : VPHADDUBQ xmmreg [r+m:       xop.m9.w0.l0.p0 d3 /r             ] ND,SSE5,FUTURE,AMD */
        /* 270(111 000) 001(d3) 100 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPHADDUBQ, 1, {XMMREG|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+62612, 467},
};

static const struct itemplate instrux_VPHADDUBW[2] = {
    /*   0 : VPHADDUBW xmmreg,xmmrm128* [rm:       xop.m9.w0.l0.p0 d1 /r             ] SSE5,FUTURE,AMD */
        /* 270(111 000) 001(d1) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPHADDUBW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+62619, 467},
    /*   1 : VPHADDUBW xmmreg [r+m:       xop.m9.w0.l0.p0 d1 /r             ] ND,SSE5,FUTURE,AMD */
        /* 270(111 000) 001(d1) 100 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPHADDUBW, 1, {XMMREG|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+62626, 467},
};

static const struct itemplate instrux_VPHADDUDQ[2] = {
    /*   0 : VPHADDUDQ xmmreg,xmmrm128* [rm:       xop.m9.w0.l0.p0 db /r             ] SSE5,FUTURE,AMD */
        /* 270(111 000) 001(db) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPHADDUDQ, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+62633, 467},
    /*   1 : VPHADDUDQ xmmreg [r+m:       xop.m9.w0.l0.p0 db /r             ] ND,SSE5,FUTURE,AMD */
        /* 270(111 000) 001(db) 100 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPHADDUDQ, 1, {XMMREG|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+62640, 467},
};

static const struct itemplate instrux_VPHADDUWD[2] = {
    /*   0 : VPHADDUWD xmmreg,xmmrm128* [rm:       xop.m9.w0.l0.p0 d6 /r             ] SSE5,FUTURE,AMD */
        /* 270(111 000) 001(d6) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPHADDUWD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+62647, 467},
    /*   1 : VPHADDUWD xmmreg [r+m:       xop.m9.w0.l0.p0 d6 /r             ] ND,SSE5,FUTURE,AMD */
        /* 270(111 000) 001(d6) 100 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPHADDUWD, 1, {XMMREG|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+62654, 467},
};

static const struct itemplate instrux_VPHADDUWQ[2] = {
    /*   0 : VPHADDUWQ xmmreg,xmmrm128* [rm:       xop.m9.w0.l0.p0 d7 /r             ] SSE5,FUTURE,AMD */
        /* 270(111 000) 001(d7) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPHADDUWQ, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+62661, 467},
    /*   1 : VPHADDUWQ xmmreg [r+m:       xop.m9.w0.l0.p0 d7 /r             ] ND,SSE5,FUTURE,AMD */
        /* 270(111 000) 001(d7) 100 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPHADDUWQ, 1, {XMMREG|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+62668, 467},
};

static const struct itemplate instrux_VPHADDWD[2] = {
    /*   0 : VPHADDWD xmmreg,xmmrm128* [rm:       xop.m9.w0.l0.p0 c6 /r             ] SSE5,FUTURE,AMD */
        /* 270(111 000) 001(c6) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPHADDWD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+62675, 467},
    /*   1 : VPHADDWD xmmreg [r+m:       xop.m9.w0.l0.p0 c6 /r             ] ND,SSE5,FUTURE,AMD */
        /* 270(111 000) 001(c6) 100 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPHADDWD, 1, {XMMREG|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+62682, 467},
};

static const struct itemplate instrux_VPHADDWQ[2] = {
    /*   0 : VPHADDWQ xmmreg,xmmrm128* [rm:       xop.m9.w0.l0.p0 c7 /r             ] SSE5,FUTURE,AMD */
        /* 270(111 000) 001(c7) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPHADDWQ, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+62689, 467},
    /*   1 : VPHADDWQ xmmreg [r+m:       xop.m9.w0.l0.p0 c7 /r             ] ND,SSE5,FUTURE,AMD */
        /* 270(111 000) 001(c7) 100 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPHADDWQ, 1, {XMMREG|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+62696, 467},
};

static const struct itemplate instrux_VPHSUBBW[2] = {
    /*   0 : VPHSUBBW xmmreg,xmmrm128* [rm:       xop.m9.w0.l0.p0 e1 /r             ] SSE5,FUTURE,AMD */
        /* 270(111 000) 001(e1) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPHSUBBW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+62703, 467},
    /*   1 : VPHSUBBW xmmreg [r+m:       xop.m9.w0.l0.p0 e1 /r             ] ND,SSE5,FUTURE,AMD */
        /* 270(111 000) 001(e1) 100 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPHSUBBW, 1, {XMMREG|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+62710, 467},
};

static const struct itemplate instrux_VPHSUBDQ[2] = {
    /*   0 : VPHSUBDQ xmmreg,xmmrm128* [rm:       xop.m9.w0.l0.p0 e3 /r             ] SSE5,FUTURE,AMD */
        /* 270(111 000) 001(e3) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPHSUBDQ, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+62717, 467},
    /*   1 : VPHSUBDQ xmmreg [r+m:       xop.m9.w0.l0.p0 e3 /r             ] ND,SSE5,FUTURE,AMD */
        /* 270(111 000) 001(e3) 100 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPHSUBDQ, 1, {XMMREG|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+62724, 467},
};

static const struct itemplate instrux_VPHSUBWD[2] = {
    /*   0 : VPHSUBWD xmmreg,xmmrm128* [rm:       xop.m9.w0.l0.p0 e2 /r             ] SSE5,FUTURE,AMD */
        /* 270(111 000) 001(e2) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPHSUBWD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+62731, 467},
    /*   1 : VPHSUBWD xmmreg [r+m:       xop.m9.w0.l0.p0 e2 /r             ] ND,SSE5,FUTURE,AMD */
        /* 270(111 000) 001(e2) 100 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPHSUBWD, 1, {XMMREG|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+62738, 467},
};

static const struct itemplate instrux_VPMACSDD[2] = {
    /*   0 : VPMACSDD xmmreg,xmmreg*,xmmrm128,xmmreg [rvms:     xop.m8.w0.nds.l0.p0 9e /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(110 000) 001(9e) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPMACSDD, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53813, 467},
    /*   1 : VPMACSDD xmmreg,xmmrm128,xmmreg [r+vms:     xop.m8.w0.nds.l0.p0 9e /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(110 000) 001(9e) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPMACSDD, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53821, 467},
};

static const struct itemplate instrux_VPMACSDQH[2] = {
    /*   0 : VPMACSDQH xmmreg,xmmreg*,xmmrm128,xmmreg [rvms:     xop.m8.w0.nds.l0.p0 9f /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(110 000) 001(9f) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPMACSDQH, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53829, 467},
    /*   1 : VPMACSDQH xmmreg,xmmrm128,xmmreg [r+vms:     xop.m8.w0.nds.l0.p0 9f /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(110 000) 001(9f) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPMACSDQH, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53837, 467},
};

static const struct itemplate instrux_VPMACSDQL[2] = {
    /*   0 : VPMACSDQL xmmreg,xmmreg*,xmmrm128,xmmreg [rvms:     xop.m8.w0.nds.l0.p0 97 /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(110 000) 001(97) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPMACSDQL, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53845, 467},
    /*   1 : VPMACSDQL xmmreg,xmmrm128,xmmreg [r+vms:     xop.m8.w0.nds.l0.p0 97 /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(110 000) 001(97) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPMACSDQL, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53853, 467},
};

static const struct itemplate instrux_VPMACSSDD[2] = {
    /*   0 : VPMACSSDD xmmreg,xmmreg*,xmmrm128,xmmreg [rvms:     xop.m8.w0.nds.l0.p0 8e /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(110 000) 001(8e) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPMACSSDD, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53861, 467},
    /*   1 : VPMACSSDD xmmreg,xmmrm128,xmmreg [r+vms:     xop.m8.w0.nds.l0.p0 8e /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(110 000) 001(8e) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPMACSSDD, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53869, 467},
};

static const struct itemplate instrux_VPMACSSDQH[2] = {
    /*   0 : VPMACSSDQH xmmreg,xmmreg*,xmmrm128,xmmreg [rvms:     xop.m8.w0.nds.l0.p0 8f /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(110 000) 001(8f) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPMACSSDQH, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53877, 467},
    /*   1 : VPMACSSDQH xmmreg,xmmrm128,xmmreg [r+vms:     xop.m8.w0.nds.l0.p0 8f /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(110 000) 001(8f) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPMACSSDQH, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53885, 467},
};

static const struct itemplate instrux_VPMACSSDQL[2] = {
    /*   0 : VPMACSSDQL xmmreg,xmmreg*,xmmrm128,xmmreg [rvms:     xop.m8.w0.nds.l0.p0 87 /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(110 000) 001(87) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPMACSSDQL, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53893, 467},
    /*   1 : VPMACSSDQL xmmreg,xmmrm128,xmmreg [r+vms:     xop.m8.w0.nds.l0.p0 87 /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(110 000) 001(87) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPMACSSDQL, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53901, 467},
};

static const struct itemplate instrux_VPMACSSWD[2] = {
    /*   0 : VPMACSSWD xmmreg,xmmreg*,xmmrm128,xmmreg [rvms:     xop.m8.w0.nds.l0.p0 86 /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(110 000) 001(86) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPMACSSWD, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53909, 467},
    /*   1 : VPMACSSWD xmmreg,xmmrm128,xmmreg [r+vms:     xop.m8.w0.nds.l0.p0 86 /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(110 000) 001(86) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPMACSSWD, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53917, 467},
};

static const struct itemplate instrux_VPMACSSWW[2] = {
    /*   0 : VPMACSSWW xmmreg,xmmreg*,xmmrm128,xmmreg [rvms:     xop.m8.w0.nds.l0.p0 85 /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(110 000) 001(85) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPMACSSWW, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53925, 467},
    /*   1 : VPMACSSWW xmmreg,xmmrm128,xmmreg [r+vms:     xop.m8.w0.nds.l0.p0 85 /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(110 000) 001(85) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPMACSSWW, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53933, 467},
};

static const struct itemplate instrux_VPMACSWD[2] = {
    /*   0 : VPMACSWD xmmreg,xmmreg*,xmmrm128,xmmreg [rvms:     xop.m8.w0.nds.l0.p0 96 /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(110 000) 001(96) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPMACSWD, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53941, 467},
    /*   1 : VPMACSWD xmmreg,xmmrm128,xmmreg [r+vms:     xop.m8.w0.nds.l0.p0 96 /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(110 000) 001(96) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPMACSWD, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53949, 467},
};

static const struct itemplate instrux_VPMACSWW[2] = {
    /*   0 : VPMACSWW xmmreg,xmmreg*,xmmrm128,xmmreg [rvms:     xop.m8.w0.nds.l0.p0 95 /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(110 000) 001(95) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPMACSWW, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53957, 467},
    /*   1 : VPMACSWW xmmreg,xmmrm128,xmmreg [r+vms:     xop.m8.w0.nds.l0.p0 95 /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(110 000) 001(95) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPMACSWW, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53965, 467},
};

static const struct itemplate instrux_VPMADCSSWD[2] = {
    /*   0 : VPMADCSSWD xmmreg,xmmreg*,xmmrm128,xmmreg [rvms:     xop.m8.w0.nds.l0.p0 a6 /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(110 000) 001(a6) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPMADCSSWD, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53973, 467},
    /*   1 : VPMADCSSWD xmmreg,xmmrm128,xmmreg [r+vms:     xop.m8.w0.nds.l0.p0 a6 /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(110 000) 001(a6) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPMADCSSWD, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53981, 467},
};

static const struct itemplate instrux_VPMADCSWD[2] = {
    /*   0 : VPMADCSWD xmmreg,xmmreg*,xmmrm128,xmmreg [rvms:     xop.m8.w0.nds.l0.p0 b6 /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(110 000) 001(b6) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPMADCSWD, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+53989, 467},
    /*   1 : VPMADCSWD xmmreg,xmmrm128,xmmreg [r+vms:     xop.m8.w0.nds.l0.p0 b6 /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(110 000) 001(b6) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPMADCSWD, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+53997, 467},
};

static const struct itemplate instrux_VPPERM[4] = {
    /*   0 : VPPERM xmmreg,xmmreg*,xmmreg,xmmrm128 [rvsm:     xop.m8.w1.nds.l0.p0 a3 /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(110 200) 001(a3) 130 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPPERM, 4, {XMMREG|RN_L16,XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+54005, 467},
    /*   1 : VPPERM xmmreg,xmmreg,xmmrm128 [r+vsm:     xop.m8.w1.nds.l0.p0 a3 /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(110 200) 001(a3) 120 175 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPPERM, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+54013, 467},
    /*   2 : VPPERM xmmreg,xmmreg*,xmmrm128,xmmreg [rvms:     xop.m8.w0.nds.l0.p0 a3 /r /is4    ] SSE5,FUTURE,AMD */
        /* 261(110 000) 001(a3) 120 177 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPPERM, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0}, NO_DECORATOR, nasm_bytecodes+54021, 467},
    /*   3 : VPPERM xmmreg,xmmrm128,xmmreg [r+vms:     xop.m8.w0.nds.l0.p0 a3 /r /is4    ] ND,SSE5,FUTURE,AMD */
        /* 260(110 000) 001(a3) 110 176 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPPERM, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+54029, 467},
};

static const struct itemplate instrux_VPROTB[6] = {
    /*   0 : VPROTB xmmreg,xmmrm128*,xmmreg [rmv:      xop.m9.w0.nds.l0.p0 90 /r         ] SSE5,FUTURE,AMD */
        /* 262(111 000) 001(90) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPROTB, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62745, 467},
    /*   1 : VPROTB xmmreg,xmmreg [r+mv:      xop.m9.w0.nds.l0.p0 90 /r         ] ND,SSE5,FUTURE,AMD */
        /* 261(111 000) 001(90) 100 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPROTB, 2, {XMMREG|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+62752, 467},
    /*   2 : VPROTB xmmreg,xmmreg*,xmmrm128 [rvm:      xop.m9.w1.nds.l0.p0 90 /r         ] SSE5,FUTURE,AMD */
        /* 261(111 200) 001(90) 120 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPROTB, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62759, 467},
    /*   3 : VPROTB xmmreg,xmmrm128 [r+vm:      xop.m9.w1.nds.l0.p0 90 /r         ] ND,SSE5,FUTURE,AMD */
        /* 260(111 200) 001(90) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPROTB, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+62766, 467},
    /*   4 : VPROTB xmmreg,xmmrm128*,imm8 [rmi:      xop.m8.w0.l0.p0 c0 /r ib          ] SSE5,FUTURE,AMD */
        /* 270(110 000) 001(c0) 110 022 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPROTB, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54037, 467},
    /*   5 : VPROTB xmmreg,imm8 [r+mi:      xop.m8.w0.l0.p0 c0 /r ib          ] ND,SSE5,FUTURE,AMD */
        /* 270(110 000) 001(c0) 100 021 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPROTB, 2, {XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+54045, 467},
};

static const struct itemplate instrux_VPROTD[6] = {
    /*   0 : VPROTD xmmreg,xmmrm128*,xmmreg [rmv:      xop.m9.w0.nds.l0.p0 92 /r         ] SSE5,FUTURE,AMD */
        /* 262(111 000) 001(92) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPROTD, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62773, 467},
    /*   1 : VPROTD xmmreg,xmmreg [r+mv:      xop.m9.w0.nds.l0.p0 92 /r         ] ND,SSE5,FUTURE,AMD */
        /* 261(111 000) 001(92) 100 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPROTD, 2, {XMMREG|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+62780, 467},
    /*   2 : VPROTD xmmreg,xmmreg*,xmmrm128 [rvm:      xop.m9.w1.nds.l0.p0 92 /r         ] SSE5,FUTURE,AMD */
        /* 261(111 200) 001(92) 120 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPROTD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62787, 467},
    /*   3 : VPROTD xmmreg,xmmrm128 [r+vm:      xop.m9.w1.nds.l0.p0 92 /r         ] ND,SSE5,FUTURE,AMD */
        /* 260(111 200) 001(92) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPROTD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+62794, 467},
    /*   4 : VPROTD xmmreg,xmmrm128*,imm8 [rmi:      xop.m8.w0.l0.p0 c2 /r ib          ] SSE5,FUTURE,AMD */
        /* 270(110 000) 001(c2) 110 022 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPROTD, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54053, 467},
    /*   5 : VPROTD xmmreg,imm8 [r+mi:      xop.m8.w0.l0.p0 c2 /r ib          ] ND,SSE5,FUTURE,AMD */
        /* 270(110 000) 001(c2) 100 021 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPROTD, 2, {XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+54061, 467},
};

static const struct itemplate instrux_VPROTQ[6] = {
    /*   0 : VPROTQ xmmreg,xmmrm128*,xmmreg [rmv:      xop.m9.w0.nds.l0.p0 93 /r         ] SSE5,FUTURE,AMD */
        /* 262(111 000) 001(93) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPROTQ, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62801, 467},
    /*   1 : VPROTQ xmmreg,xmmreg [r+mv:      xop.m9.w0.nds.l0.p0 93 /r         ] ND,SSE5,FUTURE,AMD */
        /* 261(111 000) 001(93) 100 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPROTQ, 2, {XMMREG|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+62808, 467},
    /*   2 : VPROTQ xmmreg,xmmreg*,xmmrm128 [rvm:      xop.m9.w1.nds.l0.p0 93 /r         ] SSE5,FUTURE,AMD */
        /* 261(111 200) 001(93) 120 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPROTQ, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62815, 467},
    /*   3 : VPROTQ xmmreg,xmmrm128 [r+vm:      xop.m9.w1.nds.l0.p0 93 /r         ] ND,SSE5,FUTURE,AMD */
        /* 260(111 200) 001(93) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPROTQ, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+62822, 467},
    /*   4 : VPROTQ xmmreg,xmmrm128*,imm8 [rmi:      xop.m8.w0.l0.p0 c3 /r ib          ] SSE5,FUTURE,AMD */
        /* 270(110 000) 001(c3) 110 022 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPROTQ, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54069, 467},
    /*   5 : VPROTQ xmmreg,imm8 [r+mi:      xop.m8.w0.l0.p0 c3 /r ib          ] ND,SSE5,FUTURE,AMD */
        /* 270(110 000) 001(c3) 100 021 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPROTQ, 2, {XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+54077, 467},
};

static const struct itemplate instrux_VPROTW[6] = {
    /*   0 : VPROTW xmmreg,xmmrm128*,xmmreg [rmv:      xop.m9.w0.nds.l0.p0 91 /r         ] SSE5,FUTURE,AMD */
        /* 262(111 000) 001(91) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPROTW, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62829, 467},
    /*   1 : VPROTW xmmreg,xmmreg [r+mv:      xop.m9.w0.nds.l0.p0 91 /r         ] ND,SSE5,FUTURE,AMD */
        /* 261(111 000) 001(91) 100 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPROTW, 2, {XMMREG|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+62836, 467},
    /*   2 : VPROTW xmmreg,xmmreg*,xmmrm128 [rvm:      xop.m9.w1.nds.l0.p0 91 /r         ] SSE5,FUTURE,AMD */
        /* 261(111 200) 001(91) 120 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPROTW, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62843, 467},
    /*   3 : VPROTW xmmreg,xmmrm128 [r+vm:      xop.m9.w1.nds.l0.p0 91 /r         ] ND,SSE5,FUTURE,AMD */
        /* 260(111 200) 001(91) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPROTW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+62850, 467},
    /*   4 : VPROTW xmmreg,xmmrm128*,imm8 [rmi:      xop.m8.w0.l0.p0 c1 /r ib          ] SSE5,FUTURE,AMD */
        /* 270(110 000) 001(c1) 110 022 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPROTW, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54085, 467},
    /*   5 : VPROTW xmmreg,imm8 [r+mi:      xop.m8.w0.l0.p0 c1 /r ib          ] ND,SSE5,FUTURE,AMD */
        /* 270(110 000) 001(c1) 100 021 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPROTW, 2, {XMMREG|RN_L16,IMM_NORMAL|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+54093, 467},
};

static const struct itemplate instrux_VPSHAB[4] = {
    /*   0 : VPSHAB xmmreg,xmmrm128*,xmmreg [rmv:      xop.m9.w0.nds.l0.p0 98 /r         ] SSE5,FUTURE,AMD */
        /* 262(111 000) 001(98) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPSHAB, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62857, 467},
    /*   1 : VPSHAB xmmreg,xmmreg [r+mv:      xop.m9.w0.nds.l0.p0 98 /r         ] ND,SSE5,FUTURE,AMD */
        /* 261(111 000) 001(98) 100 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPSHAB, 2, {XMMREG|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+62864, 467},
    /*   2 : VPSHAB xmmreg,xmmreg*,xmmrm128 [rvm:      xop.m9.w1.nds.l0.p0 98 /r         ] SSE5,FUTURE,AMD */
        /* 261(111 200) 001(98) 120 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPSHAB, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62871, 467},
    /*   3 : VPSHAB xmmreg,xmmrm128 [r+vm:      xop.m9.w1.nds.l0.p0 98 /r         ] ND,SSE5,FUTURE,AMD */
        /* 260(111 200) 001(98) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPSHAB, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+62878, 467},
};

static const struct itemplate instrux_VPSHAD[4] = {
    /*   0 : VPSHAD xmmreg,xmmrm128*,xmmreg [rmv:      xop.m9.w0.nds.l0.p0 9a /r         ] SSE5,FUTURE,AMD */
        /* 262(111 000) 001(9a) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPSHAD, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62885, 467},
    /*   1 : VPSHAD xmmreg,xmmreg [r+mv:      xop.m9.w0.nds.l0.p0 9a /r         ] ND,SSE5,FUTURE,AMD */
        /* 261(111 000) 001(9a) 100 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPSHAD, 2, {XMMREG|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+62892, 467},
    /*   2 : VPSHAD xmmreg,xmmreg*,xmmrm128 [rvm:      xop.m9.w1.nds.l0.p0 9a /r         ] SSE5,FUTURE,AMD */
        /* 261(111 200) 001(9a) 120 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPSHAD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62899, 467},
    /*   3 : VPSHAD xmmreg,xmmrm128 [r+vm:      xop.m9.w1.nds.l0.p0 9a /r         ] ND,SSE5,FUTURE,AMD */
        /* 260(111 200) 001(9a) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPSHAD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+62906, 467},
};

static const struct itemplate instrux_VPSHAQ[4] = {
    /*   0 : VPSHAQ xmmreg,xmmrm128*,xmmreg [rmv:      xop.m9.w0.nds.l0.p0 9b /r         ] SSE5,FUTURE,AMD */
        /* 262(111 000) 001(9b) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPSHAQ, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62913, 467},
    /*   1 : VPSHAQ xmmreg,xmmreg [r+mv:      xop.m9.w0.nds.l0.p0 9b /r         ] ND,SSE5,FUTURE,AMD */
        /* 261(111 000) 001(9b) 100 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPSHAQ, 2, {XMMREG|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+62920, 467},
    /*   2 : VPSHAQ xmmreg,xmmreg*,xmmrm128 [rvm:      xop.m9.w1.nds.l0.p0 9b /r         ] SSE5,FUTURE,AMD */
        /* 261(111 200) 001(9b) 120 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPSHAQ, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62927, 467},
    /*   3 : VPSHAQ xmmreg,xmmrm128 [r+vm:      xop.m9.w1.nds.l0.p0 9b /r         ] ND,SSE5,FUTURE,AMD */
        /* 260(111 200) 001(9b) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPSHAQ, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+62934, 467},
};

static const struct itemplate instrux_VPSHAW[4] = {
    /*   0 : VPSHAW xmmreg,xmmrm128*,xmmreg [rmv:      xop.m9.w0.nds.l0.p0 99 /r         ] SSE5,FUTURE,AMD */
        /* 262(111 000) 001(99) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPSHAW, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62941, 467},
    /*   1 : VPSHAW xmmreg,xmmreg [r+mv:      xop.m9.w0.nds.l0.p0 99 /r         ] ND,SSE5,FUTURE,AMD */
        /* 261(111 000) 001(99) 100 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPSHAW, 2, {XMMREG|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+62948, 467},
    /*   2 : VPSHAW xmmreg,xmmreg*,xmmrm128 [rvm:      xop.m9.w1.nds.l0.p0 99 /r         ] SSE5,FUTURE,AMD */
        /* 261(111 200) 001(99) 120 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPSHAW, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62955, 467},
    /*   3 : VPSHAW xmmreg,xmmrm128 [r+vm:      xop.m9.w1.nds.l0.p0 99 /r         ] ND,SSE5,FUTURE,AMD */
        /* 260(111 200) 001(99) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPSHAW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+62962, 467},
};

static const struct itemplate instrux_VPSHLB[4] = {
    /*   0 : VPSHLB xmmreg,xmmrm128*,xmmreg [rmv:      xop.m9.w0.nds.l0.p0 94 /r         ] SSE5,FUTURE,AMD */
        /* 262(111 000) 001(94) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPSHLB, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62969, 467},
    /*   1 : VPSHLB xmmreg,xmmreg [r+mv:      xop.m9.w0.nds.l0.p0 94 /r         ] ND,SSE5,FUTURE,AMD */
        /* 261(111 000) 001(94) 100 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPSHLB, 2, {XMMREG|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+62976, 467},
    /*   2 : VPSHLB xmmreg,xmmreg*,xmmrm128 [rvm:      xop.m9.w1.nds.l0.p0 94 /r         ] SSE5,FUTURE,AMD */
        /* 261(111 200) 001(94) 120 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPSHLB, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62983, 467},
    /*   3 : VPSHLB xmmreg,xmmrm128 [r+vm:      xop.m9.w1.nds.l0.p0 94 /r         ] ND,SSE5,FUTURE,AMD */
        /* 260(111 200) 001(94) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPSHLB, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+62990, 467},
};

static const struct itemplate instrux_VPSHLD[4] = {
    /*   0 : VPSHLD xmmreg,xmmrm128*,xmmreg [rmv:      xop.m9.w0.nds.l0.p0 96 /r         ] SSE5,FUTURE,AMD */
        /* 262(111 000) 001(96) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPSHLD, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+62997, 467},
    /*   1 : VPSHLD xmmreg,xmmreg [r+mv:      xop.m9.w0.nds.l0.p0 96 /r         ] ND,SSE5,FUTURE,AMD */
        /* 261(111 000) 001(96) 100 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPSHLD, 2, {XMMREG|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63004, 467},
    /*   2 : VPSHLD xmmreg,xmmreg*,xmmrm128 [rvm:      xop.m9.w1.nds.l0.p0 96 /r         ] SSE5,FUTURE,AMD */
        /* 261(111 200) 001(96) 120 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPSHLD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63011, 467},
    /*   3 : VPSHLD xmmreg,xmmrm128 [r+vm:      xop.m9.w1.nds.l0.p0 96 /r         ] ND,SSE5,FUTURE,AMD */
        /* 260(111 200) 001(96) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPSHLD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63018, 467},
};

static const struct itemplate instrux_VPSHLQ[4] = {
    /*   0 : VPSHLQ xmmreg,xmmrm128*,xmmreg [rmv:      xop.m9.w0.nds.l0.p0 97 /r         ] SSE5,FUTURE,AMD */
        /* 262(111 000) 001(97) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPSHLQ, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63025, 467},
    /*   1 : VPSHLQ xmmreg,xmmreg [r+mv:      xop.m9.w0.nds.l0.p0 97 /r         ] ND,SSE5,FUTURE,AMD */
        /* 261(111 000) 001(97) 100 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPSHLQ, 2, {XMMREG|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63032, 467},
    /*   2 : VPSHLQ xmmreg,xmmreg*,xmmrm128 [rvm:      xop.m9.w1.nds.l0.p0 97 /r         ] SSE5,FUTURE,AMD */
        /* 261(111 200) 001(97) 120 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPSHLQ, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63039, 467},
    /*   3 : VPSHLQ xmmreg,xmmrm128 [r+vm:      xop.m9.w1.nds.l0.p0 97 /r         ] ND,SSE5,FUTURE,AMD */
        /* 260(111 200) 001(97) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPSHLQ, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63046, 467},
};

static const struct itemplate instrux_VPSHLW[4] = {
    /*   0 : VPSHLW xmmreg,xmmrm128*,xmmreg [rmv:      xop.m9.w0.nds.l0.p0 95 /r         ] SSE5,FUTURE,AMD */
        /* 262(111 000) 001(95) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPSHLW, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63053, 467},
    /*   1 : VPSHLW xmmreg,xmmreg [r+mv:      xop.m9.w0.nds.l0.p0 95 /r         ] ND,SSE5,FUTURE,AMD */
        /* 261(111 000) 001(95) 100 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPSHLW, 2, {XMMREG|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63060, 467},
    /*   2 : VPSHLW xmmreg,xmmreg*,xmmrm128 [rvm:      xop.m9.w1.nds.l0.p0 95 /r         ] SSE5,FUTURE,AMD */
        /* 261(111 200) 001(95) 120 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPSHLW, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+63067, 467},
    /*   3 : VPSHLW xmmreg,xmmrm128 [r+vm:      xop.m9.w1.nds.l0.p0 95 /r         ] ND,SSE5,FUTURE,AMD */
        /* 260(111 200) 001(95) 110 : NOAPX,VEX,SSE5,FUTURE,AMD */
        {I_VPSHLW, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+63074, 467},
};

static const struct itemplate instrux_VBROADCASTI128[1] = {
    /*   0 : VBROADCASTI128 ymmreg,mem128 [rm:       vex.256.66.0f38.w0 5a /r          ] AVX2,FUTURE */
        /* 270(002 005) 001(5a) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VBROADCASTI128, 2, {YMMREG|RN_L16,MEMORY|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64348, 469},
};

static const struct itemplate instrux_VPBLENDD[4] = {
    /*   0 : VPBLENDD xmmreg,xmmreg*,xmmrm128,imm8 [rvmi:     vex.nds.128.66.0f3a.w0 02 /r ib   ] AVX2,FUTURE */
        /* 261(003 001) 001(02) 120 023 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPBLENDD, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+54349, 469},
    /*   1 : VPBLENDD xmmreg,xmmrm128,imm8 [r+vmi:     vex.nds.128.66.0f3a.w0 02 /r ib   ] ND,AVX2,FUTURE */
        /* 260(003 001) 001(02) 110 022 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPBLENDD, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54357, 469},
    /*   2 : VPBLENDD ymmreg,ymmreg*,ymmrm256,imm8 [rvmi:     vex.nds.256.66.0f3a.w0 02 /r ib   ] AVX2,FUTURE */
        /* 261(003 005) 001(02) 120 023 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPBLENDD, 4, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+54365, 469},
    /*   3 : VPBLENDD ymmreg,ymmrm256,imm8 [r+vmi:     vex.nds.256.66.0f3a.w0 02 /r ib   ] ND,AVX2,FUTURE */
        /* 260(003 005) 001(02) 110 022 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPBLENDD, 3, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54373, 469},
};

static const struct itemplate instrux_VPBROADCASTB[19] = {
    /*   0 : VPBROADCASTB xmmreg,mem8 [rm:       vex.128.66.0f38.w0 78 /r          ] AVX2,FUTURE */
        /* 270(002 001) 001(78) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPBROADCASTB, 2, {XMMREG|RN_L16,MEMORY|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64355, 469},
    /*   1 : VPBROADCASTB xmmreg,xmmreg [rm:       vex.128.66.0f38.w0 78 /r          ] AVX2,FUTURE */
        /* 270(002 001) 001(78) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPBROADCASTB, 2, {XMMREG|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64355, 469},
    /*   2 : VPBROADCASTB ymmreg,mem8 [rm:       vex.256.66.0f38.w0 78 /r          ] AVX2,FUTURE */
        /* 270(002 005) 001(78) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPBROADCASTB, 2, {YMMREG|RN_L16,MEMORY|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64362, 469},
    /*   3 : VPBROADCASTB ymmreg,xmmreg [rm:       vex.256.66.0f38.w0 78 /r          ] AVX2,FUTURE */
        /* 270(002 005) 001(78) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPBROADCASTB, 2, {YMMREG|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64362, 469},
    /*   4 : VPBROADCASTB xmmreg|mask|z,xmmrm8 [rm:t1s8:  evex.128.66.0f38.w0 78 /r         ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7d 08) 304 001(78) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPBROADCASTB, 2, {XMMREG,RM_XMM|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36585, 550},
    /*   5 : VPBROADCASTB ymmreg|mask|z,xmmrm8 [rm:t1s8:  evex.256.66.0f38.w0 78 /r         ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7d 28) 304 001(78) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPBROADCASTB, 2, {YMMREG,RM_XMM|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36594, 550},
    /*   6 : VPBROADCASTB zmmreg|mask|z,xmmrm8 [rm:t1s8:  evex.512.66.0f38.w0 78 /r         ] AVX512BW,FUTURE */
        /* 250(f2 7d 48) 304 001(78) 110 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPBROADCASTB, 2, {ZMMREG,RM_XMM|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36603, 551},
    /*   7 : VPBROADCASTB xmmreg|mask|z,reg8 [rm:       evex.128.66.0f38.w0 7a /r         ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7d 08) 300 001(7a) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPBROADCASTB, 2, {XMMREG,REG_GPR|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36612, 550},
    /*   8 : VPBROADCASTB xmmreg|mask|z,reg16 [rm:       evex.128.66.0f38.w0 7a /r         ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7d 08) 300 001(7a) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPBROADCASTB, 2, {XMMREG,REG_GPR|BITS16,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36612, 550},
    /*   9 : VPBROADCASTB xmmreg|mask|z,reg32 [rm:       evex.128.66.0f38.w0 7a /r         ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7d 08) 300 001(7a) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPBROADCASTB, 2, {XMMREG,REG_GPR|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36612, 550},
    /*  10 : VPBROADCASTB xmmreg|mask|z,reg64 [rm:       evex.128.66.0f38.w0 7a /r         ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7d 08) 300 001(7a) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPBROADCASTB, 2, {XMMREG,REG_GPR|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36612, 550},
    /*  11 : VPBROADCASTB ymmreg|mask|z,reg8 [rm:       evex.256.66.0f38.w0 7a /r         ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7d 28) 300 001(7a) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPBROADCASTB, 2, {YMMREG,REG_GPR|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36621, 550},
    /*  12 : VPBROADCASTB ymmreg|mask|z,reg16 [rm:       evex.256.66.0f38.w0 7a /r         ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7d 28) 300 001(7a) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPBROADCASTB, 2, {YMMREG,REG_GPR|BITS16,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36621, 550},
    /*  13 : VPBROADCASTB ymmreg|mask|z,reg32 [rm:       evex.256.66.0f38.w0 7a /r         ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7d 28) 300 001(7a) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPBROADCASTB, 2, {YMMREG,REG_GPR|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36621, 550},
    /*  14 : VPBROADCASTB ymmreg|mask|z,reg64 [rm:       evex.256.66.0f38.w0 7a /r         ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7d 28) 300 001(7a) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPBROADCASTB, 2, {YMMREG,REG_GPR|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36621, 550},
    /*  15 : VPBROADCASTB zmmreg|mask|z,reg8 [rm:       evex.512.66.0f38.w0 7a /r         ] AVX512BW,FUTURE */
        /* 250(f2 7d 48) 300 001(7a) 110 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPBROADCASTB, 2, {ZMMREG,REG_GPR|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36630, 551},
    /*  16 : VPBROADCASTB zmmreg|mask|z,reg16 [rm:       evex.512.66.0f38.w0 7a /r         ] AVX512BW,FUTURE */
        /* 250(f2 7d 48) 300 001(7a) 110 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPBROADCASTB, 2, {ZMMREG,REG_GPR|BITS16,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36630, 551},
    /*  17 : VPBROADCASTB zmmreg|mask|z,reg32 [rm:       evex.512.66.0f38.w0 7a /r         ] AVX512BW,FUTURE */
        /* 250(f2 7d 48) 300 001(7a) 110 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPBROADCASTB, 2, {ZMMREG,REG_GPR|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36630, 551},
    /*  18 : VPBROADCASTB zmmreg|mask|z,reg64 [rm:       evex.512.66.0f38.w0 7a /r         ] AVX512BW,FUTURE */
        /* 250(f2 7d 48) 300 001(7a) 110 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPBROADCASTB, 2, {ZMMREG,REG_GPR|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36630, 551},
};

static const struct itemplate instrux_VPBROADCASTW[16] = {
    /*   0 : VPBROADCASTW xmmreg,mem16 [rm:       vex.128.66.0f38.w0 79 /r          ] AVX2,FUTURE */
        /* 270(002 001) 001(79) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPBROADCASTW, 2, {XMMREG|RN_L16,MEMORY|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64369, 469},
    /*   1 : VPBROADCASTW xmmreg,xmmreg [rm:       vex.128.66.0f38.w0 79 /r          ] AVX2,FUTURE */
        /* 270(002 001) 001(79) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPBROADCASTW, 2, {XMMREG|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64369, 469},
    /*   2 : VPBROADCASTW ymmreg,mem16 [rm:       vex.256.66.0f38.w0 79 /r          ] AVX2,FUTURE */
        /* 270(002 005) 001(79) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPBROADCASTW, 2, {YMMREG|RN_L16,MEMORY|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64376, 469},
    /*   3 : VPBROADCASTW ymmreg,xmmreg [rm:       vex.256.66.0f38.w0 79 /r          ] AVX2,FUTURE */
        /* 270(002 005) 001(79) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPBROADCASTW, 2, {YMMREG|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64376, 469},
    /*   4 : VPBROADCASTW xmmreg|mask|z,xmmrm16 [rm:t1s16: evex.128.66.0f38.w0 79 /r         ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7d 08) 305 001(79) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPBROADCASTW, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36855, 550},
    /*   5 : VPBROADCASTW ymmreg|mask|z,xmmrm16 [rm:t1s16: evex.256.66.0f38.w0 79 /r         ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7d 28) 305 001(79) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPBROADCASTW, 2, {YMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36864, 550},
    /*   6 : VPBROADCASTW zmmreg|mask|z,xmmrm16 [rm:t1s16: evex.512.66.0f38.w0 79 /r         ] AVX512BW,FUTURE */
        /* 250(f2 7d 48) 305 001(79) 110 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPBROADCASTW, 2, {ZMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36873, 551},
    /*   7 : VPBROADCASTW xmmreg|mask|z,reg16 [rm:       evex.128.66.0f38.w0 7b /r         ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7d 08) 300 001(7b) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPBROADCASTW, 2, {XMMREG,REG_GPR|BITS16,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36882, 550},
    /*   8 : VPBROADCASTW xmmreg|mask|z,reg32 [rm:       evex.128.66.0f38.w0 7b /r         ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7d 08) 300 001(7b) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPBROADCASTW, 2, {XMMREG,REG_GPR|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36882, 550},
    /*   9 : VPBROADCASTW xmmreg|mask|z,reg64 [rm:       evex.128.66.0f38.w0 7b /r         ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7d 08) 300 001(7b) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPBROADCASTW, 2, {XMMREG,REG_GPR|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36882, 550},
    /*  10 : VPBROADCASTW ymmreg|mask|z,reg16 [rm:       evex.256.66.0f38.w0 7b /r         ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7d 28) 300 001(7b) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPBROADCASTW, 2, {YMMREG,REG_GPR|BITS16,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36891, 550},
    /*  11 : VPBROADCASTW ymmreg|mask|z,reg32 [rm:       evex.256.66.0f38.w0 7b /r         ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7d 28) 300 001(7b) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPBROADCASTW, 2, {YMMREG,REG_GPR|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36891, 550},
    /*  12 : VPBROADCASTW ymmreg|mask|z,reg64 [rm:       evex.256.66.0f38.w0 7b /r         ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7d 28) 300 001(7b) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPBROADCASTW, 2, {YMMREG,REG_GPR|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36891, 550},
    /*  13 : VPBROADCASTW zmmreg|mask|z,reg16 [rm:       evex.512.66.0f38.w0 7b /r         ] AVX512BW,FUTURE */
        /* 250(f2 7d 48) 300 001(7b) 110 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPBROADCASTW, 2, {ZMMREG,REG_GPR|BITS16,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36900, 551},
    /*  14 : VPBROADCASTW zmmreg|mask|z,reg32 [rm:       evex.512.66.0f38.w0 7b /r         ] AVX512BW,FUTURE */
        /* 250(f2 7d 48) 300 001(7b) 110 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPBROADCASTW, 2, {ZMMREG,REG_GPR|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36900, 551},
    /*  15 : VPBROADCASTW zmmreg|mask|z,reg64 [rm:       evex.512.66.0f38.w0 7b /r         ] AVX512BW,FUTURE */
        /* 250(f2 7d 48) 300 001(7b) 110 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPBROADCASTW, 2, {ZMMREG,REG_GPR|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36900, 551},
};

static const struct itemplate instrux_VPBROADCASTD[13] = {
    /*   0 : VPBROADCASTD xmmreg,mem32 [rm:       vex.128.66.0f38.w0 58 /r          ] AVX2,FUTURE */
        /* 270(002 001) 001(58) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPBROADCASTD, 2, {XMMREG|RN_L16,MEMORY|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64383, 469},
    /*   1 : VPBROADCASTD xmmreg,xmmreg [rm:       vex.128.66.0f38.w0 58 /r          ] AVX2,FUTURE */
        /* 270(002 001) 001(58) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPBROADCASTD, 2, {XMMREG|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64383, 469},
    /*   2 : VPBROADCASTD ymmreg,mem32 [rm:       vex.256.66.0f38.w0 58 /r          ] AVX2,FUTURE */
        /* 270(002 005) 001(58) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPBROADCASTD, 2, {YMMREG|RN_L16,MEMORY|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64390, 469},
    /*   3 : VPBROADCASTD ymmreg,xmmreg [rm:       vex.256.66.0f38.w0 58 /r          ] AVX2,FUTURE */
        /* 270(002 005) 001(58) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPBROADCASTD, 2, {YMMREG|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64390, 469},
    /*   4 : VPBROADCASTD xmmreg|mask|z,mem32 [rm:t1s:   evex.128.66.0f38.w0 58 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 08) 306 001(58) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPBROADCASTD, 2, {XMMREG,MEMORY|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36639, 544},
    /*   5 : VPBROADCASTD ymmreg|mask|z,mem32 [rm:t1s:   evex.256.66.0f38.w0 58 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 28) 306 001(58) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPBROADCASTD, 2, {YMMREG,MEMORY|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36648, 544},
    /*   6 : VPBROADCASTD zmmreg|mask|z,mem32 [rm:t1s:   evex.512.66.0f38.w0 58 /r         ] AVX512,FUTURE */
        /* 250(f2 7d 48) 306 001(58) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPBROADCASTD, 2, {ZMMREG,MEMORY|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36657, 545},
    /*   7 : VPBROADCASTD xmmreg|mask|z,xmmreg [rm:       evex.128.66.0f38.w0 58 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 08) 300 001(58) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPBROADCASTD, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36666, 544},
    /*   8 : VPBROADCASTD ymmreg|mask|z,xmmreg [rm:       evex.256.66.0f38.w0 58 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 28) 300 001(58) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPBROADCASTD, 2, {YMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36675, 544},
    /*   9 : VPBROADCASTD zmmreg|mask|z,xmmreg [rm:       evex.512.66.0f38.w0 58 /r         ] AVX512,FUTURE */
        /* 250(f2 7d 48) 300 001(58) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPBROADCASTD, 2, {ZMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36684, 545},
    /*  10 : VPBROADCASTD xmmreg|mask|z,reg32 [rm:       evex.128.66.0f38.w0 7c /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 08) 300 001(7c) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPBROADCASTD, 2, {XMMREG,REG_GPR|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36693, 544},
    /*  11 : VPBROADCASTD ymmreg|mask|z,reg32 [rm:       evex.256.66.0f38.w0 7c /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 28) 300 001(7c) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPBROADCASTD, 2, {YMMREG,REG_GPR|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36702, 544},
    /*  12 : VPBROADCASTD zmmreg|mask|z,reg32 [rm:       evex.512.66.0f38.w0 7c /r         ] AVX512,FUTURE */
        /* 250(f2 7d 48) 300 001(7c) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPBROADCASTD, 2, {ZMMREG,REG_GPR|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36711, 545},
};

static const struct itemplate instrux_VPBROADCASTQ[13] = {
    /*   0 : VPBROADCASTQ xmmreg,mem64 [rm:       vex.128.66.0f38.w0 59 /r          ] AVX2,FUTURE */
        /* 270(002 001) 001(59) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPBROADCASTQ, 2, {XMMREG|RN_L16,MEMORY|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64397, 469},
    /*   1 : VPBROADCASTQ xmmreg,xmmreg [rm:       vex.128.66.0f38.w0 59 /r          ] AVX2,FUTURE */
        /* 270(002 001) 001(59) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPBROADCASTQ, 2, {XMMREG|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64397, 469},
    /*   2 : VPBROADCASTQ ymmreg,mem64 [rm:       vex.256.66.0f38.w0 59 /r          ] AVX2,FUTURE */
        /* 270(002 005) 001(59) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPBROADCASTQ, 2, {YMMREG|RN_L16,MEMORY|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64404, 469},
    /*   3 : VPBROADCASTQ ymmreg,xmmreg [rm:       vex.256.66.0f38.w0 59 /r          ] AVX2,FUTURE */
        /* 270(002 005) 001(59) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPBROADCASTQ, 2, {YMMREG|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64404, 469},
    /*   4 : VPBROADCASTQ xmmreg|mask|z,mem64 [rm:t1s:   evex.128.66.0f38.w1 59 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 fd 08) 306 001(59) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPBROADCASTQ, 2, {XMMREG,MEMORY|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36774, 544},
    /*   5 : VPBROADCASTQ ymmreg|mask|z,mem64 [rm:t1s:   evex.256.66.0f38.w1 59 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 fd 28) 306 001(59) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPBROADCASTQ, 2, {YMMREG,MEMORY|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36783, 544},
    /*   6 : VPBROADCASTQ zmmreg|mask|z,mem64 [rm:t1s:   evex.512.66.0f38.w1 59 /r         ] AVX512,FUTURE */
        /* 250(f2 fd 48) 306 001(59) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPBROADCASTQ, 2, {ZMMREG,MEMORY|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36792, 545},
    /*   7 : VPBROADCASTQ xmmreg|mask|z,xmmreg [rm:       evex.128.66.0f38.w1 59 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 fd 08) 300 001(59) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPBROADCASTQ, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36801, 544},
    /*   8 : VPBROADCASTQ ymmreg|mask|z,xmmreg [rm:       evex.256.66.0f38.w1 59 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 fd 28) 300 001(59) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPBROADCASTQ, 2, {YMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36810, 544},
    /*   9 : VPBROADCASTQ zmmreg|mask|z,xmmreg [rm:       evex.512.66.0f38.w1 59 /r         ] AVX512,FUTURE */
        /* 250(f2 fd 48) 300 001(59) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPBROADCASTQ, 2, {ZMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36819, 545},
    /*  10 : VPBROADCASTQ xmmreg|mask|z,reg64 [rm:       evex.128.66.0f38.w1 7c /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 fd 08) 300 001(7c) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPBROADCASTQ, 2, {XMMREG,REG_GPR|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36828, 544},
    /*  11 : VPBROADCASTQ ymmreg|mask|z,reg64 [rm:       evex.256.66.0f38.w1 7c /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 fd 28) 300 001(7c) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPBROADCASTQ, 2, {YMMREG,REG_GPR|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36837, 544},
    /*  12 : VPBROADCASTQ zmmreg|mask|z,reg64 [rm:       evex.512.66.0f38.w1 7c /r         ] AVX512,FUTURE */
        /* 250(f2 fd 48) 300 001(7c) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPBROADCASTQ, 2, {ZMMREG,REG_GPR|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36846, 545},
};

static const struct itemplate instrux_VPERMD[6] = {
    /*   0 : VPERMD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f38.w0 36 /r      ] AVX2,FUTURE */
        /* 261(002 005) 001(36) 120 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPERMD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64411, 469},
    /*   1 : VPERMD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f38.w0 36 /r      ] ND,AVX2,FUTURE */
        /* 260(002 005) 001(36) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPERMD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64418, 469},
    /*   2 : VPERMD ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f38.w0 36 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 28) 301 001(36) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPERMD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+37341, 544},
    /*   3 : VPERMD ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.nds.256.66.0f38.w0 36 /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 7d 28) 301 001(36) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPERMD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+37350, 544},
    /*   4 : VPERMD zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv:   evex.nds.512.66.0f38.w0 36 /r     ] AVX512,FUTURE */
        /* 241(f2 7d 48) 301 001(36) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPERMD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+37359, 545},
    /*   5 : VPERMD zmmreg|mask|z,zmmrm512|b32 [r+vm:fv:   evex.nds.512.66.0f38.w0 36 /r     ] ND,AVX512,FUTURE */
        /* 240(f2 7d 48) 301 001(36) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPERMD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+37368, 545},
};

static const struct itemplate instrux_VPERMPD[7] = {
    /*   0 : VPERMPD ymmreg,ymmrm256,imm8 [rmi:      vex.256.66.0f3a.w1 01 /r ib       ] AVX2,FUTURE */
        /* 270(003 205) 001(01) 110 022 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPERMPD, 3, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54381, 469},
    /*   1 : VPERMPD ymmreg|mask|z,ymmrm256|b64,imm8 [rmi:fv:   evex.256.66.0f3a.w1 01 /r ib      ] AVX512,AVX512VL,FUTURE */
        /* 250(f3 fd 28) 301 001(01) 110 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPERMPD, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+19813, 544},
    /*   2 : VPERMPD zmmreg|mask|z,zmmrm512|b64,imm8 [rmi:fv:   evex.512.66.0f3a.w1 01 /r ib      ] AVX512,FUTURE */
        /* 250(f3 fd 48) 301 001(01) 110 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VPERMPD, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+19823, 545},
    /*   3 : VPERMPD ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 16 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 28) 301 001(16) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPERMPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+37647, 544},
    /*   4 : VPERMPD ymmreg|mask|z,ymmrm256|b64 [r+vm:fv:   evex.nds.256.66.0f38.w1 16 /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 fd 28) 301 001(16) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPERMPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+37656, 544},
    /*   5 : VPERMPD zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv:   evex.nds.512.66.0f38.w1 16 /r     ] AVX512,FUTURE */
        /* 241(f2 fd 48) 301 001(16) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPERMPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+37665, 545},
    /*   6 : VPERMPD zmmreg|mask|z,zmmrm512|b64 [r+vm:fv:   evex.nds.512.66.0f38.w1 16 /r     ] ND,AVX512,FUTURE */
        /* 240(f2 fd 48) 301 001(16) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPERMPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+37674, 545},
};

static const struct itemplate instrux_VPERMPS[6] = {
    /*   0 : VPERMPS ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f38.w0 16 /r      ] AVX2,FUTURE */
        /* 261(002 005) 001(16) 120 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPERMPS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64425, 469},
    /*   1 : VPERMPS ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f38.w0 16 /r      ] ND,AVX2,FUTURE */
        /* 260(002 005) 001(16) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPERMPS, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64432, 469},
    /*   2 : VPERMPS ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f38.w0 16 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 28) 301 001(16) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPERMPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+37683, 544},
    /*   3 : VPERMPS ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.nds.256.66.0f38.w0 16 /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 7d 28) 301 001(16) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPERMPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+37692, 544},
    /*   4 : VPERMPS zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv:   evex.nds.512.66.0f38.w0 16 /r     ] AVX512,FUTURE */
        /* 241(f2 7d 48) 301 001(16) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPERMPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+37701, 545},
    /*   5 : VPERMPS zmmreg|mask|z,zmmrm512|b32 [r+vm:fv:   evex.nds.512.66.0f38.w0 16 /r     ] ND,AVX512,FUTURE */
        /* 240(f2 7d 48) 301 001(16) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPERMPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+37710, 545},
};

static const struct itemplate instrux_VPERMQ[7] = {
    /*   0 : VPERMQ ymmreg,ymmrm256,imm8 [rmi:      vex.256.66.0f3a.w1 00 /r ib       ] AVX2,FUTURE */
        /* 270(003 205) 001(00) 110 022 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPERMQ, 3, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54389, 469},
    /*   1 : VPERMQ ymmreg|mask|z,ymmrm256|b64,imm8 [rmi:fv:   evex.256.66.0f3a.w1 00 /r ib      ] AVX512,AVX512VL,FUTURE */
        /* 250(f3 fd 28) 301 001(00) 110 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPERMQ, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+19833, 544},
    /*   2 : VPERMQ zmmreg|mask|z,zmmrm512|b64,imm8 [rmi:fv:   evex.512.66.0f3a.w1 00 /r ib      ] AVX512,FUTURE */
        /* 250(f3 fd 48) 301 001(00) 110 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VPERMQ, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+19843, 545},
    /*   3 : VPERMQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 36 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 28) 301 001(36) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPERMQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+37719, 544},
    /*   4 : VPERMQ ymmreg|mask|z,ymmrm256|b64 [r+vm:fv:   evex.nds.256.66.0f38.w1 36 /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 fd 28) 301 001(36) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPERMQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+37728, 544},
    /*   5 : VPERMQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv:   evex.nds.512.66.0f38.w1 36 /r     ] AVX512,FUTURE */
        /* 241(f2 fd 48) 301 001(36) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPERMQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+37737, 545},
    /*   6 : VPERMQ zmmreg|mask|z,zmmrm512|b64 [r+vm:fv:   evex.nds.512.66.0f38.w1 36 /r     ] ND,AVX512,FUTURE */
        /* 240(f2 fd 48) 301 001(36) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPERMQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+37746, 545},
};

static const struct itemplate instrux_VPERM2I128[2] = {
    /*   0 : VPERM2I128 ymmreg,ymmreg*,ymmrm256,imm8 [rvmi:     vex.nds.256.66.0f3a.w0 46 /r ib   ] AVX2,FUTURE */
        /* 261(003 005) 001(46) 120 023 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPERM2I128, 4, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+54397, 469},
    /*   1 : VPERM2I128 ymmreg,ymmrm256,imm8 [r+vmi:     vex.nds.256.66.0f3a.w0 46 /r ib   ] ND,AVX2,FUTURE */
        /* 260(003 005) 001(46) 110 022 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPERM2I128, 3, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54405, 469},
};

static const struct itemplate instrux_VEXTRACTI128[1] = {
    /*   0 : VEXTRACTI128 xmmrm128,ymmreg,imm8 [mri:      vex.256.66.0f3a.w0 39 /r ib       ] AVX2,FUTURE */
        /* 270(003 005) 001(39) 101 022 : NOAPX,VEX,AVX2,FUTURE */
        {I_VEXTRACTI128, 3, {RM_XMM|BITS128|RN_L16,YMMREG|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54413, 469},
};

static const struct itemplate instrux_VINSERTI128[2] = {
    /*   0 : VINSERTI128 ymmreg,ymmreg*,xmmrm128,imm8 [rvmi:     vex.nds.256.66.0f3a.w0 38 /r ib   ] AVX2,FUTURE */
        /* 261(003 005) 001(38) 120 023 : NOAPX,VEX,AVX2,FUTURE */
        {I_VINSERTI128, 4, {YMMREG|RN_L16,YMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+54421, 469},
    /*   1 : VINSERTI128 ymmreg,xmmrm128,imm8 [r+vmi:     vex.nds.256.66.0f3a.w0 38 /r ib   ] ND,AVX2,FUTURE */
        /* 260(003 005) 001(38) 110 022 : NOAPX,VEX,AVX2,FUTURE */
        {I_VINSERTI128, 3, {YMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54429, 469},
};

static const struct itemplate instrux_VPMASKMOVD[6] = {
    /*   0 : VPMASKMOVD xmmreg,xmmreg*,mem128 [rvm:      vex.nds.128.66.0f38.w0 8c /r      ] AVX2,FUTURE */
        /* 261(002 001) 001(8c) 120 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPMASKMOVD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,MEMORY|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64439, 469},
    /*   1 : VPMASKMOVD xmmreg,mem128 [r+vm:      vex.nds.128.66.0f38.w0 8c /r      ] ND,AVX2,FUTURE */
        /* 260(002 001) 001(8c) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPMASKMOVD, 2, {XMMREG|RN_L16,MEMORY|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64446, 469},
    /*   2 : VPMASKMOVD ymmreg,ymmreg*,mem256 [rvm:      vex.nds.256.66.0f38.w0 8c /r      ] AVX2,FUTURE */
        /* 261(002 005) 001(8c) 120 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPMASKMOVD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,MEMORY|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64453, 469},
    /*   3 : VPMASKMOVD ymmreg,mem256 [r+vm:      vex.nds.256.66.0f38.w0 8c /r      ] ND,AVX2,FUTURE */
        /* 260(002 005) 001(8c) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPMASKMOVD, 2, {YMMREG|RN_L16,MEMORY|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64460, 469},
    /*   4 : VPMASKMOVD mem128,xmmreg,xmmreg [mvr:      vex.nds.128.66.0f38.w0 8e /r      ] AVX2,FUTURE */
        /* 261(002 001) 001(8e) 102 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPMASKMOVD, 3, {MEMORY|BITS128|RN_L16,XMMREG|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64495, 469},
    /*   5 : VPMASKMOVD mem256,ymmreg,ymmreg [mvr:      vex.nds.256.66.0f38.w0 8e /r      ] AVX2,FUTURE */
        /* 261(002 005) 001(8e) 102 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPMASKMOVD, 3, {MEMORY|BITS256|RN_L16,YMMREG|RN_L16,YMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64502, 469},
};

static const struct itemplate instrux_VPMASKMOVQ[6] = {
    /*   0 : VPMASKMOVQ xmmreg,xmmreg*,mem128 [rvm:      vex.nds.128.66.0f38.w1 8c /r      ] AVX2,FUTURE */
        /* 261(002 201) 001(8c) 120 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPMASKMOVQ, 3, {XMMREG|RN_L16,XMMREG|RN_L16,MEMORY|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64467, 469},
    /*   1 : VPMASKMOVQ xmmreg,mem128 [r+vm:      vex.nds.128.66.0f38.w1 8c /r      ] ND,AVX2,FUTURE */
        /* 260(002 201) 001(8c) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPMASKMOVQ, 2, {XMMREG|RN_L16,MEMORY|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64474, 469},
    /*   2 : VPMASKMOVQ ymmreg,ymmreg*,mem256 [rvm:      vex.nds.256.66.0f38.w1 8c /r      ] AVX2,FUTURE */
        /* 261(002 205) 001(8c) 120 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPMASKMOVQ, 3, {YMMREG|RN_L16,YMMREG|RN_L16,MEMORY|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64481, 469},
    /*   3 : VPMASKMOVQ ymmreg,mem256 [r+vm:      vex.nds.256.66.0f38.w1 8c /r      ] ND,AVX2,FUTURE */
        /* 260(002 205) 001(8c) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPMASKMOVQ, 2, {YMMREG|RN_L16,MEMORY|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64488, 469},
    /*   4 : VPMASKMOVQ mem128,xmmreg,xmmreg [mvr:      vex.nds.128.66.0f38.w1 8e /r      ] AVX2,FUTURE */
        /* 261(002 201) 001(8e) 102 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPMASKMOVQ, 3, {MEMORY|BITS128|RN_L16,XMMREG|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64509, 469},
    /*   5 : VPMASKMOVQ mem256,ymmreg,ymmreg [mvr:      vex.nds.256.66.0f38.w1 8e /r      ] AVX2,FUTURE */
        /* 261(002 205) 001(8e) 102 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPMASKMOVQ, 3, {MEMORY|BITS256|RN_L16,YMMREG|RN_L16,YMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64516, 469},
};

static const struct itemplate instrux_VPSLLVD[10] = {
    /*   0 : VPSLLVD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f38.w0 47 /r      ] AVX2,FUTURE */
        /* 261(002 001) 001(47) 120 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPSLLVD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64523, 469},
    /*   1 : VPSLLVD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f38.w0 47 /r      ] ND,AVX2,FUTURE */
        /* 260(002 001) 001(47) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPSLLVD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64530, 469},
    /*   2 : VPSLLVD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f38.w0 47 /r      ] AVX2,FUTURE */
        /* 261(002 005) 001(47) 120 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPSLLVD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64551, 469},
    /*   3 : VPSLLVD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f38.w0 47 /r      ] ND,AVX2,FUTURE */
        /* 260(002 005) 001(47) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPSLLVD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64558, 469},
    /*   4 : VPSLLVD xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f38.w0 47 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 08) 301 001(47) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSLLVD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+41643, 544},
    /*   5 : VPSLLVD xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.nds.128.66.0f38.w0 47 /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 7d 08) 301 001(47) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSLLVD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+41652, 544},
    /*   6 : VPSLLVD ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f38.w0 47 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 28) 301 001(47) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSLLVD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+41661, 544},
    /*   7 : VPSLLVD ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.nds.256.66.0f38.w0 47 /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 7d 28) 301 001(47) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSLLVD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+41670, 544},
    /*   8 : VPSLLVD zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv:   evex.nds.512.66.0f38.w0 47 /r     ] AVX512,FUTURE */
        /* 241(f2 7d 48) 301 001(47) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSLLVD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+41679, 545},
    /*   9 : VPSLLVD zmmreg|mask|z,zmmrm512|b32 [r+vm:fv:   evex.nds.512.66.0f38.w0 47 /r     ] ND,AVX512,FUTURE */
        /* 240(f2 7d 48) 301 001(47) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSLLVD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+41688, 545},
};

static const struct itemplate instrux_VPSLLVQ[10] = {
    /*   0 : VPSLLVQ xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f38.w1 47 /r      ] AVX2,FUTURE */
        /* 261(002 201) 001(47) 120 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPSLLVQ, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64537, 469},
    /*   1 : VPSLLVQ xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f38.w1 47 /r      ] ND,AVX2,FUTURE */
        /* 260(002 201) 001(47) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPSLLVQ, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64544, 469},
    /*   2 : VPSLLVQ ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f38.w1 47 /r      ] AVX2,FUTURE */
        /* 261(002 205) 001(47) 120 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPSLLVQ, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64565, 469},
    /*   3 : VPSLLVQ ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f38.w1 47 /r      ] ND,AVX2,FUTURE */
        /* 260(002 205) 001(47) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPSLLVQ, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64572, 469},
    /*   4 : VPSLLVQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 47 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 08) 301 001(47) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSLLVQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+41697, 544},
    /*   5 : VPSLLVQ xmmreg|mask|z,xmmrm128|b64 [r+vm:fv:   evex.nds.128.66.0f38.w1 47 /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 fd 08) 301 001(47) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSLLVQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+41706, 544},
    /*   6 : VPSLLVQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 47 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 28) 301 001(47) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSLLVQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+41715, 544},
    /*   7 : VPSLLVQ ymmreg|mask|z,ymmrm256|b64 [r+vm:fv:   evex.nds.256.66.0f38.w1 47 /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 fd 28) 301 001(47) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSLLVQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+41724, 544},
    /*   8 : VPSLLVQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv:   evex.nds.512.66.0f38.w1 47 /r     ] AVX512,FUTURE */
        /* 241(f2 fd 48) 301 001(47) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSLLVQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+41733, 545},
    /*   9 : VPSLLVQ zmmreg|mask|z,zmmrm512|b64 [r+vm:fv:   evex.nds.512.66.0f38.w1 47 /r     ] ND,AVX512,FUTURE */
        /* 240(f2 fd 48) 301 001(47) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSLLVQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+41742, 545},
};

static const struct itemplate instrux_VPSRAVD[10] = {
    /*   0 : VPSRAVD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f38.w0 46 /r      ] AVX2,FUTURE */
        /* 261(002 001) 001(46) 120 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPSRAVD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64579, 469},
    /*   1 : VPSRAVD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f38.w0 46 /r      ] ND,AVX2,FUTURE */
        /* 260(002 001) 001(46) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPSRAVD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64586, 469},
    /*   2 : VPSRAVD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f38.w0 46 /r      ] AVX2,FUTURE */
        /* 261(002 005) 001(46) 120 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPSRAVD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64593, 469},
    /*   3 : VPSRAVD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f38.w0 46 /r      ] ND,AVX2,FUTURE */
        /* 260(002 005) 001(46) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPSRAVD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64600, 469},
    /*   4 : VPSRAVD xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f38.w0 46 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 08) 301 001(46) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRAVD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+41967, 544},
    /*   5 : VPSRAVD xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.nds.128.66.0f38.w0 46 /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 7d 08) 301 001(46) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRAVD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+41976, 544},
    /*   6 : VPSRAVD ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f38.w0 46 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 28) 301 001(46) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRAVD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+41985, 544},
    /*   7 : VPSRAVD ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.nds.256.66.0f38.w0 46 /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 7d 28) 301 001(46) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRAVD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+41994, 544},
    /*   8 : VPSRAVD zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv:   evex.nds.512.66.0f38.w0 46 /r     ] AVX512,FUTURE */
        /* 241(f2 7d 48) 301 001(46) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSRAVD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+42003, 545},
    /*   9 : VPSRAVD zmmreg|mask|z,zmmrm512|b32 [r+vm:fv:   evex.nds.512.66.0f38.w0 46 /r     ] ND,AVX512,FUTURE */
        /* 240(f2 7d 48) 301 001(46) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSRAVD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+42012, 545},
};

static const struct itemplate instrux_VPSRLVD[10] = {
    /*   0 : VPSRLVD xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f38.w0 45 /r      ] AVX2,FUTURE */
        /* 261(002 001) 001(45) 120 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPSRLVD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64607, 469},
    /*   1 : VPSRLVD xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f38.w0 45 /r      ] ND,AVX2,FUTURE */
        /* 260(002 001) 001(45) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPSRLVD, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64614, 469},
    /*   2 : VPSRLVD ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f38.w0 45 /r      ] AVX2,FUTURE */
        /* 261(002 005) 001(45) 120 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPSRLVD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64635, 469},
    /*   3 : VPSRLVD ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f38.w0 45 /r      ] ND,AVX2,FUTURE */
        /* 260(002 005) 001(45) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPSRLVD, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64642, 469},
    /*   4 : VPSRLVD xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f38.w0 45 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 08) 301 001(45) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRLVD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+42291, 544},
    /*   5 : VPSRLVD xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.nds.128.66.0f38.w0 45 /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 7d 08) 301 001(45) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRLVD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+42300, 544},
    /*   6 : VPSRLVD ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f38.w0 45 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 28) 301 001(45) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRLVD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+42309, 544},
    /*   7 : VPSRLVD ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.nds.256.66.0f38.w0 45 /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 7d 28) 301 001(45) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRLVD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+42318, 544},
    /*   8 : VPSRLVD zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv:   evex.nds.512.66.0f38.w0 45 /r     ] AVX512,FUTURE */
        /* 241(f2 7d 48) 301 001(45) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSRLVD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+42327, 545},
    /*   9 : VPSRLVD zmmreg|mask|z,zmmrm512|b32 [r+vm:fv:   evex.nds.512.66.0f38.w0 45 /r     ] ND,AVX512,FUTURE */
        /* 240(f2 7d 48) 301 001(45) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSRLVD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+42336, 545},
};

static const struct itemplate instrux_VPSRLVQ[10] = {
    /*   0 : VPSRLVQ xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f38.w1 45 /r      ] AVX2,FUTURE */
        /* 261(002 201) 001(45) 120 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPSRLVQ, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64621, 469},
    /*   1 : VPSRLVQ xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f38.w1 45 /r      ] ND,AVX2,FUTURE */
        /* 260(002 201) 001(45) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPSRLVQ, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64628, 469},
    /*   2 : VPSRLVQ ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f38.w1 45 /r      ] AVX2,FUTURE */
        /* 261(002 205) 001(45) 120 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPSRLVQ, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64649, 469},
    /*   3 : VPSRLVQ ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f38.w1 45 /r      ] ND,AVX2,FUTURE */
        /* 260(002 205) 001(45) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPSRLVQ, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64656, 469},
    /*   4 : VPSRLVQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 45 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 08) 301 001(45) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRLVQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+42345, 544},
    /*   5 : VPSRLVQ xmmreg|mask|z,xmmrm128|b64 [r+vm:fv:   evex.nds.128.66.0f38.w1 45 /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 fd 08) 301 001(45) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRLVQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+42354, 544},
    /*   6 : VPSRLVQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 45 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 28) 301 001(45) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRLVQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+42363, 544},
    /*   7 : VPSRLVQ ymmreg|mask|z,ymmrm256|b64 [r+vm:fv:   evex.nds.256.66.0f38.w1 45 /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 fd 28) 301 001(45) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRLVQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+42372, 544},
    /*   8 : VPSRLVQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv:   evex.nds.512.66.0f38.w1 45 /r     ] AVX512,FUTURE */
        /* 241(f2 fd 48) 301 001(45) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSRLVQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+42381, 545},
    /*   9 : VPSRLVQ zmmreg|mask|z,zmmrm512|b64 [r+vm:fv:   evex.nds.512.66.0f38.w1 45 /r     ] ND,AVX512,FUTURE */
        /* 240(f2 fd 48) 301 001(45) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSRLVQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+42390, 545},
};

static const struct itemplate instrux_VGATHERDPD[5] = {
    /*   0 : VGATHERDPD xmmreg,xmem64,xmmreg [rmv:      vm32x vex.dds.128.66.0f38.w1 92 /r] AVX2,FUTURE */
        /* 374 262(002 201) 001(92) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VGATHERDPD, 3, {XMMREG|RN_L16,XMEM|BITS64|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+54437, 469},
    /*   1 : VGATHERDPD ymmreg,xmem64,ymmreg [rmv:      vm32x vex.dds.256.66.0f38.w1 92 /r] AVX2,FUTURE */
        /* 374 262(002 205) 001(92) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VGATHERDPD, 3, {YMMREG|RN_L16,XMEM|BITS64|RN_L16,YMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+54453, 469},
    /*   2 : VGATHERDPD xmmreg|mask,xmem64 [rm:t1s:   vsibx evex.128.66.0f38.w1 92 /r   ] AVX512,AVX512VL,FUTURE */
        /* 374 250(f2 fd 08) 306 001(92) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VGATHERDPD, 2, {XMMREG,XMEM|BITS64,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+18913, 544},
    /*   3 : VGATHERDPD ymmreg|mask,xmem64 [rm:t1s:   vsibx evex.256.66.0f38.w1 92 /r   ] AVX512,AVX512VL,FUTURE */
        /* 374 250(f2 fd 28) 306 001(92) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VGATHERDPD, 2, {YMMREG,XMEM|BITS64,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+18923, 544},
    /*   4 : VGATHERDPD zmmreg|mask,ymem64 [rm:t1s:   vsiby evex.512.66.0f38.w1 92 /r   ] AVX512,FUTURE */
        /* 375 250(f2 fd 48) 306 001(92) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VGATHERDPD, 2, {ZMMREG,YMEM|BITS64,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+18933, 545},
};

static const struct itemplate instrux_VGATHERQPD[5] = {
    /*   0 : VGATHERQPD xmmreg,xmem64,xmmreg [rmv:      vm64x vex.dds.128.66.0f38.w1 93 /r] AVX2,FUTURE */
        /* 374 262(002 201) 001(93) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VGATHERQPD, 3, {XMMREG|RN_L16,XMEM|BITS64|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+54445, 469},
    /*   1 : VGATHERQPD ymmreg,ymem64,ymmreg [rmv:      vm64y vex.dds.256.66.0f38.w1 93 /r] AVX2,FUTURE */
        /* 375 262(002 205) 001(93) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VGATHERQPD, 3, {YMMREG|RN_L16,YMEM|BITS64|RN_L16,YMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+54461, 469},
    /*   2 : VGATHERQPD xmmreg|mask,xmem64 [rm:t1s:   vsibx evex.128.66.0f38.w1 93 /r   ] AVX512,AVX512VL,FUTURE */
        /* 374 250(f2 fd 08) 306 001(93) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VGATHERQPD, 2, {XMMREG,XMEM|BITS64,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+19053, 544},
    /*   3 : VGATHERQPD ymmreg|mask,ymem64 [rm:t1s:   vsiby evex.256.66.0f38.w1 93 /r   ] AVX512,AVX512VL,FUTURE */
        /* 375 250(f2 fd 28) 306 001(93) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VGATHERQPD, 2, {YMMREG,YMEM|BITS64,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+19063, 544},
    /*   4 : VGATHERQPD zmmreg|mask,zmem64 [rm:t1s:   vsibz evex.512.66.0f38.w1 93 /r   ] AVX512,FUTURE */
        /* 376 250(f2 fd 48) 306 001(93) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VGATHERQPD, 2, {ZMMREG,ZMEM|BITS64,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+19073, 545},
};

static const struct itemplate instrux_VGATHERDPS[5] = {
    /*   0 : VGATHERDPS xmmreg,xmem32,xmmreg [rmv:      vm32x vex.dds.128.66.0f38.w0 92 /r] AVX2,FUTURE */
        /* 374 262(002 001) 001(92) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VGATHERDPS, 3, {XMMREG|RN_L16,XMEM|BITS32|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+54469, 469},
    /*   1 : VGATHERDPS ymmreg,ymem32,ymmreg [rmv:      vm32y vex.dds.256.66.0f38.w0 92 /r] AVX2,FUTURE */
        /* 375 262(002 005) 001(92) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VGATHERDPS, 3, {YMMREG|RN_L16,YMEM|BITS32|RN_L16,YMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+54485, 469},
    /*   2 : VGATHERDPS xmmreg|mask,xmem32 [rm:t1s:   vsibx evex.128.66.0f38.w0 92 /r   ] AVX512,AVX512VL,FUTURE */
        /* 374 250(f2 7d 08) 306 001(92) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VGATHERDPS, 2, {XMMREG,XMEM|BITS32,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+18943, 544},
    /*   3 : VGATHERDPS ymmreg|mask,ymem32 [rm:t1s:   vsiby evex.256.66.0f38.w0 92 /r   ] AVX512,AVX512VL,FUTURE */
        /* 375 250(f2 7d 28) 306 001(92) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VGATHERDPS, 2, {YMMREG,YMEM|BITS32,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+18953, 544},
    /*   4 : VGATHERDPS zmmreg|mask,zmem32 [rm:t1s:   vsibz evex.512.66.0f38.w0 92 /r   ] AVX512,FUTURE */
        /* 376 250(f2 7d 48) 306 001(92) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VGATHERDPS, 2, {ZMMREG,ZMEM|BITS32,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+18963, 545},
};

static const struct itemplate instrux_VGATHERQPS[5] = {
    /*   0 : VGATHERQPS xmmreg,xmem32,xmmreg [rmv:      vm64x vex.dds.128.66.0f38.w0 93 /r] AVX2,FUTURE */
        /* 374 262(002 001) 001(93) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VGATHERQPS, 3, {XMMREG|RN_L16,XMEM|BITS32|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+54477, 469},
    /*   1 : VGATHERQPS xmmreg,ymem32,xmmreg [rmv:      vm64y vex.dds.256.66.0f38.w0 93 /r] AVX2,FUTURE */
        /* 375 262(002 005) 001(93) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VGATHERQPS, 3, {XMMREG|RN_L16,YMEM|BITS32|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+54493, 469},
    /*   2 : VGATHERQPS xmmreg|mask,xmem32 [rm:t1s:   vsibx evex.128.66.0f38.w0 93 /r   ] AVX512,AVX512VL,FUTURE */
        /* 374 250(f2 7d 08) 306 001(93) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VGATHERQPS, 2, {XMMREG,XMEM|BITS32,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+19083, 544},
    /*   3 : VGATHERQPS xmmreg|mask,ymem32 [rm:t1s:   vsiby evex.256.66.0f38.w0 93 /r   ] AVX512,AVX512VL,FUTURE */
        /* 375 250(f2 7d 28) 306 001(93) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VGATHERQPS, 2, {XMMREG,YMEM|BITS32,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+19093, 544},
    /*   4 : VGATHERQPS ymmreg|mask,zmem32 [rm:t1s:   vsibz evex.512.66.0f38.w0 93 /r   ] AVX512,FUTURE */
        /* 376 250(f2 7d 48) 306 001(93) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VGATHERQPS, 2, {YMMREG,ZMEM|BITS32,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+19103, 545},
};

static const struct itemplate instrux_VPGATHERDD[5] = {
    /*   0 : VPGATHERDD xmmreg,xmem32,xmmreg [rmv:      vm32x vex.dds.128.66.0f38.w0 90 /r] AVX2,FUTURE */
        /* 374 262(002 001) 001(90) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPGATHERDD, 3, {XMMREG|RN_L16,XMEM|BITS32|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+54501, 469},
    /*   1 : VPGATHERDD ymmreg,ymem32,ymmreg [rmv:      vm32y vex.dds.256.66.0f38.w0 90 /r] AVX2,FUTURE */
        /* 375 262(002 005) 001(90) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPGATHERDD, 3, {YMMREG|RN_L16,YMEM|BITS32|RN_L16,YMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+54517, 469},
    /*   2 : VPGATHERDD xmmreg|mask,xmem32 [rm:t1s:   vsibx evex.128.66.0f38.w0 90 /r   ] AVX512,AVX512VL,FUTURE */
        /* 374 250(f2 7d 08) 306 001(90) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPGATHERDD, 2, {XMMREG,XMEM|BITS32,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+19903, 544},
    /*   3 : VPGATHERDD ymmreg|mask,ymem32 [rm:t1s:   vsiby evex.256.66.0f38.w0 90 /r   ] AVX512,AVX512VL,FUTURE */
        /* 375 250(f2 7d 28) 306 001(90) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPGATHERDD, 2, {YMMREG,YMEM|BITS32,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+19913, 544},
    /*   4 : VPGATHERDD zmmreg|mask,zmem32 [rm:t1s:   vsibz evex.512.66.0f38.w0 90 /r   ] AVX512,FUTURE */
        /* 376 250(f2 7d 48) 306 001(90) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPGATHERDD, 2, {ZMMREG,ZMEM|BITS32,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+19923, 545},
};

static const struct itemplate instrux_VPGATHERQD[5] = {
    /*   0 : VPGATHERQD xmmreg,xmem32,xmmreg [rmv:      vm64x vex.dds.128.66.0f38.w0 91 /r] AVX2,FUTURE */
        /* 374 262(002 001) 001(91) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPGATHERQD, 3, {XMMREG|RN_L16,XMEM|BITS32|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+54509, 469},
    /*   1 : VPGATHERQD xmmreg,ymem32,xmmreg [rmv:      vm64y vex.dds.256.66.0f38.w0 91 /r] AVX2,FUTURE */
        /* 375 262(002 005) 001(91) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPGATHERQD, 3, {XMMREG|RN_L16,YMEM|BITS32|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+54525, 469},
    /*   2 : VPGATHERQD xmmreg|mask,xmem32 [rm:t1s:   vsibx evex.128.66.0f38.w0 91 /r   ] AVX512,AVX512VL,FUTURE */
        /* 374 250(f2 7d 08) 306 001(91) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPGATHERQD, 2, {XMMREG,XMEM|BITS32,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+19963, 544},
    /*   3 : VPGATHERQD xmmreg|mask,ymem32 [rm:t1s:   vsiby evex.256.66.0f38.w0 91 /r   ] AVX512,AVX512VL,FUTURE */
        /* 375 250(f2 7d 28) 306 001(91) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPGATHERQD, 2, {XMMREG,YMEM|BITS32,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+19973, 544},
    /*   4 : VPGATHERQD ymmreg|mask,zmem32 [rm:t1s:   vsibz evex.512.66.0f38.w0 91 /r   ] AVX512,FUTURE */
        /* 376 250(f2 7d 48) 306 001(91) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPGATHERQD, 2, {YMMREG,ZMEM|BITS32,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+19983, 545},
};

static const struct itemplate instrux_VPGATHERDQ[5] = {
    /*   0 : VPGATHERDQ xmmreg,xmem64,xmmreg [rmv:      vm32x vex.dds.128.66.0f38.w1 90 /r] AVX2,FUTURE */
        /* 374 262(002 201) 001(90) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPGATHERDQ, 3, {XMMREG|RN_L16,XMEM|BITS64|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+54533, 469},
    /*   1 : VPGATHERDQ ymmreg,xmem64,ymmreg [rmv:      vm32x vex.dds.256.66.0f38.w1 90 /r] AVX2,FUTURE */
        /* 374 262(002 205) 001(90) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPGATHERDQ, 3, {YMMREG|RN_L16,XMEM|BITS64|RN_L16,YMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+54549, 469},
    /*   2 : VPGATHERDQ xmmreg|mask,xmem64 [rm:t1s:   vsibx evex.128.66.0f38.w1 90 /r   ] AVX512,AVX512VL,FUTURE */
        /* 374 250(f2 fd 08) 306 001(90) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPGATHERDQ, 2, {XMMREG,XMEM|BITS64,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+19933, 544},
    /*   3 : VPGATHERDQ ymmreg|mask,xmem64 [rm:t1s:   vsibx evex.256.66.0f38.w1 90 /r   ] AVX512,AVX512VL,FUTURE */
        /* 374 250(f2 fd 28) 306 001(90) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPGATHERDQ, 2, {YMMREG,XMEM|BITS64,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+19943, 544},
    /*   4 : VPGATHERDQ zmmreg|mask,ymem64 [rm:t1s:   vsiby evex.512.66.0f38.w1 90 /r   ] AVX512,FUTURE */
        /* 375 250(f2 fd 48) 306 001(90) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPGATHERDQ, 2, {ZMMREG,YMEM|BITS64,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+19953, 545},
};

static const struct itemplate instrux_VPGATHERQQ[5] = {
    /*   0 : VPGATHERQQ xmmreg,xmem64,xmmreg [rmv:      vm64x vex.dds.128.66.0f38.w1 91 /r] AVX2,FUTURE */
        /* 374 262(002 201) 001(91) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPGATHERQQ, 3, {XMMREG|RN_L16,XMEM|BITS64|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+54541, 469},
    /*   1 : VPGATHERQQ ymmreg,ymem64,ymmreg [rmv:      vm64y vex.dds.256.66.0f38.w1 91 /r] AVX2,FUTURE */
        /* 375 262(002 205) 001(91) 110 : NOAPX,VEX,AVX2,FUTURE */
        {I_VPGATHERQQ, 3, {YMMREG|RN_L16,YMEM|BITS64|RN_L16,YMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+54557, 469},
    /*   2 : VPGATHERQQ xmmreg|mask,xmem64 [rm:t1s:   vsibx evex.128.66.0f38.w1 91 /r   ] AVX512,AVX512VL,FUTURE */
        /* 374 250(f2 fd 08) 306 001(91) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPGATHERQQ, 2, {XMMREG,XMEM|BITS64,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+19993, 544},
    /*   3 : VPGATHERQQ ymmreg|mask,ymem64 [rm:t1s:   vsiby evex.256.66.0f38.w1 91 /r   ] AVX512,AVX512VL,FUTURE */
        /* 375 250(f2 fd 28) 306 001(91) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPGATHERQQ, 2, {YMMREG,YMEM|BITS64,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+20003, 544},
    /*   4 : VPGATHERQQ zmmreg|mask,zmem64 [rm:t1s:   vsibz evex.512.66.0f38.w1 91 /r   ] AVX512,FUTURE */
        /* 376 250(f2 fd 48) 306 001(91) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPGATHERQQ, 2, {ZMMREG,ZMEM|BITS64,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+20013, 545},
};

static const struct itemplate instrux_XABORT[1] = {
    /*   0 : XABORT imm8 [i:        c6 f8 ib                          ] RTM,FUTURE */
        /* 002(c6 f8) 020 : RTM,FUTURE */
        {I_XABORT, 1, {IMM_NORMAL|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72368, 470},
};

static const struct itemplate instrux_XBEGIN[4] = {
    /*   0 : XBEGIN imm16|near [i:        nw o16 c7 f8 rel                  ] AR0,OSIZE,NOREX,NOAPX,NOLONG,RTM,FUTURE */
        /* 327 320 002(c7 f8) 064 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,RTM,FUTURE */
        {I_XBEGIN, 1, {IMM_NORMAL|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+64663, 471},
    /*   1 : XBEGIN imm32|near [i:        nw o32 c7 f8 rel                  ] AR0,OSIZE,NOREX,NOAPX,NOLONG,RTM,FUTURE */
        /* 327 321 002(c7 f8) 064 : AR0,NWSIZE,OSIZE,NOREX,NOAPX,NOLONG,RTM,FUTURE */
        {I_XBEGIN, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+64670, 471},
    /*   2 : XBEGIN imm64|near [i:        nw o64 c7 f8 rel                  ] AR0,OSIZE,LONG,PROT,RTM,X86_64 */
        /* 327 324 002(c7 f8) 064 : AR0,NWSIZE,OSIZE,LONG,PROT,RTM,X86_64 */
        {I_XBEGIN, 1, {IMM_NORMAL|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+64677, 472},
    /*   3 : XBEGIN imm32|near [i:        nw o64 c7 f8 rel                  ] ND,AR0,SX,LONG,PROT,RTM,X86_64 */
        /* 327 324 002(c7 f8) 064 : AR0,NWSIZE,SX,LONG,PROT,RTM,X86_64 */
        {I_XBEGIN, 1, {IMM_NORMAL|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+64677, 473},
};

static const struct itemplate instrux_XEND[1] = {
    /*   0 : XEND void [          0f 01 d5                          ] RTM,FUTURE */
        /* 355 002(01 d5) : RTM,FUTURE */
        {I_XEND, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72373, 470},
};

static const struct itemplate instrux_XTEST[1] = {
    /*   0 : XTEST void [          0f 01 d6                          ] HLE,FL,RTM,FUTURE */
        /* 355 002(01 d6) : HLE,FL,RTM,FUTURE */
        {I_XTEST, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72378, 474},
};

static const struct itemplate instrux_PREFETCHWT1[1] = {
    /*   0 : PREFETCHWT1 mem8 [m:        0f 0d /2                          ] PREFETCHWT1,FUTURE */
        /* 355 001(0d) 202 : PREFETCHWT1,FUTURE */
        {I_PREFETCHWT1, 1, {MEMORY|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+72383, 475},
};

static const struct itemplate instrux_BNDMK[1] = {
    /*   0 : BNDMK bndreg,mem [rm:       f3 0f 1b /r                       ] MIB,MPX,FUTURE */
        /* 333 355 001(1b) 110 : MIB,MPX,FUTURE */
        {I_BNDMK, 2, {BNDREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+69872, 476},
};

static const struct itemplate instrux_BNDCL[3] = {
    /*   0 : BNDCL bndreg,mem [rm:       f3 0f 1a /r                       ] MPX,FUTURE */
        /* 333 355 001(1a) 110 : MPX,FUTURE */
        {I_BNDCL, 2, {BNDREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+64685, 477},
    /*   1 : BNDCL bndreg,reg32 [rm:       f3 0f 1a /r                       ] NOREX,NOAPX,NOLONG,MPX,FUTURE */
        /* 333 355 001(1a) 110 : NOREX,NOAPX,NOLONG,MPX,FUTURE */
        {I_BNDCL, 2, {BNDREG|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64685, 478},
    /*   2 : BNDCL bndreg,reg64 [rm:       o64nw f3 0f 1a /r                 ] LONG,PROT,MPX,X86_64 */
        /* 323 333 355 001(1a) 110 : NWSIZE,LONG,PROT,MPX,X86_64 */
        {I_BNDCL, 2, {BNDREG,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+64684, 479},
};

static const struct itemplate instrux_BNDCU[3] = {
    /*   0 : BNDCU bndreg,mem [rm:       f2 0f 1a /r                       ] MPX,FUTURE */
        /* 332 355 001(1a) 110 : MPX,FUTURE */
        {I_BNDCU, 2, {BNDREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+64692, 477},
    /*   1 : BNDCU bndreg,reg32 [rm:       f2 0f 1a /r                       ] NOREX,NOAPX,NOLONG,MPX,FUTURE */
        /* 332 355 001(1a) 110 : NOREX,NOAPX,NOLONG,MPX,FUTURE */
        {I_BNDCU, 2, {BNDREG|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64692, 478},
    /*   2 : BNDCU bndreg,reg64 [rm:       o64nw f2 0f 1a /r                 ] LONG,PROT,MPX,X86_64 */
        /* 323 332 355 001(1a) 110 : NWSIZE,LONG,PROT,MPX,X86_64 */
        {I_BNDCU, 2, {BNDREG,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+64691, 479},
};

static const struct itemplate instrux_BNDCN[3] = {
    /*   0 : BNDCN bndreg,mem [rm:       f2 0f 1b /r                       ] MPX,FUTURE */
        /* 332 355 001(1b) 110 : MPX,FUTURE */
        {I_BNDCN, 2, {BNDREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+64699, 477},
    /*   1 : BNDCN bndreg,reg32 [rm:       f2 0f 1b /r                       ] NOREX,NOAPX,NOLONG,MPX,FUTURE */
        /* 332 355 001(1b) 110 : NOREX,NOAPX,NOLONG,MPX,FUTURE */
        {I_BNDCN, 2, {BNDREG|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64699, 478},
    /*   2 : BNDCN bndreg,reg64 [rm:       o64nw f2 0f 1b /r                 ] LONG,PROT,MPX,X86_64 */
        /* 323 332 355 001(1b) 110 : NWSIZE,LONG,PROT,MPX,X86_64 */
        {I_BNDCN, 2, {BNDREG,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+64698, 479},
};

static const struct itemplate instrux_BNDMOV[4] = {
    /*   0 : BNDMOV bndreg,bndreg [rm:       66 0f 1a /r                       ] MPX,FUTURE */
        /* 361 355 001(1a) 110 : MPX,FUTURE */
        {I_BNDMOV, 2, {BNDREG,BNDREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+69878, 477},
    /*   1 : BNDMOV bndreg,mem [rm:       66 0f 1a /r                       ] MPX,FUTURE */
        /* 361 355 001(1a) 110 : MPX,FUTURE */
        {I_BNDMOV, 2, {BNDREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+69878, 477},
    /*   2 : BNDMOV bndreg,bndreg [mr:       66 0f 1b /r                       ] MPX,FUTURE */
        /* 361 355 001(1b) 101 : MPX,FUTURE */
        {I_BNDMOV, 2, {BNDREG,BNDREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+69884, 477},
    /*   3 : BNDMOV mem,bndreg [mr:       66 0f 1b /r                       ] MPX,FUTURE */
        /* 361 355 001(1b) 101 : MPX,FUTURE */
        {I_BNDMOV, 2, {MEMORY,BNDREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+69884, 477},
};

static const struct itemplate instrux_BNDLDX[3] = {
    /*   0 : BNDLDX bndreg,mem [rm:       0f 1a /r                          ] MIB,MPX,FUTURE */
        /* 355 001(1a) 110 : MIB,MPX,FUTURE */
        {I_BNDLDX, 2, {BNDREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+69879, 476},
    /*   1 : BNDLDX bndreg,mem,reg32 [rmx:      0f 1a /r                          ] NOREX,NOAPX,NOLONG,MIB,MPX,FUTURE */
        /* 355 001(1a) 016 110 : NOREX,NOAPX,NOLONG,MIB,MPX,FUTURE */
        {I_BNDLDX, 3, {BNDREG|RN_L16,MEMORY|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+69890, 480},
    /*   2 : BNDLDX bndreg,mem,reg64 [rmx:      0f 1a /r                          ] LONG,MIB,PROT,MPX,X86_64 */
        /* 355 001(1a) 016 110 : LONG,MIB,PROT,MPX,X86_64 */
        {I_BNDLDX, 3, {BNDREG,MEMORY,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+69890, 481},
};

static const struct itemplate instrux_BNDSTX[5] = {
    /*   0 : BNDSTX mem,bndreg [mr:       0f 1b /r                          ] MIB,MPX,FUTURE */
        /* 355 001(1b) 101 : MIB,MPX,FUTURE */
        {I_BNDSTX, 2, {MEMORY,BNDREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+69885, 476},
    /*   1 : BNDSTX mem,reg32,bndreg [mxr:      0f 1b /r                          ] NOREX,NOAPX,NOLONG,MIB,MPX,FUTURE */
        /* 355 001(1b) 015 102 : NOREX,NOAPX,NOLONG,MIB,MPX,FUTURE */
        {I_BNDSTX, 3, {MEMORY|RN_L16,REG_GPR|BITS32|RN_L16,BNDREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+69896, 480},
    /*   2 : BNDSTX mem,reg64,bndreg [mxr:      0f 1b /r                          ] LONG,MIB,PROT,MPX,X86_64 */
        /* 355 001(1b) 015 102 : LONG,MIB,PROT,MPX,X86_64 */
        {I_BNDSTX, 3, {MEMORY,REG_GPR|BITS64,BNDREG,0,0}, NO_DECORATOR, nasm_bytecodes+69896, 481},
    /*   3 : BNDSTX mem,bndreg,reg32 [mrx:      0f 1b /r                          ] NOREX,NOAPX,NOLONG,MIB,MPX,FUTURE */
        /* 355 001(1b) 016 101 : NOREX,NOAPX,NOLONG,MIB,MPX,FUTURE */
        {I_BNDSTX, 3, {MEMORY|RN_L16,BNDREG|RN_L16,REG_GPR|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+69902, 480},
    /*   4 : BNDSTX mem,bndreg,reg64 [mrx:      0f 1b /r                          ] LONG,MIB,PROT,MPX,X86_64 */
        /* 355 001(1b) 016 101 : LONG,MIB,PROT,MPX,X86_64 */
        {I_BNDSTX, 3, {MEMORY,BNDREG,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+69902, 481},
};

static const struct itemplate instrux_SHA1MSG1[1] = {
    /*   0 : SHA1MSG1 xmmreg,xmmrm128 [rm:       0f38 c9 /r                        ] SHA,FUTURE */
        /* 356 001(c9) 110 : NOAPX,SHA,FUTURE */
        {I_SHA1MSG1, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+72388, 482},
};

static const struct itemplate instrux_SHA1MSG2[1] = {
    /*   0 : SHA1MSG2 xmmreg,xmmrm128 [rm:       0f38 ca /r                        ] SHA,FUTURE */
        /* 356 001(ca) 110 : NOAPX,SHA,FUTURE */
        {I_SHA1MSG2, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+72393, 482},
};

static const struct itemplate instrux_SHA1NEXTE[1] = {
    /*   0 : SHA1NEXTE xmmreg,xmmrm128 [rm:       0f38 c8 /r                        ] SHA,FUTURE */
        /* 356 001(c8) 110 : NOAPX,SHA,FUTURE */
        {I_SHA1NEXTE, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+72398, 482},
};

static const struct itemplate instrux_SHA1RNDS4[1] = {
    /*   0 : SHA1RNDS4 xmmreg,xmmrm128,imm8 [rmi:      0f3a cc /r ib                     ] SHA,FUTURE */
        /* 357 001(cc) 110 022 : NOAPX,SHA,FUTURE */
        {I_SHA1RNDS4, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+69908, 482},
};

static const struct itemplate instrux_SHA256MSG1[1] = {
    /*   0 : SHA256MSG1 xmmreg,xmmrm128 [rm:       0f38 cc /r                        ] SHA,FUTURE */
        /* 356 001(cc) 110 : NOAPX,SHA,FUTURE */
        {I_SHA256MSG1, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+72403, 482},
};

static const struct itemplate instrux_SHA256MSG2[1] = {
    /*   0 : SHA256MSG2 xmmreg,xmmrm128 [rm:       0f38 cd /r                        ] SHA,FUTURE */
        /* 356 001(cd) 110 : NOAPX,SHA,FUTURE */
        {I_SHA256MSG2, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+72408, 482},
};

static const struct itemplate instrux_SHA256RNDS2[2] = {
    /*   0 : SHA256RNDS2 xmmreg,xmmrm128,xmm0 [rm-:      0f38 cb /r                        ] SHA,FUTURE */
        /* 356 001(cb) 110 : NOAPX,SHA,FUTURE */
        {I_SHA256RNDS2, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,XMMREG|RN_ZERO|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+72413, 482},
    /*   1 : SHA256RNDS2 xmmreg,xmmrm128 [rm:       0f38 cb /r                        ] SHA,FUTURE */
        /* 356 001(cb) 110 : NOAPX,SHA,FUTURE */
        {I_SHA256RNDS2, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+72413, 482},
};

static const struct itemplate instrux_VSHA512MSG1[1] = {
    /*   0 : VSHA512MSG1 ymmreg,xmmreg [rm:       vex.256.f2.0f38.w0 cc /r          ] AVX,SHA512,FUTURE */
        /* 270(002 007) 001(cc) 110 : NOAPX,VEX,AVX,SHA512,FUTURE */
        {I_VSHA512MSG1, 2, {YMMREG|RN_L16,XMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64705, 483},
};

static const struct itemplate instrux_VSHA512MSG2[1] = {
    /*   0 : VSHA512MSG2 ymmreg,ymmreg [rm:       vex.256.f2.0f38.w0 cd /r          ] AVX,SHA512,FUTURE */
        /* 270(002 007) 001(cd) 110 : NOAPX,VEX,AVX,SHA512,FUTURE */
        {I_VSHA512MSG2, 2, {YMMREG|RN_L16,YMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64712, 483},
};

static const struct itemplate instrux_VSHA512RNDS2[1] = {
    /*   0 : VSHA512RNDS2 ymmreg,ymmreg,xmmreg [rvm:      vex.nds.256.f2.0f38.w0 cb /r      ] AVX,SHA512,FUTURE */
        /* 261(002 007) 001(cb) 120 : NOAPX,VEX,AVX,SHA512,FUTURE */
        {I_VSHA512RNDS2, 3, {YMMREG|RN_L16,YMMREG|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64719, 483},
};

static const struct itemplate instrux_VSM3MSG1[1] = {
    /*   0 : VSM3MSG1 xmmreg,xmmreg,xmmreg [rvm:      vex.nds.128.p0.0f38.w0 da /r      ] AVX,HSM3,FUTURE */
        /* 261(002 000) 001(da) 120 : NOAPX,VEX,AVX,HSM3,FUTURE */
        {I_VSM3MSG1, 3, {XMMREG|RN_L16,XMMREG|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64726, 484},
};

static const struct itemplate instrux_VSM3MSG2[1] = {
    /*   0 : VSM3MSG2 xmmreg,xmmreg,xmmreg [rvm:      vex.nds.128.66.0f38.w0 da /r      ] AVX,HSM3,FUTURE */
        /* 261(002 001) 001(da) 120 : NOAPX,VEX,AVX,HSM3,FUTURE */
        {I_VSM3MSG2, 3, {XMMREG|RN_L16,XMMREG|RN_L16,XMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64733, 484},
};

static const struct itemplate instrux_VSM3RNDS2[1] = {
    /*   0 : VSM3RNDS2 xmmreg,xmmreg,xmmreg,imm8 [rvmi:     vex.nds.128.66.0f3a.w0 de /r ib   ] AVX,HSM3,FUTURE */
        /* 261(003 001) 001(de) 120 023 : NOAPX,VEX,AVX,HSM3,FUTURE */
        {I_VSM3RNDS2, 4, {XMMREG|RN_L16,XMMREG|RN_L16,XMMREG|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+54565, 484},
};

static const struct itemplate instrux_VSM4KEY4[5] = {
    /*   0 : VSM4KEY4 xmmreg,xmmreg,xmmrm128 [rvm:      vex.nds.128.f3.0f38.w0 da /r      ] AVX,HSM4,FUTURE */
        /* 261(002 002) 001(da) 120 : NOAPX,VEX,AVX,HSM4,FUTURE */
        {I_VSM4KEY4, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64740, 485},
    /*   1 : VSM4KEY4 ymmreg,ymmreg,ymmrm256 [rvm:      vex.nds.256.f3.0f38.w0 da /r      ] AVX,HSM4,FUTURE */
        /* 261(002 006) 001(da) 120 : NOAPX,VEX,AVX,HSM4,FUTURE */
        {I_VSM4KEY4, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64747, 485},
    /*   2 : VSM4KEY4 xmmreg,xmmreg,xmmrm128 [rvm:      evex.nds.128.f3.0f38.w0 da /r     ] AVX,HSM4,FUTURE */
        /* 241(f2 7e 08) 300 001(da) 120 : EVEX,PROT,AVX,HSM4,FUTURE */
        {I_VSM4KEY4, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+29610, 486},
    /*   3 : VSM4KEY4 ymmreg,ymmreg,ymmrm256 [rvm:      evex.nds.256.f3.0f38.w0 da /r     ] AVX,HSM4,FUTURE */
        /* 241(f2 7e 28) 300 001(da) 120 : EVEX,PROT,AVX,HSM4,FUTURE */
        {I_VSM4KEY4, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+29619, 486},
    /*   4 : VSM4KEY4 zmmreg,zmmreg,zmmrm512 [rvm:      evex.nds.512.f3.0f38.w0 da /r     ] AVX,HSM4,FUTURE */
        /* 241(f2 7e 48) 300 001(da) 120 : EVEX,PROT,AVX,HSM4,FUTURE */
        {I_VSM4KEY4, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, NO_DECORATOR, nasm_bytecodes+29628, 486},
};

static const struct itemplate instrux_VSM4RNDS4[5] = {
    /*   0 : VSM4RNDS4 xmmreg,xmmreg,xmmrm128 [rvm:      vex.nds.128.f2.0f38.w0 da /r      ] AVX,HSM4,FUTURE */
        /* 261(002 003) 001(da) 120 : NOAPX,VEX,AVX,HSM4,FUTURE */
        {I_VSM4RNDS4, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64754, 485},
    /*   1 : VSM4RNDS4 ymmreg,ymmreg,ymmrm256 [rvm:      vex.nds.256.f2.0f38.w0 da /r      ] AVX,HSM4,FUTURE */
        /* 261(002 007) 001(da) 120 : NOAPX,VEX,AVX,HSM4,FUTURE */
        {I_VSM4RNDS4, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64761, 485},
    /*   2 : VSM4RNDS4 xmmreg,xmmreg,xmmrm128 [rvm:      evex.nds.128.f2.0f38.w0 da /r     ] AVX,HSM4,FUTURE */
        /* 241(f2 7f 08) 300 001(da) 120 : EVEX,PROT,AVX,HSM4,FUTURE */
        {I_VSM4RNDS4, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+29637, 486},
    /*   3 : VSM4RNDS4 ymmreg,ymmreg,ymmrm256 [rvm:      evex.nds.256.f2.0f38.w0 da /r     ] AVX,HSM4,FUTURE */
        /* 241(f2 7f 28) 300 001(da) 120 : EVEX,PROT,AVX,HSM4,FUTURE */
        {I_VSM4RNDS4, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+29646, 486},
    /*   4 : VSM4RNDS4 zmmreg,zmmreg,zmmrm512 [rvm:      evex.nds.512.f2.0f38.w0 da /r     ] AVX,HSM4,FUTURE */
        /* 241(f2 7f 48) 300 001(da) 120 : EVEX,PROT,AVX,HSM4,FUTURE */
        {I_VSM4RNDS4, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, NO_DECORATOR, nasm_bytecodes+29655, 486},
};

static const struct itemplate instrux_VBCSTNEBF16PS[2] = {
    /*   0 : VBCSTNEBF16PS xmmreg,mem16 [rm:       vex.128.f3.0f38.w0 b1 /r          ] AR0-1,SW,AVXNECONVERT,FUTURE */
        /* 270(002 002) 001(b1) 110 : AR0,AR1,SW,NOAPX,VEX,AVXNECONVERT,FUTURE */
        {I_VBCSTNEBF16PS, 2, {XMMREG|RN_L16,MEMORY|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64768, 487},
    /*   1 : VBCSTNEBF16PS ymmreg,mem16 [rm:       vex.256.f3.0f38.w0 b1 /r          ] AR0-1,SW,AVXNECONVERT,FUTURE */
        /* 270(002 006) 001(b1) 110 : AR0,AR1,SW,NOAPX,VEX,AVXNECONVERT,FUTURE */
        {I_VBCSTNEBF16PS, 2, {YMMREG|RN_L16,MEMORY|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64775, 487},
};

static const struct itemplate instrux_VBCSTNEBF162PS[2] = {
    /*   0 : VBCSTNEBF162PS xmmreg,mem16 [rm:       vex.128.f3.0f38.w0 b1 /r          ] AR0-1,SW,AVXNECONVERT,FUTURE */
        /* 270(002 002) 001(b1) 110 : AR0,AR1,SW,NOAPX,VEX,AVXNECONVERT,FUTURE */
        {I_VBCSTNEBF162PS, 2, {XMMREG|RN_L16,MEMORY|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64768, 487},
    /*   1 : VBCSTNEBF162PS ymmreg,mem16 [rm:       vex.256.f3.0f38.w0 b1 /r          ] AR0-1,SW,AVXNECONVERT,FUTURE */
        /* 270(002 006) 001(b1) 110 : AR0,AR1,SW,NOAPX,VEX,AVXNECONVERT,FUTURE */
        {I_VBCSTNEBF162PS, 2, {YMMREG|RN_L16,MEMORY|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64775, 487},
};

static const struct itemplate instrux_VBCSTNESH2PS[2] = {
    /*   0 : VBCSTNESH2PS xmmreg,mem16 [rm:       vex.128.66.0f38.w0 b1 /r          ] AR0-1,SW,AVXNECONVERT,FUTURE */
        /* 270(002 001) 001(b1) 110 : AR0,AR1,SW,NOAPX,VEX,AVXNECONVERT,FUTURE */
        {I_VBCSTNESH2PS, 2, {XMMREG|RN_L16,MEMORY|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64782, 487},
    /*   1 : VBCSTNESH2PS ymmreg,mem16 [rm:       vex.256.66.0f38.w0 b1 /r          ] AR0-1,SW,AVXNECONVERT,FUTURE */
        /* 270(002 005) 001(b1) 110 : AR0,AR1,SW,NOAPX,VEX,AVXNECONVERT,FUTURE */
        {I_VBCSTNESH2PS, 2, {YMMREG|RN_L16,MEMORY|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64789, 487},
};

static const struct itemplate instrux_VCVTNEEBF162PS[2] = {
    /*   0 : VCVTNEEBF162PS xmmreg,mem128 [rm:       vex.128.f3.0f38.w0 b0 /r          ] AR0-1,SO,AVXNECONVERT,FUTURE */
        /* 270(002 002) 001(b0) 110 : AR0,AR1,SO,NOAPX,VEX,AVXNECONVERT,FUTURE */
        {I_VCVTNEEBF162PS, 2, {XMMREG|RN_L16,MEMORY|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64796, 488},
    /*   1 : VCVTNEEBF162PS ymmreg,mem256 [rm:       vex.256.f3.0f38.w0 b0 /r          ] AR0-1,SY,AVXNECONVERT,FUTURE */
        /* 270(002 006) 001(b0) 110 : AR0,AR1,SY,NOAPX,VEX,AVXNECONVERT,FUTURE */
        {I_VCVTNEEBF162PS, 2, {YMMREG|RN_L16,MEMORY|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64803, 489},
};

static const struct itemplate instrux_VCVTNEEPH2PS[2] = {
    /*   0 : VCVTNEEPH2PS xmmreg,mem128 [rm:       vex.128.66.0f38.w0 b0 /r          ] AR0-1,SO,AVXNECONVERT,FUTURE */
        /* 270(002 001) 001(b0) 110 : AR0,AR1,SO,NOAPX,VEX,AVXNECONVERT,FUTURE */
        {I_VCVTNEEPH2PS, 2, {XMMREG|RN_L16,MEMORY|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64810, 488},
    /*   1 : VCVTNEEPH2PS ymmreg,mem256 [rm:       vex.256.66.0f38.w0 b0 /r          ] AR0-1,SY,AVXNECONVERT,FUTURE */
        /* 270(002 005) 001(b0) 110 : AR0,AR1,SY,NOAPX,VEX,AVXNECONVERT,FUTURE */
        {I_VCVTNEEPH2PS, 2, {YMMREG|RN_L16,MEMORY|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64817, 489},
};

static const struct itemplate instrux_VCVTNEOBF162PS[2] = {
    /*   0 : VCVTNEOBF162PS xmmreg,mem128 [rm:       vex.128.f2.0f38.w0 b0 /r          ] AR0-1,SO,AVXNECONVERT,FUTURE */
        /* 270(002 003) 001(b0) 110 : AR0,AR1,SO,NOAPX,VEX,AVXNECONVERT,FUTURE */
        {I_VCVTNEOBF162PS, 2, {XMMREG|RN_L16,MEMORY|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64824, 488},
    /*   1 : VCVTNEOBF162PS ymmreg,mem256 [rm:       vex.256.f2.0f38.w0 b0 /r          ] AR0-1,SY,AVXNECONVERT,FUTURE */
        /* 270(002 007) 001(b0) 110 : AR0,AR1,SY,NOAPX,VEX,AVXNECONVERT,FUTURE */
        {I_VCVTNEOBF162PS, 2, {YMMREG|RN_L16,MEMORY|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64831, 489},
};

static const struct itemplate instrux_VCVTNEOPH2PS[2] = {
    /*   0 : VCVTNEOPH2PS xmmreg,mem128 [rm:       vex.128.np.0f38.w0 b0 /r          ] AR0-1,SO,AVXNECONVERT,FUTURE */
        /* 270(002 000) 001(b0) 110 : AR0,AR1,SO,NOAPX,VEX,AVXNECONVERT,FUTURE */
        {I_VCVTNEOPH2PS, 2, {XMMREG|RN_L16,MEMORY|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64838, 488},
    /*   1 : VCVTNEOPH2PS ymmreg,mem256 [rm:       vex.256.np.0f38.w0 b0 /r          ] AR0-1,SY,AVXNECONVERT,FUTURE */
        /* 270(002 004) 001(b0) 110 : AR0,AR1,SY,NOAPX,VEX,AVXNECONVERT,FUTURE */
        {I_VCVTNEOPH2PS, 2, {YMMREG|RN_L16,MEMORY|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64845, 489},
};

static const struct itemplate instrux_VCVTNEPS2BF16[5] = {
    /*   0 : VCVTNEPS2BF16 xmmreg,xmmrm128 [rm:       vex.128.f3.0f38.w0 72 /r          ] AR0-1,SO,LATEVEX,AVXNECONVERT,FUTURE */
        /* 270(002 002) 001(72) 110 : AR0,AR1,SO,LATEVEX,NOAPX,VEX,AVXNECONVERT,FUTURE */
        {I_VCVTNEPS2BF16, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64852, 490},
    /*   1 : VCVTNEPS2BF16 xmmreg,ymmrm256 [rm:       vex.256.f3.0f38.w0 72 /r          ] AR0-1,SY,LATEVEX,AVXNECONVERT,FUTURE */
        /* 270(002 006) 001(72) 110 : AR0,AR1,SY,LATEVEX,NOAPX,VEX,AVXNECONVERT,FUTURE */
        {I_VCVTNEPS2BF16, 2, {XMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+64859, 491},
    /*   2 : VCVTNEPS2BF16 xmmreg|mask|z,xmmrm128|b32 [rm:fv:    evex.128.f3.0f38.w0 72 /r         ] AVX512VL,AVX512BF16,FUTURE */
        /* 250(f2 7e 08) 301 001(72) 110 : EVEX,PROT,AVX512VL,AVX512BF16,FUTURE */
        {I_VCVTNEPS2BF16, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+45783, 614},
    /*   3 : VCVTNEPS2BF16 xmmreg|mask|z,ymmrm256|b32 [rm:fv:    evex.256.f3.0f38.w0 72 /r         ] AVX512VL,AVX512BF16,FUTURE */
        /* 250(f2 7e 28) 301 001(72) 110 : EVEX,PROT,AVX512VL,AVX512BF16,FUTURE */
        {I_VCVTNEPS2BF16, 2, {XMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+45792, 614},
    /*   4 : VCVTNEPS2BF16 ymmreg|mask|z,zmmrm512|b32 [rm:fv:    evex.512.f3.0f38.w0 72 /r         ] AVX512BF16,FUTURE */
        /* 250(f2 7e 48) 301 001(72) 110 : EVEX,PROT,AVX512BF16,FUTURE */
        {I_VCVTNEPS2BF16, 2, {YMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+45801, 615},
};

static const struct itemplate instrux_VPDPBUSD[8] = {
    /*   0 : VPDPBUSD xmmreg,xmmreg,xmmrm128 [rvm:      vex.128.66.0f38.w0 50 /r          ] AR0-2,SO,LATEVEX,AVXVNNI,FUTURE */
        /* 261(002 001) 001(50) 120 : AR0,AR1,AR2,SO,LATEVEX,NOAPX,VEX,AVXVNNI,FUTURE */
        {I_VPDPBUSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64866, 492},
    /*   1 : VPDPBUSD ymmreg,ymmreg,ymmrm256 [rvm:      vex.256.66.0f38.w0 50 /r          ] AR0-2,SY,LATEVEX,AVXVNNI,FUTURE */
        /* 261(002 005) 001(50) 120 : AR0,AR1,AR2,SY,LATEVEX,NOAPX,VEX,AVXVNNI,FUTURE */
        {I_VPDPBUSD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64873, 493},
    /*   2 : VPDPBUSD xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.dds.128.66.0f38.w0 50 /r     ] AVX512VL,AVX512VNNI,FUTURE */
        /* 241(f2 7d 08) 301 001(50) 120 : EVEX,PROT,AVX512VL,AVX512VNNI,FUTURE */
        {I_VPDPBUSD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+45270, 589},
    /*   3 : VPDPBUSD xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.dds.128.66.0f38.w0 50 /r     ] ND,AVX512VL,AVX512VNNI,FUTURE */
        /* 240(f2 7d 08) 301 001(50) 110 : EVEX,PROT,AVX512VL,AVX512VNNI,FUTURE */
        {I_VPDPBUSD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+45279, 589},
    /*   4 : VPDPBUSD ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.dds.256.66.0f38.w0 50 /r     ] AVX512VL,AVX512VNNI,FUTURE */
        /* 241(f2 7d 28) 301 001(50) 120 : EVEX,PROT,AVX512VL,AVX512VNNI,FUTURE */
        {I_VPDPBUSD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+45288, 589},
    /*   5 : VPDPBUSD ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.dds.256.66.0f38.w0 50 /r     ] ND,AVX512VL,AVX512VNNI,FUTURE */
        /* 240(f2 7d 28) 301 001(50) 110 : EVEX,PROT,AVX512VL,AVX512VNNI,FUTURE */
        {I_VPDPBUSD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+45297, 589},
    /*   6 : VPDPBUSD zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv:   evex.dds.512.66.0f38.w0 50 /r     ] AVX512VNNI,FUTURE */
        /* 241(f2 7d 48) 301 001(50) 120 : EVEX,PROT,AVX512VNNI,FUTURE */
        {I_VPDPBUSD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+45306, 590},
    /*   7 : VPDPBUSD zmmreg|mask|z,zmmrm512|b32 [r+vm:fv:   evex.dds.512.66.0f38.w0 50 /r     ] ND,AVX512VNNI,FUTURE */
        /* 240(f2 7d 48) 301 001(50) 110 : EVEX,PROT,AVX512VNNI,FUTURE */
        {I_VPDPBUSD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+45315, 590},
};

static const struct itemplate instrux_VPDPBUSDS[8] = {
    /*   0 : VPDPBUSDS xmmreg,xmmreg,xmmrm128 [rvm:      vex.128.66.0f38.w0 51 /r          ] AR0-2,SO,LATEVEX,AVXVNNI,FUTURE */
        /* 261(002 001) 001(51) 120 : AR0,AR1,AR2,SO,LATEVEX,NOAPX,VEX,AVXVNNI,FUTURE */
        {I_VPDPBUSDS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64880, 492},
    /*   1 : VPDPBUSDS ymmreg,ymmreg,ymmrm256 [rvm:      vex.256.66.0f38.w0 51 /r          ] AR0-2,SY,LATEVEX,AVXVNNI,FUTURE */
        /* 261(002 005) 001(51) 120 : AR0,AR1,AR2,SY,LATEVEX,NOAPX,VEX,AVXVNNI,FUTURE */
        {I_VPDPBUSDS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64887, 493},
    /*   2 : VPDPBUSDS xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.dds.128.66.0f38.w0 51 /r     ] AVX512VL,AVX512VNNI,FUTURE */
        /* 241(f2 7d 08) 301 001(51) 120 : EVEX,PROT,AVX512VL,AVX512VNNI,FUTURE */
        {I_VPDPBUSDS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+45324, 589},
    /*   3 : VPDPBUSDS xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.dds.128.66.0f38.w0 51 /r     ] ND,AVX512VL,AVX512VNNI,FUTURE */
        /* 240(f2 7d 08) 301 001(51) 110 : EVEX,PROT,AVX512VL,AVX512VNNI,FUTURE */
        {I_VPDPBUSDS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+45333, 589},
    /*   4 : VPDPBUSDS ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.dds.256.66.0f38.w0 51 /r     ] AVX512VL,AVX512VNNI,FUTURE */
        /* 241(f2 7d 28) 301 001(51) 120 : EVEX,PROT,AVX512VL,AVX512VNNI,FUTURE */
        {I_VPDPBUSDS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+45342, 589},
    /*   5 : VPDPBUSDS ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.dds.256.66.0f38.w0 51 /r     ] ND,AVX512VL,AVX512VNNI,FUTURE */
        /* 240(f2 7d 28) 301 001(51) 110 : EVEX,PROT,AVX512VL,AVX512VNNI,FUTURE */
        {I_VPDPBUSDS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+45351, 589},
    /*   6 : VPDPBUSDS zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv:   evex.dds.512.66.0f38.w0 51 /r     ] AVX512VNNI,FUTURE */
        /* 241(f2 7d 48) 301 001(51) 120 : EVEX,PROT,AVX512VNNI,FUTURE */
        {I_VPDPBUSDS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+45360, 590},
    /*   7 : VPDPBUSDS zmmreg|mask|z,zmmrm512|b32 [r+vm:fv:   evex.dds.512.66.0f38.w0 51 /r     ] ND,AVX512VNNI,FUTURE */
        /* 240(f2 7d 48) 301 001(51) 110 : EVEX,PROT,AVX512VNNI,FUTURE */
        {I_VPDPBUSDS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+45369, 590},
};

static const struct itemplate instrux_VPDPWSSD[8] = {
    /*   0 : VPDPWSSD xmmreg,xmmreg,xmmrm128 [rvm:      vex.128.66.0f38.w0 52 /r          ] AR0-2,SO,LATEVEX,AVXVNNI,FUTURE */
        /* 261(002 001) 001(52) 120 : AR0,AR1,AR2,SO,LATEVEX,NOAPX,VEX,AVXVNNI,FUTURE */
        {I_VPDPWSSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64894, 492},
    /*   1 : VPDPWSSD ymmreg,ymmreg,ymmrm256 [rvm:      vex.256.66.0f38.w0 52 /r          ] AR0-2,SY,LATEVEX,AVXVNNI,FUTURE */
        /* 261(002 005) 001(52) 120 : AR0,AR1,AR2,SY,LATEVEX,NOAPX,VEX,AVXVNNI,FUTURE */
        {I_VPDPWSSD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64901, 493},
    /*   2 : VPDPWSSD xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.dds.128.66.0f38.w0 52 /r     ] AVX512VL,AVX512VNNI,FUTURE */
        /* 241(f2 7d 08) 301 001(52) 120 : EVEX,PROT,AVX512VL,AVX512VNNI,FUTURE */
        {I_VPDPWSSD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+45378, 589},
    /*   3 : VPDPWSSD xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.dds.128.66.0f38.w0 52 /r     ] ND,AVX512VL,AVX512VNNI,FUTURE */
        /* 240(f2 7d 08) 301 001(52) 110 : EVEX,PROT,AVX512VL,AVX512VNNI,FUTURE */
        {I_VPDPWSSD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+45387, 589},
    /*   4 : VPDPWSSD ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.dds.256.66.0f38.w0 52 /r     ] AVX512VL,AVX512VNNI,FUTURE */
        /* 241(f2 7d 28) 301 001(52) 120 : EVEX,PROT,AVX512VL,AVX512VNNI,FUTURE */
        {I_VPDPWSSD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+45396, 589},
    /*   5 : VPDPWSSD ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.dds.256.66.0f38.w0 52 /r     ] ND,AVX512VL,AVX512VNNI,FUTURE */
        /* 240(f2 7d 28) 301 001(52) 110 : EVEX,PROT,AVX512VL,AVX512VNNI,FUTURE */
        {I_VPDPWSSD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+45405, 589},
    /*   6 : VPDPWSSD zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv:   evex.dds.512.66.0f38.w0 52 /r     ] AVX512VNNI,FUTURE */
        /* 241(f2 7d 48) 301 001(52) 120 : EVEX,PROT,AVX512VNNI,FUTURE */
        {I_VPDPWSSD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+45414, 590},
    /*   7 : VPDPWSSD zmmreg|mask|z,zmmrm512|b32 [r+vm:fv:   evex.dds.512.66.0f38.w0 52 /r     ] ND,AVX512VNNI,FUTURE */
        /* 240(f2 7d 48) 301 001(52) 110 : EVEX,PROT,AVX512VNNI,FUTURE */
        {I_VPDPWSSD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+45423, 590},
};

static const struct itemplate instrux_VPDPWSSDS[8] = {
    /*   0 : VPDPWSSDS xmmreg,xmmreg,xmmrm128 [rvm:      vex.128.66.0f38.w0 53 /r          ] AR0-2,SO,LATEVEX,AVXVNNI,FUTURE */
        /* 261(002 001) 001(53) 120 : AR0,AR1,AR2,SO,LATEVEX,NOAPX,VEX,AVXVNNI,FUTURE */
        {I_VPDPWSSDS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64908, 492},
    /*   1 : VPDPWSSDS ymmreg,ymmreg,ymmrm256 [rvm:      vex.256.66.0f38.w0 53 /r          ] AR0-2,SY,LATEVEX,AVXVNNI,FUTURE */
        /* 261(002 005) 001(53) 120 : AR0,AR1,AR2,SY,LATEVEX,NOAPX,VEX,AVXVNNI,FUTURE */
        {I_VPDPWSSDS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64915, 493},
    /*   2 : VPDPWSSDS xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.dds.128.66.0f38.w0 53 /r     ] AVX512VL,AVX512VNNI,FUTURE */
        /* 241(f2 7d 08) 301 001(53) 120 : EVEX,PROT,AVX512VL,AVX512VNNI,FUTURE */
        {I_VPDPWSSDS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+45432, 589},
    /*   3 : VPDPWSSDS xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.dds.128.66.0f38.w0 53 /r     ] ND,AVX512VL,AVX512VNNI,FUTURE */
        /* 240(f2 7d 08) 301 001(53) 110 : EVEX,PROT,AVX512VL,AVX512VNNI,FUTURE */
        {I_VPDPWSSDS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+45441, 589},
    /*   4 : VPDPWSSDS ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.dds.256.66.0f38.w0 53 /r     ] AVX512VL,AVX512VNNI,FUTURE */
        /* 241(f2 7d 28) 301 001(53) 120 : EVEX,PROT,AVX512VL,AVX512VNNI,FUTURE */
        {I_VPDPWSSDS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+45450, 589},
    /*   5 : VPDPWSSDS ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.dds.256.66.0f38.w0 53 /r     ] ND,AVX512VL,AVX512VNNI,FUTURE */
        /* 240(f2 7d 28) 301 001(53) 110 : EVEX,PROT,AVX512VL,AVX512VNNI,FUTURE */
        {I_VPDPWSSDS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+45459, 589},
    /*   6 : VPDPWSSDS zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv:   evex.dds.512.66.0f38.w0 53 /r     ] AVX512VNNI,FUTURE */
        /* 241(f2 7d 48) 301 001(53) 120 : EVEX,PROT,AVX512VNNI,FUTURE */
        {I_VPDPWSSDS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+45468, 590},
    /*   7 : VPDPWSSDS zmmreg|mask|z,zmmrm512|b32 [r+vm:fv:   evex.dds.512.66.0f38.w0 53 /r     ] ND,AVX512VNNI,FUTURE */
        /* 240(f2 7d 48) 301 001(53) 110 : EVEX,PROT,AVX512VNNI,FUTURE */
        {I_VPDPWSSDS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+45477, 590},
};

static const struct itemplate instrux_VPDPBSSD[5] = {
    /*   0 : VPDPBSSD xmmreg,xmmreg,xmmrm128 [rvm:      vex.128.f2.0f38.w0 50 /r          ] AR0-2,SO,LATEVEX,AVX,AVXVNNIINT8,FUTURE */
        /* 261(002 003) 001(50) 120 : AR0,AR1,AR2,SO,LATEVEX,NOAPX,VEX,AVX,AVXVNNIINT8,FUTURE */
        {I_VPDPBSSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64922, 494},
    /*   1 : VPDPBSSD ymmreg,ymmreg,ymmrm256 [rvm:      vex.256.f2.0f38.w0 50 /r          ] AR0-2,SY,LATEVEX,AVX,AVXVNNIINT8,FUTURE */
        /* 261(002 007) 001(50) 120 : AR0,AR1,AR2,SY,LATEVEX,NOAPX,VEX,AVX,AVXVNNIINT8,FUTURE */
        {I_VPDPBSSD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64929, 495},
    /*   2 : VPDPBSSD xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv:   evex.128.f2.0f38.w0 50 /r         ] AVX10_2,AVX10_VNNIINT,FUTURE */
        /* 241(f2 7f 08) 301 001(50) 120 : EVEX,PROT,AVX10_2,AVX10_VNNIINT,FUTURE */
        {I_VPDPBSSD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+50121, 647},
    /*   3 : VPDPBSSD ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv:   evex.256.f2.0f38.w0 50 /r         ] AVX10_2,AVX10_VNNIINT,FUTURE */
        /* 241(f2 7f 28) 301 001(50) 120 : EVEX,PROT,AVX10_2,AVX10_VNNIINT,FUTURE */
        {I_VPDPBSSD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+50130, 647},
    /*   4 : VPDPBSSD zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv:   evex.512.f2.0f38.w0 50 /r         ] AVX10_2,AVX10_VNNIINT,FUTURE */
        /* 241(f2 7f 48) 301 001(50) 120 : EVEX,PROT,AVX10_2,AVX10_VNNIINT,FUTURE */
        {I_VPDPBSSD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+50139, 647},
};

static const struct itemplate instrux_VPDPBSSDS[5] = {
    /*   0 : VPDPBSSDS xmmreg,xmmreg,xmmrm128 [rvm:      vex.128.f2.0f38.w0 51 /r          ] AR0-2,SO,LATEVEX,AVX,AVXVNNIINT8,FUTURE */
        /* 261(002 003) 001(51) 120 : AR0,AR1,AR2,SO,LATEVEX,NOAPX,VEX,AVX,AVXVNNIINT8,FUTURE */
        {I_VPDPBSSDS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64936, 494},
    /*   1 : VPDPBSSDS ymmreg,ymmreg,ymmrm256 [rvm:      vex.256.f2.0f38.w0 51 /r          ] AR0-2,SY,LATEVEX,AVX,AVXVNNIINT8,FUTURE */
        /* 261(002 007) 001(51) 120 : AR0,AR1,AR2,SY,LATEVEX,NOAPX,VEX,AVX,AVXVNNIINT8,FUTURE */
        {I_VPDPBSSDS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64943, 495},
    /*   2 : VPDPBSSDS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv:   evex.128.f2.0f38.w0 51 /r         ] AVX10_2,AVX10_VNNIINT,FUTURE */
        /* 241(f2 7f 08) 301 001(51) 120 : EVEX,PROT,AVX10_2,AVX10_VNNIINT,FUTURE */
        {I_VPDPBSSDS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+50148, 647},
    /*   3 : VPDPBSSDS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv:   evex.256.f2.0f38.w0 51 /r         ] AVX10_2,AVX10_VNNIINT,FUTURE */
        /* 241(f2 7f 28) 301 001(51) 120 : EVEX,PROT,AVX10_2,AVX10_VNNIINT,FUTURE */
        {I_VPDPBSSDS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+50157, 647},
    /*   4 : VPDPBSSDS zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv:   evex.512.f2.0f38.w0 51 /r         ] AVX10_2,AVX10_VNNIINT,FUTURE */
        /* 241(f2 7f 48) 301 001(51) 120 : EVEX,PROT,AVX10_2,AVX10_VNNIINT,FUTURE */
        {I_VPDPBSSDS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+50166, 647},
};

static const struct itemplate instrux_VPDPBSUD[5] = {
    /*   0 : VPDPBSUD xmmreg,xmmreg,xmmrm128 [rvm:      vex.128.f3.0f38.w0 50 /r          ] AR0-2,SO,LATEVEX,AVX,AVXVNNIINT8,FUTURE */
        /* 261(002 002) 001(50) 120 : AR0,AR1,AR2,SO,LATEVEX,NOAPX,VEX,AVX,AVXVNNIINT8,FUTURE */
        {I_VPDPBSUD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64950, 494},
    /*   1 : VPDPBSUD ymmreg,ymmreg,ymmrm256 [rvm:      vex.256.f3.0f38.w0 50 /r          ] AR0-2,SY,LATEVEX,AVX,AVXVNNIINT8,FUTURE */
        /* 261(002 006) 001(50) 120 : AR0,AR1,AR2,SY,LATEVEX,NOAPX,VEX,AVX,AVXVNNIINT8,FUTURE */
        {I_VPDPBSUD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64957, 495},
    /*   2 : VPDPBSUD xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv:   evex.128.f3.0f38.w0 50 /r         ] AVX10_2,AVX10_VNNIINT,FUTURE */
        /* 241(f2 7e 08) 301 001(50) 120 : EVEX,PROT,AVX10_2,AVX10_VNNIINT,FUTURE */
        {I_VPDPBSUD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+50175, 647},
    /*   3 : VPDPBSUD ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv:   evex.256.f3.0f38.w0 50 /r         ] AVX10_2,AVX10_VNNIINT,FUTURE */
        /* 241(f2 7e 28) 301 001(50) 120 : EVEX,PROT,AVX10_2,AVX10_VNNIINT,FUTURE */
        {I_VPDPBSUD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+50184, 647},
    /*   4 : VPDPBSUD zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv:   evex.512.f3.0f38.w0 50 /r         ] AVX10_2,AVX10_VNNIINT,FUTURE */
        /* 241(f2 7e 48) 301 001(50) 120 : EVEX,PROT,AVX10_2,AVX10_VNNIINT,FUTURE */
        {I_VPDPBSUD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+50193, 647},
};

static const struct itemplate instrux_VPDPBSUDS[5] = {
    /*   0 : VPDPBSUDS xmmreg,xmmreg,xmmrm128 [rvm:      vex.128.f3.0f38.w0 51 /r          ] AR0-2,SO,LATEVEX,AVX,AVXVNNIINT8,FUTURE */
        /* 261(002 002) 001(51) 120 : AR0,AR1,AR2,SO,LATEVEX,NOAPX,VEX,AVX,AVXVNNIINT8,FUTURE */
        {I_VPDPBSUDS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64964, 494},
    /*   1 : VPDPBSUDS ymmreg,ymmreg,ymmrm256 [rvm:      vex.256.f3.0f38.w0 51 /r          ] AR0-2,SY,LATEVEX,AVX,AVXVNNIINT8,FUTURE */
        /* 261(002 006) 001(51) 120 : AR0,AR1,AR2,SY,LATEVEX,NOAPX,VEX,AVX,AVXVNNIINT8,FUTURE */
        {I_VPDPBSUDS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64971, 495},
    /*   2 : VPDPBSUDS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv:   evex.128.f3.0f38.w0 51 /r         ] AVX10_2,AVX10_VNNIINT,FUTURE */
        /* 241(f2 7e 08) 301 001(51) 120 : EVEX,PROT,AVX10_2,AVX10_VNNIINT,FUTURE */
        {I_VPDPBSUDS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+50202, 647},
    /*   3 : VPDPBSUDS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv:   evex.256.f3.0f38.w0 51 /r         ] AVX10_2,AVX10_VNNIINT,FUTURE */
        /* 241(f2 7e 28) 301 001(51) 120 : EVEX,PROT,AVX10_2,AVX10_VNNIINT,FUTURE */
        {I_VPDPBSUDS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+50211, 647},
    /*   4 : VPDPBSUDS zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv:   evex.512.f3.0f38.w0 51 /r         ] AVX10_2,AVX10_VNNIINT,FUTURE */
        /* 241(f2 7e 48) 301 001(51) 120 : EVEX,PROT,AVX10_2,AVX10_VNNIINT,FUTURE */
        {I_VPDPBSUDS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+50220, 647},
};

static const struct itemplate instrux_VPDPBUUD[5] = {
    /*   0 : VPDPBUUD xmmreg,xmmreg,xmmrm128 [rvm:      vex.128.np.0f38.w0 50 /r          ] AR0-2,SO,LATEVEX,AVX,AVXVNNIINT8,FUTURE */
        /* 261(002 000) 001(50) 120 : AR0,AR1,AR2,SO,LATEVEX,NOAPX,VEX,AVX,AVXVNNIINT8,FUTURE */
        {I_VPDPBUUD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64978, 494},
    /*   1 : VPDPBUUD ymmreg,ymmreg,ymmrm256 [rvm:      vex.256.np.0f38.w0 50 /r          ] AR0-2,SY,LATEVEX,AVX,AVXVNNIINT8,FUTURE */
        /* 261(002 004) 001(50) 120 : AR0,AR1,AR2,SY,LATEVEX,NOAPX,VEX,AVX,AVXVNNIINT8,FUTURE */
        {I_VPDPBUUD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64985, 495},
    /*   2 : VPDPBUUD xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv:   evex.128.np.0f38.w0 50 /r         ] AVX10_2,AVX10_VNNIINT,FUTURE */
        /* 241(f2 7c 08) 301 001(50) 120 : EVEX,PROT,AVX10_2,AVX10_VNNIINT,FUTURE */
        {I_VPDPBUUD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+50229, 647},
    /*   3 : VPDPBUUD ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv:   evex.256.np.0f38.w0 50 /r         ] AVX10_2,AVX10_VNNIINT,FUTURE */
        /* 241(f2 7c 28) 301 001(50) 120 : EVEX,PROT,AVX10_2,AVX10_VNNIINT,FUTURE */
        {I_VPDPBUUD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+50238, 647},
    /*   4 : VPDPBUUD zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv:   evex.512.np.0f38.w0 50 /r         ] AVX10_2,AVX10_VNNIINT,FUTURE */
        /* 241(f2 7c 48) 301 001(50) 120 : EVEX,PROT,AVX10_2,AVX10_VNNIINT,FUTURE */
        {I_VPDPBUUD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+50247, 647},
};

static const struct itemplate instrux_VPDPBUUDS[5] = {
    /*   0 : VPDPBUUDS xmmreg,xmmreg,xmmrm128 [rvm:      vex.128.np.0f38.w0 51 /r          ] AR0-2,SO,LATEVEX,AVX,AVXVNNIINT8,FUTURE */
        /* 261(002 000) 001(51) 120 : AR0,AR1,AR2,SO,LATEVEX,NOAPX,VEX,AVX,AVXVNNIINT8,FUTURE */
        {I_VPDPBUUDS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64992, 494},
    /*   1 : VPDPBUUDS ymmreg,ymmreg,ymmrm256 [rvm:      vex.256.np.0f38.w0 51 /r          ] AR0-2,SY,LATEVEX,AVX,AVXVNNIINT8,FUTURE */
        /* 261(002 004) 001(51) 120 : AR0,AR1,AR2,SY,LATEVEX,NOAPX,VEX,AVX,AVXVNNIINT8,FUTURE */
        {I_VPDPBUUDS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+64999, 495},
    /*   2 : VPDPBUUDS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv:   evex.128.np.0f38.w0 51 /r         ] AVX10_2,AVX10_VNNIINT,FUTURE */
        /* 241(f2 7c 08) 301 001(51) 120 : EVEX,PROT,AVX10_2,AVX10_VNNIINT,FUTURE */
        {I_VPDPBUUDS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+50256, 647},
    /*   3 : VPDPBUUDS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv:   evex.256.np.0f38.w0 51 /r         ] AVX10_2,AVX10_VNNIINT,FUTURE */
        /* 241(f2 7c 28) 301 001(51) 120 : EVEX,PROT,AVX10_2,AVX10_VNNIINT,FUTURE */
        {I_VPDPBUUDS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+50265, 647},
    /*   4 : VPDPBUUDS zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv:   evex.512.np.0f38.w0 51 /r         ] AVX10_2,AVX10_VNNIINT,FUTURE */
        /* 241(f2 7c 48) 301 001(51) 120 : EVEX,PROT,AVX10_2,AVX10_VNNIINT,FUTURE */
        {I_VPDPBUUDS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+50274, 647},
};

static const struct itemplate instrux_VPDPWSUD[5] = {
    /*   0 : VPDPWSUD xmmreg,xmmreg,xmmrm128 [rvm:      vex.128.f3.0f38.w0 d2 /r          ] AR0-2,SO,LATEVEX,AVX,AVXVNNIINT16,FUTURE */
        /* 261(002 002) 001(d2) 120 : AR0,AR1,AR2,SO,LATEVEX,NOAPX,VEX,AVX,AVXVNNIINT16,FUTURE */
        {I_VPDPWSUD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65006, 496},
    /*   1 : VPDPWSUD ymmreg,ymmreg,ymmrm256 [rvm:      vex.256.f3.0f38.w0 d2 /r          ] AR0-2,SY,LATEVEX,AVX,AVXVNNIINT16,FUTURE */
        /* 261(002 006) 001(d2) 120 : AR0,AR1,AR2,SY,LATEVEX,NOAPX,VEX,AVX,AVXVNNIINT16,FUTURE */
        {I_VPDPWSUD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65013, 497},
    /*   2 : VPDPWSUD xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv:   evex.128.f3.0f38.w0 d2 /r         ] AVX10_2,AVX10_VNNIINT,FUTURE */
        /* 241(f2 7e 08) 301 001(d2) 120 : EVEX,PROT,AVX10_2,AVX10_VNNIINT,FUTURE */
        {I_VPDPWSUD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+50283, 647},
    /*   3 : VPDPWSUD ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv:   evex.256.f3.0f38.w0 d2 /r         ] AVX10_2,AVX10_VNNIINT,FUTURE */
        /* 241(f2 7e 28) 301 001(d2) 120 : EVEX,PROT,AVX10_2,AVX10_VNNIINT,FUTURE */
        {I_VPDPWSUD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+50292, 647},
    /*   4 : VPDPWSUD zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv:   evex.512.f3.0f38.w0 d2 /r         ] AVX10_2,AVX10_VNNIINT,FUTURE */
        /* 241(f2 7e 48) 301 001(d2) 120 : EVEX,PROT,AVX10_2,AVX10_VNNIINT,FUTURE */
        {I_VPDPWSUD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+50301, 647},
};

static const struct itemplate instrux_VPDPWSUDS[5] = {
    /*   0 : VPDPWSUDS xmmreg,xmmreg,xmmrm128 [rvm:      vex.128.f3.0f38.w0 d3 /r          ] AR0-2,SO,LATEVEX,AVX,AVXVNNIINT16,FUTURE */
        /* 261(002 002) 001(d3) 120 : AR0,AR1,AR2,SO,LATEVEX,NOAPX,VEX,AVX,AVXVNNIINT16,FUTURE */
        {I_VPDPWSUDS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65020, 496},
    /*   1 : VPDPWSUDS ymmreg,ymmreg,ymmrm256 [rvm:      vex.256.f3.0f38.w0 d3 /r          ] AR0-2,SY,LATEVEX,AVX,AVXVNNIINT16,FUTURE */
        /* 261(002 006) 001(d3) 120 : AR0,AR1,AR2,SY,LATEVEX,NOAPX,VEX,AVX,AVXVNNIINT16,FUTURE */
        {I_VPDPWSUDS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65027, 497},
    /*   2 : VPDPWSUDS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv:   evex.128.f3.0f38.w0 d3 /r         ] AVX10_2,AVX10_VNNIINT,FUTURE */
        /* 241(f2 7e 08) 301 001(d3) 120 : EVEX,PROT,AVX10_2,AVX10_VNNIINT,FUTURE */
        {I_VPDPWSUDS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+50310, 647},
    /*   3 : VPDPWSUDS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv:   evex.256.f3.0f38.w0 d3 /r         ] AVX10_2,AVX10_VNNIINT,FUTURE */
        /* 241(f2 7e 28) 301 001(d3) 120 : EVEX,PROT,AVX10_2,AVX10_VNNIINT,FUTURE */
        {I_VPDPWSUDS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+50319, 647},
    /*   4 : VPDPWSUDS zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv:   evex.512.f3.0f38.w0 d3 /r         ] AVX10_2,AVX10_VNNIINT,FUTURE */
        /* 241(f2 7e 48) 301 001(d3) 120 : EVEX,PROT,AVX10_2,AVX10_VNNIINT,FUTURE */
        {I_VPDPWSUDS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+50328, 647},
};

static const struct itemplate instrux_VPDPWUSD[5] = {
    /*   0 : VPDPWUSD xmmreg,xmmreg,xmmrm128 [rvm:      vex.128.66.0f38.w0 d2 /r          ] AR0-2,SO,LATEVEX,AVX,AVXVNNIINT16,FUTURE */
        /* 261(002 001) 001(d2) 120 : AR0,AR1,AR2,SO,LATEVEX,NOAPX,VEX,AVX,AVXVNNIINT16,FUTURE */
        {I_VPDPWUSD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65034, 496},
    /*   1 : VPDPWUSD ymmreg,ymmreg,ymmrm256 [rvm:      vex.256.66.0f38.w0 d2 /r          ] AR0-2,SY,LATEVEX,AVX,AVXVNNIINT16,FUTURE */
        /* 261(002 005) 001(d2) 120 : AR0,AR1,AR2,SY,LATEVEX,NOAPX,VEX,AVX,AVXVNNIINT16,FUTURE */
        {I_VPDPWUSD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65041, 497},
    /*   2 : VPDPWUSD xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv:   evex.128.66.0f38.w0 d2 /r         ] AVX10_2,AVX10_VNNIINT,FUTURE */
        /* 241(f2 7d 08) 301 001(d2) 120 : EVEX,PROT,AVX10_2,AVX10_VNNIINT,FUTURE */
        {I_VPDPWUSD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+50337, 647},
    /*   3 : VPDPWUSD ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv:   evex.256.66.0f38.w0 d2 /r         ] AVX10_2,AVX10_VNNIINT,FUTURE */
        /* 241(f2 7d 28) 301 001(d2) 120 : EVEX,PROT,AVX10_2,AVX10_VNNIINT,FUTURE */
        {I_VPDPWUSD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+50346, 647},
    /*   4 : VPDPWUSD zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv:   evex.512.66.0f38.w0 d2 /r         ] AVX10_2,AVX10_VNNIINT,FUTURE */
        /* 241(f2 7d 48) 301 001(d2) 120 : EVEX,PROT,AVX10_2,AVX10_VNNIINT,FUTURE */
        {I_VPDPWUSD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+50355, 647},
};

static const struct itemplate instrux_VPDPWUSDS[5] = {
    /*   0 : VPDPWUSDS xmmreg,xmmreg,xmmrm128 [rvm:      vex.128.66.0f38.w0 d3 /r          ] AR0-2,SO,LATEVEX,AVX,AVXVNNIINT16,FUTURE */
        /* 261(002 001) 001(d3) 120 : AR0,AR1,AR2,SO,LATEVEX,NOAPX,VEX,AVX,AVXVNNIINT16,FUTURE */
        {I_VPDPWUSDS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65048, 496},
    /*   1 : VPDPWUSDS ymmreg,ymmreg,ymmrm256 [rvm:      vex.256.66.0f38.w0 d3 /r          ] AR0-2,SY,LATEVEX,AVX,AVXVNNIINT16,FUTURE */
        /* 261(002 005) 001(d3) 120 : AR0,AR1,AR2,SY,LATEVEX,NOAPX,VEX,AVX,AVXVNNIINT16,FUTURE */
        {I_VPDPWUSDS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65055, 497},
    /*   2 : VPDPWUSDS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv:   evex.128.66.0f38.w0 d3 /r         ] AVX10_2,AVX10_VNNIINT,FUTURE */
        /* 241(f2 7d 08) 301 001(d3) 120 : EVEX,PROT,AVX10_2,AVX10_VNNIINT,FUTURE */
        {I_VPDPWUSDS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+50364, 647},
    /*   3 : VPDPWUSDS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv:   evex.256.66.0f38.w0 d3 /r         ] AVX10_2,AVX10_VNNIINT,FUTURE */
        /* 241(f2 7d 28) 301 001(d3) 120 : EVEX,PROT,AVX10_2,AVX10_VNNIINT,FUTURE */
        {I_VPDPWUSDS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+50373, 647},
    /*   4 : VPDPWUSDS zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv:   evex.512.66.0f38.w0 d3 /r         ] AVX10_2,AVX10_VNNIINT,FUTURE */
        /* 241(f2 7d 48) 301 001(d3) 120 : EVEX,PROT,AVX10_2,AVX10_VNNIINT,FUTURE */
        {I_VPDPWUSDS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+50382, 647},
};

static const struct itemplate instrux_VPDPWUUD[5] = {
    /*   0 : VPDPWUUD xmmreg,xmmreg,xmmrm128 [rvm:      vex.128.np.0f38.w0 d2 /r          ] AR0-2,SO,LATEVEX,AVX,AVXVNNIINT16,FUTURE */
        /* 261(002 000) 001(d2) 120 : AR0,AR1,AR2,SO,LATEVEX,NOAPX,VEX,AVX,AVXVNNIINT16,FUTURE */
        {I_VPDPWUUD, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65062, 496},
    /*   1 : VPDPWUUD ymmreg,ymmreg,ymmrm256 [rvm:      vex.256.np.0f38.w0 d2 /r          ] AR0-2,SY,LATEVEX,AVX,AVXVNNIINT16,FUTURE */
        /* 261(002 004) 001(d2) 120 : AR0,AR1,AR2,SY,LATEVEX,NOAPX,VEX,AVX,AVXVNNIINT16,FUTURE */
        {I_VPDPWUUD, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65069, 497},
    /*   2 : VPDPWUUD xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv:   evex.128.np.0f38.w0 d2 /r         ] AVX10_2,AVX10_VNNIINT,FUTURE */
        /* 241(f2 7c 08) 301 001(d2) 120 : EVEX,PROT,AVX10_2,AVX10_VNNIINT,FUTURE */
        {I_VPDPWUUD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+50391, 647},
    /*   3 : VPDPWUUD ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv:   evex.256.np.0f38.w0 d2 /r         ] AVX10_2,AVX10_VNNIINT,FUTURE */
        /* 241(f2 7c 28) 301 001(d2) 120 : EVEX,PROT,AVX10_2,AVX10_VNNIINT,FUTURE */
        {I_VPDPWUUD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+50400, 647},
    /*   4 : VPDPWUUD zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv:   evex.512.np.0f38.w0 d2 /r         ] AVX10_2,AVX10_VNNIINT,FUTURE */
        /* 241(f2 7c 48) 301 001(d2) 120 : EVEX,PROT,AVX10_2,AVX10_VNNIINT,FUTURE */
        {I_VPDPWUUD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+50409, 647},
};

static const struct itemplate instrux_VPDPWUUDS[5] = {
    /*   0 : VPDPWUUDS xmmreg,xmmreg,xmmrm128 [rvm:      vex.128.np.0f38.w0 d3 /r          ] AR0-2,SO,LATEVEX,AVX,AVXVNNIINT16,FUTURE */
        /* 261(002 000) 001(d3) 120 : AR0,AR1,AR2,SO,LATEVEX,NOAPX,VEX,AVX,AVXVNNIINT16,FUTURE */
        {I_VPDPWUUDS, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65076, 496},
    /*   1 : VPDPWUUDS ymmreg,ymmreg,ymmrm256 [rvm:      vex.256.np.0f38.w0 d3 /r          ] AR0-2,SY,LATEVEX,AVX,AVXVNNIINT16,FUTURE */
        /* 261(002 004) 001(d3) 120 : AR0,AR1,AR2,SY,LATEVEX,NOAPX,VEX,AVX,AVXVNNIINT16,FUTURE */
        {I_VPDPWUUDS, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65083, 497},
    /*   2 : VPDPWUUDS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv:   evex.128.np.0f38.w0 d3 /r         ] AVX10_2,AVX10_VNNIINT,FUTURE */
        /* 241(f2 7c 08) 301 001(d3) 120 : EVEX,PROT,AVX10_2,AVX10_VNNIINT,FUTURE */
        {I_VPDPWUUDS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+50418, 647},
    /*   3 : VPDPWUUDS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv:   evex.256.np.0f38.w0 d3 /r         ] AVX10_2,AVX10_VNNIINT,FUTURE */
        /* 241(f2 7c 28) 301 001(d3) 120 : EVEX,PROT,AVX10_2,AVX10_VNNIINT,FUTURE */
        {I_VPDPWUUDS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+50427, 647},
    /*   4 : VPDPWUUDS zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv:   evex.512.np.0f38.w0 d3 /r         ] AVX10_2,AVX10_VNNIINT,FUTURE */
        /* 241(f2 7c 48) 301 001(d3) 120 : EVEX,PROT,AVX10_2,AVX10_VNNIINT,FUTURE */
        {I_VPDPWUUDS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+50436, 647},
};

static const struct itemplate instrux_VPMADD52HUQ[5] = {
    /*   0 : VPMADD52HUQ xmmreg,xmmreg,xmmrm128 [rvm:      vex.128.66.0f38.w1 b5 /r          ] AR0-2,SO,LATEVEX,AVXIFMA,FUTURE */
        /* 261(002 201) 001(b5) 120 : AR0,AR1,AR2,SO,LATEVEX,NOAPX,VEX,AVXIFMA,FUTURE */
        {I_VPMADD52HUQ, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65090, 498},
    /*   1 : VPMADD52HUQ ymmreg,ymmreg,ymmrm256 [rvm:      vex.256.66.0f38.w1 b5 /r          ] AR0-2,SY,LATEVEX,AVXIFMA,FUTURE */
        /* 261(002 205) 001(b5) 120 : AR0,AR1,AR2,SY,LATEVEX,NOAPX,VEX,AVXIFMA,FUTURE */
        {I_VPMADD52HUQ, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65097, 499},
    /*   2 : VPMADD52HUQ xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 b5 /r     ] AVX512VL,AVX512IFMA,FUTURE */
        /* 241(f2 fd 08) 301 001(b5) 120 : EVEX,PROT,AVX512VL,AVX512IFMA,FUTURE */
        {I_VPMADD52HUQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+38079, 562},
    /*   3 : VPMADD52HUQ ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 b5 /r     ] AVX512VL,AVX512IFMA,FUTURE */
        /* 241(f2 fd 28) 301 001(b5) 120 : EVEX,PROT,AVX512VL,AVX512IFMA,FUTURE */
        {I_VPMADD52HUQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+38088, 562},
    /*   4 : VPMADD52HUQ zmmreg|mask|z,zmmreg,zmmrm512|b64 [rvm:fv:   evex.nds.512.66.0f38.w1 b5 /r     ] AVX512IFMA,FUTURE */
        /* 241(f2 fd 48) 301 001(b5) 120 : EVEX,PROT,AVX512IFMA,FUTURE */
        {I_VPMADD52HUQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+38097, 563},
};

static const struct itemplate instrux_VPMADD52LUQ[5] = {
    /*   0 : VPMADD52LUQ xmmreg,xmmreg,xmmrm128 [rvm:      vex.128.66.0f38.w1 b4 /r          ] AR0-2,SO,LATEVEX,AVXIFMA,FUTURE */
        /* 261(002 201) 001(b4) 120 : AR0,AR1,AR2,SO,LATEVEX,NOAPX,VEX,AVXIFMA,FUTURE */
        {I_VPMADD52LUQ, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65104, 498},
    /*   1 : VPMADD52LUQ ymmreg,ymmreg,ymmrm256 [rvm:      vex.256.66.0f38.w1 b4 /r          ] AR0-2,SY,LATEVEX,AVXIFMA,FUTURE */
        /* 261(002 205) 001(b4) 120 : AR0,AR1,AR2,SY,LATEVEX,NOAPX,VEX,AVXIFMA,FUTURE */
        {I_VPMADD52LUQ, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65111, 499},
    /*   2 : VPMADD52LUQ xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 b4 /r     ] AVX512VL,AVX512IFMA,FUTURE */
        /* 241(f2 fd 08) 301 001(b4) 120 : EVEX,PROT,AVX512VL,AVX512IFMA,FUTURE */
        {I_VPMADD52LUQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+38106, 562},
    /*   3 : VPMADD52LUQ ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 b4 /r     ] AVX512VL,AVX512IFMA,FUTURE */
        /* 241(f2 fd 28) 301 001(b4) 120 : EVEX,PROT,AVX512VL,AVX512IFMA,FUTURE */
        {I_VPMADD52LUQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+38115, 562},
    /*   4 : VPMADD52LUQ zmmreg|mask|z,zmmreg,zmmrm512|b64 [rvm:fv:   evex.nds.512.66.0f38.w1 b4 /r     ] AVX512IFMA,FUTURE */
        /* 241(f2 fd 48) 301 001(b4) 120 : EVEX,PROT,AVX512IFMA,FUTURE */
        {I_VPMADD52LUQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+38124, 563},
};

static const struct itemplate instrux_KMOVB[10] = {
    /*   0 : KMOVB kreg8,krm8 [rm:       vex.l0.0f.ko8 90 /r              ] ZU,AVX512DQ,FUTURE */
        /* 270(001 001) 001(90) 110 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KMOVB, 2, {OPMASKREG|BITS8|RN_L16,RM_OPMASK|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65118, 500},
    /*   1 : KMOVB kreg8,krm8 [rm:       evex.l0.0f.ko8 90 /r              ] ZU,AVX512DQ,FUTURE,APX */
        /* 250(f1 7d 08) 300 001(90) 110 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KMOVB, 2, {OPMASKREG|BITS8,RM_OPMASK|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+29664, 501},
    /*   2 : KMOVB mem8,kreg8 [mr:       vex.l0.0f.ko8 91 /r              ] ZU,AVX512DQ,FUTURE */
        /* 270(001 001) 001(91) 101 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KMOVB, 2, {MEMORY|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65146, 500},
    /*   3 : KMOVB mem8,kreg8 [mr:       evex.l0.0f.ko8 91 /r              ] ZU,AVX512DQ,FUTURE,APX */
        /* 250(f1 7d 08) 300 001(91) 101 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KMOVB, 2, {MEMORY|BITS8,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+29700, 501},
    /*   4 : KMOVB kreg8,reg32 [rm:       vex.l0.0f.66.w0 92 /r            ] ZU,AVX512DQ,FUTURE */
        /* 270(001 001) 001(92) 110 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KMOVB, 2, {OPMASKREG|BITS8|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65202, 500},
    /*   5 : KMOVB kreg8,reg32 [rm:       evex.l0.0f.66.w0 92 /r            ] ZU,AVX512DQ,FUTURE,APX */
        /* 250(f1 7d 08) 300 001(92) 110 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KMOVB, 2, {OPMASKREG|BITS8,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+29772, 501},
    /*   6 : KMOVB kreg8,reg8 [rm:       vex.l0.0f.66.w0 92 /r            ] ND,ZU,AVX512DQ,FUTURE */
        /* 270(001 001) 001(92) 110 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KMOVB, 2, {OPMASKREG|BITS8|RN_L16,REG_GPR|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65202, 500},
    /*   7 : KMOVB kreg8,reg8 [rm:       evex.l0.0f.66.w0 92 /r            ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 250(f1 7d 08) 300 001(92) 110 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KMOVB, 2, {OPMASKREG|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+29772, 501},
    /*   8 : KMOVB reg32,kreg8 [rm:       vex.l0.0f.66.w0 93 /r            ] ZU,AVX512DQ,FUTURE */
        /* 270(001 001) 001(93) 110 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KMOVB, 2, {REG_GPR|BITS32|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65216, 500},
    /*   9 : KMOVB reg32,kreg8 [rm:       evex.l0.0f.66.w0 93 /r            ] ZU,AVX512DQ,FUTURE,APX */
        /* 250(f1 7d 08) 300 001(93) 110 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KMOVB, 2, {REG_GPR|BITS32,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+29790, 501},
};

static const struct itemplate instrux_KMOVW[10] = {
    /*   0 : KMOVW kreg16,krm16 [rm:       vex.l0.0f.ko16 90 /r             ] ZU,AVX512F,FUTURE */
        /* 270(001 000) 001(90) 110 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KMOVW, 2, {OPMASKREG|BITS16|RN_L16,RM_OPMASK|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65125, 502},
    /*   1 : KMOVW kreg16,krm16 [rm:       evex.l0.0f.ko16 90 /r             ] ZU,AVX512F,FUTURE,APX */
        /* 250(f1 7c 08) 300 001(90) 110 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KMOVW, 2, {OPMASKREG|BITS16,RM_OPMASK|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29673, 503},
    /*   2 : KMOVW mem16,kreg16 [mr:       vex.l0.0f.ko16 91 /r             ] ZU,AVX512DQ,FUTURE */
        /* 270(001 000) 001(91) 101 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KMOVW, 2, {MEMORY|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65153, 500},
    /*   3 : KMOVW mem16,kreg16 [mr:       evex.l0.0f.ko16 91 /r             ] ZU,AVX512DQ,FUTURE,APX */
        /* 250(f1 7c 08) 300 001(91) 101 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KMOVW, 2, {MEMORY|BITS16,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29709, 501},
    /*   4 : KMOVW kreg16,reg32 [rm:       vex.l0.0f.np.w0 92 /r            ] ZU,AVX512F,FUTURE */
        /* 270(001 000) 001(92) 110 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KMOVW, 2, {OPMASKREG|BITS16|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65209, 502},
    /*   5 : KMOVW kreg16,reg32 [rm:       evex.l0.0f.np.w0 92 /r            ] ZU,AVX512F,FUTURE,APX */
        /* 250(f1 7c 08) 300 001(92) 110 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KMOVW, 2, {OPMASKREG|BITS16,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+29781, 503},
    /*   6 : KMOVW kreg16,reg16 [rm:       vex.l0.0f.np.w0 92 /r            ] ND,ZU,AVX512F,FUTURE */
        /* 270(001 000) 001(92) 110 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KMOVW, 2, {OPMASKREG|BITS16|RN_L16,REG_GPR|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65209, 502},
    /*   7 : KMOVW kreg16,reg16 [rm:       evex.l0.0f.np.w0 92 /r            ] ND,ZU,AVX512F,FUTURE,APX */
        /* 250(f1 7c 08) 300 001(92) 110 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KMOVW, 2, {OPMASKREG|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29781, 503},
    /*   8 : KMOVW reg32,kreg16 [rm:       vex.l0.0f.np.w0 93 /r            ] ZU,AVX512F,FUTURE */
        /* 270(001 000) 001(93) 110 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KMOVW, 2, {REG_GPR|BITS32|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65223, 502},
    /*   9 : KMOVW reg32,kreg16 [rm:       evex.l0.0f.np.w0 93 /r            ] ZU,AVX512F,FUTURE,APX */
        /* 250(f1 7c 08) 300 001(93) 110 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KMOVW, 2, {REG_GPR|BITS32,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29799, 503},
};

static const struct itemplate instrux_KMOVD[8] = {
    /*   0 : KMOVD kreg32,krm32 [rm:       vex.l0.0f.ko32 90 /r             ] ZU,AVX512BW,FUTURE */
        /* 270(001 201) 001(90) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KMOVD, 2, {OPMASKREG|BITS32|RN_L16,RM_OPMASK|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65132, 504},
    /*   1 : KMOVD kreg32,krm32 [rm:       evex.l0.0f.ko32 90 /r             ] ZU,AVX512BW,FUTURE,APX */
        /* 250(f1 fd 08) 300 001(90) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KMOVD, 2, {OPMASKREG|BITS32,RM_OPMASK|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+29682, 505},
    /*   2 : KMOVD mem32,kreg32 [mr:       vex.l0.0f.ko32 91 /r             ] ZU,AVX512BW,FUTURE */
        /* 270(001 201) 001(91) 101 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KMOVD, 2, {MEMORY|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65160, 504},
    /*   3 : KMOVD mem32,kreg32 [mr:       evex.l0.0f.ko32 91 /r             ] ZU,AVX512BW,FUTURE,APX */
        /* 250(f1 fd 08) 300 001(91) 101 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KMOVD, 2, {MEMORY|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+29718, 505},
    /*   4 : KMOVD kreg32,reg32 [rm:       vex.l0.0f.f2.w0 92 /r            ] ZU,AVX512BW,FUTURE */
        /* 270(001 003) 001(92) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KMOVD, 2, {OPMASKREG|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65174, 504},
    /*   5 : KMOVD kreg32,reg32 [rm:       evex.l0.0f.f2.w0 92 /r            ] ZU,AVX512BW,FUTURE,APX */
        /* 250(f1 7f 08) 300 001(92) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KMOVD, 2, {OPMASKREG|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+29736, 505},
    /*   6 : KMOVD reg32,kreg32 [rm:       vex.l0.0f.f2.w0 93 /r            ] ZU,AVX512BW,FUTURE */
        /* 270(001 003) 001(93) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KMOVD, 2, {REG_GPR|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65188, 504},
    /*   7 : KMOVD reg32,kreg32 [rm:       evex.l0.0f.f2.w0 93 /r            ] ZU,AVX512BW,FUTURE,APX */
        /* 250(f1 7f 08) 300 001(93) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KMOVD, 2, {REG_GPR|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+29754, 505},
};

static const struct itemplate instrux_KMOVQ[8] = {
    /*   0 : KMOVQ kreg64,krm64 [rm:       vex.l0.0f.ko64 90 /r             ] ZU,AVX512BW,FUTURE */
        /* 270(001 200) 001(90) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KMOVQ, 2, {OPMASKREG|BITS64|RN_L16,RM_OPMASK|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65139, 504},
    /*   1 : KMOVQ kreg64,krm64 [rm:       evex.l0.0f.ko64 90 /r             ] ZU,AVX512BW,FUTURE,APX */
        /* 250(f1 fc 08) 300 001(90) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KMOVQ, 2, {OPMASKREG|BITS64,RM_OPMASK|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+29691, 505},
    /*   2 : KMOVQ mem64,kreg64 [mr:       vex.l0.0f.ko64 91 /r             ] ZU,AVX512BW,FUTURE */
        /* 270(001 200) 001(91) 101 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KMOVQ, 2, {MEMORY|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65167, 504},
    /*   3 : KMOVQ mem64,kreg64 [mr:       evex.l0.0f.ko64 91 /r             ] ZU,AVX512BW,FUTURE,APX */
        /* 250(f1 fc 08) 300 001(91) 101 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KMOVQ, 2, {MEMORY|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+29727, 505},
    /*   4 : KMOVQ kreg64,reg64 [rm:       vex.l0.0f.f2.w1 92 /r            ] ZU,LONG,PROT,AVX512BW,X86_64 */
        /* 270(001 203) 001(92) 110 : NOAPX,ZU,LONG,VEX,PROT,AVX512BW,X86_64 */
        {I_KMOVQ, 2, {OPMASKREG|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65181, 506},
    /*   5 : KMOVQ kreg64,reg64 [rm:       evex.l0.0f.f2.w1 92 /r            ] ZU,LONG,PROT,AVX512BW,X86_64,APX */
        /* 250(f1 ff 08) 300 001(92) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,X86_64 */
        {I_KMOVQ, 2, {OPMASKREG|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+29745, 507},
    /*   6 : KMOVQ reg64,kreg64 [rm:       vex.l0.0f.f2.w1 93 /r            ] ZU,LONG,PROT,AVX512BW,X86_64 */
        /* 270(001 203) 001(93) 110 : NOAPX,ZU,LONG,VEX,PROT,AVX512BW,X86_64 */
        {I_KMOVQ, 2, {REG_GPR|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65195, 506},
    /*   7 : KMOVQ reg64,kreg64 [rm:       evex.l0.0f.f2.w1 93 /r            ] ZU,LONG,PROT,AVX512BW,X86_64,APX */
        /* 250(f1 ff 08) 300 001(93) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,X86_64 */
        {I_KMOVQ, 2, {REG_GPR|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+29763, 507},
};

static const struct itemplate instrux_KMOV[36] = {
    /*   0 : KMOV kreg8,krm8 [rm:       vex.l0.0f.ko8 90 /r              ] ND,ZU,AVX512DQ,FUTURE */
        /* 270(001 001) 001(90) 110 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KMOV, 2, {OPMASKREG|BITS8|RN_L16,RM_OPMASK|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65118, 500},
    /*   1 : KMOV kreg8,krm8 [rm:       evex.l0.0f.ko8 90 /r              ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 250(f1 7d 08) 300 001(90) 110 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KMOV, 2, {OPMASKREG|BITS8,RM_OPMASK|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+29664, 501},
    /*   2 : KMOV kreg16,krm16 [rm:       vex.l0.0f.ko16 90 /r             ] ND,ZU,AVX512F,FUTURE */
        /* 270(001 000) 001(90) 110 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KMOV, 2, {OPMASKREG|BITS16|RN_L16,RM_OPMASK|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65125, 502},
    /*   3 : KMOV kreg16,krm16 [rm:       evex.l0.0f.ko16 90 /r             ] ND,ZU,AVX512F,FUTURE,APX */
        /* 250(f1 7c 08) 300 001(90) 110 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KMOV, 2, {OPMASKREG|BITS16,RM_OPMASK|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29673, 503},
    /*   4 : KMOV kreg32,krm32 [rm:       vex.l0.0f.ko32 90 /r             ] ND,ZU,AVX512BW,FUTURE */
        /* 270(001 201) 001(90) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KMOV, 2, {OPMASKREG|BITS32|RN_L16,RM_OPMASK|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65132, 504},
    /*   5 : KMOV kreg32,krm32 [rm:       evex.l0.0f.ko32 90 /r             ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 250(f1 fd 08) 300 001(90) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KMOV, 2, {OPMASKREG|BITS32,RM_OPMASK|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+29682, 505},
    /*   6 : KMOV kreg64,krm64 [rm:       vex.l0.0f.ko64 90 /r             ] ND,ZU,AVX512BW,FUTURE */
        /* 270(001 200) 001(90) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KMOV, 2, {OPMASKREG|BITS64|RN_L16,RM_OPMASK|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65139, 504},
    /*   7 : KMOV kreg64,krm64 [rm:       evex.l0.0f.ko64 90 /r             ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 250(f1 fc 08) 300 001(90) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KMOV, 2, {OPMASKREG|BITS64,RM_OPMASK|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+29691, 505},
    /*   8 : KMOV mem8,kreg8 [mr:       vex.l0.0f.ko8 91 /r              ] ND,ZU,AVX512DQ,FUTURE */
        /* 270(001 001) 001(91) 101 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KMOV, 2, {MEMORY|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65146, 500},
    /*   9 : KMOV mem8,kreg8 [mr:       evex.l0.0f.ko8 91 /r              ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 250(f1 7d 08) 300 001(91) 101 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KMOV, 2, {MEMORY|BITS8,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+29700, 501},
    /*  10 : KMOV mem16,kreg16 [mr:       vex.l0.0f.ko16 91 /r             ] ND,ZU,AVX512DQ,FUTURE */
        /* 270(001 000) 001(91) 101 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KMOV, 2, {MEMORY|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65153, 500},
    /*  11 : KMOV mem16,kreg16 [mr:       evex.l0.0f.ko16 91 /r             ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 250(f1 7c 08) 300 001(91) 101 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KMOV, 2, {MEMORY|BITS16,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29709, 501},
    /*  12 : KMOV mem32,kreg32 [mr:       vex.l0.0f.ko32 91 /r             ] ND,ZU,AVX512BW,FUTURE */
        /* 270(001 201) 001(91) 101 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KMOV, 2, {MEMORY|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65160, 504},
    /*  13 : KMOV mem32,kreg32 [mr:       evex.l0.0f.ko32 91 /r             ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 250(f1 fd 08) 300 001(91) 101 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KMOV, 2, {MEMORY|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+29718, 505},
    /*  14 : KMOV mem64,kreg64 [mr:       vex.l0.0f.ko64 91 /r             ] ND,ZU,AVX512BW,FUTURE */
        /* 270(001 200) 001(91) 101 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KMOV, 2, {MEMORY|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65167, 504},
    /*  15 : KMOV mem64,kreg64 [mr:       evex.l0.0f.ko64 91 /r             ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 250(f1 fc 08) 300 001(91) 101 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KMOV, 2, {MEMORY|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+29727, 505},
    /*  16 : KMOV kreg32,reg32 [rm:       vex.l0.0f.f2.w0 92 /r            ] ND,ZU,AVX512BW,FUTURE */
        /* 270(001 003) 001(92) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KMOV, 2, {OPMASKREG|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65174, 504},
    /*  17 : KMOV kreg32,reg32 [rm:       evex.l0.0f.f2.w0 92 /r            ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 250(f1 7f 08) 300 001(92) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KMOV, 2, {OPMASKREG|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+29736, 505},
    /*  18 : KMOV kreg64,reg64 [rm:       vex.l0.0f.f2.w1 92 /r            ] ND,ZU,LONG,PROT,AVX512BW,X86_64 */
        /* 270(001 203) 001(92) 110 : NOAPX,ZU,LONG,VEX,PROT,AVX512BW,X86_64 */
        {I_KMOV, 2, {OPMASKREG|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65181, 506},
    /*  19 : KMOV kreg64,reg64 [rm:       evex.l0.0f.f2.w1 92 /r            ] ND,ZU,LONG,PROT,AVX512BW,X86_64,APX */
        /* 250(f1 ff 08) 300 001(92) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,X86_64 */
        {I_KMOV, 2, {OPMASKREG|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+29745, 507},
    /*  20 : KMOV reg32,kreg32 [rm:       vex.l0.0f.f2.w0 93 /r            ] ND,ZU,AVX512BW,FUTURE */
        /* 270(001 003) 001(93) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KMOV, 2, {REG_GPR|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65188, 504},
    /*  21 : KMOV reg32,kreg32 [rm:       evex.l0.0f.f2.w0 93 /r            ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 250(f1 7f 08) 300 001(93) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KMOV, 2, {REG_GPR|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+29754, 505},
    /*  22 : KMOV reg64,kreg64 [rm:       vex.l0.0f.f2.w1 93 /r            ] ND,ZU,LONG,PROT,AVX512BW,X86_64 */
        /* 270(001 203) 001(93) 110 : NOAPX,ZU,LONG,VEX,PROT,AVX512BW,X86_64 */
        {I_KMOV, 2, {REG_GPR|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65195, 506},
    /*  23 : KMOV reg64,kreg64 [rm:       evex.l0.0f.f2.w1 93 /r            ] ND,ZU,LONG,PROT,AVX512BW,X86_64,APX */
        /* 250(f1 ff 08) 300 001(93) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,X86_64 */
        {I_KMOV, 2, {REG_GPR|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+29763, 507},
    /*  24 : KMOV kreg8,reg32 [rm:       vex.l0.0f.66.w0 92 /r            ] ND,ZU,AVX512DQ,FUTURE */
        /* 270(001 001) 001(92) 110 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KMOV, 2, {OPMASKREG|BITS8|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65202, 500},
    /*  25 : KMOV kreg8,reg32 [rm:       evex.l0.0f.66.w0 92 /r            ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 250(f1 7d 08) 300 001(92) 110 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KMOV, 2, {OPMASKREG|BITS8,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+29772, 501},
    /*  26 : KMOV kreg8,reg8 [rm:       vex.l0.0f.66.w0 92 /r            ] ND,ZU,AVX512DQ,FUTURE */
        /* 270(001 001) 001(92) 110 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KMOV, 2, {OPMASKREG|BITS8|RN_L16,REG_GPR|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65202, 500},
    /*  27 : KMOV kreg8,reg8 [rm:       evex.l0.0f.66.w0 92 /r            ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 250(f1 7d 08) 300 001(92) 110 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KMOV, 2, {OPMASKREG|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+29772, 501},
    /*  28 : KMOV kreg16,reg32 [rm:       vex.l0.0f.np.w0 92 /r            ] ND,ZU,AVX512F,FUTURE */
        /* 270(001 000) 001(92) 110 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KMOV, 2, {OPMASKREG|BITS16|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65209, 502},
    /*  29 : KMOV kreg16,reg32 [rm:       evex.l0.0f.np.w0 92 /r            ] ND,ZU,AVX512F,FUTURE,APX */
        /* 250(f1 7c 08) 300 001(92) 110 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KMOV, 2, {OPMASKREG|BITS16,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+29781, 503},
    /*  30 : KMOV kreg16,reg16 [rm:       vex.l0.0f.np.w0 92 /r            ] ND,ZU,AVX512F,FUTURE */
        /* 270(001 000) 001(92) 110 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KMOV, 2, {OPMASKREG|BITS16|RN_L16,REG_GPR|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65209, 502},
    /*  31 : KMOV kreg16,reg16 [rm:       evex.l0.0f.np.w0 92 /r            ] ND,ZU,AVX512F,FUTURE,APX */
        /* 250(f1 7c 08) 300 001(92) 110 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KMOV, 2, {OPMASKREG|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29781, 503},
    /*  32 : KMOV reg32,kreg8 [rm:       vex.l0.0f.66.w0 93 /r            ] ND,ZU,AVX512DQ,FUTURE */
        /* 270(001 001) 001(93) 110 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KMOV, 2, {REG_GPR|BITS32|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65216, 500},
    /*  33 : KMOV reg32,kreg8 [rm:       evex.l0.0f.66.w0 93 /r            ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 250(f1 7d 08) 300 001(93) 110 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KMOV, 2, {REG_GPR|BITS32,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+29790, 501},
    /*  34 : KMOV reg32,kreg16 [rm:       vex.l0.0f.np.w0 93 /r            ] ND,ZU,AVX512F,FUTURE */
        /* 270(001 000) 001(93) 110 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KMOV, 2, {REG_GPR|BITS32|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65223, 502},
    /*  35 : KMOV reg32,kreg16 [rm:       evex.l0.0f.np.w0 93 /r            ] ND,ZU,AVX512F,FUTURE,APX */
        /* 250(f1 7c 08) 300 001(93) 110 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KMOV, 2, {REG_GPR|BITS32,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29799, 503},
};

static const struct itemplate instrux_MOVB[10] = {
    /*   0 : MOVB kreg8,krm8 [rm:       vex.l0.0f.ko8 90 /r              ] ND,ZU,AVX512DQ,FUTURE */
        /* 270(001 001) 001(90) 110 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_MOVB, 2, {OPMASKREG|BITS8|RN_L16,RM_OPMASK|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65118, 500},
    /*   1 : MOVB kreg8,krm8 [rm:       evex.l0.0f.ko8 90 /r              ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 250(f1 7d 08) 300 001(90) 110 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_MOVB, 2, {OPMASKREG|BITS8,RM_OPMASK|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+29664, 501},
    /*   2 : MOVB mem8,kreg8 [mr:       vex.l0.0f.ko8 91 /r              ] ND,ZU,AVX512DQ,FUTURE */
        /* 270(001 001) 001(91) 101 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_MOVB, 2, {MEMORY|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65146, 500},
    /*   3 : MOVB mem8,kreg8 [mr:       evex.l0.0f.ko8 91 /r              ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 250(f1 7d 08) 300 001(91) 101 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_MOVB, 2, {MEMORY|BITS8,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+29700, 501},
    /*   4 : MOVB kreg8,reg32 [rm:       vex.l0.0f.66.w0 92 /r            ] ND,ZU,AVX512DQ,FUTURE */
        /* 270(001 001) 001(92) 110 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_MOVB, 2, {OPMASKREG|BITS8|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65202, 500},
    /*   5 : MOVB kreg8,reg32 [rm:       evex.l0.0f.66.w0 92 /r            ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 250(f1 7d 08) 300 001(92) 110 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_MOVB, 2, {OPMASKREG|BITS8,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+29772, 501},
    /*   6 : MOVB kreg8,reg8 [rm:       vex.l0.0f.66.w0 92 /r            ] ND,ZU,AVX512DQ,FUTURE */
        /* 270(001 001) 001(92) 110 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_MOVB, 2, {OPMASKREG|BITS8|RN_L16,REG_GPR|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65202, 500},
    /*   7 : MOVB kreg8,reg8 [rm:       evex.l0.0f.66.w0 92 /r            ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 250(f1 7d 08) 300 001(92) 110 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_MOVB, 2, {OPMASKREG|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+29772, 501},
    /*   8 : MOVB reg32,kreg8 [rm:       vex.l0.0f.66.w0 93 /r            ] ND,ZU,AVX512DQ,FUTURE */
        /* 270(001 001) 001(93) 110 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_MOVB, 2, {REG_GPR|BITS32|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65216, 500},
    /*   9 : MOVB reg32,kreg8 [rm:       evex.l0.0f.66.w0 93 /r            ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 250(f1 7d 08) 300 001(93) 110 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_MOVB, 2, {REG_GPR|BITS32,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+29790, 501},
};

static const struct itemplate instrux_MOVW[10] = {
    /*   0 : MOVW kreg16,krm16 [rm:       vex.l0.0f.ko16 90 /r             ] ND,ZU,AVX512F,FUTURE */
        /* 270(001 000) 001(90) 110 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_MOVW, 2, {OPMASKREG|BITS16|RN_L16,RM_OPMASK|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65125, 502},
    /*   1 : MOVW kreg16,krm16 [rm:       evex.l0.0f.ko16 90 /r             ] ND,ZU,AVX512F,FUTURE,APX */
        /* 250(f1 7c 08) 300 001(90) 110 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_MOVW, 2, {OPMASKREG|BITS16,RM_OPMASK|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29673, 503},
    /*   2 : MOVW mem16,kreg16 [mr:       vex.l0.0f.ko16 91 /r             ] ND,ZU,AVX512DQ,FUTURE */
        /* 270(001 000) 001(91) 101 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_MOVW, 2, {MEMORY|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65153, 500},
    /*   3 : MOVW mem16,kreg16 [mr:       evex.l0.0f.ko16 91 /r             ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 250(f1 7c 08) 300 001(91) 101 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_MOVW, 2, {MEMORY|BITS16,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29709, 501},
    /*   4 : MOVW kreg16,reg32 [rm:       vex.l0.0f.np.w0 92 /r            ] ND,ZU,AVX512F,FUTURE */
        /* 270(001 000) 001(92) 110 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_MOVW, 2, {OPMASKREG|BITS16|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65209, 502},
    /*   5 : MOVW kreg16,reg32 [rm:       evex.l0.0f.np.w0 92 /r            ] ND,ZU,AVX512F,FUTURE,APX */
        /* 250(f1 7c 08) 300 001(92) 110 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_MOVW, 2, {OPMASKREG|BITS16,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+29781, 503},
    /*   6 : MOVW kreg16,reg16 [rm:       vex.l0.0f.np.w0 92 /r            ] ND,ZU,AVX512F,FUTURE */
        /* 270(001 000) 001(92) 110 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_MOVW, 2, {OPMASKREG|BITS16|RN_L16,REG_GPR|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65209, 502},
    /*   7 : MOVW kreg16,reg16 [rm:       evex.l0.0f.np.w0 92 /r            ] ND,ZU,AVX512F,FUTURE,APX */
        /* 250(f1 7c 08) 300 001(92) 110 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_MOVW, 2, {OPMASKREG|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29781, 503},
    /*   8 : MOVW reg32,kreg16 [rm:       vex.l0.0f.np.w0 93 /r            ] ND,ZU,AVX512F,FUTURE */
        /* 270(001 000) 001(93) 110 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_MOVW, 2, {REG_GPR|BITS32|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65223, 502},
    /*   9 : MOVW reg32,kreg16 [rm:       evex.l0.0f.np.w0 93 /r            ] ND,ZU,AVX512F,FUTURE,APX */
        /* 250(f1 7c 08) 300 001(93) 110 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_MOVW, 2, {REG_GPR|BITS32,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29799, 503},
};

static const struct itemplate instrux_KADDB[4] = {
    /*   0 : KADDB kreg8,kreg8*,kreg8 [rvm:      vex.l1.0f.ko8 4a /r              ] ZU,AVX512DQ,FUTURE */
        /* 261(001 005) 001(4a) 120 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KADDB, 3, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65230, 500},
    /*   1 : KADDB kreg8,kreg8*,kreg8 [rvm:      evex.l1.0f.ko8 4a /r              ] ZU,AVX512DQ,FUTURE,APX */
        /* 241(f1 7d 28) 300 001(4a) 120 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KADDB, 3, {OPMASKREG|BITS8,OPMASKREG|BITS8,OPMASKREG|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+29808, 501},
    /*   2 : KADDB kreg8,kreg8 [r+vm:      vex.l1.0f.ko8 4a /r              ] ND,ZU,AVX512DQ,FUTURE */
        /* 260(001 005) 001(4a) 110 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KADDB, 2, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65237, 500},
    /*   3 : KADDB kreg8,kreg8 [r+vm:      evex.l1.0f.ko8 4a /r              ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 240(f1 7d 28) 300 001(4a) 110 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KADDB, 2, {OPMASKREG|BITS8,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+29817, 501},
};

static const struct itemplate instrux_KADDW[4] = {
    /*   0 : KADDW kreg16,kreg16*,kreg16 [rvm:      vex.l1.0f.ko16 4a /r             ] ZU,AVX512DQ,FUTURE */
        /* 261(001 004) 001(4a) 120 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KADDW, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65244, 500},
    /*   1 : KADDW kreg16,kreg16*,kreg16 [rvm:      evex.l1.0f.ko16 4a /r             ] ZU,AVX512DQ,FUTURE,APX */
        /* 241(f1 7c 28) 300 001(4a) 120 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KADDW, 3, {OPMASKREG|BITS16,OPMASKREG|BITS16,OPMASKREG|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+29826, 501},
    /*   2 : KADDW kreg16,kreg16 [r+vm:      vex.l1.0f.ko16 4a /r             ] ND,ZU,AVX512DQ,FUTURE */
        /* 260(001 004) 001(4a) 110 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KADDW, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65251, 500},
    /*   3 : KADDW kreg16,kreg16 [r+vm:      evex.l1.0f.ko16 4a /r             ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 240(f1 7c 28) 300 001(4a) 110 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KADDW, 2, {OPMASKREG|BITS16,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29835, 501},
};

static const struct itemplate instrux_KADDD[4] = {
    /*   0 : KADDD kreg32,kreg32*,kreg32 [rvm:      vex.l1.0f.ko32 4a /r             ] ZU,AVX512BW,FUTURE */
        /* 261(001 205) 001(4a) 120 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KADDD, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65258, 504},
    /*   1 : KADDD kreg32,kreg32*,kreg32 [rvm:      evex.l1.0f.ko32 4a /r             ] ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fd 28) 300 001(4a) 120 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KADDD, 3, {OPMASKREG|BITS32,OPMASKREG|BITS32,OPMASKREG|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+29844, 505},
    /*   2 : KADDD kreg32,kreg32 [r+vm:      vex.l1.0f.ko32 4a /r             ] ND,ZU,AVX512BW,FUTURE */
        /* 260(001 205) 001(4a) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KADDD, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65265, 504},
    /*   3 : KADDD kreg32,kreg32 [r+vm:      evex.l1.0f.ko32 4a /r             ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fd 28) 300 001(4a) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KADDD, 2, {OPMASKREG|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+29853, 505},
};

static const struct itemplate instrux_KADDQ[4] = {
    /*   0 : KADDQ kreg64,kreg64*,kreg64 [rvm:      vex.l1.0f.ko64 4a /r             ] ZU,AVX512BW,FUTURE */
        /* 261(001 204) 001(4a) 120 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KADDQ, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65272, 504},
    /*   1 : KADDQ kreg64,kreg64*,kreg64 [rvm:      evex.l1.0f.ko64 4a /r             ] ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fc 28) 300 001(4a) 120 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KADDQ, 3, {OPMASKREG|BITS64,OPMASKREG|BITS64,OPMASKREG|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+29862, 505},
    /*   2 : KADDQ kreg64,kreg64 [r+vm:      vex.l1.0f.ko64 4a /r             ] ND,ZU,AVX512BW,FUTURE */
        /* 260(001 204) 001(4a) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KADDQ, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65279, 504},
    /*   3 : KADDQ kreg64,kreg64 [r+vm:      evex.l1.0f.ko64 4a /r             ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fc 28) 300 001(4a) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KADDQ, 2, {OPMASKREG|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+29871, 505},
};

static const struct itemplate instrux_KADD[16] = {
    /*   0 : KADD kreg8,kreg8*,kreg8 [rvm:      vex.l1.0f.ko8 4a /r              ] ND,SM0,SM1,SM2,ZU,AVX512DQ,FUTURE */
        /* 261(001 005) 001(4a) 120 : SM0,SM1,SM2,NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KADD, 3, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65230, 508},
    /*   1 : KADD kreg8,kreg8*,kreg8 [rvm:      evex.l1.0f.ko8 4a /r              ] ND,SM0,SM1,SM2,ZU,AVX512DQ,FUTURE,APX */
        /* 241(f1 7d 28) 300 001(4a) 120 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KADD, 3, {OPMASKREG|BITS8,OPMASKREG|BITS8,OPMASKREG|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+29808, 509},
    /*   2 : KADD kreg8,kreg8 [r+vm:      vex.l1.0f.ko8 4a /r              ] ND,SM0,SM1,ZU,AVX512DQ,FUTURE */
        /* 260(001 005) 001(4a) 110 : SM0,SM1,NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KADD, 2, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65237, 510},
    /*   3 : KADD kreg8,kreg8 [r+vm:      evex.l1.0f.ko8 4a /r              ] ND,SM0,SM1,ZU,AVX512DQ,FUTURE,APX */
        /* 240(f1 7d 28) 300 001(4a) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KADD, 2, {OPMASKREG|BITS8,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+29817, 511},
    /*   4 : KADD kreg16,kreg16*,kreg16 [rvm:      vex.l1.0f.ko16 4a /r             ] ND,SM0,SM1,SM2,ZU,AVX512DQ,FUTURE */
        /* 261(001 004) 001(4a) 120 : SM0,SM1,SM2,NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KADD, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65244, 508},
    /*   5 : KADD kreg16,kreg16*,kreg16 [rvm:      evex.l1.0f.ko16 4a /r             ] ND,SM0,SM1,SM2,ZU,AVX512DQ,FUTURE,APX */
        /* 241(f1 7c 28) 300 001(4a) 120 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KADD, 3, {OPMASKREG|BITS16,OPMASKREG|BITS16,OPMASKREG|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+29826, 509},
    /*   6 : KADD kreg16,kreg16 [r+vm:      vex.l1.0f.ko16 4a /r             ] ND,SM0,SM1,ZU,AVX512DQ,FUTURE */
        /* 260(001 004) 001(4a) 110 : SM0,SM1,NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KADD, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65251, 510},
    /*   7 : KADD kreg16,kreg16 [r+vm:      evex.l1.0f.ko16 4a /r             ] ND,SM0,SM1,ZU,AVX512DQ,FUTURE,APX */
        /* 240(f1 7c 28) 300 001(4a) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KADD, 2, {OPMASKREG|BITS16,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29835, 511},
    /*   8 : KADD kreg32,kreg32*,kreg32 [rvm:      vex.l1.0f.ko32 4a /r             ] ND,SM0,SM1,SM2,ZU,AVX512BW,FUTURE */
        /* 261(001 205) 001(4a) 120 : SM0,SM1,SM2,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KADD, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65258, 512},
    /*   9 : KADD kreg32,kreg32*,kreg32 [rvm:      evex.l1.0f.ko32 4a /r             ] ND,SM0,SM1,SM2,ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fd 28) 300 001(4a) 120 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KADD, 3, {OPMASKREG|BITS32,OPMASKREG|BITS32,OPMASKREG|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+29844, 513},
    /*  10 : KADD kreg32,kreg32 [r+vm:      vex.l1.0f.ko32 4a /r             ] ND,SM0,SM1,ZU,AVX512BW,FUTURE */
        /* 260(001 205) 001(4a) 110 : SM0,SM1,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KADD, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65265, 514},
    /*  11 : KADD kreg32,kreg32 [r+vm:      evex.l1.0f.ko32 4a /r             ] ND,SM0,SM1,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fd 28) 300 001(4a) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KADD, 2, {OPMASKREG|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+29853, 515},
    /*  12 : KADD kreg64,kreg64*,kreg64 [rvm:      vex.l1.0f.ko64 4a /r             ] ND,SM0,SM1,SM2,ZU,AVX512BW,FUTURE */
        /* 261(001 204) 001(4a) 120 : SM0,SM1,SM2,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KADD, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65272, 512},
    /*  13 : KADD kreg64,kreg64*,kreg64 [rvm:      evex.l1.0f.ko64 4a /r             ] ND,SM0,SM1,SM2,ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fc 28) 300 001(4a) 120 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KADD, 3, {OPMASKREG|BITS64,OPMASKREG|BITS64,OPMASKREG|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+29862, 513},
    /*  14 : KADD kreg64,kreg64 [r+vm:      vex.l1.0f.ko64 4a /r             ] ND,SM0,SM1,ZU,AVX512BW,FUTURE */
        /* 260(001 204) 001(4a) 110 : SM0,SM1,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KADD, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65279, 514},
    /*  15 : KADD kreg64,kreg64 [r+vm:      evex.l1.0f.ko64 4a /r             ] ND,SM0,SM1,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fc 28) 300 001(4a) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KADD, 2, {OPMASKREG|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+29871, 515},
};

static const struct itemplate instrux_ADDB[4] = {
    /*   0 : ADDB kreg8,kreg8*,kreg8 [rvm:      vex.l1.0f.ko8 4a /r              ] ND,ZU,AVX512DQ,FUTURE */
        /* 261(001 005) 001(4a) 120 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_ADDB, 3, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65230, 500},
    /*   1 : ADDB kreg8,kreg8*,kreg8 [rvm:      evex.l1.0f.ko8 4a /r              ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 241(f1 7d 28) 300 001(4a) 120 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_ADDB, 3, {OPMASKREG|BITS8,OPMASKREG|BITS8,OPMASKREG|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+29808, 501},
    /*   2 : ADDB kreg8,kreg8 [r+vm:      vex.l1.0f.ko8 4a /r              ] ND,ZU,AVX512DQ,FUTURE */
        /* 260(001 005) 001(4a) 110 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_ADDB, 2, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65237, 500},
    /*   3 : ADDB kreg8,kreg8 [r+vm:      evex.l1.0f.ko8 4a /r              ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 240(f1 7d 28) 300 001(4a) 110 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_ADDB, 2, {OPMASKREG|BITS8,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+29817, 501},
};

static const struct itemplate instrux_ADDW[4] = {
    /*   0 : ADDW kreg16,kreg16*,kreg16 [rvm:      vex.l1.0f.ko16 4a /r             ] ND,ZU,AVX512DQ,FUTURE */
        /* 261(001 004) 001(4a) 120 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_ADDW, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65244, 500},
    /*   1 : ADDW kreg16,kreg16*,kreg16 [rvm:      evex.l1.0f.ko16 4a /r             ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 241(f1 7c 28) 300 001(4a) 120 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_ADDW, 3, {OPMASKREG|BITS16,OPMASKREG|BITS16,OPMASKREG|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+29826, 501},
    /*   2 : ADDW kreg16,kreg16 [r+vm:      vex.l1.0f.ko16 4a /r             ] ND,ZU,AVX512DQ,FUTURE */
        /* 260(001 004) 001(4a) 110 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_ADDW, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65251, 500},
    /*   3 : ADDW kreg16,kreg16 [r+vm:      evex.l1.0f.ko16 4a /r             ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 240(f1 7c 28) 300 001(4a) 110 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_ADDW, 2, {OPMASKREG|BITS16,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29835, 501},
};

static const struct itemplate instrux_ADDD[4] = {
    /*   0 : ADDD kreg32,kreg32*,kreg32 [rvm:      vex.l1.0f.ko32 4a /r             ] ND,ZU,AVX512BW,FUTURE */
        /* 261(001 205) 001(4a) 120 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_ADDD, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65258, 504},
    /*   1 : ADDD kreg32,kreg32*,kreg32 [rvm:      evex.l1.0f.ko32 4a /r             ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fd 28) 300 001(4a) 120 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_ADDD, 3, {OPMASKREG|BITS32,OPMASKREG|BITS32,OPMASKREG|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+29844, 505},
    /*   2 : ADDD kreg32,kreg32 [r+vm:      vex.l1.0f.ko32 4a /r             ] ND,ZU,AVX512BW,FUTURE */
        /* 260(001 205) 001(4a) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_ADDD, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65265, 504},
    /*   3 : ADDD kreg32,kreg32 [r+vm:      evex.l1.0f.ko32 4a /r             ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fd 28) 300 001(4a) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_ADDD, 2, {OPMASKREG|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+29853, 505},
};

static const struct itemplate instrux_ADDQ[4] = {
    /*   0 : ADDQ kreg64,kreg64*,kreg64 [rvm:      vex.l1.0f.ko64 4a /r             ] ND,ZU,AVX512BW,FUTURE */
        /* 261(001 204) 001(4a) 120 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_ADDQ, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65272, 504},
    /*   1 : ADDQ kreg64,kreg64*,kreg64 [rvm:      evex.l1.0f.ko64 4a /r             ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fc 28) 300 001(4a) 120 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_ADDQ, 3, {OPMASKREG|BITS64,OPMASKREG|BITS64,OPMASKREG|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+29862, 505},
    /*   2 : ADDQ kreg64,kreg64 [r+vm:      vex.l1.0f.ko64 4a /r             ] ND,ZU,AVX512BW,FUTURE */
        /* 260(001 204) 001(4a) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_ADDQ, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65279, 504},
    /*   3 : ADDQ kreg64,kreg64 [r+vm:      evex.l1.0f.ko64 4a /r             ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fc 28) 300 001(4a) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_ADDQ, 2, {OPMASKREG|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+29871, 505},
};

static const struct itemplate instrux_KANDB[4] = {
    /*   0 : KANDB kreg8,kreg8*,kreg8 [rvm:      vex.l1.0f.ko8 41 /r              ] ZU,AVX512DQ,FUTURE */
        /* 261(001 005) 001(41) 120 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KANDB, 3, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65286, 500},
    /*   1 : KANDB kreg8,kreg8*,kreg8 [rvm:      evex.l1.0f.ko8 41 /r              ] ZU,AVX512DQ,FUTURE,APX */
        /* 241(f1 7d 28) 300 001(41) 120 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KANDB, 3, {OPMASKREG|BITS8,OPMASKREG|BITS8,OPMASKREG|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+29880, 501},
    /*   2 : KANDB kreg8,kreg8 [r+vm:      vex.l1.0f.ko8 41 /r              ] ND,ZU,AVX512DQ,FUTURE */
        /* 260(001 005) 001(41) 110 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KANDB, 2, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65293, 500},
    /*   3 : KANDB kreg8,kreg8 [r+vm:      evex.l1.0f.ko8 41 /r              ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 240(f1 7d 28) 300 001(41) 110 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KANDB, 2, {OPMASKREG|BITS8,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+29889, 501},
};

static const struct itemplate instrux_KANDW[4] = {
    /*   0 : KANDW kreg16,kreg16*,kreg16 [rvm:      vex.l1.0f.ko16 41 /r             ] ZU,AVX512F,FUTURE */
        /* 261(001 004) 001(41) 120 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KANDW, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65300, 502},
    /*   1 : KANDW kreg16,kreg16*,kreg16 [rvm:      evex.l1.0f.ko16 41 /r             ] ZU,AVX512F,FUTURE,APX */
        /* 241(f1 7c 28) 300 001(41) 120 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KANDW, 3, {OPMASKREG|BITS16,OPMASKREG|BITS16,OPMASKREG|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+29898, 503},
    /*   2 : KANDW kreg16,kreg16 [r+vm:      vex.l1.0f.ko16 41 /r             ] ND,ZU,AVX512F,FUTURE */
        /* 260(001 004) 001(41) 110 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KANDW, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65307, 502},
    /*   3 : KANDW kreg16,kreg16 [r+vm:      evex.l1.0f.ko16 41 /r             ] ND,ZU,AVX512F,FUTURE,APX */
        /* 240(f1 7c 28) 300 001(41) 110 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KANDW, 2, {OPMASKREG|BITS16,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29907, 503},
};

static const struct itemplate instrux_KANDD[4] = {
    /*   0 : KANDD kreg32,kreg32*,kreg32 [rvm:      vex.l1.0f.ko32 41 /r             ] ZU,AVX512BW,FUTURE */
        /* 261(001 205) 001(41) 120 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KANDD, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65314, 504},
    /*   1 : KANDD kreg32,kreg32*,kreg32 [rvm:      evex.l1.0f.ko32 41 /r             ] ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fd 28) 300 001(41) 120 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KANDD, 3, {OPMASKREG|BITS32,OPMASKREG|BITS32,OPMASKREG|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+29916, 505},
    /*   2 : KANDD kreg32,kreg32 [r+vm:      vex.l1.0f.ko32 41 /r             ] ND,ZU,AVX512BW,FUTURE */
        /* 260(001 205) 001(41) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KANDD, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65321, 504},
    /*   3 : KANDD kreg32,kreg32 [r+vm:      evex.l1.0f.ko32 41 /r             ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fd 28) 300 001(41) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KANDD, 2, {OPMASKREG|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+29925, 505},
};

static const struct itemplate instrux_KANDQ[4] = {
    /*   0 : KANDQ kreg64,kreg64*,kreg64 [rvm:      vex.l1.0f.ko64 41 /r             ] ZU,AVX512BW,FUTURE */
        /* 261(001 204) 001(41) 120 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KANDQ, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65328, 504},
    /*   1 : KANDQ kreg64,kreg64*,kreg64 [rvm:      evex.l1.0f.ko64 41 /r             ] ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fc 28) 300 001(41) 120 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KANDQ, 3, {OPMASKREG|BITS64,OPMASKREG|BITS64,OPMASKREG|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+29934, 505},
    /*   2 : KANDQ kreg64,kreg64 [r+vm:      vex.l1.0f.ko64 41 /r             ] ND,ZU,AVX512BW,FUTURE */
        /* 260(001 204) 001(41) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KANDQ, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65335, 504},
    /*   3 : KANDQ kreg64,kreg64 [r+vm:      evex.l1.0f.ko64 41 /r             ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fc 28) 300 001(41) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KANDQ, 2, {OPMASKREG|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+29943, 505},
};

static const struct itemplate instrux_KAND[16] = {
    /*   0 : KAND kreg8,kreg8*,kreg8 [rvm:      vex.l1.0f.ko8 41 /r              ] ND,SM0,SM1,SM2,ZU,AVX512DQ,FUTURE */
        /* 261(001 005) 001(41) 120 : SM0,SM1,SM2,NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KAND, 3, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65286, 508},
    /*   1 : KAND kreg8,kreg8*,kreg8 [rvm:      evex.l1.0f.ko8 41 /r              ] ND,SM0,SM1,SM2,ZU,AVX512DQ,FUTURE,APX */
        /* 241(f1 7d 28) 300 001(41) 120 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KAND, 3, {OPMASKREG|BITS8,OPMASKREG|BITS8,OPMASKREG|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+29880, 509},
    /*   2 : KAND kreg8,kreg8 [r+vm:      vex.l1.0f.ko8 41 /r              ] ND,SM0,SM1,ZU,AVX512DQ,FUTURE */
        /* 260(001 005) 001(41) 110 : SM0,SM1,NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KAND, 2, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65293, 510},
    /*   3 : KAND kreg8,kreg8 [r+vm:      evex.l1.0f.ko8 41 /r              ] ND,SM0,SM1,ZU,AVX512DQ,FUTURE,APX */
        /* 240(f1 7d 28) 300 001(41) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KAND, 2, {OPMASKREG|BITS8,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+29889, 511},
    /*   4 : KAND kreg16,kreg16*,kreg16 [rvm:      vex.l1.0f.ko16 41 /r             ] ND,SM0,SM1,SM2,ZU,AVX512F,FUTURE */
        /* 261(001 004) 001(41) 120 : SM0,SM1,SM2,NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KAND, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65300, 524},
    /*   5 : KAND kreg16,kreg16*,kreg16 [rvm:      evex.l1.0f.ko16 41 /r             ] ND,SM0,SM1,SM2,ZU,AVX512F,FUTURE,APX */
        /* 241(f1 7c 28) 300 001(41) 120 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KAND, 3, {OPMASKREG|BITS16,OPMASKREG|BITS16,OPMASKREG|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+29898, 525},
    /*   6 : KAND kreg16,kreg16 [r+vm:      vex.l1.0f.ko16 41 /r             ] ND,SM0,SM1,ZU,AVX512F,FUTURE */
        /* 260(001 004) 001(41) 110 : SM0,SM1,NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KAND, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65307, 526},
    /*   7 : KAND kreg16,kreg16 [r+vm:      evex.l1.0f.ko16 41 /r             ] ND,SM0,SM1,ZU,AVX512F,FUTURE,APX */
        /* 240(f1 7c 28) 300 001(41) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KAND, 2, {OPMASKREG|BITS16,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29907, 527},
    /*   8 : KAND kreg32,kreg32*,kreg32 [rvm:      vex.l1.0f.ko32 41 /r             ] ND,SM0,SM1,SM2,ZU,AVX512BW,FUTURE */
        /* 261(001 205) 001(41) 120 : SM0,SM1,SM2,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KAND, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65314, 512},
    /*   9 : KAND kreg32,kreg32*,kreg32 [rvm:      evex.l1.0f.ko32 41 /r             ] ND,SM0,SM1,SM2,ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fd 28) 300 001(41) 120 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KAND, 3, {OPMASKREG|BITS32,OPMASKREG|BITS32,OPMASKREG|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+29916, 513},
    /*  10 : KAND kreg32,kreg32 [r+vm:      vex.l1.0f.ko32 41 /r             ] ND,SM0,SM1,ZU,AVX512BW,FUTURE */
        /* 260(001 205) 001(41) 110 : SM0,SM1,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KAND, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65321, 514},
    /*  11 : KAND kreg32,kreg32 [r+vm:      evex.l1.0f.ko32 41 /r             ] ND,SM0,SM1,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fd 28) 300 001(41) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KAND, 2, {OPMASKREG|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+29925, 515},
    /*  12 : KAND kreg64,kreg64*,kreg64 [rvm:      vex.l1.0f.ko64 41 /r             ] ND,SM0,SM1,SM2,ZU,AVX512BW,FUTURE */
        /* 261(001 204) 001(41) 120 : SM0,SM1,SM2,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KAND, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65328, 512},
    /*  13 : KAND kreg64,kreg64*,kreg64 [rvm:      evex.l1.0f.ko64 41 /r             ] ND,SM0,SM1,SM2,ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fc 28) 300 001(41) 120 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KAND, 3, {OPMASKREG|BITS64,OPMASKREG|BITS64,OPMASKREG|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+29934, 513},
    /*  14 : KAND kreg64,kreg64 [r+vm:      vex.l1.0f.ko64 41 /r             ] ND,SM0,SM1,ZU,AVX512BW,FUTURE */
        /* 260(001 204) 001(41) 110 : SM0,SM1,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KAND, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65335, 514},
    /*  15 : KAND kreg64,kreg64 [r+vm:      evex.l1.0f.ko64 41 /r             ] ND,SM0,SM1,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fc 28) 300 001(41) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KAND, 2, {OPMASKREG|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+29943, 515},
};

static const struct itemplate instrux_ANDB[4] = {
    /*   0 : ANDB kreg8,kreg8*,kreg8 [rvm:      vex.l1.0f.ko8 41 /r              ] ND,ZU,AVX512DQ,FUTURE */
        /* 261(001 005) 001(41) 120 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_ANDB, 3, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65286, 500},
    /*   1 : ANDB kreg8,kreg8*,kreg8 [rvm:      evex.l1.0f.ko8 41 /r              ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 241(f1 7d 28) 300 001(41) 120 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_ANDB, 3, {OPMASKREG|BITS8,OPMASKREG|BITS8,OPMASKREG|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+29880, 501},
    /*   2 : ANDB kreg8,kreg8 [r+vm:      vex.l1.0f.ko8 41 /r              ] ND,ZU,AVX512DQ,FUTURE */
        /* 260(001 005) 001(41) 110 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_ANDB, 2, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65293, 500},
    /*   3 : ANDB kreg8,kreg8 [r+vm:      evex.l1.0f.ko8 41 /r              ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 240(f1 7d 28) 300 001(41) 110 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_ANDB, 2, {OPMASKREG|BITS8,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+29889, 501},
};

static const struct itemplate instrux_ANDW[4] = {
    /*   0 : ANDW kreg16,kreg16*,kreg16 [rvm:      vex.l1.0f.ko16 41 /r             ] ND,ZU,AVX512F,FUTURE */
        /* 261(001 004) 001(41) 120 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_ANDW, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65300, 502},
    /*   1 : ANDW kreg16,kreg16*,kreg16 [rvm:      evex.l1.0f.ko16 41 /r             ] ND,ZU,AVX512F,FUTURE,APX */
        /* 241(f1 7c 28) 300 001(41) 120 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_ANDW, 3, {OPMASKREG|BITS16,OPMASKREG|BITS16,OPMASKREG|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+29898, 503},
    /*   2 : ANDW kreg16,kreg16 [r+vm:      vex.l1.0f.ko16 41 /r             ] ND,ZU,AVX512F,FUTURE */
        /* 260(001 004) 001(41) 110 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_ANDW, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65307, 502},
    /*   3 : ANDW kreg16,kreg16 [r+vm:      evex.l1.0f.ko16 41 /r             ] ND,ZU,AVX512F,FUTURE,APX */
        /* 240(f1 7c 28) 300 001(41) 110 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_ANDW, 2, {OPMASKREG|BITS16,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29907, 503},
};

static const struct itemplate instrux_ANDD[4] = {
    /*   0 : ANDD kreg32,kreg32*,kreg32 [rvm:      vex.l1.0f.ko32 41 /r             ] ND,ZU,AVX512BW,FUTURE */
        /* 261(001 205) 001(41) 120 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_ANDD, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65314, 504},
    /*   1 : ANDD kreg32,kreg32*,kreg32 [rvm:      evex.l1.0f.ko32 41 /r             ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fd 28) 300 001(41) 120 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_ANDD, 3, {OPMASKREG|BITS32,OPMASKREG|BITS32,OPMASKREG|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+29916, 505},
    /*   2 : ANDD kreg32,kreg32 [r+vm:      vex.l1.0f.ko32 41 /r             ] ND,ZU,AVX512BW,FUTURE */
        /* 260(001 205) 001(41) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_ANDD, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65321, 504},
    /*   3 : ANDD kreg32,kreg32 [r+vm:      evex.l1.0f.ko32 41 /r             ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fd 28) 300 001(41) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_ANDD, 2, {OPMASKREG|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+29925, 505},
};

static const struct itemplate instrux_ANDQ[4] = {
    /*   0 : ANDQ kreg64,kreg64*,kreg64 [rvm:      vex.l1.0f.ko64 41 /r             ] ND,ZU,AVX512BW,FUTURE */
        /* 261(001 204) 001(41) 120 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_ANDQ, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65328, 504},
    /*   1 : ANDQ kreg64,kreg64*,kreg64 [rvm:      evex.l1.0f.ko64 41 /r             ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fc 28) 300 001(41) 120 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_ANDQ, 3, {OPMASKREG|BITS64,OPMASKREG|BITS64,OPMASKREG|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+29934, 505},
    /*   2 : ANDQ kreg64,kreg64 [r+vm:      vex.l1.0f.ko64 41 /r             ] ND,ZU,AVX512BW,FUTURE */
        /* 260(001 204) 001(41) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_ANDQ, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65335, 504},
    /*   3 : ANDQ kreg64,kreg64 [r+vm:      evex.l1.0f.ko64 41 /r             ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fc 28) 300 001(41) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_ANDQ, 2, {OPMASKREG|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+29943, 505},
};

static const struct itemplate instrux_KANDNB[4] = {
    /*   0 : KANDNB kreg8,kreg8*,kreg8 [rvm:      vex.l1.0f.ko8 42 /r              ] ZU,AVX512DQ,FUTURE */
        /* 261(001 005) 001(42) 120 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KANDNB, 3, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65342, 500},
    /*   1 : KANDNB kreg8,kreg8*,kreg8 [rvm:      evex.l1.0f.ko8 42 /r              ] ZU,AVX512DQ,FUTURE,APX */
        /* 241(f1 7d 28) 300 001(42) 120 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KANDNB, 3, {OPMASKREG|BITS8,OPMASKREG|BITS8,OPMASKREG|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+29952, 501},
    /*   2 : KANDNB kreg8,kreg8 [r+vm:      vex.l1.0f.ko8 42 /r              ] ND,ZU,AVX512DQ,FUTURE */
        /* 260(001 005) 001(42) 110 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KANDNB, 2, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65349, 500},
    /*   3 : KANDNB kreg8,kreg8 [r+vm:      evex.l1.0f.ko8 42 /r              ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 240(f1 7d 28) 300 001(42) 110 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KANDNB, 2, {OPMASKREG|BITS8,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+29961, 501},
};

static const struct itemplate instrux_KANDNW[4] = {
    /*   0 : KANDNW kreg16,kreg16*,kreg16 [rvm:      vex.l1.0f.ko16 42 /r             ] ZU,AVX512F,FUTURE */
        /* 261(001 004) 001(42) 120 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KANDNW, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65356, 502},
    /*   1 : KANDNW kreg16,kreg16*,kreg16 [rvm:      evex.l1.0f.ko16 42 /r             ] ZU,AVX512F,FUTURE,APX */
        /* 241(f1 7c 28) 300 001(42) 120 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KANDNW, 3, {OPMASKREG|BITS16,OPMASKREG|BITS16,OPMASKREG|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+29970, 503},
    /*   2 : KANDNW kreg16,kreg16 [r+vm:      vex.l1.0f.ko16 42 /r             ] ND,ZU,AVX512F,FUTURE */
        /* 260(001 004) 001(42) 110 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KANDNW, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65363, 502},
    /*   3 : KANDNW kreg16,kreg16 [r+vm:      evex.l1.0f.ko16 42 /r             ] ND,ZU,AVX512F,FUTURE,APX */
        /* 240(f1 7c 28) 300 001(42) 110 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KANDNW, 2, {OPMASKREG|BITS16,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29979, 503},
};

static const struct itemplate instrux_KANDND[4] = {
    /*   0 : KANDND kreg32,kreg32*,kreg32 [rvm:      vex.l1.0f.ko32 42 /r             ] ZU,AVX512BW,FUTURE */
        /* 261(001 205) 001(42) 120 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KANDND, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65370, 504},
    /*   1 : KANDND kreg32,kreg32*,kreg32 [rvm:      evex.l1.0f.ko32 42 /r             ] ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fd 28) 300 001(42) 120 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KANDND, 3, {OPMASKREG|BITS32,OPMASKREG|BITS32,OPMASKREG|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+29988, 505},
    /*   2 : KANDND kreg32,kreg32 [r+vm:      vex.l1.0f.ko32 42 /r             ] ND,ZU,AVX512BW,FUTURE */
        /* 260(001 205) 001(42) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KANDND, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65377, 504},
    /*   3 : KANDND kreg32,kreg32 [r+vm:      evex.l1.0f.ko32 42 /r             ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fd 28) 300 001(42) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KANDND, 2, {OPMASKREG|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+29997, 505},
};

static const struct itemplate instrux_KANDNQ[4] = {
    /*   0 : KANDNQ kreg64,kreg64*,kreg64 [rvm:      vex.l1.0f.ko64 42 /r             ] ZU,AVX512BW,FUTURE */
        /* 261(001 204) 001(42) 120 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KANDNQ, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65384, 504},
    /*   1 : KANDNQ kreg64,kreg64*,kreg64 [rvm:      evex.l1.0f.ko64 42 /r             ] ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fc 28) 300 001(42) 120 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KANDNQ, 3, {OPMASKREG|BITS64,OPMASKREG|BITS64,OPMASKREG|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+30006, 505},
    /*   2 : KANDNQ kreg64,kreg64 [r+vm:      vex.l1.0f.ko64 42 /r             ] ND,ZU,AVX512BW,FUTURE */
        /* 260(001 204) 001(42) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KANDNQ, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65391, 504},
    /*   3 : KANDNQ kreg64,kreg64 [r+vm:      evex.l1.0f.ko64 42 /r             ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fc 28) 300 001(42) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KANDNQ, 2, {OPMASKREG|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+30015, 505},
};

static const struct itemplate instrux_KANDN[16] = {
    /*   0 : KANDN kreg8,kreg8*,kreg8 [rvm:      vex.l1.0f.ko8 42 /r              ] ND,SM0,SM1,SM2,ZU,AVX512DQ,FUTURE */
        /* 261(001 005) 001(42) 120 : SM0,SM1,SM2,NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KANDN, 3, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65342, 508},
    /*   1 : KANDN kreg8,kreg8*,kreg8 [rvm:      evex.l1.0f.ko8 42 /r              ] ND,SM0,SM1,SM2,ZU,AVX512DQ,FUTURE,APX */
        /* 241(f1 7d 28) 300 001(42) 120 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KANDN, 3, {OPMASKREG|BITS8,OPMASKREG|BITS8,OPMASKREG|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+29952, 509},
    /*   2 : KANDN kreg8,kreg8 [r+vm:      vex.l1.0f.ko8 42 /r              ] ND,SM0,SM1,ZU,AVX512DQ,FUTURE */
        /* 260(001 005) 001(42) 110 : SM0,SM1,NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KANDN, 2, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65349, 510},
    /*   3 : KANDN kreg8,kreg8 [r+vm:      evex.l1.0f.ko8 42 /r              ] ND,SM0,SM1,ZU,AVX512DQ,FUTURE,APX */
        /* 240(f1 7d 28) 300 001(42) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KANDN, 2, {OPMASKREG|BITS8,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+29961, 511},
    /*   4 : KANDN kreg16,kreg16*,kreg16 [rvm:      vex.l1.0f.ko16 42 /r             ] ND,SM0,SM1,SM2,ZU,AVX512F,FUTURE */
        /* 261(001 004) 001(42) 120 : SM0,SM1,SM2,NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KANDN, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65356, 524},
    /*   5 : KANDN kreg16,kreg16*,kreg16 [rvm:      evex.l1.0f.ko16 42 /r             ] ND,SM0,SM1,SM2,ZU,AVX512F,FUTURE,APX */
        /* 241(f1 7c 28) 300 001(42) 120 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KANDN, 3, {OPMASKREG|BITS16,OPMASKREG|BITS16,OPMASKREG|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+29970, 525},
    /*   6 : KANDN kreg16,kreg16 [r+vm:      vex.l1.0f.ko16 42 /r             ] ND,SM0,SM1,ZU,AVX512F,FUTURE */
        /* 260(001 004) 001(42) 110 : SM0,SM1,NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KANDN, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65363, 526},
    /*   7 : KANDN kreg16,kreg16 [r+vm:      evex.l1.0f.ko16 42 /r             ] ND,SM0,SM1,ZU,AVX512F,FUTURE,APX */
        /* 240(f1 7c 28) 300 001(42) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KANDN, 2, {OPMASKREG|BITS16,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29979, 527},
    /*   8 : KANDN kreg32,kreg32*,kreg32 [rvm:      vex.l1.0f.ko32 42 /r             ] ND,SM0,SM1,SM2,ZU,AVX512BW,FUTURE */
        /* 261(001 205) 001(42) 120 : SM0,SM1,SM2,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KANDN, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65370, 512},
    /*   9 : KANDN kreg32,kreg32*,kreg32 [rvm:      evex.l1.0f.ko32 42 /r             ] ND,SM0,SM1,SM2,ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fd 28) 300 001(42) 120 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KANDN, 3, {OPMASKREG|BITS32,OPMASKREG|BITS32,OPMASKREG|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+29988, 513},
    /*  10 : KANDN kreg32,kreg32 [r+vm:      vex.l1.0f.ko32 42 /r             ] ND,SM0,SM1,ZU,AVX512BW,FUTURE */
        /* 260(001 205) 001(42) 110 : SM0,SM1,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KANDN, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65377, 514},
    /*  11 : KANDN kreg32,kreg32 [r+vm:      evex.l1.0f.ko32 42 /r             ] ND,SM0,SM1,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fd 28) 300 001(42) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KANDN, 2, {OPMASKREG|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+29997, 515},
    /*  12 : KANDN kreg64,kreg64*,kreg64 [rvm:      vex.l1.0f.ko64 42 /r             ] ND,SM0,SM1,SM2,ZU,AVX512BW,FUTURE */
        /* 261(001 204) 001(42) 120 : SM0,SM1,SM2,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KANDN, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65384, 512},
    /*  13 : KANDN kreg64,kreg64*,kreg64 [rvm:      evex.l1.0f.ko64 42 /r             ] ND,SM0,SM1,SM2,ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fc 28) 300 001(42) 120 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KANDN, 3, {OPMASKREG|BITS64,OPMASKREG|BITS64,OPMASKREG|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+30006, 513},
    /*  14 : KANDN kreg64,kreg64 [r+vm:      vex.l1.0f.ko64 42 /r             ] ND,SM0,SM1,ZU,AVX512BW,FUTURE */
        /* 260(001 204) 001(42) 110 : SM0,SM1,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KANDN, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65391, 514},
    /*  15 : KANDN kreg64,kreg64 [r+vm:      evex.l1.0f.ko64 42 /r             ] ND,SM0,SM1,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fc 28) 300 001(42) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KANDN, 2, {OPMASKREG|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+30015, 515},
};

static const struct itemplate instrux_ANDNB[4] = {
    /*   0 : ANDNB kreg8,kreg8*,kreg8 [rvm:      vex.l1.0f.ko8 42 /r              ] ND,ZU,AVX512DQ,FUTURE */
        /* 261(001 005) 001(42) 120 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_ANDNB, 3, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65342, 500},
    /*   1 : ANDNB kreg8,kreg8*,kreg8 [rvm:      evex.l1.0f.ko8 42 /r              ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 241(f1 7d 28) 300 001(42) 120 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_ANDNB, 3, {OPMASKREG|BITS8,OPMASKREG|BITS8,OPMASKREG|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+29952, 501},
    /*   2 : ANDNB kreg8,kreg8 [r+vm:      vex.l1.0f.ko8 42 /r              ] ND,ZU,AVX512DQ,FUTURE */
        /* 260(001 005) 001(42) 110 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_ANDNB, 2, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65349, 500},
    /*   3 : ANDNB kreg8,kreg8 [r+vm:      evex.l1.0f.ko8 42 /r              ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 240(f1 7d 28) 300 001(42) 110 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_ANDNB, 2, {OPMASKREG|BITS8,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+29961, 501},
};

static const struct itemplate instrux_ANDNW[4] = {
    /*   0 : ANDNW kreg16,kreg16*,kreg16 [rvm:      vex.l1.0f.ko16 42 /r             ] ND,ZU,AVX512F,FUTURE */
        /* 261(001 004) 001(42) 120 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_ANDNW, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65356, 502},
    /*   1 : ANDNW kreg16,kreg16*,kreg16 [rvm:      evex.l1.0f.ko16 42 /r             ] ND,ZU,AVX512F,FUTURE,APX */
        /* 241(f1 7c 28) 300 001(42) 120 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_ANDNW, 3, {OPMASKREG|BITS16,OPMASKREG|BITS16,OPMASKREG|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+29970, 503},
    /*   2 : ANDNW kreg16,kreg16 [r+vm:      vex.l1.0f.ko16 42 /r             ] ND,ZU,AVX512F,FUTURE */
        /* 260(001 004) 001(42) 110 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_ANDNW, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65363, 502},
    /*   3 : ANDNW kreg16,kreg16 [r+vm:      evex.l1.0f.ko16 42 /r             ] ND,ZU,AVX512F,FUTURE,APX */
        /* 240(f1 7c 28) 300 001(42) 110 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_ANDNW, 2, {OPMASKREG|BITS16,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29979, 503},
};

static const struct itemplate instrux_ANDND[4] = {
    /*   0 : ANDND kreg32,kreg32*,kreg32 [rvm:      vex.l1.0f.ko32 42 /r             ] ND,ZU,AVX512BW,FUTURE */
        /* 261(001 205) 001(42) 120 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_ANDND, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65370, 504},
    /*   1 : ANDND kreg32,kreg32*,kreg32 [rvm:      evex.l1.0f.ko32 42 /r             ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fd 28) 300 001(42) 120 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_ANDND, 3, {OPMASKREG|BITS32,OPMASKREG|BITS32,OPMASKREG|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+29988, 505},
    /*   2 : ANDND kreg32,kreg32 [r+vm:      vex.l1.0f.ko32 42 /r             ] ND,ZU,AVX512BW,FUTURE */
        /* 260(001 205) 001(42) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_ANDND, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65377, 504},
    /*   3 : ANDND kreg32,kreg32 [r+vm:      evex.l1.0f.ko32 42 /r             ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fd 28) 300 001(42) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_ANDND, 2, {OPMASKREG|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+29997, 505},
};

static const struct itemplate instrux_ANDNQ[4] = {
    /*   0 : ANDNQ kreg64,kreg64*,kreg64 [rvm:      vex.l1.0f.ko64 42 /r             ] ND,ZU,AVX512BW,FUTURE */
        /* 261(001 204) 001(42) 120 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_ANDNQ, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65384, 504},
    /*   1 : ANDNQ kreg64,kreg64*,kreg64 [rvm:      evex.l1.0f.ko64 42 /r             ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fc 28) 300 001(42) 120 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_ANDNQ, 3, {OPMASKREG|BITS64,OPMASKREG|BITS64,OPMASKREG|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+30006, 505},
    /*   2 : ANDNQ kreg64,kreg64 [r+vm:      vex.l1.0f.ko64 42 /r             ] ND,ZU,AVX512BW,FUTURE */
        /* 260(001 204) 001(42) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_ANDNQ, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65391, 504},
    /*   3 : ANDNQ kreg64,kreg64 [r+vm:      evex.l1.0f.ko64 42 /r             ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fc 28) 300 001(42) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_ANDNQ, 2, {OPMASKREG|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+30015, 505},
};

static const struct itemplate instrux_KNOTB[4] = {
    /*   0 : KNOTB kreg8,kreg8* [rm:       vex.l0.0f.ko8 44 /r              ] ZU,AVX512DQ,FUTURE */
        /* 270(001 001) 001(44) 110 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KNOTB, 2, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65398, 500},
    /*   1 : KNOTB kreg8,kreg8* [rm:       evex.l0.0f.ko8 44 /r              ] ZU,AVX512DQ,FUTURE,APX */
        /* 250(f1 7d 08) 300 001(44) 110 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KNOTB, 2, {OPMASKREG|BITS8,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+30024, 501},
    /*   2 : KNOTB kreg8 [r+m:       vex.l0.0f.ko8 44 /r              ] ND,ZU,AVX512DQ,FUTURE */
        /* 270(001 001) 001(44) 100 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KNOTB, 1, {OPMASKREG|BITS8|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+65405, 500},
    /*   3 : KNOTB kreg8 [r+m:       evex.l0.0f.ko8 44 /r              ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 250(f1 7d 08) 300 001(44) 100 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KNOTB, 1, {OPMASKREG|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+30033, 501},
};

static const struct itemplate instrux_KNOTW[4] = {
    /*   0 : KNOTW kreg16,kreg16* [rm:       vex.l0.0f.ko16 44 /r             ] ZU,AVX512F,FUTURE */
        /* 270(001 000) 001(44) 110 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KNOTW, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65412, 502},
    /*   1 : KNOTW kreg16,kreg16* [rm:       evex.l0.0f.ko16 44 /r             ] ZU,AVX512F,FUTURE,APX */
        /* 250(f1 7c 08) 300 001(44) 110 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KNOTW, 2, {OPMASKREG|BITS16,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+30042, 503},
    /*   2 : KNOTW kreg16 [r+m:       vex.l0.0f.ko16 44 /r             ] ND,ZU,AVX512F,FUTURE */
        /* 270(001 000) 001(44) 100 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KNOTW, 1, {OPMASKREG|BITS16|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+65419, 502},
    /*   3 : KNOTW kreg16 [r+m:       evex.l0.0f.ko16 44 /r             ] ND,ZU,AVX512F,FUTURE,APX */
        /* 250(f1 7c 08) 300 001(44) 100 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KNOTW, 1, {OPMASKREG|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+30051, 503},
};

static const struct itemplate instrux_KNOTD[4] = {
    /*   0 : KNOTD kreg32,kreg32* [rm:       vex.l0.0f.ko32 44 /r             ] ZU,AVX512BW,FUTURE */
        /* 270(001 201) 001(44) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KNOTD, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65426, 504},
    /*   1 : KNOTD kreg32,kreg32* [rm:       evex.l0.0f.ko32 44 /r             ] ZU,AVX512BW,FUTURE,APX */
        /* 250(f1 fd 08) 300 001(44) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KNOTD, 2, {OPMASKREG|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+30060, 505},
    /*   2 : KNOTD kreg32 [r+m:       vex.l0.0f.ko32 44 /r             ] ND,ZU,AVX512BW,FUTURE */
        /* 270(001 201) 001(44) 100 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KNOTD, 1, {OPMASKREG|BITS32|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+65433, 504},
    /*   3 : KNOTD kreg32 [r+m:       evex.l0.0f.ko32 44 /r             ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 250(f1 fd 08) 300 001(44) 100 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KNOTD, 1, {OPMASKREG|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+30069, 505},
};

static const struct itemplate instrux_KNOTQ[4] = {
    /*   0 : KNOTQ kreg64,kreg64* [rm:       vex.l0.0f.ko64 44 /r             ] ZU,AVX512BW,FUTURE */
        /* 270(001 200) 001(44) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KNOTQ, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65440, 504},
    /*   1 : KNOTQ kreg64,kreg64* [rm:       evex.l0.0f.ko64 44 /r             ] ZU,AVX512BW,FUTURE,APX */
        /* 250(f1 fc 08) 300 001(44) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KNOTQ, 2, {OPMASKREG|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+30078, 505},
    /*   2 : KNOTQ kreg64 [r+m:       vex.l0.0f.ko64 44 /r             ] ND,ZU,AVX512BW,FUTURE */
        /* 270(001 200) 001(44) 100 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KNOTQ, 1, {OPMASKREG|BITS64|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+65447, 504},
    /*   3 : KNOTQ kreg64 [r+m:       evex.l0.0f.ko64 44 /r             ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 250(f1 fc 08) 300 001(44) 100 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KNOTQ, 1, {OPMASKREG|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+30087, 505},
};

static const struct itemplate instrux_KNOT[16] = {
    /*   0 : KNOT kreg8,kreg8* [rm:       vex.l0.0f.ko8 44 /r              ] ND,SM0,SM1,ZU,AVX512DQ,FUTURE */
        /* 270(001 001) 001(44) 110 : SM0,SM1,NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KNOT, 2, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65398, 510},
    /*   1 : KNOT kreg8,kreg8* [rm:       evex.l0.0f.ko8 44 /r              ] ND,SM0,SM1,ZU,AVX512DQ,FUTURE,APX */
        /* 250(f1 7d 08) 300 001(44) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KNOT, 2, {OPMASKREG|BITS8,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+30024, 511},
    /*   2 : KNOT kreg8 [r+m:       vex.l0.0f.ko8 44 /r              ] ND,SM0,ZU,AVX512DQ,FUTURE */
        /* 270(001 001) 001(44) 100 : SM0,NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KNOT, 1, {OPMASKREG|BITS8|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+65405, 532},
    /*   3 : KNOT kreg8 [r+m:       evex.l0.0f.ko8 44 /r              ] ND,SM0,ZU,AVX512DQ,FUTURE,APX */
        /* 250(f1 7d 08) 300 001(44) 100 : SM0,ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KNOT, 1, {OPMASKREG|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+30033, 533},
    /*   4 : KNOT kreg16,kreg16* [rm:       vex.l0.0f.ko16 44 /r             ] ND,SM0,SM1,ZU,AVX512F,FUTURE */
        /* 270(001 000) 001(44) 110 : SM0,SM1,NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KNOT, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65412, 526},
    /*   5 : KNOT kreg16,kreg16* [rm:       evex.l0.0f.ko16 44 /r             ] ND,SM0,SM1,ZU,AVX512F,FUTURE,APX */
        /* 250(f1 7c 08) 300 001(44) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KNOT, 2, {OPMASKREG|BITS16,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+30042, 527},
    /*   6 : KNOT kreg16 [r+m:       vex.l0.0f.ko16 44 /r             ] ND,SM0,ZU,AVX512F,FUTURE */
        /* 270(001 000) 001(44) 100 : SM0,NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KNOT, 1, {OPMASKREG|BITS16|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+65419, 534},
    /*   7 : KNOT kreg16 [r+m:       evex.l0.0f.ko16 44 /r             ] ND,SM0,ZU,AVX512F,FUTURE,APX */
        /* 250(f1 7c 08) 300 001(44) 100 : SM0,ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KNOT, 1, {OPMASKREG|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+30051, 535},
    /*   8 : KNOT kreg32,kreg32* [rm:       vex.l0.0f.ko32 44 /r             ] ND,SM0,SM1,ZU,AVX512BW,FUTURE */
        /* 270(001 201) 001(44) 110 : SM0,SM1,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KNOT, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65426, 514},
    /*   9 : KNOT kreg32,kreg32* [rm:       evex.l0.0f.ko32 44 /r             ] ND,SM0,SM1,ZU,AVX512BW,FUTURE,APX */
        /* 250(f1 fd 08) 300 001(44) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KNOT, 2, {OPMASKREG|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+30060, 515},
    /*  10 : KNOT kreg32 [r+m:       vex.l0.0f.ko32 44 /r             ] ND,SM0,ZU,AVX512BW,FUTURE */
        /* 270(001 201) 001(44) 100 : SM0,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KNOT, 1, {OPMASKREG|BITS32|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+65433, 536},
    /*  11 : KNOT kreg32 [r+m:       evex.l0.0f.ko32 44 /r             ] ND,SM0,ZU,AVX512BW,FUTURE,APX */
        /* 250(f1 fd 08) 300 001(44) 100 : SM0,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KNOT, 1, {OPMASKREG|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+30069, 537},
    /*  12 : KNOT kreg64,kreg64* [rm:       vex.l0.0f.ko64 44 /r             ] ND,SM0,SM1,ZU,AVX512BW,FUTURE */
        /* 270(001 200) 001(44) 110 : SM0,SM1,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KNOT, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65440, 514},
    /*  13 : KNOT kreg64,kreg64* [rm:       evex.l0.0f.ko64 44 /r             ] ND,SM0,SM1,ZU,AVX512BW,FUTURE,APX */
        /* 250(f1 fc 08) 300 001(44) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KNOT, 2, {OPMASKREG|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+30078, 515},
    /*  14 : KNOT kreg64 [r+m:       vex.l0.0f.ko64 44 /r             ] ND,SM0,ZU,AVX512BW,FUTURE */
        /* 270(001 200) 001(44) 100 : SM0,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KNOT, 1, {OPMASKREG|BITS64|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+65447, 536},
    /*  15 : KNOT kreg64 [r+m:       evex.l0.0f.ko64 44 /r             ] ND,SM0,ZU,AVX512BW,FUTURE,APX */
        /* 250(f1 fc 08) 300 001(44) 100 : SM0,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KNOT, 1, {OPMASKREG|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+30087, 537},
};

static const struct itemplate instrux_NOTB[4] = {
    /*   0 : NOTB kreg8,kreg8* [rm:       vex.l0.0f.ko8 44 /r              ] ND,ZU,AVX512DQ,FUTURE */
        /* 270(001 001) 001(44) 110 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_NOTB, 2, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65398, 500},
    /*   1 : NOTB kreg8,kreg8* [rm:       evex.l0.0f.ko8 44 /r              ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 250(f1 7d 08) 300 001(44) 110 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_NOTB, 2, {OPMASKREG|BITS8,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+30024, 501},
    /*   2 : NOTB kreg8 [r+m:       vex.l0.0f.ko8 44 /r              ] ND,ZU,AVX512DQ,FUTURE */
        /* 270(001 001) 001(44) 100 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_NOTB, 1, {OPMASKREG|BITS8|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+65405, 500},
    /*   3 : NOTB kreg8 [r+m:       evex.l0.0f.ko8 44 /r              ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 250(f1 7d 08) 300 001(44) 100 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_NOTB, 1, {OPMASKREG|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+30033, 501},
};

static const struct itemplate instrux_NOTW[4] = {
    /*   0 : NOTW kreg16,kreg16* [rm:       vex.l0.0f.ko16 44 /r             ] ND,ZU,AVX512F,FUTURE */
        /* 270(001 000) 001(44) 110 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_NOTW, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65412, 502},
    /*   1 : NOTW kreg16,kreg16* [rm:       evex.l0.0f.ko16 44 /r             ] ND,ZU,AVX512F,FUTURE,APX */
        /* 250(f1 7c 08) 300 001(44) 110 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_NOTW, 2, {OPMASKREG|BITS16,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+30042, 503},
    /*   2 : NOTW kreg16 [r+m:       vex.l0.0f.ko16 44 /r             ] ND,ZU,AVX512F,FUTURE */
        /* 270(001 000) 001(44) 100 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_NOTW, 1, {OPMASKREG|BITS16|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+65419, 502},
    /*   3 : NOTW kreg16 [r+m:       evex.l0.0f.ko16 44 /r             ] ND,ZU,AVX512F,FUTURE,APX */
        /* 250(f1 7c 08) 300 001(44) 100 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_NOTW, 1, {OPMASKREG|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+30051, 503},
};

static const struct itemplate instrux_NOTD[4] = {
    /*   0 : NOTD kreg32,kreg32* [rm:       vex.l0.0f.ko32 44 /r             ] ND,ZU,AVX512BW,FUTURE */
        /* 270(001 201) 001(44) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_NOTD, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65426, 504},
    /*   1 : NOTD kreg32,kreg32* [rm:       evex.l0.0f.ko32 44 /r             ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 250(f1 fd 08) 300 001(44) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_NOTD, 2, {OPMASKREG|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+30060, 505},
    /*   2 : NOTD kreg32 [r+m:       vex.l0.0f.ko32 44 /r             ] ND,ZU,AVX512BW,FUTURE */
        /* 270(001 201) 001(44) 100 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_NOTD, 1, {OPMASKREG|BITS32|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+65433, 504},
    /*   3 : NOTD kreg32 [r+m:       evex.l0.0f.ko32 44 /r             ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 250(f1 fd 08) 300 001(44) 100 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_NOTD, 1, {OPMASKREG|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+30069, 505},
};

static const struct itemplate instrux_NOTQ[4] = {
    /*   0 : NOTQ kreg64,kreg64* [rm:       vex.l0.0f.ko64 44 /r             ] ND,ZU,AVX512BW,FUTURE */
        /* 270(001 200) 001(44) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_NOTQ, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65440, 504},
    /*   1 : NOTQ kreg64,kreg64* [rm:       evex.l0.0f.ko64 44 /r             ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 250(f1 fc 08) 300 001(44) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_NOTQ, 2, {OPMASKREG|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+30078, 505},
    /*   2 : NOTQ kreg64 [r+m:       vex.l0.0f.ko64 44 /r             ] ND,ZU,AVX512BW,FUTURE */
        /* 270(001 200) 001(44) 100 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_NOTQ, 1, {OPMASKREG|BITS64|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+65447, 504},
    /*   3 : NOTQ kreg64 [r+m:       evex.l0.0f.ko64 44 /r             ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 250(f1 fc 08) 300 001(44) 100 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_NOTQ, 1, {OPMASKREG|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+30087, 505},
};

static const struct itemplate instrux_KORB[4] = {
    /*   0 : KORB kreg8,kreg8*,kreg8 [rvm:      vex.nds.l1.0f.ko8 45 /r          ] ZU,AVX512DQ,FUTURE */
        /* 261(001 005) 001(45) 120 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KORB, 3, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65454, 500},
    /*   1 : KORB kreg8,kreg8*,kreg8 [rvm:      evex.nds.l1.0f.ko8 45 /r          ] ZU,AVX512DQ,FUTURE,APX */
        /* 241(f1 7d 28) 300 001(45) 120 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KORB, 3, {OPMASKREG|BITS8,OPMASKREG|BITS8,OPMASKREG|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+30096, 501},
    /*   2 : KORB kreg8,kreg8 [r+vm:      vex.nds.l1.0f.ko8 45 /r          ] ND,ZU,AVX512DQ,FUTURE */
        /* 260(001 005) 001(45) 110 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KORB, 2, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65461, 500},
    /*   3 : KORB kreg8,kreg8 [r+vm:      evex.nds.l1.0f.ko8 45 /r          ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 240(f1 7d 28) 300 001(45) 110 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KORB, 2, {OPMASKREG|BITS8,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+30105, 501},
};

static const struct itemplate instrux_KORW[4] = {
    /*   0 : KORW kreg16,kreg16*,kreg16 [rvm:      vex.nds.l1.0f.ko16 45 /r         ] ZU,AVX512F,FUTURE */
        /* 261(001 004) 001(45) 120 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KORW, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65468, 502},
    /*   1 : KORW kreg16,kreg16*,kreg16 [rvm:      evex.nds.l1.0f.ko16 45 /r         ] ZU,AVX512F,FUTURE,APX */
        /* 241(f1 7c 28) 300 001(45) 120 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KORW, 3, {OPMASKREG|BITS16,OPMASKREG|BITS16,OPMASKREG|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+30114, 503},
    /*   2 : KORW kreg16,kreg16 [r+vm:      vex.nds.l1.0f.ko16 45 /r         ] ND,ZU,AVX512F,FUTURE */
        /* 260(001 004) 001(45) 110 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KORW, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65475, 502},
    /*   3 : KORW kreg16,kreg16 [r+vm:      evex.nds.l1.0f.ko16 45 /r         ] ND,ZU,AVX512F,FUTURE,APX */
        /* 240(f1 7c 28) 300 001(45) 110 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KORW, 2, {OPMASKREG|BITS16,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+30123, 503},
};

static const struct itemplate instrux_KORD[4] = {
    /*   0 : KORD kreg32,kreg32*,kreg32 [rvm:      vex.nds.l1.0f.ko32 45 /r         ] ZU,AVX512BW,FUTURE */
        /* 261(001 205) 001(45) 120 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KORD, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65482, 504},
    /*   1 : KORD kreg32,kreg32*,kreg32 [rvm:      evex.nds.l1.0f.ko32 45 /r         ] ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fd 28) 300 001(45) 120 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KORD, 3, {OPMASKREG|BITS32,OPMASKREG|BITS32,OPMASKREG|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+30132, 505},
    /*   2 : KORD kreg32,kreg32 [r+vm:      vex.nds.l1.0f.ko32 45 /r         ] ND,ZU,AVX512BW,FUTURE */
        /* 260(001 205) 001(45) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KORD, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65489, 504},
    /*   3 : KORD kreg32,kreg32 [r+vm:      evex.nds.l1.0f.ko32 45 /r         ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fd 28) 300 001(45) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KORD, 2, {OPMASKREG|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+30141, 505},
};

static const struct itemplate instrux_KORQ[4] = {
    /*   0 : KORQ kreg64,kreg64*,kreg64 [rvm:      vex.nds.l1.0f.ko64 45 /r         ] ZU,AVX512BW,FUTURE */
        /* 261(001 204) 001(45) 120 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KORQ, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65496, 504},
    /*   1 : KORQ kreg64,kreg64*,kreg64 [rvm:      evex.nds.l1.0f.ko64 45 /r         ] ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fc 28) 300 001(45) 120 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KORQ, 3, {OPMASKREG|BITS64,OPMASKREG|BITS64,OPMASKREG|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+30150, 505},
    /*   2 : KORQ kreg64,kreg64 [r+vm:      vex.nds.l1.0f.ko64 45 /r         ] ND,ZU,AVX512BW,FUTURE */
        /* 260(001 204) 001(45) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KORQ, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65503, 504},
    /*   3 : KORQ kreg64,kreg64 [r+vm:      evex.nds.l1.0f.ko64 45 /r         ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fc 28) 300 001(45) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KORQ, 2, {OPMASKREG|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+30159, 505},
};

static const struct itemplate instrux_KOR[16] = {
    /*   0 : KOR kreg8,kreg8*,kreg8 [rvm:      vex.nds.l1.0f.ko8 45 /r          ] ND,SM0,SM1,SM2,ZU,AVX512DQ,FUTURE */
        /* 261(001 005) 001(45) 120 : SM0,SM1,SM2,NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KOR, 3, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65454, 508},
    /*   1 : KOR kreg8,kreg8*,kreg8 [rvm:      evex.nds.l1.0f.ko8 45 /r          ] ND,SM0,SM1,SM2,ZU,AVX512DQ,FUTURE,APX */
        /* 241(f1 7d 28) 300 001(45) 120 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KOR, 3, {OPMASKREG|BITS8,OPMASKREG|BITS8,OPMASKREG|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+30096, 509},
    /*   2 : KOR kreg8,kreg8 [r+vm:      vex.nds.l1.0f.ko8 45 /r          ] ND,SM0,SM1,ZU,AVX512DQ,FUTURE */
        /* 260(001 005) 001(45) 110 : SM0,SM1,NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KOR, 2, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65461, 510},
    /*   3 : KOR kreg8,kreg8 [r+vm:      evex.nds.l1.0f.ko8 45 /r          ] ND,SM0,SM1,ZU,AVX512DQ,FUTURE,APX */
        /* 240(f1 7d 28) 300 001(45) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KOR, 2, {OPMASKREG|BITS8,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+30105, 511},
    /*   4 : KOR kreg16,kreg16*,kreg16 [rvm:      vex.nds.l1.0f.ko16 45 /r         ] ND,SM0,SM1,SM2,ZU,AVX512F,FUTURE */
        /* 261(001 004) 001(45) 120 : SM0,SM1,SM2,NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KOR, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65468, 524},
    /*   5 : KOR kreg16,kreg16*,kreg16 [rvm:      evex.nds.l1.0f.ko16 45 /r         ] ND,SM0,SM1,SM2,ZU,AVX512F,FUTURE,APX */
        /* 241(f1 7c 28) 300 001(45) 120 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KOR, 3, {OPMASKREG|BITS16,OPMASKREG|BITS16,OPMASKREG|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+30114, 525},
    /*   6 : KOR kreg16,kreg16 [r+vm:      vex.nds.l1.0f.ko16 45 /r         ] ND,SM0,SM1,ZU,AVX512F,FUTURE */
        /* 260(001 004) 001(45) 110 : SM0,SM1,NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KOR, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65475, 526},
    /*   7 : KOR kreg16,kreg16 [r+vm:      evex.nds.l1.0f.ko16 45 /r         ] ND,SM0,SM1,ZU,AVX512F,FUTURE,APX */
        /* 240(f1 7c 28) 300 001(45) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KOR, 2, {OPMASKREG|BITS16,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+30123, 527},
    /*   8 : KOR kreg32,kreg32*,kreg32 [rvm:      vex.nds.l1.0f.ko32 45 /r         ] ND,SM0,SM1,SM2,ZU,AVX512BW,FUTURE */
        /* 261(001 205) 001(45) 120 : SM0,SM1,SM2,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KOR, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65482, 512},
    /*   9 : KOR kreg32,kreg32*,kreg32 [rvm:      evex.nds.l1.0f.ko32 45 /r         ] ND,SM0,SM1,SM2,ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fd 28) 300 001(45) 120 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KOR, 3, {OPMASKREG|BITS32,OPMASKREG|BITS32,OPMASKREG|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+30132, 513},
    /*  10 : KOR kreg32,kreg32 [r+vm:      vex.nds.l1.0f.ko32 45 /r         ] ND,SM0,SM1,ZU,AVX512BW,FUTURE */
        /* 260(001 205) 001(45) 110 : SM0,SM1,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KOR, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65489, 514},
    /*  11 : KOR kreg32,kreg32 [r+vm:      evex.nds.l1.0f.ko32 45 /r         ] ND,SM0,SM1,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fd 28) 300 001(45) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KOR, 2, {OPMASKREG|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+30141, 515},
    /*  12 : KOR kreg64,kreg64*,kreg64 [rvm:      vex.nds.l1.0f.ko64 45 /r         ] ND,SM0,SM1,SM2,ZU,AVX512BW,FUTURE */
        /* 261(001 204) 001(45) 120 : SM0,SM1,SM2,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KOR, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65496, 512},
    /*  13 : KOR kreg64,kreg64*,kreg64 [rvm:      evex.nds.l1.0f.ko64 45 /r         ] ND,SM0,SM1,SM2,ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fc 28) 300 001(45) 120 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KOR, 3, {OPMASKREG|BITS64,OPMASKREG|BITS64,OPMASKREG|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+30150, 513},
    /*  14 : KOR kreg64,kreg64 [r+vm:      vex.nds.l1.0f.ko64 45 /r         ] ND,SM0,SM1,ZU,AVX512BW,FUTURE */
        /* 260(001 204) 001(45) 110 : SM0,SM1,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KOR, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65503, 514},
    /*  15 : KOR kreg64,kreg64 [r+vm:      evex.nds.l1.0f.ko64 45 /r         ] ND,SM0,SM1,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fc 28) 300 001(45) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KOR, 2, {OPMASKREG|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+30159, 515},
};

static const struct itemplate instrux_ORB[4] = {
    /*   0 : ORB kreg8,kreg8*,kreg8 [rvm:      vex.nds.l1.0f.ko8 45 /r          ] ND,ZU,AVX512DQ,FUTURE */
        /* 261(001 005) 001(45) 120 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_ORB, 3, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65454, 500},
    /*   1 : ORB kreg8,kreg8*,kreg8 [rvm:      evex.nds.l1.0f.ko8 45 /r          ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 241(f1 7d 28) 300 001(45) 120 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_ORB, 3, {OPMASKREG|BITS8,OPMASKREG|BITS8,OPMASKREG|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+30096, 501},
    /*   2 : ORB kreg8,kreg8 [r+vm:      vex.nds.l1.0f.ko8 45 /r          ] ND,ZU,AVX512DQ,FUTURE */
        /* 260(001 005) 001(45) 110 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_ORB, 2, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65461, 500},
    /*   3 : ORB kreg8,kreg8 [r+vm:      evex.nds.l1.0f.ko8 45 /r          ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 240(f1 7d 28) 300 001(45) 110 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_ORB, 2, {OPMASKREG|BITS8,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+30105, 501},
};

static const struct itemplate instrux_ORW[4] = {
    /*   0 : ORW kreg16,kreg16*,kreg16 [rvm:      vex.nds.l1.0f.ko16 45 /r         ] ND,ZU,AVX512F,FUTURE */
        /* 261(001 004) 001(45) 120 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_ORW, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65468, 502},
    /*   1 : ORW kreg16,kreg16*,kreg16 [rvm:      evex.nds.l1.0f.ko16 45 /r         ] ND,ZU,AVX512F,FUTURE,APX */
        /* 241(f1 7c 28) 300 001(45) 120 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_ORW, 3, {OPMASKREG|BITS16,OPMASKREG|BITS16,OPMASKREG|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+30114, 503},
    /*   2 : ORW kreg16,kreg16 [r+vm:      vex.nds.l1.0f.ko16 45 /r         ] ND,ZU,AVX512F,FUTURE */
        /* 260(001 004) 001(45) 110 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_ORW, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65475, 502},
    /*   3 : ORW kreg16,kreg16 [r+vm:      evex.nds.l1.0f.ko16 45 /r         ] ND,ZU,AVX512F,FUTURE,APX */
        /* 240(f1 7c 28) 300 001(45) 110 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_ORW, 2, {OPMASKREG|BITS16,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+30123, 503},
};

static const struct itemplate instrux_ORD[4] = {
    /*   0 : ORD kreg32,kreg32*,kreg32 [rvm:      vex.nds.l1.0f.ko32 45 /r         ] ND,ZU,AVX512BW,FUTURE */
        /* 261(001 205) 001(45) 120 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_ORD, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65482, 504},
    /*   1 : ORD kreg32,kreg32*,kreg32 [rvm:      evex.nds.l1.0f.ko32 45 /r         ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fd 28) 300 001(45) 120 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_ORD, 3, {OPMASKREG|BITS32,OPMASKREG|BITS32,OPMASKREG|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+30132, 505},
    /*   2 : ORD kreg32,kreg32 [r+vm:      vex.nds.l1.0f.ko32 45 /r         ] ND,ZU,AVX512BW,FUTURE */
        /* 260(001 205) 001(45) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_ORD, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65489, 504},
    /*   3 : ORD kreg32,kreg32 [r+vm:      evex.nds.l1.0f.ko32 45 /r         ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fd 28) 300 001(45) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_ORD, 2, {OPMASKREG|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+30141, 505},
};

static const struct itemplate instrux_ORQ[4] = {
    /*   0 : ORQ kreg64,kreg64*,kreg64 [rvm:      vex.nds.l1.0f.ko64 45 /r         ] ND,ZU,AVX512BW,FUTURE */
        /* 261(001 204) 001(45) 120 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_ORQ, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65496, 504},
    /*   1 : ORQ kreg64,kreg64*,kreg64 [rvm:      evex.nds.l1.0f.ko64 45 /r         ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fc 28) 300 001(45) 120 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_ORQ, 3, {OPMASKREG|BITS64,OPMASKREG|BITS64,OPMASKREG|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+30150, 505},
    /*   2 : ORQ kreg64,kreg64 [r+vm:      vex.nds.l1.0f.ko64 45 /r         ] ND,ZU,AVX512BW,FUTURE */
        /* 260(001 204) 001(45) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_ORQ, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65503, 504},
    /*   3 : ORQ kreg64,kreg64 [r+vm:      evex.nds.l1.0f.ko64 45 /r         ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fc 28) 300 001(45) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_ORQ, 2, {OPMASKREG|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+30159, 505},
};

static const struct itemplate instrux_KORTESTB[2] = {
    /*   0 : KORTESTB kreg8,kreg8 [rm:       vex.l0.0f.ko8 98 /r              ] ZU,FL,AVX512DQ,FUTURE */
        /* 270(001 001) 001(98) 110 : NOAPX,ZU,FL,VEX,AVX512DQ,FUTURE */
        {I_KORTESTB, 2, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65510, 538},
    /*   1 : KORTESTB kreg8,kreg8 [rm:       evex.l0.0f.ko8 98 /r              ] ZU,FL,AVX512DQ,FUTURE,APX */
        /* 250(f1 7d 08) 300 001(98) 110 : ZU,LONG,FL,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KORTESTB, 2, {OPMASKREG|BITS8,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+30168, 539},
};

static const struct itemplate instrux_KORTESTW[2] = {
    /*   0 : KORTESTW kreg16,kreg16 [rm:       vex.l0.0f.ko16 98 /r             ] ZU,FL,AVX512F,FUTURE */
        /* 270(001 000) 001(98) 110 : NOAPX,ZU,FL,VEX,AVX512F,FUTURE */
        {I_KORTESTW, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65517, 540},
    /*   1 : KORTESTW kreg16,kreg16 [rm:       evex.l0.0f.ko16 98 /r             ] ZU,FL,AVX512F,FUTURE,APX */
        /* 250(f1 7c 08) 300 001(98) 110 : ZU,LONG,FL,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KORTESTW, 2, {OPMASKREG|BITS16,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+30177, 541},
};

static const struct itemplate instrux_KORTESTD[2] = {
    /*   0 : KORTESTD kreg32,kreg32 [rm:       vex.l0.0f.ko32 98 /r             ] ZU,FL,AVX512BW,FUTURE */
        /* 270(001 201) 001(98) 110 : NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_KORTESTD, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65524, 542},
    /*   1 : KORTESTD kreg32,kreg32 [rm:       evex.l0.0f.ko32 98 /r             ] ZU,FL,AVX512BW,FUTURE,APX */
        /* 250(f1 fd 08) 300 001(98) 110 : ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KORTESTD, 2, {OPMASKREG|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+30186, 543},
};

static const struct itemplate instrux_KORTESTQ[2] = {
    /*   0 : KORTESTQ kreg64,kreg64 [rm:       vex.l0.0f.ko64 98 /r             ] ZU,FL,AVX512BW,FUTURE */
        /* 270(001 200) 001(98) 110 : NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_KORTESTQ, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65531, 542},
    /*   1 : KORTESTQ kreg64,kreg64 [rm:       evex.l0.0f.ko64 98 /r             ] ZU,FL,AVX512BW,FUTURE,APX */
        /* 250(f1 fc 08) 300 001(98) 110 : ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KORTESTQ, 2, {OPMASKREG|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+30195, 543},
};

static const struct itemplate instrux_KORTEST[8] = {
    /*   0 : KORTEST kreg8,kreg8 [rm:       vex.l0.0f.ko8 98 /r              ] ND,SM0-1,ZU,FL,AVX512DQ,FUTURE */
        /* 270(001 001) 001(98) 110 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512DQ,FUTURE */
        {I_KORTEST, 2, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65510, 518},
    /*   1 : KORTEST kreg8,kreg8 [rm:       evex.l0.0f.ko8 98 /r              ] ND,SM0-1,ZU,FL,AVX512DQ,FUTURE,APX */
        /* 250(f1 7d 08) 300 001(98) 110 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KORTEST, 2, {OPMASKREG|BITS8,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+30168, 519},
    /*   2 : KORTEST kreg16,kreg16 [rm:       vex.l0.0f.ko16 98 /r             ] ND,SM0-1,ZU,FL,AVX512F,FUTURE */
        /* 270(001 000) 001(98) 110 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512F,FUTURE */
        {I_KORTEST, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65517, 530},
    /*   3 : KORTEST kreg16,kreg16 [rm:       evex.l0.0f.ko16 98 /r             ] ND,SM0-1,ZU,FL,AVX512F,FUTURE,APX */
        /* 250(f1 7c 08) 300 001(98) 110 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KORTEST, 2, {OPMASKREG|BITS16,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+30177, 531},
    /*   4 : KORTEST kreg32,kreg32 [rm:       vex.l0.0f.ko32 98 /r             ] ND,SM0-1,ZU,FL,AVX512BW,FUTURE */
        /* 270(001 201) 001(98) 110 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_KORTEST, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65524, 522},
    /*   5 : KORTEST kreg32,kreg32 [rm:       evex.l0.0f.ko32 98 /r             ] ND,SM0-1,ZU,FL,AVX512BW,FUTURE,APX */
        /* 250(f1 fd 08) 300 001(98) 110 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KORTEST, 2, {OPMASKREG|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+30186, 523},
    /*   6 : KORTEST kreg64,kreg64 [rm:       vex.l0.0f.ko64 98 /r             ] ND,SM0-1,ZU,FL,AVX512BW,FUTURE */
        /* 270(001 200) 001(98) 110 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_KORTEST, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65531, 522},
    /*   7 : KORTEST kreg64,kreg64 [rm:       evex.l0.0f.ko64 98 /r             ] ND,SM0-1,ZU,FL,AVX512BW,FUTURE,APX */
        /* 250(f1 fc 08) 300 001(98) 110 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KORTEST, 2, {OPMASKREG|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+30195, 523},
};

static const struct itemplate instrux_ORTESTB[2] = {
    /*   0 : ORTESTB kreg8,kreg8 [rm:       vex.l0.0f.ko8 98 /r              ] ND,ZU,FL,AVX512DQ,FUTURE */
        /* 270(001 001) 001(98) 110 : NOAPX,ZU,FL,VEX,AVX512DQ,FUTURE */
        {I_ORTESTB, 2, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65510, 538},
    /*   1 : ORTESTB kreg8,kreg8 [rm:       evex.l0.0f.ko8 98 /r              ] ND,ZU,FL,AVX512DQ,FUTURE,APX */
        /* 250(f1 7d 08) 300 001(98) 110 : ZU,LONG,FL,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_ORTESTB, 2, {OPMASKREG|BITS8,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+30168, 539},
};

static const struct itemplate instrux_ORTESTW[2] = {
    /*   0 : ORTESTW kreg16,kreg16 [rm:       vex.l0.0f.ko16 98 /r             ] ND,ZU,FL,AVX512F,FUTURE */
        /* 270(001 000) 001(98) 110 : NOAPX,ZU,FL,VEX,AVX512F,FUTURE */
        {I_ORTESTW, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65517, 540},
    /*   1 : ORTESTW kreg16,kreg16 [rm:       evex.l0.0f.ko16 98 /r             ] ND,ZU,FL,AVX512F,FUTURE,APX */
        /* 250(f1 7c 08) 300 001(98) 110 : ZU,LONG,FL,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_ORTESTW, 2, {OPMASKREG|BITS16,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+30177, 541},
};

static const struct itemplate instrux_ORTESTD[2] = {
    /*   0 : ORTESTD kreg32,kreg32 [rm:       vex.l0.0f.ko32 98 /r             ] ND,ZU,FL,AVX512BW,FUTURE */
        /* 270(001 201) 001(98) 110 : NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_ORTESTD, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65524, 542},
    /*   1 : ORTESTD kreg32,kreg32 [rm:       evex.l0.0f.ko32 98 /r             ] ND,ZU,FL,AVX512BW,FUTURE,APX */
        /* 250(f1 fd 08) 300 001(98) 110 : ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_ORTESTD, 2, {OPMASKREG|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+30186, 543},
};

static const struct itemplate instrux_ORTESTQ[2] = {
    /*   0 : ORTESTQ kreg64,kreg64 [rm:       vex.l0.0f.ko64 98 /r             ] ND,ZU,FL,AVX512BW,FUTURE */
        /* 270(001 200) 001(98) 110 : NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_ORTESTQ, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65531, 542},
    /*   1 : ORTESTQ kreg64,kreg64 [rm:       evex.l0.0f.ko64 98 /r             ] ND,ZU,FL,AVX512BW,FUTURE,APX */
        /* 250(f1 fc 08) 300 001(98) 110 : ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_ORTESTQ, 2, {OPMASKREG|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+30195, 543},
};

static const struct itemplate instrux_ORTEST[8] = {
    /*   0 : ORTEST kreg8,kreg8 [rm:       vex.l0.0f.ko8 98 /r              ] ND,SM0-1,ZU,FL,AVX512DQ,FUTURE */
        /* 270(001 001) 001(98) 110 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512DQ,FUTURE */
        {I_ORTEST, 2, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65510, 518},
    /*   1 : ORTEST kreg8,kreg8 [rm:       evex.l0.0f.ko8 98 /r              ] ND,SM0-1,ZU,FL,AVX512DQ,FUTURE,APX */
        /* 250(f1 7d 08) 300 001(98) 110 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_ORTEST, 2, {OPMASKREG|BITS8,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+30168, 519},
    /*   2 : ORTEST kreg16,kreg16 [rm:       vex.l0.0f.ko16 98 /r             ] ND,SM0-1,ZU,FL,AVX512F,FUTURE */
        /* 270(001 000) 001(98) 110 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512F,FUTURE */
        {I_ORTEST, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65517, 530},
    /*   3 : ORTEST kreg16,kreg16 [rm:       evex.l0.0f.ko16 98 /r             ] ND,SM0-1,ZU,FL,AVX512F,FUTURE,APX */
        /* 250(f1 7c 08) 300 001(98) 110 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_ORTEST, 2, {OPMASKREG|BITS16,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+30177, 531},
    /*   4 : ORTEST kreg32,kreg32 [rm:       vex.l0.0f.ko32 98 /r             ] ND,SM0-1,ZU,FL,AVX512BW,FUTURE */
        /* 270(001 201) 001(98) 110 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_ORTEST, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65524, 522},
    /*   5 : ORTEST kreg32,kreg32 [rm:       evex.l0.0f.ko32 98 /r             ] ND,SM0-1,ZU,FL,AVX512BW,FUTURE,APX */
        /* 250(f1 fd 08) 300 001(98) 110 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_ORTEST, 2, {OPMASKREG|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+30186, 523},
    /*   6 : ORTEST kreg64,kreg64 [rm:       vex.l0.0f.ko64 98 /r             ] ND,SM0-1,ZU,FL,AVX512BW,FUTURE */
        /* 270(001 200) 001(98) 110 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_ORTEST, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65531, 522},
    /*   7 : ORTEST kreg64,kreg64 [rm:       evex.l0.0f.ko64 98 /r             ] ND,SM0-1,ZU,FL,AVX512BW,FUTURE,APX */
        /* 250(f1 fc 08) 300 001(98) 110 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_ORTEST, 2, {OPMASKREG|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+30195, 523},
};

static const struct itemplate instrux_KSHIFTLB[2] = {
    /*   0 : KSHIFTLB kreg8,kreg8,imm8 [rmi:      vex.l0.66.0f3a.w0 32 /r ib       ] ZU,AVX512DQ,FUTURE */
        /* 270(003 001) 001(32) 110 022 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KSHIFTLB, 3, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54573, 500},
    /*   1 : KSHIFTLB kreg8,kreg8,imm8 [rmi:      evex.l0.66.0f3a.w0 32 /r ib       ] ZU,AVX512DQ,FUTURE,APX */
        /* 250(f3 7d 08) 300 001(32) 110 022 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KSHIFTLB, 3, {OPMASKREG|BITS8,OPMASKREG|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18053, 501},
};

static const struct itemplate instrux_KSHIFTLW[2] = {
    /*   0 : KSHIFTLW kreg16,kreg16,imm8 [rmi:      vex.l0.66.0f3a.w1 32 /r ib       ] ZU,AVX512F,FUTURE */
        /* 270(003 201) 001(32) 110 022 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KSHIFTLW, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54581, 502},
    /*   1 : KSHIFTLW kreg16,kreg16,imm8 [rmi:      evex.l0.66.0f3a.w1 32 /r ib       ] ZU,AVX512F,FUTURE,APX */
        /* 250(f3 fd 08) 300 001(32) 110 022 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KSHIFTLW, 3, {OPMASKREG|BITS16,OPMASKREG|BITS16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18063, 503},
};

static const struct itemplate instrux_KSHIFTLD[2] = {
    /*   0 : KSHIFTLD kreg32,kreg32,imm8 [rmi:      vex.l0.66.0f3a.w0 33 /r ib       ] ZU,AVX512BW,FUTURE */
        /* 270(003 001) 001(33) 110 022 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KSHIFTLD, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54589, 504},
    /*   1 : KSHIFTLD kreg32,kreg32,imm8 [rmi:      evex.l0.66.0f3a.w0 33 /r ib       ] ZU,AVX512BW,FUTURE,APX */
        /* 250(f3 7d 08) 300 001(33) 110 022 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KSHIFTLD, 3, {OPMASKREG|BITS32,OPMASKREG|BITS32,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18073, 505},
};

static const struct itemplate instrux_KSHIFTLQ[2] = {
    /*   0 : KSHIFTLQ kreg64,kreg64,imm8 [rmi:      vex.l0.66.0f3a.w1 33 /r ib       ] ZU,AVX512BW,FUTURE */
        /* 270(003 201) 001(33) 110 022 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KSHIFTLQ, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54597, 504},
    /*   1 : KSHIFTLQ kreg64,kreg64,imm8 [rmi:      evex.l0.66.0f3a.w1 33 /r ib       ] ZU,AVX512BW,FUTURE,APX */
        /* 250(f3 fd 08) 300 001(33) 110 022 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KSHIFTLQ, 3, {OPMASKREG|BITS64,OPMASKREG|BITS64,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18083, 505},
};

static const struct itemplate instrux_KSHIFTL[8] = {
    /*   0 : KSHIFTL kreg8,kreg8,imm8 [rmi:      vex.l0.66.0f3a.w0 32 /r ib       ] ND,SM0-1,ZU,AVX512DQ,FUTURE */
        /* 270(003 001) 001(32) 110 022 : SM0,SM1,NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KSHIFTL, 3, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54573, 510},
    /*   1 : KSHIFTL kreg8,kreg8,imm8 [rmi:      evex.l0.66.0f3a.w0 32 /r ib       ] ND,SM0-1,ZU,AVX512DQ,FUTURE,APX */
        /* 250(f3 7d 08) 300 001(32) 110 022 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KSHIFTL, 3, {OPMASKREG|BITS8,OPMASKREG|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18053, 511},
    /*   2 : KSHIFTL kreg16,kreg16,imm8 [rmi:      vex.l0.66.0f3a.w1 32 /r ib       ] ND,SM0-1,ZU,AVX512F,FUTURE */
        /* 270(003 201) 001(32) 110 022 : SM0,SM1,NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KSHIFTL, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54581, 526},
    /*   3 : KSHIFTL kreg16,kreg16,imm8 [rmi:      evex.l0.66.0f3a.w1 32 /r ib       ] ND,SM0-1,ZU,AVX512F,FUTURE,APX */
        /* 250(f3 fd 08) 300 001(32) 110 022 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KSHIFTL, 3, {OPMASKREG|BITS16,OPMASKREG|BITS16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18063, 527},
    /*   4 : KSHIFTL kreg32,kreg32,imm8 [rmi:      vex.l0.66.0f3a.w0 33 /r ib       ] ND,SM0-1,ZU,AVX512BW,FUTURE */
        /* 270(003 001) 001(33) 110 022 : SM0,SM1,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KSHIFTL, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54589, 514},
    /*   5 : KSHIFTL kreg32,kreg32,imm8 [rmi:      evex.l0.66.0f3a.w0 33 /r ib       ] ND,SM0-1,ZU,AVX512BW,FUTURE,APX */
        /* 250(f3 7d 08) 300 001(33) 110 022 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KSHIFTL, 3, {OPMASKREG|BITS32,OPMASKREG|BITS32,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18073, 515},
    /*   6 : KSHIFTL kreg64,kreg64,imm8 [rmi:      vex.l0.66.0f3a.w1 33 /r ib       ] ND,SM0-1,ZU,AVX512BW,FUTURE */
        /* 270(003 201) 001(33) 110 022 : SM0,SM1,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KSHIFTL, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54597, 514},
    /*   7 : KSHIFTL kreg64,kreg64,imm8 [rmi:      evex.l0.66.0f3a.w1 33 /r ib       ] ND,SM0-1,ZU,AVX512BW,FUTURE,APX */
        /* 250(f3 fd 08) 300 001(33) 110 022 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KSHIFTL, 3, {OPMASKREG|BITS64,OPMASKREG|BITS64,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18083, 515},
};

static const struct itemplate instrux_SHIFTLB[2] = {
    /*   0 : SHIFTLB kreg8,kreg8,imm8 [rmi:      vex.l0.66.0f3a.w0 32 /r ib       ] ND,ZU,AVX512DQ,FUTURE */
        /* 270(003 001) 001(32) 110 022 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_SHIFTLB, 3, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54573, 500},
    /*   1 : SHIFTLB kreg8,kreg8,imm8 [rmi:      evex.l0.66.0f3a.w0 32 /r ib       ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 250(f3 7d 08) 300 001(32) 110 022 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_SHIFTLB, 3, {OPMASKREG|BITS8,OPMASKREG|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18053, 501},
};

static const struct itemplate instrux_SHIFTLW[2] = {
    /*   0 : SHIFTLW kreg16,kreg16,imm8 [rmi:      vex.l0.66.0f3a.w1 32 /r ib       ] ND,ZU,AVX512F,FUTURE */
        /* 270(003 201) 001(32) 110 022 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_SHIFTLW, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54581, 502},
    /*   1 : SHIFTLW kreg16,kreg16,imm8 [rmi:      evex.l0.66.0f3a.w1 32 /r ib       ] ND,ZU,AVX512F,FUTURE,APX */
        /* 250(f3 fd 08) 300 001(32) 110 022 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_SHIFTLW, 3, {OPMASKREG|BITS16,OPMASKREG|BITS16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18063, 503},
};

static const struct itemplate instrux_SHIFTLD[2] = {
    /*   0 : SHIFTLD kreg32,kreg32,imm8 [rmi:      vex.l0.66.0f3a.w0 33 /r ib       ] ND,ZU,AVX512BW,FUTURE */
        /* 270(003 001) 001(33) 110 022 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_SHIFTLD, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54589, 504},
    /*   1 : SHIFTLD kreg32,kreg32,imm8 [rmi:      evex.l0.66.0f3a.w0 33 /r ib       ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 250(f3 7d 08) 300 001(33) 110 022 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_SHIFTLD, 3, {OPMASKREG|BITS32,OPMASKREG|BITS32,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18073, 505},
};

static const struct itemplate instrux_SHIFTLQ[2] = {
    /*   0 : SHIFTLQ kreg64,kreg64,imm8 [rmi:      vex.l0.66.0f3a.w1 33 /r ib       ] ND,ZU,AVX512BW,FUTURE */
        /* 270(003 201) 001(33) 110 022 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_SHIFTLQ, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54597, 504},
    /*   1 : SHIFTLQ kreg64,kreg64,imm8 [rmi:      evex.l0.66.0f3a.w1 33 /r ib       ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 250(f3 fd 08) 300 001(33) 110 022 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_SHIFTLQ, 3, {OPMASKREG|BITS64,OPMASKREG|BITS64,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18083, 505},
};

static const struct itemplate instrux_SHIFTL[8] = {
    /*   0 : SHIFTL kreg8,kreg8,imm8 [rmi:      vex.l0.66.0f3a.w0 32 /r ib       ] ND,SM0-1,ZU,AVX512DQ,FUTURE */
        /* 270(003 001) 001(32) 110 022 : SM0,SM1,NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_SHIFTL, 3, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54573, 510},
    /*   1 : SHIFTL kreg8,kreg8,imm8 [rmi:      evex.l0.66.0f3a.w0 32 /r ib       ] ND,SM0-1,ZU,AVX512DQ,FUTURE,APX */
        /* 250(f3 7d 08) 300 001(32) 110 022 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_SHIFTL, 3, {OPMASKREG|BITS8,OPMASKREG|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18053, 511},
    /*   2 : SHIFTL kreg16,kreg16,imm8 [rmi:      vex.l0.66.0f3a.w1 32 /r ib       ] ND,SM0-1,ZU,AVX512F,FUTURE */
        /* 270(003 201) 001(32) 110 022 : SM0,SM1,NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_SHIFTL, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54581, 526},
    /*   3 : SHIFTL kreg16,kreg16,imm8 [rmi:      evex.l0.66.0f3a.w1 32 /r ib       ] ND,SM0-1,ZU,AVX512F,FUTURE,APX */
        /* 250(f3 fd 08) 300 001(32) 110 022 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_SHIFTL, 3, {OPMASKREG|BITS16,OPMASKREG|BITS16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18063, 527},
    /*   4 : SHIFTL kreg32,kreg32,imm8 [rmi:      vex.l0.66.0f3a.w0 33 /r ib       ] ND,SM0-1,ZU,AVX512BW,FUTURE */
        /* 270(003 001) 001(33) 110 022 : SM0,SM1,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_SHIFTL, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54589, 514},
    /*   5 : SHIFTL kreg32,kreg32,imm8 [rmi:      evex.l0.66.0f3a.w0 33 /r ib       ] ND,SM0-1,ZU,AVX512BW,FUTURE,APX */
        /* 250(f3 7d 08) 300 001(33) 110 022 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_SHIFTL, 3, {OPMASKREG|BITS32,OPMASKREG|BITS32,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18073, 515},
    /*   6 : SHIFTL kreg64,kreg64,imm8 [rmi:      vex.l0.66.0f3a.w1 33 /r ib       ] ND,SM0-1,ZU,AVX512BW,FUTURE */
        /* 270(003 201) 001(33) 110 022 : SM0,SM1,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_SHIFTL, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54597, 514},
    /*   7 : SHIFTL kreg64,kreg64,imm8 [rmi:      evex.l0.66.0f3a.w1 33 /r ib       ] ND,SM0-1,ZU,AVX512BW,FUTURE,APX */
        /* 250(f3 fd 08) 300 001(33) 110 022 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_SHIFTL, 3, {OPMASKREG|BITS64,OPMASKREG|BITS64,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18083, 515},
};

static const struct itemplate instrux_KSHLB[2] = {
    /*   0 : KSHLB kreg8,kreg8,imm8 [rmi:      vex.l0.66.0f3a.w0 32 /r ib       ] ND,ZU,AVX512DQ,FUTURE */
        /* 270(003 001) 001(32) 110 022 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KSHLB, 3, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54573, 500},
    /*   1 : KSHLB kreg8,kreg8,imm8 [rmi:      evex.l0.66.0f3a.w0 32 /r ib       ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 250(f3 7d 08) 300 001(32) 110 022 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KSHLB, 3, {OPMASKREG|BITS8,OPMASKREG|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18053, 501},
};

static const struct itemplate instrux_KSHLW[2] = {
    /*   0 : KSHLW kreg16,kreg16,imm8 [rmi:      vex.l0.66.0f3a.w1 32 /r ib       ] ND,ZU,AVX512F,FUTURE */
        /* 270(003 201) 001(32) 110 022 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KSHLW, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54581, 502},
    /*   1 : KSHLW kreg16,kreg16,imm8 [rmi:      evex.l0.66.0f3a.w1 32 /r ib       ] ND,ZU,AVX512F,FUTURE,APX */
        /* 250(f3 fd 08) 300 001(32) 110 022 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KSHLW, 3, {OPMASKREG|BITS16,OPMASKREG|BITS16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18063, 503},
};

static const struct itemplate instrux_KSHLD[2] = {
    /*   0 : KSHLD kreg32,kreg32,imm8 [rmi:      vex.l0.66.0f3a.w0 33 /r ib       ] ND,ZU,AVX512BW,FUTURE */
        /* 270(003 001) 001(33) 110 022 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KSHLD, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54589, 504},
    /*   1 : KSHLD kreg32,kreg32,imm8 [rmi:      evex.l0.66.0f3a.w0 33 /r ib       ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 250(f3 7d 08) 300 001(33) 110 022 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KSHLD, 3, {OPMASKREG|BITS32,OPMASKREG|BITS32,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18073, 505},
};

static const struct itemplate instrux_KSHLQ[2] = {
    /*   0 : KSHLQ kreg64,kreg64,imm8 [rmi:      vex.l0.66.0f3a.w1 33 /r ib       ] ND,ZU,AVX512BW,FUTURE */
        /* 270(003 201) 001(33) 110 022 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KSHLQ, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54597, 504},
    /*   1 : KSHLQ kreg64,kreg64,imm8 [rmi:      evex.l0.66.0f3a.w1 33 /r ib       ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 250(f3 fd 08) 300 001(33) 110 022 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KSHLQ, 3, {OPMASKREG|BITS64,OPMASKREG|BITS64,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18083, 505},
};

static const struct itemplate instrux_KSHL[8] = {
    /*   0 : KSHL kreg8,kreg8,imm8 [rmi:      vex.l0.66.0f3a.w0 32 /r ib       ] ND,SM0-1,ZU,AVX512DQ,FUTURE */
        /* 270(003 001) 001(32) 110 022 : SM0,SM1,NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KSHL, 3, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54573, 510},
    /*   1 : KSHL kreg8,kreg8,imm8 [rmi:      evex.l0.66.0f3a.w0 32 /r ib       ] ND,SM0-1,ZU,AVX512DQ,FUTURE,APX */
        /* 250(f3 7d 08) 300 001(32) 110 022 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KSHL, 3, {OPMASKREG|BITS8,OPMASKREG|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18053, 511},
    /*   2 : KSHL kreg16,kreg16,imm8 [rmi:      vex.l0.66.0f3a.w1 32 /r ib       ] ND,SM0-1,ZU,AVX512F,FUTURE */
        /* 270(003 201) 001(32) 110 022 : SM0,SM1,NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KSHL, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54581, 526},
    /*   3 : KSHL kreg16,kreg16,imm8 [rmi:      evex.l0.66.0f3a.w1 32 /r ib       ] ND,SM0-1,ZU,AVX512F,FUTURE,APX */
        /* 250(f3 fd 08) 300 001(32) 110 022 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KSHL, 3, {OPMASKREG|BITS16,OPMASKREG|BITS16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18063, 527},
    /*   4 : KSHL kreg32,kreg32,imm8 [rmi:      vex.l0.66.0f3a.w0 33 /r ib       ] ND,SM0-1,ZU,AVX512BW,FUTURE */
        /* 270(003 001) 001(33) 110 022 : SM0,SM1,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KSHL, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54589, 514},
    /*   5 : KSHL kreg32,kreg32,imm8 [rmi:      evex.l0.66.0f3a.w0 33 /r ib       ] ND,SM0-1,ZU,AVX512BW,FUTURE,APX */
        /* 250(f3 7d 08) 300 001(33) 110 022 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KSHL, 3, {OPMASKREG|BITS32,OPMASKREG|BITS32,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18073, 515},
    /*   6 : KSHL kreg64,kreg64,imm8 [rmi:      vex.l0.66.0f3a.w1 33 /r ib       ] ND,SM0-1,ZU,AVX512BW,FUTURE */
        /* 270(003 201) 001(33) 110 022 : SM0,SM1,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KSHL, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54597, 514},
    /*   7 : KSHL kreg64,kreg64,imm8 [rmi:      evex.l0.66.0f3a.w1 33 /r ib       ] ND,SM0-1,ZU,AVX512BW,FUTURE,APX */
        /* 250(f3 fd 08) 300 001(33) 110 022 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KSHL, 3, {OPMASKREG|BITS64,OPMASKREG|BITS64,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18083, 515},
};

static const struct itemplate instrux_SHLB[2] = {
    /*   0 : SHLB kreg8,kreg8,imm8 [rmi:      vex.l0.66.0f3a.w0 32 /r ib       ] ND,ZU,AVX512DQ,FUTURE */
        /* 270(003 001) 001(32) 110 022 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_SHLB, 3, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54573, 500},
    /*   1 : SHLB kreg8,kreg8,imm8 [rmi:      evex.l0.66.0f3a.w0 32 /r ib       ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 250(f3 7d 08) 300 001(32) 110 022 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_SHLB, 3, {OPMASKREG|BITS8,OPMASKREG|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18053, 501},
};

static const struct itemplate instrux_SHLW[2] = {
    /*   0 : SHLW kreg16,kreg16,imm8 [rmi:      vex.l0.66.0f3a.w1 32 /r ib       ] ND,ZU,AVX512F,FUTURE */
        /* 270(003 201) 001(32) 110 022 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_SHLW, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54581, 502},
    /*   1 : SHLW kreg16,kreg16,imm8 [rmi:      evex.l0.66.0f3a.w1 32 /r ib       ] ND,ZU,AVX512F,FUTURE,APX */
        /* 250(f3 fd 08) 300 001(32) 110 022 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_SHLW, 3, {OPMASKREG|BITS16,OPMASKREG|BITS16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18063, 503},
};

static const struct itemplate instrux_SHLQ[2] = {
    /*   0 : SHLQ kreg64,kreg64,imm8 [rmi:      vex.l0.66.0f3a.w1 33 /r ib       ] ND,ZU,AVX512BW,FUTURE */
        /* 270(003 201) 001(33) 110 022 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_SHLQ, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54597, 504},
    /*   1 : SHLQ kreg64,kreg64,imm8 [rmi:      evex.l0.66.0f3a.w1 33 /r ib       ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 250(f3 fd 08) 300 001(33) 110 022 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_SHLQ, 3, {OPMASKREG|BITS64,OPMASKREG|BITS64,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18083, 505},
};

static const struct itemplate instrux_KSHIFTRB[2] = {
    /*   0 : KSHIFTRB kreg8,kreg8,imm8 [rmi:      vex.l0.66.0f3a.w0 30 /r ib       ] ZU,AVX512DQ,FUTURE */
        /* 270(003 001) 001(30) 110 022 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KSHIFTRB, 3, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54605, 500},
    /*   1 : KSHIFTRB kreg8,kreg8,imm8 [rmi:      evex.l0.66.0f3a.w0 30 /r ib       ] ZU,AVX512DQ,FUTURE,APX */
        /* 250(f3 7d 08) 300 001(30) 110 022 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KSHIFTRB, 3, {OPMASKREG|BITS8,OPMASKREG|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18093, 501},
};

static const struct itemplate instrux_KSHIFTRW[2] = {
    /*   0 : KSHIFTRW kreg16,kreg16,imm8 [rmi:      vex.l0.66.0f3a.w1 30 /r ib       ] ZU,AVX512F,FUTURE */
        /* 270(003 201) 001(30) 110 022 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KSHIFTRW, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54613, 502},
    /*   1 : KSHIFTRW kreg16,kreg16,imm8 [rmi:      evex.l0.66.0f3a.w1 30 /r ib       ] ZU,AVX512F,FUTURE,APX */
        /* 250(f3 fd 08) 300 001(30) 110 022 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KSHIFTRW, 3, {OPMASKREG|BITS16,OPMASKREG|BITS16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18103, 503},
};

static const struct itemplate instrux_KSHIFTRD[2] = {
    /*   0 : KSHIFTRD kreg32,kreg32,imm8 [rmi:      vex.l0.66.0f3a.w0 31 /r ib       ] ZU,AVX512BW,FUTURE */
        /* 270(003 001) 001(31) 110 022 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KSHIFTRD, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54621, 504},
    /*   1 : KSHIFTRD kreg32,kreg32,imm8 [rmi:      evex.l0.66.0f3a.w0 31 /r ib       ] ZU,AVX512BW,FUTURE,APX */
        /* 250(f3 7d 08) 300 001(31) 110 022 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KSHIFTRD, 3, {OPMASKREG|BITS32,OPMASKREG|BITS32,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18113, 505},
};

static const struct itemplate instrux_KSHIFTRQ[2] = {
    /*   0 : KSHIFTRQ kreg64,kreg64,imm8 [rmi:      vex.l0.66.0f3a.w1 31 /r ib       ] ZU,AVX512BW,FUTURE */
        /* 270(003 201) 001(31) 110 022 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KSHIFTRQ, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54629, 504},
    /*   1 : KSHIFTRQ kreg64,kreg64,imm8 [rmi:      evex.l0.66.0f3a.w1 31 /r ib       ] ZU,AVX512BW,FUTURE,APX */
        /* 250(f3 fd 08) 300 001(31) 110 022 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KSHIFTRQ, 3, {OPMASKREG|BITS64,OPMASKREG|BITS64,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18123, 505},
};

static const struct itemplate instrux_KSHIFTR[8] = {
    /*   0 : KSHIFTR kreg8,kreg8,imm8 [rmi:      vex.l0.66.0f3a.w0 30 /r ib       ] ND,SM0-1,ZU,AVX512DQ,FUTURE */
        /* 270(003 001) 001(30) 110 022 : SM0,SM1,NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KSHIFTR, 3, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54605, 510},
    /*   1 : KSHIFTR kreg8,kreg8,imm8 [rmi:      evex.l0.66.0f3a.w0 30 /r ib       ] ND,SM0-1,ZU,AVX512DQ,FUTURE,APX */
        /* 250(f3 7d 08) 300 001(30) 110 022 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KSHIFTR, 3, {OPMASKREG|BITS8,OPMASKREG|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18093, 511},
    /*   2 : KSHIFTR kreg16,kreg16,imm8 [rmi:      vex.l0.66.0f3a.w1 30 /r ib       ] ND,SM0-1,ZU,AVX512F,FUTURE */
        /* 270(003 201) 001(30) 110 022 : SM0,SM1,NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KSHIFTR, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54613, 526},
    /*   3 : KSHIFTR kreg16,kreg16,imm8 [rmi:      evex.l0.66.0f3a.w1 30 /r ib       ] ND,SM0-1,ZU,AVX512F,FUTURE,APX */
        /* 250(f3 fd 08) 300 001(30) 110 022 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KSHIFTR, 3, {OPMASKREG|BITS16,OPMASKREG|BITS16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18103, 527},
    /*   4 : KSHIFTR kreg32,kreg32,imm8 [rmi:      vex.l0.66.0f3a.w0 31 /r ib       ] ND,SM0-1,ZU,AVX512BW,FUTURE */
        /* 270(003 001) 001(31) 110 022 : SM0,SM1,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KSHIFTR, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54621, 514},
    /*   5 : KSHIFTR kreg32,kreg32,imm8 [rmi:      evex.l0.66.0f3a.w0 31 /r ib       ] ND,SM0-1,ZU,AVX512BW,FUTURE,APX */
        /* 250(f3 7d 08) 300 001(31) 110 022 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KSHIFTR, 3, {OPMASKREG|BITS32,OPMASKREG|BITS32,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18113, 515},
    /*   6 : KSHIFTR kreg64,kreg64,imm8 [rmi:      vex.l0.66.0f3a.w1 31 /r ib       ] ND,SM0-1,ZU,AVX512BW,FUTURE */
        /* 270(003 201) 001(31) 110 022 : SM0,SM1,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KSHIFTR, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54629, 514},
    /*   7 : KSHIFTR kreg64,kreg64,imm8 [rmi:      evex.l0.66.0f3a.w1 31 /r ib       ] ND,SM0-1,ZU,AVX512BW,FUTURE,APX */
        /* 250(f3 fd 08) 300 001(31) 110 022 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KSHIFTR, 3, {OPMASKREG|BITS64,OPMASKREG|BITS64,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18123, 515},
};

static const struct itemplate instrux_SHIFTRB[2] = {
    /*   0 : SHIFTRB kreg8,kreg8,imm8 [rmi:      vex.l0.66.0f3a.w0 30 /r ib       ] ND,ZU,AVX512DQ,FUTURE */
        /* 270(003 001) 001(30) 110 022 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_SHIFTRB, 3, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54605, 500},
    /*   1 : SHIFTRB kreg8,kreg8,imm8 [rmi:      evex.l0.66.0f3a.w0 30 /r ib       ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 250(f3 7d 08) 300 001(30) 110 022 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_SHIFTRB, 3, {OPMASKREG|BITS8,OPMASKREG|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18093, 501},
};

static const struct itemplate instrux_SHIFTRW[2] = {
    /*   0 : SHIFTRW kreg16,kreg16,imm8 [rmi:      vex.l0.66.0f3a.w1 30 /r ib       ] ND,ZU,AVX512F,FUTURE */
        /* 270(003 201) 001(30) 110 022 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_SHIFTRW, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54613, 502},
    /*   1 : SHIFTRW kreg16,kreg16,imm8 [rmi:      evex.l0.66.0f3a.w1 30 /r ib       ] ND,ZU,AVX512F,FUTURE,APX */
        /* 250(f3 fd 08) 300 001(30) 110 022 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_SHIFTRW, 3, {OPMASKREG|BITS16,OPMASKREG|BITS16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18103, 503},
};

static const struct itemplate instrux_SHIFTRD[2] = {
    /*   0 : SHIFTRD kreg32,kreg32,imm8 [rmi:      vex.l0.66.0f3a.w0 31 /r ib       ] ND,ZU,AVX512BW,FUTURE */
        /* 270(003 001) 001(31) 110 022 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_SHIFTRD, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54621, 504},
    /*   1 : SHIFTRD kreg32,kreg32,imm8 [rmi:      evex.l0.66.0f3a.w0 31 /r ib       ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 250(f3 7d 08) 300 001(31) 110 022 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_SHIFTRD, 3, {OPMASKREG|BITS32,OPMASKREG|BITS32,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18113, 505},
};

static const struct itemplate instrux_SHIFTRQ[2] = {
    /*   0 : SHIFTRQ kreg64,kreg64,imm8 [rmi:      vex.l0.66.0f3a.w1 31 /r ib       ] ND,ZU,AVX512BW,FUTURE */
        /* 270(003 201) 001(31) 110 022 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_SHIFTRQ, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54629, 504},
    /*   1 : SHIFTRQ kreg64,kreg64,imm8 [rmi:      evex.l0.66.0f3a.w1 31 /r ib       ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 250(f3 fd 08) 300 001(31) 110 022 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_SHIFTRQ, 3, {OPMASKREG|BITS64,OPMASKREG|BITS64,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18123, 505},
};

static const struct itemplate instrux_SHIFTR[8] = {
    /*   0 : SHIFTR kreg8,kreg8,imm8 [rmi:      vex.l0.66.0f3a.w0 30 /r ib       ] ND,SM0-1,ZU,AVX512DQ,FUTURE */
        /* 270(003 001) 001(30) 110 022 : SM0,SM1,NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_SHIFTR, 3, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54605, 510},
    /*   1 : SHIFTR kreg8,kreg8,imm8 [rmi:      evex.l0.66.0f3a.w0 30 /r ib       ] ND,SM0-1,ZU,AVX512DQ,FUTURE,APX */
        /* 250(f3 7d 08) 300 001(30) 110 022 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_SHIFTR, 3, {OPMASKREG|BITS8,OPMASKREG|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18093, 511},
    /*   2 : SHIFTR kreg16,kreg16,imm8 [rmi:      vex.l0.66.0f3a.w1 30 /r ib       ] ND,SM0-1,ZU,AVX512F,FUTURE */
        /* 270(003 201) 001(30) 110 022 : SM0,SM1,NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_SHIFTR, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54613, 526},
    /*   3 : SHIFTR kreg16,kreg16,imm8 [rmi:      evex.l0.66.0f3a.w1 30 /r ib       ] ND,SM0-1,ZU,AVX512F,FUTURE,APX */
        /* 250(f3 fd 08) 300 001(30) 110 022 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_SHIFTR, 3, {OPMASKREG|BITS16,OPMASKREG|BITS16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18103, 527},
    /*   4 : SHIFTR kreg32,kreg32,imm8 [rmi:      vex.l0.66.0f3a.w0 31 /r ib       ] ND,SM0-1,ZU,AVX512BW,FUTURE */
        /* 270(003 001) 001(31) 110 022 : SM0,SM1,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_SHIFTR, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54621, 514},
    /*   5 : SHIFTR kreg32,kreg32,imm8 [rmi:      evex.l0.66.0f3a.w0 31 /r ib       ] ND,SM0-1,ZU,AVX512BW,FUTURE,APX */
        /* 250(f3 7d 08) 300 001(31) 110 022 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_SHIFTR, 3, {OPMASKREG|BITS32,OPMASKREG|BITS32,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18113, 515},
    /*   6 : SHIFTR kreg64,kreg64,imm8 [rmi:      vex.l0.66.0f3a.w1 31 /r ib       ] ND,SM0-1,ZU,AVX512BW,FUTURE */
        /* 270(003 201) 001(31) 110 022 : SM0,SM1,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_SHIFTR, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54629, 514},
    /*   7 : SHIFTR kreg64,kreg64,imm8 [rmi:      evex.l0.66.0f3a.w1 31 /r ib       ] ND,SM0-1,ZU,AVX512BW,FUTURE,APX */
        /* 250(f3 fd 08) 300 001(31) 110 022 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_SHIFTR, 3, {OPMASKREG|BITS64,OPMASKREG|BITS64,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18123, 515},
};

static const struct itemplate instrux_KSHRB[2] = {
    /*   0 : KSHRB kreg8,kreg8,imm8 [rmi:      vex.l0.66.0f3a.w0 30 /r ib       ] ND,ZU,AVX512DQ,FUTURE */
        /* 270(003 001) 001(30) 110 022 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KSHRB, 3, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54605, 500},
    /*   1 : KSHRB kreg8,kreg8,imm8 [rmi:      evex.l0.66.0f3a.w0 30 /r ib       ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 250(f3 7d 08) 300 001(30) 110 022 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KSHRB, 3, {OPMASKREG|BITS8,OPMASKREG|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18093, 501},
};

static const struct itemplate instrux_KSHRW[2] = {
    /*   0 : KSHRW kreg16,kreg16,imm8 [rmi:      vex.l0.66.0f3a.w1 30 /r ib       ] ND,ZU,AVX512F,FUTURE */
        /* 270(003 201) 001(30) 110 022 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KSHRW, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54613, 502},
    /*   1 : KSHRW kreg16,kreg16,imm8 [rmi:      evex.l0.66.0f3a.w1 30 /r ib       ] ND,ZU,AVX512F,FUTURE,APX */
        /* 250(f3 fd 08) 300 001(30) 110 022 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KSHRW, 3, {OPMASKREG|BITS16,OPMASKREG|BITS16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18103, 503},
};

static const struct itemplate instrux_KSHRD[2] = {
    /*   0 : KSHRD kreg32,kreg32,imm8 [rmi:      vex.l0.66.0f3a.w0 31 /r ib       ] ND,ZU,AVX512BW,FUTURE */
        /* 270(003 001) 001(31) 110 022 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KSHRD, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54621, 504},
    /*   1 : KSHRD kreg32,kreg32,imm8 [rmi:      evex.l0.66.0f3a.w0 31 /r ib       ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 250(f3 7d 08) 300 001(31) 110 022 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KSHRD, 3, {OPMASKREG|BITS32,OPMASKREG|BITS32,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18113, 505},
};

static const struct itemplate instrux_KSHRQ[2] = {
    /*   0 : KSHRQ kreg64,kreg64,imm8 [rmi:      vex.l0.66.0f3a.w1 31 /r ib       ] ND,ZU,AVX512BW,FUTURE */
        /* 270(003 201) 001(31) 110 022 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KSHRQ, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54629, 504},
    /*   1 : KSHRQ kreg64,kreg64,imm8 [rmi:      evex.l0.66.0f3a.w1 31 /r ib       ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 250(f3 fd 08) 300 001(31) 110 022 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KSHRQ, 3, {OPMASKREG|BITS64,OPMASKREG|BITS64,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18123, 505},
};

static const struct itemplate instrux_KSHR[8] = {
    /*   0 : KSHR kreg8,kreg8,imm8 [rmi:      vex.l0.66.0f3a.w0 30 /r ib       ] ND,SM0-1,ZU,AVX512DQ,FUTURE */
        /* 270(003 001) 001(30) 110 022 : SM0,SM1,NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KSHR, 3, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54605, 510},
    /*   1 : KSHR kreg8,kreg8,imm8 [rmi:      evex.l0.66.0f3a.w0 30 /r ib       ] ND,SM0-1,ZU,AVX512DQ,FUTURE,APX */
        /* 250(f3 7d 08) 300 001(30) 110 022 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KSHR, 3, {OPMASKREG|BITS8,OPMASKREG|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18093, 511},
    /*   2 : KSHR kreg16,kreg16,imm8 [rmi:      vex.l0.66.0f3a.w1 30 /r ib       ] ND,SM0-1,ZU,AVX512F,FUTURE */
        /* 270(003 201) 001(30) 110 022 : SM0,SM1,NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KSHR, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54613, 526},
    /*   3 : KSHR kreg16,kreg16,imm8 [rmi:      evex.l0.66.0f3a.w1 30 /r ib       ] ND,SM0-1,ZU,AVX512F,FUTURE,APX */
        /* 250(f3 fd 08) 300 001(30) 110 022 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KSHR, 3, {OPMASKREG|BITS16,OPMASKREG|BITS16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18103, 527},
    /*   4 : KSHR kreg32,kreg32,imm8 [rmi:      vex.l0.66.0f3a.w0 31 /r ib       ] ND,SM0-1,ZU,AVX512BW,FUTURE */
        /* 270(003 001) 001(31) 110 022 : SM0,SM1,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KSHR, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54621, 514},
    /*   5 : KSHR kreg32,kreg32,imm8 [rmi:      evex.l0.66.0f3a.w0 31 /r ib       ] ND,SM0-1,ZU,AVX512BW,FUTURE,APX */
        /* 250(f3 7d 08) 300 001(31) 110 022 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KSHR, 3, {OPMASKREG|BITS32,OPMASKREG|BITS32,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18113, 515},
    /*   6 : KSHR kreg64,kreg64,imm8 [rmi:      vex.l0.66.0f3a.w1 31 /r ib       ] ND,SM0-1,ZU,AVX512BW,FUTURE */
        /* 270(003 201) 001(31) 110 022 : SM0,SM1,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KSHR, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54629, 514},
    /*   7 : KSHR kreg64,kreg64,imm8 [rmi:      evex.l0.66.0f3a.w1 31 /r ib       ] ND,SM0-1,ZU,AVX512BW,FUTURE,APX */
        /* 250(f3 fd 08) 300 001(31) 110 022 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KSHR, 3, {OPMASKREG|BITS64,OPMASKREG|BITS64,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18123, 515},
};

static const struct itemplate instrux_SHRB[2] = {
    /*   0 : SHRB kreg8,kreg8,imm8 [rmi:      vex.l0.66.0f3a.w0 30 /r ib       ] ND,ZU,AVX512DQ,FUTURE */
        /* 270(003 001) 001(30) 110 022 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_SHRB, 3, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54605, 500},
    /*   1 : SHRB kreg8,kreg8,imm8 [rmi:      evex.l0.66.0f3a.w0 30 /r ib       ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 250(f3 7d 08) 300 001(30) 110 022 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_SHRB, 3, {OPMASKREG|BITS8,OPMASKREG|BITS8,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18093, 501},
};

static const struct itemplate instrux_SHRW[2] = {
    /*   0 : SHRW kreg16,kreg16,imm8 [rmi:      vex.l0.66.0f3a.w1 30 /r ib       ] ND,ZU,AVX512F,FUTURE */
        /* 270(003 201) 001(30) 110 022 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_SHRW, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54613, 502},
    /*   1 : SHRW kreg16,kreg16,imm8 [rmi:      evex.l0.66.0f3a.w1 30 /r ib       ] ND,ZU,AVX512F,FUTURE,APX */
        /* 250(f3 fd 08) 300 001(30) 110 022 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_SHRW, 3, {OPMASKREG|BITS16,OPMASKREG|BITS16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18103, 503},
};

static const struct itemplate instrux_SHRQ[2] = {
    /*   0 : SHRQ kreg64,kreg64,imm8 [rmi:      vex.l0.66.0f3a.w1 31 /r ib       ] ND,ZU,AVX512BW,FUTURE */
        /* 270(003 201) 001(31) 110 022 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_SHRQ, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54629, 504},
    /*   1 : SHRQ kreg64,kreg64,imm8 [rmi:      evex.l0.66.0f3a.w1 31 /r ib       ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 250(f3 fd 08) 300 001(31) 110 022 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_SHRQ, 3, {OPMASKREG|BITS64,OPMASKREG|BITS64,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+18123, 505},
};

static const struct itemplate instrux_KTESTB[2] = {
    /*   0 : KTESTB kreg8,kreg8 [rm:       vex.l0.0f.ko8 99 /r              ] ZU,FL,AVX512DQ,FUTURE */
        /* 270(001 001) 001(99) 110 : NOAPX,ZU,FL,VEX,AVX512DQ,FUTURE */
        {I_KTESTB, 2, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65538, 538},
    /*   1 : KTESTB kreg8,kreg8 [rm:       evex.l0.0f.ko8 99 /r              ] ZU,FL,AVX512DQ,FUTURE,APX */
        /* 250(f1 7d 08) 300 001(99) 110 : ZU,LONG,FL,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KTESTB, 2, {OPMASKREG|BITS8,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+30204, 539},
};

static const struct itemplate instrux_KTESTW[2] = {
    /*   0 : KTESTW kreg16,kreg16 [rm:       vex.l0.0f.ko16 99 /r             ] ZU,FL,AVX512DQ,FUTURE */
        /* 270(001 000) 001(99) 110 : NOAPX,ZU,FL,VEX,AVX512DQ,FUTURE */
        {I_KTESTW, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65545, 538},
    /*   1 : KTESTW kreg16,kreg16 [rm:       evex.l0.0f.ko16 99 /r             ] ZU,FL,AVX512DQ,FUTURE,APX */
        /* 250(f1 7c 08) 300 001(99) 110 : ZU,LONG,FL,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KTESTW, 2, {OPMASKREG|BITS16,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+30213, 539},
};

static const struct itemplate instrux_KTESTD[2] = {
    /*   0 : KTESTD kreg32,kreg32 [rm:       vex.l0.0f.ko32 99 /r             ] ZU,FL,AVX512BW,FUTURE */
        /* 270(001 201) 001(99) 110 : NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_KTESTD, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65552, 542},
    /*   1 : KTESTD kreg32,kreg32 [rm:       evex.l0.0f.ko32 99 /r             ] ZU,FL,AVX512BW,FUTURE,APX */
        /* 250(f1 fd 08) 300 001(99) 110 : ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KTESTD, 2, {OPMASKREG|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+30222, 543},
};

static const struct itemplate instrux_KTESTQ[2] = {
    /*   0 : KTESTQ kreg64,kreg64 [rm:       vex.l0.0f.ko64 99 /r             ] ZU,FL,AVX512BW,FUTURE */
        /* 270(001 200) 001(99) 110 : NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_KTESTQ, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65559, 542},
    /*   1 : KTESTQ kreg64,kreg64 [rm:       evex.l0.0f.ko64 99 /r             ] ZU,FL,AVX512BW,FUTURE,APX */
        /* 250(f1 fc 08) 300 001(99) 110 : ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KTESTQ, 2, {OPMASKREG|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+30231, 543},
};

static const struct itemplate instrux_KTEST[8] = {
    /*   0 : KTEST kreg8,kreg8 [rm:       vex.l0.0f.ko8 99 /r              ] ND,SM0-1,ZU,FL,AVX512DQ,FUTURE */
        /* 270(001 001) 001(99) 110 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512DQ,FUTURE */
        {I_KTEST, 2, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65538, 518},
    /*   1 : KTEST kreg8,kreg8 [rm:       evex.l0.0f.ko8 99 /r              ] ND,SM0-1,ZU,FL,AVX512DQ,FUTURE,APX */
        /* 250(f1 7d 08) 300 001(99) 110 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KTEST, 2, {OPMASKREG|BITS8,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+30204, 519},
    /*   2 : KTEST kreg16,kreg16 [rm:       vex.l0.0f.ko16 99 /r             ] ND,SM0-1,ZU,FL,AVX512DQ,FUTURE */
        /* 270(001 000) 001(99) 110 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512DQ,FUTURE */
        {I_KTEST, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65545, 518},
    /*   3 : KTEST kreg16,kreg16 [rm:       evex.l0.0f.ko16 99 /r             ] ND,SM0-1,ZU,FL,AVX512DQ,FUTURE,APX */
        /* 250(f1 7c 08) 300 001(99) 110 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KTEST, 2, {OPMASKREG|BITS16,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+30213, 519},
    /*   4 : KTEST kreg32,kreg32 [rm:       vex.l0.0f.ko32 99 /r             ] ND,SM0-1,ZU,FL,AVX512BW,FUTURE */
        /* 270(001 201) 001(99) 110 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_KTEST, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65552, 522},
    /*   5 : KTEST kreg32,kreg32 [rm:       evex.l0.0f.ko32 99 /r             ] ND,SM0-1,ZU,FL,AVX512BW,FUTURE,APX */
        /* 250(f1 fd 08) 300 001(99) 110 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KTEST, 2, {OPMASKREG|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+30222, 523},
    /*   6 : KTEST kreg64,kreg64 [rm:       vex.l0.0f.ko64 99 /r             ] ND,SM0-1,ZU,FL,AVX512BW,FUTURE */
        /* 270(001 200) 001(99) 110 : SM0,SM1,NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_KTEST, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65559, 522},
    /*   7 : KTEST kreg64,kreg64 [rm:       evex.l0.0f.ko64 99 /r             ] ND,SM0-1,ZU,FL,AVX512BW,FUTURE,APX */
        /* 250(f1 fc 08) 300 001(99) 110 : SM0,SM1,ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KTEST, 2, {OPMASKREG|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+30231, 523},
};

static const struct itemplate instrux_TESTB[2] = {
    /*   0 : TESTB kreg8,kreg8 [rm:       vex.l0.0f.ko8 99 /r              ] ND,ZU,FL,AVX512DQ,FUTURE */
        /* 270(001 001) 001(99) 110 : NOAPX,ZU,FL,VEX,AVX512DQ,FUTURE */
        {I_TESTB, 2, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65538, 538},
    /*   1 : TESTB kreg8,kreg8 [rm:       evex.l0.0f.ko8 99 /r              ] ND,ZU,FL,AVX512DQ,FUTURE,APX */
        /* 250(f1 7d 08) 300 001(99) 110 : ZU,LONG,FL,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_TESTB, 2, {OPMASKREG|BITS8,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+30204, 539},
};

static const struct itemplate instrux_TESTW[2] = {
    /*   0 : TESTW kreg16,kreg16 [rm:       vex.l0.0f.ko16 99 /r             ] ND,ZU,FL,AVX512DQ,FUTURE */
        /* 270(001 000) 001(99) 110 : NOAPX,ZU,FL,VEX,AVX512DQ,FUTURE */
        {I_TESTW, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65545, 538},
    /*   1 : TESTW kreg16,kreg16 [rm:       evex.l0.0f.ko16 99 /r             ] ND,ZU,FL,AVX512DQ,FUTURE,APX */
        /* 250(f1 7c 08) 300 001(99) 110 : ZU,LONG,FL,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_TESTW, 2, {OPMASKREG|BITS16,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+30213, 539},
};

static const struct itemplate instrux_TESTD[2] = {
    /*   0 : TESTD kreg32,kreg32 [rm:       vex.l0.0f.ko32 99 /r             ] ND,ZU,FL,AVX512BW,FUTURE */
        /* 270(001 201) 001(99) 110 : NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_TESTD, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65552, 542},
    /*   1 : TESTD kreg32,kreg32 [rm:       evex.l0.0f.ko32 99 /r             ] ND,ZU,FL,AVX512BW,FUTURE,APX */
        /* 250(f1 fd 08) 300 001(99) 110 : ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_TESTD, 2, {OPMASKREG|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+30222, 543},
};

static const struct itemplate instrux_TESTQ[2] = {
    /*   0 : TESTQ kreg64,kreg64 [rm:       vex.l0.0f.ko64 99 /r             ] ND,ZU,FL,AVX512BW,FUTURE */
        /* 270(001 200) 001(99) 110 : NOAPX,ZU,FL,VEX,AVX512BW,FUTURE */
        {I_TESTQ, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65559, 542},
    /*   1 : TESTQ kreg64,kreg64 [rm:       evex.l0.0f.ko64 99 /r             ] ND,ZU,FL,AVX512BW,FUTURE,APX */
        /* 250(f1 fc 08) 300 001(99) 110 : ZU,LONG,FL,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_TESTQ, 2, {OPMASKREG|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+30231, 543},
};

static const struct itemplate instrux_KUNPCKBW[4] = {
    /*   0 : KUNPCKBW kreg16,kreg8*,kreg8 [rvm:      vex.nds.l1.66.0f.w0 4b /r        ] ZU,AVX512F,FUTURE */
        /* 261(001 005) 001(4b) 120 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KUNPCKBW, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65566, 502},
    /*   1 : KUNPCKBW kreg16,kreg8*,kreg8 [rvm:      evex.nds.l1.66.0f.w0 4b /r        ] ZU,AVX512F,FUTURE,APX */
        /* 241(f1 7d 28) 300 001(4b) 120 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KUNPCKBW, 3, {OPMASKREG|BITS16,OPMASKREG|BITS8,OPMASKREG|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+30240, 503},
    /*   2 : KUNPCKBW kreg16,kreg8 [r+vm:      vex.nds.l1.66.0f.w0 4b /r        ] ND,ZU,AVX512F,FUTURE */
        /* 260(001 005) 001(4b) 110 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KUNPCKBW, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65573, 502},
    /*   3 : KUNPCKBW kreg16,kreg8 [r+vm:      evex.nds.l1.66.0f.w0 4b /r        ] ND,ZU,AVX512F,FUTURE,APX */
        /* 240(f1 7d 28) 300 001(4b) 110 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KUNPCKBW, 2, {OPMASKREG|BITS16,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+30249, 503},
};

static const struct itemplate instrux_KUNPCKW[4] = {
    /*   0 : KUNPCKW kreg16,kreg8*,kreg8 [rvm:      vex.nds.l1.66.0f.w0 4b /r        ] ND,ZU,AVX512F,FUTURE */
        /* 261(001 005) 001(4b) 120 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KUNPCKW, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65566, 502},
    /*   1 : KUNPCKW kreg16,kreg8*,kreg8 [rvm:      evex.nds.l1.66.0f.w0 4b /r        ] ND,ZU,AVX512F,FUTURE,APX */
        /* 241(f1 7d 28) 300 001(4b) 120 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KUNPCKW, 3, {OPMASKREG|BITS16,OPMASKREG|BITS8,OPMASKREG|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+30240, 503},
    /*   2 : KUNPCKW kreg16,kreg8 [r+vm:      vex.nds.l1.66.0f.w0 4b /r        ] ND,ZU,AVX512F,FUTURE */
        /* 260(001 005) 001(4b) 110 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KUNPCKW, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65573, 502},
    /*   3 : KUNPCKW kreg16,kreg8 [r+vm:      evex.nds.l1.66.0f.w0 4b /r        ] ND,ZU,AVX512F,FUTURE,APX */
        /* 240(f1 7d 28) 300 001(4b) 110 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KUNPCKW, 2, {OPMASKREG|BITS16,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+30249, 503},
};

static const struct itemplate instrux_KUNPCK[12] = {
    /*   0 : KUNPCK kreg16,kreg8*,kreg8 [rvm:      vex.nds.l1.66.0f.w0 4b /r        ] ND,ZU,AVX512F,FUTURE */
        /* 261(001 005) 001(4b) 120 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KUNPCK, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65566, 502},
    /*   1 : KUNPCK kreg16,kreg8*,kreg8 [rvm:      evex.nds.l1.66.0f.w0 4b /r        ] ND,ZU,AVX512F,FUTURE,APX */
        /* 241(f1 7d 28) 300 001(4b) 120 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KUNPCK, 3, {OPMASKREG|BITS16,OPMASKREG|BITS8,OPMASKREG|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+30240, 503},
    /*   2 : KUNPCK kreg16,kreg8 [r+vm:      vex.nds.l1.66.0f.w0 4b /r        ] ND,ZU,AVX512F,FUTURE */
        /* 260(001 005) 001(4b) 110 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KUNPCK, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65573, 502},
    /*   3 : KUNPCK kreg16,kreg8 [r+vm:      evex.nds.l1.66.0f.w0 4b /r        ] ND,ZU,AVX512F,FUTURE,APX */
        /* 240(f1 7d 28) 300 001(4b) 110 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KUNPCK, 2, {OPMASKREG|BITS16,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+30249, 503},
    /*   4 : KUNPCK kreg32,kreg16*,kreg16 [rvm:      vex.nds.l1.0f.w0 4b /r           ] ND,ZU,AVX512BW,FUTURE */
        /* 261(001 004) 001(4b) 120 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KUNPCK, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65580, 504},
    /*   5 : KUNPCK kreg32,kreg16*,kreg16 [rvm:      evex.nds.l1.0f.w0 4b /r           ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 7c 28) 300 001(4b) 120 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KUNPCK, 3, {OPMASKREG|BITS32,OPMASKREG|BITS16,OPMASKREG|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+30258, 505},
    /*   6 : KUNPCK kreg32,kreg16 [r+vm:      vex.nds.l1.0f.w0 4b /r           ] ND,ZU,AVX512BW,FUTURE */
        /* 260(001 004) 001(4b) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KUNPCK, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65587, 504},
    /*   7 : KUNPCK kreg32,kreg16 [r+vm:      evex.nds.l1.0f.w0 4b /r           ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 7c 28) 300 001(4b) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KUNPCK, 2, {OPMASKREG|BITS32,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+30267, 505},
    /*   8 : KUNPCK kreg64,kreg32*,kreg32 [rvm:      vex.nds.l1.0f.w1 4b /r           ] ND,ZU,AVX512BW,FUTURE */
        /* 261(001 204) 001(4b) 120 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KUNPCK, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65594, 504},
    /*   9 : KUNPCK kreg64,kreg32*,kreg32 [rvm:      evex.nds.l1.0f.w1 4b /r           ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fc 28) 300 001(4b) 120 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KUNPCK, 3, {OPMASKREG|BITS64,OPMASKREG|BITS32,OPMASKREG|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+30276, 505},
    /*  10 : KUNPCK kreg64,kreg32 [r+vm:      vex.nds.l1.0f.w1 4b /r           ] ND,ZU,AVX512BW,FUTURE */
        /* 260(001 204) 001(4b) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KUNPCK, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65601, 504},
    /*  11 : KUNPCK kreg64,kreg32 [r+vm:      evex.nds.l1.0f.w1 4b /r           ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fc 28) 300 001(4b) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KUNPCK, 2, {OPMASKREG|BITS64,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+30285, 505},
};

static const struct itemplate instrux_UNPCKBW[4] = {
    /*   0 : UNPCKBW kreg16,kreg8*,kreg8 [rvm:      vex.nds.l1.66.0f.w0 4b /r        ] ND,ZU,AVX512F,FUTURE */
        /* 261(001 005) 001(4b) 120 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_UNPCKBW, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65566, 502},
    /*   1 : UNPCKBW kreg16,kreg8*,kreg8 [rvm:      evex.nds.l1.66.0f.w0 4b /r        ] ND,ZU,AVX512F,FUTURE,APX */
        /* 241(f1 7d 28) 300 001(4b) 120 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_UNPCKBW, 3, {OPMASKREG|BITS16,OPMASKREG|BITS8,OPMASKREG|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+30240, 503},
    /*   2 : UNPCKBW kreg16,kreg8 [r+vm:      vex.nds.l1.66.0f.w0 4b /r        ] ND,ZU,AVX512F,FUTURE */
        /* 260(001 005) 001(4b) 110 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_UNPCKBW, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65573, 502},
    /*   3 : UNPCKBW kreg16,kreg8 [r+vm:      evex.nds.l1.66.0f.w0 4b /r        ] ND,ZU,AVX512F,FUTURE,APX */
        /* 240(f1 7d 28) 300 001(4b) 110 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_UNPCKBW, 2, {OPMASKREG|BITS16,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+30249, 503},
};

static const struct itemplate instrux_UNPCKW[4] = {
    /*   0 : UNPCKW kreg16,kreg8*,kreg8 [rvm:      vex.nds.l1.66.0f.w0 4b /r        ] ND,ZU,AVX512F,FUTURE */
        /* 261(001 005) 001(4b) 120 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_UNPCKW, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65566, 502},
    /*   1 : UNPCKW kreg16,kreg8*,kreg8 [rvm:      evex.nds.l1.66.0f.w0 4b /r        ] ND,ZU,AVX512F,FUTURE,APX */
        /* 241(f1 7d 28) 300 001(4b) 120 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_UNPCKW, 3, {OPMASKREG|BITS16,OPMASKREG|BITS8,OPMASKREG|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+30240, 503},
    /*   2 : UNPCKW kreg16,kreg8 [r+vm:      vex.nds.l1.66.0f.w0 4b /r        ] ND,ZU,AVX512F,FUTURE */
        /* 260(001 005) 001(4b) 110 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_UNPCKW, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65573, 502},
    /*   3 : UNPCKW kreg16,kreg8 [r+vm:      evex.nds.l1.66.0f.w0 4b /r        ] ND,ZU,AVX512F,FUTURE,APX */
        /* 240(f1 7d 28) 300 001(4b) 110 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_UNPCKW, 2, {OPMASKREG|BITS16,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+30249, 503},
};

static const struct itemplate instrux_UNPCK[12] = {
    /*   0 : UNPCK kreg16,kreg8*,kreg8 [rvm:      vex.nds.l1.66.0f.w0 4b /r        ] ND,ZU,AVX512F,FUTURE */
        /* 261(001 005) 001(4b) 120 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_UNPCK, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65566, 502},
    /*   1 : UNPCK kreg16,kreg8*,kreg8 [rvm:      evex.nds.l1.66.0f.w0 4b /r        ] ND,ZU,AVX512F,FUTURE,APX */
        /* 241(f1 7d 28) 300 001(4b) 120 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_UNPCK, 3, {OPMASKREG|BITS16,OPMASKREG|BITS8,OPMASKREG|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+30240, 503},
    /*   2 : UNPCK kreg16,kreg8 [r+vm:      vex.nds.l1.66.0f.w0 4b /r        ] ND,ZU,AVX512F,FUTURE */
        /* 260(001 005) 001(4b) 110 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_UNPCK, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65573, 502},
    /*   3 : UNPCK kreg16,kreg8 [r+vm:      evex.nds.l1.66.0f.w0 4b /r        ] ND,ZU,AVX512F,FUTURE,APX */
        /* 240(f1 7d 28) 300 001(4b) 110 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_UNPCK, 2, {OPMASKREG|BITS16,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+30249, 503},
    /*   4 : UNPCK kreg32,kreg16*,kreg16 [rvm:      vex.nds.l1.0f.w0 4b /r           ] ND,ZU,AVX512BW,FUTURE */
        /* 261(001 004) 001(4b) 120 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_UNPCK, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65580, 504},
    /*   5 : UNPCK kreg32,kreg16*,kreg16 [rvm:      evex.nds.l1.0f.w0 4b /r           ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 7c 28) 300 001(4b) 120 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_UNPCK, 3, {OPMASKREG|BITS32,OPMASKREG|BITS16,OPMASKREG|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+30258, 505},
    /*   6 : UNPCK kreg32,kreg16 [r+vm:      vex.nds.l1.0f.w0 4b /r           ] ND,ZU,AVX512BW,FUTURE */
        /* 260(001 004) 001(4b) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_UNPCK, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65587, 504},
    /*   7 : UNPCK kreg32,kreg16 [r+vm:      evex.nds.l1.0f.w0 4b /r           ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 7c 28) 300 001(4b) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_UNPCK, 2, {OPMASKREG|BITS32,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+30267, 505},
    /*   8 : UNPCK kreg64,kreg32*,kreg32 [rvm:      vex.nds.l1.0f.w1 4b /r           ] ND,ZU,AVX512BW,FUTURE */
        /* 261(001 204) 001(4b) 120 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_UNPCK, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65594, 504},
    /*   9 : UNPCK kreg64,kreg32*,kreg32 [rvm:      evex.nds.l1.0f.w1 4b /r           ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fc 28) 300 001(4b) 120 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_UNPCK, 3, {OPMASKREG|BITS64,OPMASKREG|BITS32,OPMASKREG|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+30276, 505},
    /*  10 : UNPCK kreg64,kreg32 [r+vm:      vex.nds.l1.0f.w1 4b /r           ] ND,ZU,AVX512BW,FUTURE */
        /* 260(001 204) 001(4b) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_UNPCK, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65601, 504},
    /*  11 : UNPCK kreg64,kreg32 [r+vm:      evex.nds.l1.0f.w1 4b /r           ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fc 28) 300 001(4b) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_UNPCK, 2, {OPMASKREG|BITS64,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+30285, 505},
};

static const struct itemplate instrux_KUNPCKWD[4] = {
    /*   0 : KUNPCKWD kreg32,kreg16*,kreg16 [rvm:      vex.nds.l1.0f.w0 4b /r           ] ZU,AVX512BW,FUTURE */
        /* 261(001 004) 001(4b) 120 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KUNPCKWD, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65580, 504},
    /*   1 : KUNPCKWD kreg32,kreg16*,kreg16 [rvm:      evex.nds.l1.0f.w0 4b /r           ] ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 7c 28) 300 001(4b) 120 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KUNPCKWD, 3, {OPMASKREG|BITS32,OPMASKREG|BITS16,OPMASKREG|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+30258, 505},
    /*   2 : KUNPCKWD kreg32,kreg16 [r+vm:      vex.nds.l1.0f.w0 4b /r           ] ND,ZU,AVX512BW,FUTURE */
        /* 260(001 004) 001(4b) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KUNPCKWD, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65587, 504},
    /*   3 : KUNPCKWD kreg32,kreg16 [r+vm:      evex.nds.l1.0f.w0 4b /r           ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 7c 28) 300 001(4b) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KUNPCKWD, 2, {OPMASKREG|BITS32,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+30267, 505},
};

static const struct itemplate instrux_KUNPCKD[4] = {
    /*   0 : KUNPCKD kreg32,kreg16*,kreg16 [rvm:      vex.nds.l1.0f.w0 4b /r           ] ND,ZU,AVX512BW,FUTURE */
        /* 261(001 004) 001(4b) 120 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KUNPCKD, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65580, 504},
    /*   1 : KUNPCKD kreg32,kreg16*,kreg16 [rvm:      evex.nds.l1.0f.w0 4b /r           ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 7c 28) 300 001(4b) 120 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KUNPCKD, 3, {OPMASKREG|BITS32,OPMASKREG|BITS16,OPMASKREG|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+30258, 505},
    /*   2 : KUNPCKD kreg32,kreg16 [r+vm:      vex.nds.l1.0f.w0 4b /r           ] ND,ZU,AVX512BW,FUTURE */
        /* 260(001 004) 001(4b) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KUNPCKD, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65587, 504},
    /*   3 : KUNPCKD kreg32,kreg16 [r+vm:      evex.nds.l1.0f.w0 4b /r           ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 7c 28) 300 001(4b) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KUNPCKD, 2, {OPMASKREG|BITS32,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+30267, 505},
};

static const struct itemplate instrux_UNPCKWD[4] = {
    /*   0 : UNPCKWD kreg32,kreg16*,kreg16 [rvm:      vex.nds.l1.0f.w0 4b /r           ] ND,ZU,AVX512BW,FUTURE */
        /* 261(001 004) 001(4b) 120 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_UNPCKWD, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65580, 504},
    /*   1 : UNPCKWD kreg32,kreg16*,kreg16 [rvm:      evex.nds.l1.0f.w0 4b /r           ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 7c 28) 300 001(4b) 120 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_UNPCKWD, 3, {OPMASKREG|BITS32,OPMASKREG|BITS16,OPMASKREG|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+30258, 505},
    /*   2 : UNPCKWD kreg32,kreg16 [r+vm:      vex.nds.l1.0f.w0 4b /r           ] ND,ZU,AVX512BW,FUTURE */
        /* 260(001 004) 001(4b) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_UNPCKWD, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65587, 504},
    /*   3 : UNPCKWD kreg32,kreg16 [r+vm:      evex.nds.l1.0f.w0 4b /r           ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 7c 28) 300 001(4b) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_UNPCKWD, 2, {OPMASKREG|BITS32,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+30267, 505},
};

static const struct itemplate instrux_UNPCKD[4] = {
    /*   0 : UNPCKD kreg32,kreg16*,kreg16 [rvm:      vex.nds.l1.0f.w0 4b /r           ] ND,ZU,AVX512BW,FUTURE */
        /* 261(001 004) 001(4b) 120 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_UNPCKD, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65580, 504},
    /*   1 : UNPCKD kreg32,kreg16*,kreg16 [rvm:      evex.nds.l1.0f.w0 4b /r           ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 7c 28) 300 001(4b) 120 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_UNPCKD, 3, {OPMASKREG|BITS32,OPMASKREG|BITS16,OPMASKREG|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+30258, 505},
    /*   2 : UNPCKD kreg32,kreg16 [r+vm:      vex.nds.l1.0f.w0 4b /r           ] ND,ZU,AVX512BW,FUTURE */
        /* 260(001 004) 001(4b) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_UNPCKD, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65587, 504},
    /*   3 : UNPCKD kreg32,kreg16 [r+vm:      evex.nds.l1.0f.w0 4b /r           ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 7c 28) 300 001(4b) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_UNPCKD, 2, {OPMASKREG|BITS32,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+30267, 505},
};

static const struct itemplate instrux_KUNPCKDQ[4] = {
    /*   0 : KUNPCKDQ kreg64,kreg32*,kreg32 [rvm:      vex.nds.l1.0f.w1 4b /r           ] ZU,AVX512BW,FUTURE */
        /* 261(001 204) 001(4b) 120 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KUNPCKDQ, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65594, 504},
    /*   1 : KUNPCKDQ kreg64,kreg32*,kreg32 [rvm:      evex.nds.l1.0f.w1 4b /r           ] ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fc 28) 300 001(4b) 120 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KUNPCKDQ, 3, {OPMASKREG|BITS64,OPMASKREG|BITS32,OPMASKREG|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+30276, 505},
    /*   2 : KUNPCKDQ kreg64,kreg32 [r+vm:      vex.nds.l1.0f.w1 4b /r           ] ND,ZU,AVX512BW,FUTURE */
        /* 260(001 204) 001(4b) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KUNPCKDQ, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65601, 504},
    /*   3 : KUNPCKDQ kreg64,kreg32 [r+vm:      evex.nds.l1.0f.w1 4b /r           ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fc 28) 300 001(4b) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KUNPCKDQ, 2, {OPMASKREG|BITS64,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+30285, 505},
};

static const struct itemplate instrux_KUNPCKQ[4] = {
    /*   0 : KUNPCKQ kreg64,kreg32*,kreg32 [rvm:      vex.nds.l1.0f.w1 4b /r           ] ND,ZU,AVX512BW,FUTURE */
        /* 261(001 204) 001(4b) 120 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KUNPCKQ, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65594, 504},
    /*   1 : KUNPCKQ kreg64,kreg32*,kreg32 [rvm:      evex.nds.l1.0f.w1 4b /r           ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fc 28) 300 001(4b) 120 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KUNPCKQ, 3, {OPMASKREG|BITS64,OPMASKREG|BITS32,OPMASKREG|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+30276, 505},
    /*   2 : KUNPCKQ kreg64,kreg32 [r+vm:      vex.nds.l1.0f.w1 4b /r           ] ND,ZU,AVX512BW,FUTURE */
        /* 260(001 204) 001(4b) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KUNPCKQ, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65601, 504},
    /*   3 : KUNPCKQ kreg64,kreg32 [r+vm:      evex.nds.l1.0f.w1 4b /r           ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fc 28) 300 001(4b) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KUNPCKQ, 2, {OPMASKREG|BITS64,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+30285, 505},
};

static const struct itemplate instrux_UNPCKDQ[4] = {
    /*   0 : UNPCKDQ kreg64,kreg32*,kreg32 [rvm:      vex.nds.l1.0f.w1 4b /r           ] ND,ZU,AVX512BW,FUTURE */
        /* 261(001 204) 001(4b) 120 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_UNPCKDQ, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65594, 504},
    /*   1 : UNPCKDQ kreg64,kreg32*,kreg32 [rvm:      evex.nds.l1.0f.w1 4b /r           ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fc 28) 300 001(4b) 120 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_UNPCKDQ, 3, {OPMASKREG|BITS64,OPMASKREG|BITS32,OPMASKREG|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+30276, 505},
    /*   2 : UNPCKDQ kreg64,kreg32 [r+vm:      vex.nds.l1.0f.w1 4b /r           ] ND,ZU,AVX512BW,FUTURE */
        /* 260(001 204) 001(4b) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_UNPCKDQ, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65601, 504},
    /*   3 : UNPCKDQ kreg64,kreg32 [r+vm:      evex.nds.l1.0f.w1 4b /r           ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fc 28) 300 001(4b) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_UNPCKDQ, 2, {OPMASKREG|BITS64,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+30285, 505},
};

static const struct itemplate instrux_UNPCKQ[4] = {
    /*   0 : UNPCKQ kreg64,kreg32*,kreg32 [rvm:      vex.nds.l1.0f.w1 4b /r           ] ND,ZU,AVX512BW,FUTURE */
        /* 261(001 204) 001(4b) 120 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_UNPCKQ, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65594, 504},
    /*   1 : UNPCKQ kreg64,kreg32*,kreg32 [rvm:      evex.nds.l1.0f.w1 4b /r           ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fc 28) 300 001(4b) 120 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_UNPCKQ, 3, {OPMASKREG|BITS64,OPMASKREG|BITS32,OPMASKREG|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+30276, 505},
    /*   2 : UNPCKQ kreg64,kreg32 [r+vm:      vex.nds.l1.0f.w1 4b /r           ] ND,ZU,AVX512BW,FUTURE */
        /* 260(001 204) 001(4b) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_UNPCKQ, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65601, 504},
    /*   3 : UNPCKQ kreg64,kreg32 [r+vm:      evex.nds.l1.0f.w1 4b /r           ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fc 28) 300 001(4b) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_UNPCKQ, 2, {OPMASKREG|BITS64,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+30285, 505},
};

static const struct itemplate instrux_KXNORB[4] = {
    /*   0 : KXNORB kreg8,kreg8*,kreg8 [rvm:      vex.nds.l1.0f.ko8 46 /r          ] ZU,AVX512DQ,FUTURE */
        /* 261(001 005) 001(46) 120 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KXNORB, 3, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65608, 500},
    /*   1 : KXNORB kreg8,kreg8*,kreg8 [rvm:      evex.nds.l1.0f.ko8 46 /r          ] ZU,AVX512DQ,FUTURE,APX */
        /* 241(f1 7d 28) 300 001(46) 120 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KXNORB, 3, {OPMASKREG|BITS8,OPMASKREG|BITS8,OPMASKREG|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+30294, 501},
    /*   2 : KXNORB kreg8,kreg8 [r+vm:      vex.nds.l1.0f.ko8 46 /r          ] ND,ZU,AVX512DQ,FUTURE */
        /* 260(001 005) 001(46) 110 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KXNORB, 2, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65615, 500},
    /*   3 : KXNORB kreg8,kreg8 [r+vm:      evex.nds.l1.0f.ko8 46 /r          ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 240(f1 7d 28) 300 001(46) 110 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KXNORB, 2, {OPMASKREG|BITS8,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+30303, 501},
};

static const struct itemplate instrux_KXNORW[4] = {
    /*   0 : KXNORW kreg16,kreg16*,kreg16 [rvm:      vex.nds.l1.0f.ko16 46 /r         ] ZU,AVX512F,FUTURE */
        /* 261(001 004) 001(46) 120 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KXNORW, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65622, 502},
    /*   1 : KXNORW kreg16,kreg16*,kreg16 [rvm:      evex.nds.l1.0f.ko16 46 /r         ] ZU,AVX512F,FUTURE,APX */
        /* 241(f1 7c 28) 300 001(46) 120 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KXNORW, 3, {OPMASKREG|BITS16,OPMASKREG|BITS16,OPMASKREG|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+30312, 503},
    /*   2 : KXNORW kreg16,kreg16 [r+vm:      vex.nds.l1.0f.ko16 46 /r         ] ND,ZU,AVX512F,FUTURE */
        /* 260(001 004) 001(46) 110 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KXNORW, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65629, 502},
    /*   3 : KXNORW kreg16,kreg16 [r+vm:      evex.nds.l1.0f.ko16 46 /r         ] ND,ZU,AVX512F,FUTURE,APX */
        /* 240(f1 7c 28) 300 001(46) 110 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KXNORW, 2, {OPMASKREG|BITS16,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+30321, 503},
};

static const struct itemplate instrux_KXNORD[4] = {
    /*   0 : KXNORD kreg32,kreg32*,kreg32 [rvm:      vex.nds.l1.0f.ko32 46 /r         ] ZU,AVX512BW,FUTURE */
        /* 261(001 205) 001(46) 120 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KXNORD, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65636, 504},
    /*   1 : KXNORD kreg32,kreg32*,kreg32 [rvm:      evex.nds.l1.0f.ko32 46 /r         ] ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fd 28) 300 001(46) 120 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KXNORD, 3, {OPMASKREG|BITS32,OPMASKREG|BITS32,OPMASKREG|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+30330, 505},
    /*   2 : KXNORD kreg32,kreg32 [r+vm:      vex.nds.l1.0f.ko32 46 /r         ] ND,ZU,AVX512BW,FUTURE */
        /* 260(001 205) 001(46) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KXNORD, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65643, 504},
    /*   3 : KXNORD kreg32,kreg32 [r+vm:      evex.nds.l1.0f.ko32 46 /r         ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fd 28) 300 001(46) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KXNORD, 2, {OPMASKREG|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+30339, 505},
};

static const struct itemplate instrux_KXNORQ[4] = {
    /*   0 : KXNORQ kreg64,kreg64*,kreg64 [rvm:      vex.nds.l1.0f.ko64 46 /r         ] ZU,AVX512BW,FUTURE */
        /* 261(001 204) 001(46) 120 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KXNORQ, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65650, 504},
    /*   1 : KXNORQ kreg64,kreg64*,kreg64 [rvm:      evex.nds.l1.0f.ko64 46 /r         ] ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fc 28) 300 001(46) 120 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KXNORQ, 3, {OPMASKREG|BITS64,OPMASKREG|BITS64,OPMASKREG|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+30348, 505},
    /*   2 : KXNORQ kreg64,kreg64 [r+vm:      vex.nds.l1.0f.ko64 46 /r         ] ND,ZU,AVX512BW,FUTURE */
        /* 260(001 204) 001(46) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KXNORQ, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65657, 504},
    /*   3 : KXNORQ kreg64,kreg64 [r+vm:      evex.nds.l1.0f.ko64 46 /r         ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fc 28) 300 001(46) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KXNORQ, 2, {OPMASKREG|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+30357, 505},
};

static const struct itemplate instrux_KXNOR[16] = {
    /*   0 : KXNOR kreg8,kreg8*,kreg8 [rvm:      vex.nds.l1.0f.ko8 46 /r          ] ND,SM0,SM1,SM2,ZU,AVX512DQ,FUTURE */
        /* 261(001 005) 001(46) 120 : SM0,SM1,SM2,NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KXNOR, 3, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65608, 508},
    /*   1 : KXNOR kreg8,kreg8*,kreg8 [rvm:      evex.nds.l1.0f.ko8 46 /r          ] ND,SM0,SM1,SM2,ZU,AVX512DQ,FUTURE,APX */
        /* 241(f1 7d 28) 300 001(46) 120 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KXNOR, 3, {OPMASKREG|BITS8,OPMASKREG|BITS8,OPMASKREG|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+30294, 509},
    /*   2 : KXNOR kreg8,kreg8 [r+vm:      vex.nds.l1.0f.ko8 46 /r          ] ND,SM0,SM1,ZU,AVX512DQ,FUTURE */
        /* 260(001 005) 001(46) 110 : SM0,SM1,NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KXNOR, 2, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65615, 510},
    /*   3 : KXNOR kreg8,kreg8 [r+vm:      evex.nds.l1.0f.ko8 46 /r          ] ND,SM0,SM1,ZU,AVX512DQ,FUTURE,APX */
        /* 240(f1 7d 28) 300 001(46) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KXNOR, 2, {OPMASKREG|BITS8,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+30303, 511},
    /*   4 : KXNOR kreg16,kreg16*,kreg16 [rvm:      vex.nds.l1.0f.ko16 46 /r         ] ND,SM0,SM1,SM2,ZU,AVX512F,FUTURE */
        /* 261(001 004) 001(46) 120 : SM0,SM1,SM2,NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KXNOR, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65622, 524},
    /*   5 : KXNOR kreg16,kreg16*,kreg16 [rvm:      evex.nds.l1.0f.ko16 46 /r         ] ND,SM0,SM1,SM2,ZU,AVX512F,FUTURE,APX */
        /* 241(f1 7c 28) 300 001(46) 120 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KXNOR, 3, {OPMASKREG|BITS16,OPMASKREG|BITS16,OPMASKREG|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+30312, 525},
    /*   6 : KXNOR kreg16,kreg16 [r+vm:      vex.nds.l1.0f.ko16 46 /r         ] ND,SM0,SM1,ZU,AVX512F,FUTURE */
        /* 260(001 004) 001(46) 110 : SM0,SM1,NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KXNOR, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65629, 526},
    /*   7 : KXNOR kreg16,kreg16 [r+vm:      evex.nds.l1.0f.ko16 46 /r         ] ND,SM0,SM1,ZU,AVX512F,FUTURE,APX */
        /* 240(f1 7c 28) 300 001(46) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KXNOR, 2, {OPMASKREG|BITS16,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+30321, 527},
    /*   8 : KXNOR kreg32,kreg32*,kreg32 [rvm:      vex.nds.l1.0f.ko32 46 /r         ] ND,SM0,SM1,SM2,ZU,AVX512BW,FUTURE */
        /* 261(001 205) 001(46) 120 : SM0,SM1,SM2,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KXNOR, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65636, 512},
    /*   9 : KXNOR kreg32,kreg32*,kreg32 [rvm:      evex.nds.l1.0f.ko32 46 /r         ] ND,SM0,SM1,SM2,ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fd 28) 300 001(46) 120 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KXNOR, 3, {OPMASKREG|BITS32,OPMASKREG|BITS32,OPMASKREG|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+30330, 513},
    /*  10 : KXNOR kreg32,kreg32 [r+vm:      vex.nds.l1.0f.ko32 46 /r         ] ND,SM0,SM1,ZU,AVX512BW,FUTURE */
        /* 260(001 205) 001(46) 110 : SM0,SM1,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KXNOR, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65643, 514},
    /*  11 : KXNOR kreg32,kreg32 [r+vm:      evex.nds.l1.0f.ko32 46 /r         ] ND,SM0,SM1,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fd 28) 300 001(46) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KXNOR, 2, {OPMASKREG|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+30339, 515},
    /*  12 : KXNOR kreg64,kreg64*,kreg64 [rvm:      vex.nds.l1.0f.ko64 46 /r         ] ND,SM0,SM1,SM2,ZU,AVX512BW,FUTURE */
        /* 261(001 204) 001(46) 120 : SM0,SM1,SM2,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KXNOR, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65650, 512},
    /*  13 : KXNOR kreg64,kreg64*,kreg64 [rvm:      evex.nds.l1.0f.ko64 46 /r         ] ND,SM0,SM1,SM2,ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fc 28) 300 001(46) 120 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KXNOR, 3, {OPMASKREG|BITS64,OPMASKREG|BITS64,OPMASKREG|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+30348, 513},
    /*  14 : KXNOR kreg64,kreg64 [r+vm:      vex.nds.l1.0f.ko64 46 /r         ] ND,SM0,SM1,ZU,AVX512BW,FUTURE */
        /* 260(001 204) 001(46) 110 : SM0,SM1,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KXNOR, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65657, 514},
    /*  15 : KXNOR kreg64,kreg64 [r+vm:      evex.nds.l1.0f.ko64 46 /r         ] ND,SM0,SM1,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fc 28) 300 001(46) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KXNOR, 2, {OPMASKREG|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+30357, 515},
};

static const struct itemplate instrux_XNORB[4] = {
    /*   0 : XNORB kreg8,kreg8*,kreg8 [rvm:      vex.nds.l1.0f.ko8 46 /r          ] ND,ZU,AVX512DQ,FUTURE */
        /* 261(001 005) 001(46) 120 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_XNORB, 3, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65608, 500},
    /*   1 : XNORB kreg8,kreg8*,kreg8 [rvm:      evex.nds.l1.0f.ko8 46 /r          ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 241(f1 7d 28) 300 001(46) 120 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_XNORB, 3, {OPMASKREG|BITS8,OPMASKREG|BITS8,OPMASKREG|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+30294, 501},
    /*   2 : XNORB kreg8,kreg8 [r+vm:      vex.nds.l1.0f.ko8 46 /r          ] ND,ZU,AVX512DQ,FUTURE */
        /* 260(001 005) 001(46) 110 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_XNORB, 2, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65615, 500},
    /*   3 : XNORB kreg8,kreg8 [r+vm:      evex.nds.l1.0f.ko8 46 /r          ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 240(f1 7d 28) 300 001(46) 110 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_XNORB, 2, {OPMASKREG|BITS8,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+30303, 501},
};

static const struct itemplate instrux_XNORW[4] = {
    /*   0 : XNORW kreg16,kreg16*,kreg16 [rvm:      vex.nds.l1.0f.ko16 46 /r         ] ND,ZU,AVX512F,FUTURE */
        /* 261(001 004) 001(46) 120 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_XNORW, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65622, 502},
    /*   1 : XNORW kreg16,kreg16*,kreg16 [rvm:      evex.nds.l1.0f.ko16 46 /r         ] ND,ZU,AVX512F,FUTURE,APX */
        /* 241(f1 7c 28) 300 001(46) 120 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_XNORW, 3, {OPMASKREG|BITS16,OPMASKREG|BITS16,OPMASKREG|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+30312, 503},
    /*   2 : XNORW kreg16,kreg16 [r+vm:      vex.nds.l1.0f.ko16 46 /r         ] ND,ZU,AVX512F,FUTURE */
        /* 260(001 004) 001(46) 110 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_XNORW, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65629, 502},
    /*   3 : XNORW kreg16,kreg16 [r+vm:      evex.nds.l1.0f.ko16 46 /r         ] ND,ZU,AVX512F,FUTURE,APX */
        /* 240(f1 7c 28) 300 001(46) 110 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_XNORW, 2, {OPMASKREG|BITS16,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+30321, 503},
};

static const struct itemplate instrux_XNORD[4] = {
    /*   0 : XNORD kreg32,kreg32*,kreg32 [rvm:      vex.nds.l1.0f.ko32 46 /r         ] ND,ZU,AVX512BW,FUTURE */
        /* 261(001 205) 001(46) 120 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_XNORD, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65636, 504},
    /*   1 : XNORD kreg32,kreg32*,kreg32 [rvm:      evex.nds.l1.0f.ko32 46 /r         ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fd 28) 300 001(46) 120 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_XNORD, 3, {OPMASKREG|BITS32,OPMASKREG|BITS32,OPMASKREG|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+30330, 505},
    /*   2 : XNORD kreg32,kreg32 [r+vm:      vex.nds.l1.0f.ko32 46 /r         ] ND,ZU,AVX512BW,FUTURE */
        /* 260(001 205) 001(46) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_XNORD, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65643, 504},
    /*   3 : XNORD kreg32,kreg32 [r+vm:      evex.nds.l1.0f.ko32 46 /r         ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fd 28) 300 001(46) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_XNORD, 2, {OPMASKREG|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+30339, 505},
};

static const struct itemplate instrux_XNORQ[4] = {
    /*   0 : XNORQ kreg64,kreg64*,kreg64 [rvm:      vex.nds.l1.0f.ko64 46 /r         ] ND,ZU,AVX512BW,FUTURE */
        /* 261(001 204) 001(46) 120 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_XNORQ, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65650, 504},
    /*   1 : XNORQ kreg64,kreg64*,kreg64 [rvm:      evex.nds.l1.0f.ko64 46 /r         ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fc 28) 300 001(46) 120 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_XNORQ, 3, {OPMASKREG|BITS64,OPMASKREG|BITS64,OPMASKREG|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+30348, 505},
    /*   2 : XNORQ kreg64,kreg64 [r+vm:      vex.nds.l1.0f.ko64 46 /r         ] ND,ZU,AVX512BW,FUTURE */
        /* 260(001 204) 001(46) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_XNORQ, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65657, 504},
    /*   3 : XNORQ kreg64,kreg64 [r+vm:      evex.nds.l1.0f.ko64 46 /r         ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fc 28) 300 001(46) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_XNORQ, 2, {OPMASKREG|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+30357, 505},
};

static const struct itemplate instrux_XNOR[16] = {
    /*   0 : XNOR kreg8,kreg8*,kreg8 [rvm:      vex.nds.l1.0f.ko8 46 /r          ] ND,SM0,SM1,SM2,ZU,AVX512DQ,FUTURE */
        /* 261(001 005) 001(46) 120 : SM0,SM1,SM2,NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_XNOR, 3, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65608, 508},
    /*   1 : XNOR kreg8,kreg8*,kreg8 [rvm:      evex.nds.l1.0f.ko8 46 /r          ] ND,SM0,SM1,SM2,ZU,AVX512DQ,FUTURE,APX */
        /* 241(f1 7d 28) 300 001(46) 120 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_XNOR, 3, {OPMASKREG|BITS8,OPMASKREG|BITS8,OPMASKREG|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+30294, 509},
    /*   2 : XNOR kreg8,kreg8 [r+vm:      vex.nds.l1.0f.ko8 46 /r          ] ND,SM0,SM1,ZU,AVX512DQ,FUTURE */
        /* 260(001 005) 001(46) 110 : SM0,SM1,NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_XNOR, 2, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65615, 510},
    /*   3 : XNOR kreg8,kreg8 [r+vm:      evex.nds.l1.0f.ko8 46 /r          ] ND,SM0,SM1,ZU,AVX512DQ,FUTURE,APX */
        /* 240(f1 7d 28) 300 001(46) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_XNOR, 2, {OPMASKREG|BITS8,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+30303, 511},
    /*   4 : XNOR kreg16,kreg16*,kreg16 [rvm:      vex.nds.l1.0f.ko16 46 /r         ] ND,SM0,SM1,SM2,ZU,AVX512F,FUTURE */
        /* 261(001 004) 001(46) 120 : SM0,SM1,SM2,NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_XNOR, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65622, 524},
    /*   5 : XNOR kreg16,kreg16*,kreg16 [rvm:      evex.nds.l1.0f.ko16 46 /r         ] ND,SM0,SM1,SM2,ZU,AVX512F,FUTURE,APX */
        /* 241(f1 7c 28) 300 001(46) 120 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_XNOR, 3, {OPMASKREG|BITS16,OPMASKREG|BITS16,OPMASKREG|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+30312, 525},
    /*   6 : XNOR kreg16,kreg16 [r+vm:      vex.nds.l1.0f.ko16 46 /r         ] ND,SM0,SM1,ZU,AVX512F,FUTURE */
        /* 260(001 004) 001(46) 110 : SM0,SM1,NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_XNOR, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65629, 526},
    /*   7 : XNOR kreg16,kreg16 [r+vm:      evex.nds.l1.0f.ko16 46 /r         ] ND,SM0,SM1,ZU,AVX512F,FUTURE,APX */
        /* 240(f1 7c 28) 300 001(46) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_XNOR, 2, {OPMASKREG|BITS16,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+30321, 527},
    /*   8 : XNOR kreg32,kreg32*,kreg32 [rvm:      vex.nds.l1.0f.ko32 46 /r         ] ND,SM0,SM1,SM2,ZU,AVX512BW,FUTURE */
        /* 261(001 205) 001(46) 120 : SM0,SM1,SM2,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_XNOR, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65636, 512},
    /*   9 : XNOR kreg32,kreg32*,kreg32 [rvm:      evex.nds.l1.0f.ko32 46 /r         ] ND,SM0,SM1,SM2,ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fd 28) 300 001(46) 120 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_XNOR, 3, {OPMASKREG|BITS32,OPMASKREG|BITS32,OPMASKREG|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+30330, 513},
    /*  10 : XNOR kreg32,kreg32 [r+vm:      vex.nds.l1.0f.ko32 46 /r         ] ND,SM0,SM1,ZU,AVX512BW,FUTURE */
        /* 260(001 205) 001(46) 110 : SM0,SM1,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_XNOR, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65643, 514},
    /*  11 : XNOR kreg32,kreg32 [r+vm:      evex.nds.l1.0f.ko32 46 /r         ] ND,SM0,SM1,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fd 28) 300 001(46) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_XNOR, 2, {OPMASKREG|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+30339, 515},
    /*  12 : XNOR kreg64,kreg64*,kreg64 [rvm:      vex.nds.l1.0f.ko64 46 /r         ] ND,SM0,SM1,SM2,ZU,AVX512BW,FUTURE */
        /* 261(001 204) 001(46) 120 : SM0,SM1,SM2,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_XNOR, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65650, 512},
    /*  13 : XNOR kreg64,kreg64*,kreg64 [rvm:      evex.nds.l1.0f.ko64 46 /r         ] ND,SM0,SM1,SM2,ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fc 28) 300 001(46) 120 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_XNOR, 3, {OPMASKREG|BITS64,OPMASKREG|BITS64,OPMASKREG|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+30348, 513},
    /*  14 : XNOR kreg64,kreg64 [r+vm:      vex.nds.l1.0f.ko64 46 /r         ] ND,SM0,SM1,ZU,AVX512BW,FUTURE */
        /* 260(001 204) 001(46) 110 : SM0,SM1,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_XNOR, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65657, 514},
    /*  15 : XNOR kreg64,kreg64 [r+vm:      evex.nds.l1.0f.ko64 46 /r         ] ND,SM0,SM1,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fc 28) 300 001(46) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_XNOR, 2, {OPMASKREG|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+30357, 515},
};

static const struct itemplate instrux_KXORB[4] = {
    /*   0 : KXORB kreg8,kreg8*,kreg8 [rvm:      vex.nds.l1.0f.ko8 47 /r          ] ZU,AVX512DQ,FUTURE */
        /* 261(001 005) 001(47) 120 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KXORB, 3, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65664, 500},
    /*   1 : KXORB kreg8,kreg8*,kreg8 [rvm:      evex.nds.l1.0f.ko8 47 /r          ] ZU,AVX512DQ,FUTURE,APX */
        /* 241(f1 7d 28) 300 001(47) 120 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KXORB, 3, {OPMASKREG|BITS8,OPMASKREG|BITS8,OPMASKREG|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+30366, 501},
    /*   2 : KXORB kreg8,kreg8 [r+vm:      vex.nds.l1.0f.ko8 47 /r          ] ND,ZU,AVX512DQ,FUTURE */
        /* 260(001 005) 001(47) 110 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KXORB, 2, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65671, 500},
    /*   3 : KXORB kreg8,kreg8 [r+vm:      evex.nds.l1.0f.ko8 47 /r          ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 240(f1 7d 28) 300 001(47) 110 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KXORB, 2, {OPMASKREG|BITS8,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+30375, 501},
};

static const struct itemplate instrux_KXORW[4] = {
    /*   0 : KXORW kreg16,kreg16*,kreg16 [rvm:      vex.nds.l1.0f.ko16 47 /r         ] ZU,AVX512F,FUTURE */
        /* 261(001 004) 001(47) 120 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KXORW, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65678, 502},
    /*   1 : KXORW kreg16,kreg16*,kreg16 [rvm:      evex.nds.l1.0f.ko16 47 /r         ] ZU,AVX512F,FUTURE,APX */
        /* 241(f1 7c 28) 300 001(47) 120 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KXORW, 3, {OPMASKREG|BITS16,OPMASKREG|BITS16,OPMASKREG|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+30384, 503},
    /*   2 : KXORW kreg16,kreg16 [r+vm:      vex.nds.l1.0f.ko16 47 /r         ] ND,ZU,AVX512F,FUTURE */
        /* 260(001 004) 001(47) 110 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KXORW, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65685, 502},
    /*   3 : KXORW kreg16,kreg16 [r+vm:      evex.nds.l1.0f.ko16 47 /r         ] ND,ZU,AVX512F,FUTURE,APX */
        /* 240(f1 7c 28) 300 001(47) 110 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KXORW, 2, {OPMASKREG|BITS16,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+30393, 503},
};

static const struct itemplate instrux_KXORD[4] = {
    /*   0 : KXORD kreg32,kreg32*,kreg32 [rvm:      vex.nds.l1.0f.ko32 47 /r         ] ZU,AVX512BW,FUTURE */
        /* 261(001 205) 001(47) 120 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KXORD, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65692, 504},
    /*   1 : KXORD kreg32,kreg32*,kreg32 [rvm:      evex.nds.l1.0f.ko32 47 /r         ] ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fd 28) 300 001(47) 120 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KXORD, 3, {OPMASKREG|BITS32,OPMASKREG|BITS32,OPMASKREG|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+30402, 505},
    /*   2 : KXORD kreg32,kreg32 [r+vm:      vex.nds.l1.0f.ko32 47 /r         ] ND,ZU,AVX512BW,FUTURE */
        /* 260(001 205) 001(47) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KXORD, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65699, 504},
    /*   3 : KXORD kreg32,kreg32 [r+vm:      evex.nds.l1.0f.ko32 47 /r         ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fd 28) 300 001(47) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KXORD, 2, {OPMASKREG|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+30411, 505},
};

static const struct itemplate instrux_KXORQ[4] = {
    /*   0 : KXORQ kreg64,kreg64*,kreg64 [rvm:      vex.nds.l1.0f.ko64 47 /r         ] ZU,AVX512BW,FUTURE */
        /* 261(001 204) 001(47) 120 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KXORQ, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65706, 504},
    /*   1 : KXORQ kreg64,kreg64*,kreg64 [rvm:      evex.nds.l1.0f.ko64 47 /r         ] ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fc 28) 300 001(47) 120 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KXORQ, 3, {OPMASKREG|BITS64,OPMASKREG|BITS64,OPMASKREG|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+30420, 505},
    /*   2 : KXORQ kreg64,kreg64 [r+vm:      vex.nds.l1.0f.ko64 47 /r         ] ND,ZU,AVX512BW,FUTURE */
        /* 260(001 204) 001(47) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KXORQ, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65713, 504},
    /*   3 : KXORQ kreg64,kreg64 [r+vm:      evex.nds.l1.0f.ko64 47 /r         ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fc 28) 300 001(47) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KXORQ, 2, {OPMASKREG|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+30429, 505},
};

static const struct itemplate instrux_KXOR[16] = {
    /*   0 : KXOR kreg8,kreg8*,kreg8 [rvm:      vex.nds.l1.0f.ko8 47 /r          ] ND,SM0,SM1,SM2,ZU,AVX512DQ,FUTURE */
        /* 261(001 005) 001(47) 120 : SM0,SM1,SM2,NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KXOR, 3, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65664, 508},
    /*   1 : KXOR kreg8,kreg8*,kreg8 [rvm:      evex.nds.l1.0f.ko8 47 /r          ] ND,SM0,SM1,SM2,ZU,AVX512DQ,FUTURE,APX */
        /* 241(f1 7d 28) 300 001(47) 120 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KXOR, 3, {OPMASKREG|BITS8,OPMASKREG|BITS8,OPMASKREG|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+30366, 509},
    /*   2 : KXOR kreg8,kreg8 [r+vm:      vex.nds.l1.0f.ko8 47 /r          ] ND,SM0,SM1,ZU,AVX512DQ,FUTURE */
        /* 260(001 005) 001(47) 110 : SM0,SM1,NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_KXOR, 2, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65671, 510},
    /*   3 : KXOR kreg8,kreg8 [r+vm:      evex.nds.l1.0f.ko8 47 /r          ] ND,SM0,SM1,ZU,AVX512DQ,FUTURE,APX */
        /* 240(f1 7d 28) 300 001(47) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_KXOR, 2, {OPMASKREG|BITS8,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+30375, 511},
    /*   4 : KXOR kreg16,kreg16*,kreg16 [rvm:      vex.nds.l1.0f.ko16 47 /r         ] ND,SM0,SM1,SM2,ZU,AVX512F,FUTURE */
        /* 261(001 004) 001(47) 120 : SM0,SM1,SM2,NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KXOR, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65678, 524},
    /*   5 : KXOR kreg16,kreg16*,kreg16 [rvm:      evex.nds.l1.0f.ko16 47 /r         ] ND,SM0,SM1,SM2,ZU,AVX512F,FUTURE,APX */
        /* 241(f1 7c 28) 300 001(47) 120 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KXOR, 3, {OPMASKREG|BITS16,OPMASKREG|BITS16,OPMASKREG|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+30384, 525},
    /*   6 : KXOR kreg16,kreg16 [r+vm:      vex.nds.l1.0f.ko16 47 /r         ] ND,SM0,SM1,ZU,AVX512F,FUTURE */
        /* 260(001 004) 001(47) 110 : SM0,SM1,NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_KXOR, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65685, 526},
    /*   7 : KXOR kreg16,kreg16 [r+vm:      evex.nds.l1.0f.ko16 47 /r         ] ND,SM0,SM1,ZU,AVX512F,FUTURE,APX */
        /* 240(f1 7c 28) 300 001(47) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_KXOR, 2, {OPMASKREG|BITS16,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+30393, 527},
    /*   8 : KXOR kreg32,kreg32*,kreg32 [rvm:      vex.nds.l1.0f.ko32 47 /r         ] ND,SM0,SM1,SM2,ZU,AVX512BW,FUTURE */
        /* 261(001 205) 001(47) 120 : SM0,SM1,SM2,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KXOR, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65692, 512},
    /*   9 : KXOR kreg32,kreg32*,kreg32 [rvm:      evex.nds.l1.0f.ko32 47 /r         ] ND,SM0,SM1,SM2,ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fd 28) 300 001(47) 120 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KXOR, 3, {OPMASKREG|BITS32,OPMASKREG|BITS32,OPMASKREG|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+30402, 513},
    /*  10 : KXOR kreg32,kreg32 [r+vm:      vex.nds.l1.0f.ko32 47 /r         ] ND,SM0,SM1,ZU,AVX512BW,FUTURE */
        /* 260(001 205) 001(47) 110 : SM0,SM1,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KXOR, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65699, 514},
    /*  11 : KXOR kreg32,kreg32 [r+vm:      evex.nds.l1.0f.ko32 47 /r         ] ND,SM0,SM1,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fd 28) 300 001(47) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KXOR, 2, {OPMASKREG|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+30411, 515},
    /*  12 : KXOR kreg64,kreg64*,kreg64 [rvm:      vex.nds.l1.0f.ko64 47 /r         ] ND,SM0,SM1,SM2,ZU,AVX512BW,FUTURE */
        /* 261(001 204) 001(47) 120 : SM0,SM1,SM2,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KXOR, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65706, 512},
    /*  13 : KXOR kreg64,kreg64*,kreg64 [rvm:      evex.nds.l1.0f.ko64 47 /r         ] ND,SM0,SM1,SM2,ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fc 28) 300 001(47) 120 : SM0,SM1,SM2,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KXOR, 3, {OPMASKREG|BITS64,OPMASKREG|BITS64,OPMASKREG|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+30420, 513},
    /*  14 : KXOR kreg64,kreg64 [r+vm:      vex.nds.l1.0f.ko64 47 /r         ] ND,SM0,SM1,ZU,AVX512BW,FUTURE */
        /* 260(001 204) 001(47) 110 : SM0,SM1,NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_KXOR, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65713, 514},
    /*  15 : KXOR kreg64,kreg64 [r+vm:      evex.nds.l1.0f.ko64 47 /r         ] ND,SM0,SM1,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fc 28) 300 001(47) 110 : SM0,SM1,ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_KXOR, 2, {OPMASKREG|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+30429, 515},
};

static const struct itemplate instrux_XORB[4] = {
    /*   0 : XORB kreg8,kreg8*,kreg8 [rvm:      vex.nds.l1.0f.ko8 47 /r          ] ND,ZU,AVX512DQ,FUTURE */
        /* 261(001 005) 001(47) 120 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_XORB, 3, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65664, 500},
    /*   1 : XORB kreg8,kreg8*,kreg8 [rvm:      evex.nds.l1.0f.ko8 47 /r          ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 241(f1 7d 28) 300 001(47) 120 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_XORB, 3, {OPMASKREG|BITS8,OPMASKREG|BITS8,OPMASKREG|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+30366, 501},
    /*   2 : XORB kreg8,kreg8 [r+vm:      vex.nds.l1.0f.ko8 47 /r          ] ND,ZU,AVX512DQ,FUTURE */
        /* 260(001 005) 001(47) 110 : NOAPX,ZU,VEX,AVX512DQ,FUTURE */
        {I_XORB, 2, {OPMASKREG|BITS8|RN_L16,OPMASKREG|BITS8|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65671, 500},
    /*   3 : XORB kreg8,kreg8 [r+vm:      evex.nds.l1.0f.ko8 47 /r          ] ND,ZU,AVX512DQ,FUTURE,APX */
        /* 240(f1 7d 28) 300 001(47) 110 : ZU,LONG,EVEX,PROT,AVX512DQ,APX,FUTURE */
        {I_XORB, 2, {OPMASKREG|BITS8,OPMASKREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+30375, 501},
};

static const struct itemplate instrux_XORW[4] = {
    /*   0 : XORW kreg16,kreg16*,kreg16 [rvm:      vex.nds.l1.0f.ko16 47 /r         ] ND,ZU,AVX512F,FUTURE */
        /* 261(001 004) 001(47) 120 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_XORW, 3, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65678, 502},
    /*   1 : XORW kreg16,kreg16*,kreg16 [rvm:      evex.nds.l1.0f.ko16 47 /r         ] ND,ZU,AVX512F,FUTURE,APX */
        /* 241(f1 7c 28) 300 001(47) 120 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_XORW, 3, {OPMASKREG|BITS16,OPMASKREG|BITS16,OPMASKREG|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+30384, 503},
    /*   2 : XORW kreg16,kreg16 [r+vm:      vex.nds.l1.0f.ko16 47 /r         ] ND,ZU,AVX512F,FUTURE */
        /* 260(001 004) 001(47) 110 : NOAPX,ZU,VEX,AVX512F,FUTURE */
        {I_XORW, 2, {OPMASKREG|BITS16|RN_L16,OPMASKREG|BITS16|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65685, 502},
    /*   3 : XORW kreg16,kreg16 [r+vm:      evex.nds.l1.0f.ko16 47 /r         ] ND,ZU,AVX512F,FUTURE,APX */
        /* 240(f1 7c 28) 300 001(47) 110 : ZU,LONG,EVEX,PROT,AVX512F,APX,FUTURE */
        {I_XORW, 2, {OPMASKREG|BITS16,OPMASKREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+30393, 503},
};

static const struct itemplate instrux_XORD[4] = {
    /*   0 : XORD kreg32,kreg32*,kreg32 [rvm:      vex.nds.l1.0f.ko32 47 /r         ] ND,ZU,AVX512BW,FUTURE */
        /* 261(001 205) 001(47) 120 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_XORD, 3, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65692, 504},
    /*   1 : XORD kreg32,kreg32*,kreg32 [rvm:      evex.nds.l1.0f.ko32 47 /r         ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fd 28) 300 001(47) 120 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_XORD, 3, {OPMASKREG|BITS32,OPMASKREG|BITS32,OPMASKREG|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+30402, 505},
    /*   2 : XORD kreg32,kreg32 [r+vm:      vex.nds.l1.0f.ko32 47 /r         ] ND,ZU,AVX512BW,FUTURE */
        /* 260(001 205) 001(47) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_XORD, 2, {OPMASKREG|BITS32|RN_L16,OPMASKREG|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65699, 504},
    /*   3 : XORD kreg32,kreg32 [r+vm:      evex.nds.l1.0f.ko32 47 /r         ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fd 28) 300 001(47) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_XORD, 2, {OPMASKREG|BITS32,OPMASKREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+30411, 505},
};

static const struct itemplate instrux_XORQ[4] = {
    /*   0 : XORQ kreg64,kreg64*,kreg64 [rvm:      vex.nds.l1.0f.ko64 47 /r         ] ND,ZU,AVX512BW,FUTURE */
        /* 261(001 204) 001(47) 120 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_XORQ, 3, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65706, 504},
    /*   1 : XORQ kreg64,kreg64*,kreg64 [rvm:      evex.nds.l1.0f.ko64 47 /r         ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 241(f1 fc 28) 300 001(47) 120 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_XORQ, 3, {OPMASKREG|BITS64,OPMASKREG|BITS64,OPMASKREG|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+30420, 505},
    /*   2 : XORQ kreg64,kreg64 [r+vm:      vex.nds.l1.0f.ko64 47 /r         ] ND,ZU,AVX512BW,FUTURE */
        /* 260(001 204) 001(47) 110 : NOAPX,ZU,VEX,AVX512BW,FUTURE */
        {I_XORQ, 2, {OPMASKREG|BITS64|RN_L16,OPMASKREG|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65713, 504},
    /*   3 : XORQ kreg64,kreg64 [r+vm:      evex.nds.l1.0f.ko64 47 /r         ] ND,ZU,AVX512BW,FUTURE,APX */
        /* 240(f1 fc 28) 300 001(47) 110 : ZU,LONG,EVEX,PROT,AVX512BW,APX,FUTURE */
        {I_XORQ, 2, {OPMASKREG|BITS64,OPMASKREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+30429, 505},
};

static const struct itemplate instrux_VALIGND[6] = {
    /*   0 : VALIGND xmmreg|mask|z,xmmreg*,xmmrm128|b32,imm8 [rvmi:fv:  evex.nds.128.66.0f3a.w0 03 /r ib  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 08) 301 001(03) 120 023 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VALIGND, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18133, 544},
    /*   1 : VALIGND xmmreg|mask|z,xmmrm128|b32,imm8 [r+vmi:fv:  evex.nds.128.66.0f3a.w0 03 /r ib  ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f3 7d 08) 301 001(03) 110 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VALIGND, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+18143, 544},
    /*   2 : VALIGND ymmreg|mask|z,ymmreg*,ymmrm256|b32,imm8 [rvmi:fv:  evex.nds.256.66.0f3a.w0 03 /r ib  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 28) 301 001(03) 120 023 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VALIGND, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18153, 544},
    /*   3 : VALIGND ymmreg|mask|z,ymmrm256|b32,imm8 [r+vmi:fv:  evex.nds.256.66.0f3a.w0 03 /r ib  ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f3 7d 28) 301 001(03) 110 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VALIGND, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+18163, 544},
    /*   4 : VALIGND zmmreg|mask|z,zmmreg*,zmmrm512|b32,imm8 [rvmi:fv:  evex.nds.512.66.0f3a.w0 03 /r ib  ] AVX512,FUTURE */
        /* 241(f3 7d 48) 301 001(03) 120 023 : EVEX,PROT,AVX512,FUTURE */
        {I_VALIGND, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18173, 545},
    /*   5 : VALIGND zmmreg|mask|z,zmmrm512|b32,imm8 [r+vmi:fv:  evex.nds.512.66.0f3a.w0 03 /r ib  ] ND,AVX512,FUTURE */
        /* 240(f3 7d 48) 301 001(03) 110 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VALIGND, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+18183, 545},
};

static const struct itemplate instrux_VALIGNQ[6] = {
    /*   0 : VALIGNQ xmmreg|mask|z,xmmreg*,xmmrm128|b64,imm8 [rvmi:fv:  evex.nds.128.66.0f3a.w1 03 /r ib  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 08) 301 001(03) 120 023 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VALIGNQ, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18193, 544},
    /*   1 : VALIGNQ xmmreg|mask|z,xmmrm128|b64,imm8 [r+vmi:fv:  evex.nds.128.66.0f3a.w1 03 /r ib  ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f3 fd 08) 301 001(03) 110 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VALIGNQ, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+18203, 544},
    /*   2 : VALIGNQ ymmreg|mask|z,ymmreg*,ymmrm256|b64,imm8 [rvmi:fv:  evex.nds.256.66.0f3a.w1 03 /r ib  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 28) 301 001(03) 120 023 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VALIGNQ, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18213, 544},
    /*   3 : VALIGNQ ymmreg|mask|z,ymmrm256|b64,imm8 [r+vmi:fv:  evex.nds.256.66.0f3a.w1 03 /r ib  ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f3 fd 28) 301 001(03) 110 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VALIGNQ, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+18223, 544},
    /*   4 : VALIGNQ zmmreg|mask|z,zmmreg*,zmmrm512|b64,imm8 [rvmi:fv:  evex.nds.512.66.0f3a.w1 03 /r ib  ] AVX512,FUTURE */
        /* 241(f3 fd 48) 301 001(03) 120 023 : EVEX,PROT,AVX512,FUTURE */
        {I_VALIGNQ, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18233, 545},
    /*   5 : VALIGNQ zmmreg|mask|z,zmmrm512|b64,imm8 [r+vmi:fv:  evex.nds.512.66.0f3a.w1 03 /r ib  ] ND,AVX512,FUTURE */
        /* 240(f3 fd 48) 301 001(03) 110 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VALIGNQ, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+18243, 545},
};

static const struct itemplate instrux_VBLENDMPD[3] = {
    /*   0 : VBLENDMPD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 65 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 08) 301 001(65) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VBLENDMPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+30798, 544},
    /*   1 : VBLENDMPD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 65 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 28) 301 001(65) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VBLENDMPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+30807, 544},
    /*   2 : VBLENDMPD zmmreg|mask|z,zmmreg,zmmrm512|b64 [rvm:fv:   evex.nds.512.66.0f38.w1 65 /r     ] AVX512,FUTURE */
        /* 241(f2 fd 48) 301 001(65) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VBLENDMPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+30816, 545},
};

static const struct itemplate instrux_VBLENDMPS[3] = {
    /*   0 : VBLENDMPS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f38.w0 65 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 08) 301 001(65) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VBLENDMPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+30825, 544},
    /*   1 : VBLENDMPS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f38.w0 65 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 28) 301 001(65) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VBLENDMPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+30834, 544},
    /*   2 : VBLENDMPS zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv:   evex.nds.512.66.0f38.w0 65 /r     ] AVX512,FUTURE */
        /* 241(f2 7d 48) 301 001(65) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VBLENDMPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+30843, 545},
};

static const struct itemplate instrux_VBROADCASTF32X2[2] = {
    /*   0 : VBROADCASTF32X2 ymmreg|mask|z,xmmrm64 [rm:t2:    evex.256.66.0f38.w0 19 /r         ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f2 7d 28) 311 001(19) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VBROADCASTF32X2, 2, {YMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+30852, 547},
    /*   1 : VBROADCASTF32X2 zmmreg|mask|z,xmmrm64 [rm:t2:    evex.512.66.0f38.w0 19 /r         ] AVX512DQ,FUTURE */
        /* 250(f2 7d 48) 311 001(19) 110 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VBROADCASTF32X2, 2, {ZMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+30861, 548},
};

static const struct itemplate instrux_VBROADCASTF32X4[2] = {
    /*   0 : VBROADCASTF32X4 ymmreg|mask|z,mem128 [rm:t4:    evex.256.66.0f38.w0 1a /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 28) 312 001(1a) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VBROADCASTF32X4, 2, {YMMREG,MEMORY|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+30870, 544},
    /*   1 : VBROADCASTF32X4 zmmreg|mask|z,mem128 [rm:t4:    evex.512.66.0f38.w0 1a /r         ] AVX512,FUTURE */
        /* 250(f2 7d 48) 312 001(1a) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VBROADCASTF32X4, 2, {ZMMREG,MEMORY|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+30879, 545},
};

static const struct itemplate instrux_VBROADCASTF32X8[1] = {
    /*   0 : VBROADCASTF32X8 zmmreg|mask|z,mem256 [rm:t8:    evex.512.66.0f38.w0 1b /r         ] AVX512DQ,FUTURE */
        /* 250(f2 7d 48) 313 001(1b) 110 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VBROADCASTF32X8, 2, {ZMMREG,MEMORY|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+30888, 548},
};

static const struct itemplate instrux_VBROADCASTF64X2[2] = {
    /*   0 : VBROADCASTF64X2 ymmreg|mask|z,mem128 [rm:t2:    evex.256.66.0f38.w1 1a /r         ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f2 fd 28) 311 001(1a) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VBROADCASTF64X2, 2, {YMMREG,MEMORY|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+30897, 547},
    /*   1 : VBROADCASTF64X2 zmmreg|mask|z,mem128 [rm:t2:    evex.512.66.0f38.w1 1a /r         ] AVX512DQ,FUTURE */
        /* 250(f2 fd 48) 311 001(1a) 110 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VBROADCASTF64X2, 2, {ZMMREG,MEMORY|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+30906, 548},
};

static const struct itemplate instrux_VBROADCASTF64X4[1] = {
    /*   0 : VBROADCASTF64X4 zmmreg|mask|z,mem256 [rm:t4:    evex.512.66.0f38.w1 1b /r         ] AVX512,FUTURE */
        /* 250(f2 fd 48) 312 001(1b) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VBROADCASTF64X4, 2, {ZMMREG,MEMORY|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+30915, 545},
};

static const struct itemplate instrux_VBROADCASTI32X2[3] = {
    /*   0 : VBROADCASTI32X2 xmmreg|mask|z,xmmrm64 [rm:t2:    evex.128.66.0f38.w0 59 /r         ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f2 7d 08) 311 001(59) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VBROADCASTI32X2, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+30924, 547},
    /*   1 : VBROADCASTI32X2 ymmreg|mask|z,xmmrm64 [rm:t2:    evex.256.66.0f38.w0 59 /r         ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f2 7d 28) 311 001(59) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VBROADCASTI32X2, 2, {YMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+30933, 547},
    /*   2 : VBROADCASTI32X2 zmmreg|mask|z,xmmrm64 [rm:t2:    evex.512.66.0f38.w0 59 /r         ] AVX512DQ,FUTURE */
        /* 250(f2 7d 48) 311 001(59) 110 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VBROADCASTI32X2, 2, {ZMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+30942, 548},
};

static const struct itemplate instrux_VBROADCASTI32X4[2] = {
    /*   0 : VBROADCASTI32X4 ymmreg|mask|z,mem128 [rm:t4:    evex.256.66.0f38.w0 5a /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 28) 312 001(5a) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VBROADCASTI32X4, 2, {YMMREG,MEMORY|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+30951, 544},
    /*   1 : VBROADCASTI32X4 zmmreg|mask|z,mem128 [rm:t4:    evex.512.66.0f38.w0 5a /r         ] AVX512,FUTURE */
        /* 250(f2 7d 48) 312 001(5a) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VBROADCASTI32X4, 2, {ZMMREG,MEMORY|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+30960, 545},
};

static const struct itemplate instrux_VBROADCASTI32X8[1] = {
    /*   0 : VBROADCASTI32X8 zmmreg|mask|z,mem256 [rm:t8:    evex.512.66.0f38.w0 5b /r         ] AVX512DQ,FUTURE */
        /* 250(f2 7d 48) 313 001(5b) 110 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VBROADCASTI32X8, 2, {ZMMREG,MEMORY|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+30969, 548},
};

static const struct itemplate instrux_VBROADCASTI64X2[2] = {
    /*   0 : VBROADCASTI64X2 ymmreg|mask|z,mem128 [rm:t2:    evex.256.66.0f38.w1 5a /r         ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f2 fd 28) 311 001(5a) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VBROADCASTI64X2, 2, {YMMREG,MEMORY|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+30978, 547},
    /*   1 : VBROADCASTI64X2 zmmreg|mask|z,mem128 [rm:t2:    evex.512.66.0f38.w1 5a /r         ] AVX512DQ,FUTURE */
        /* 250(f2 fd 48) 311 001(5a) 110 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VBROADCASTI64X2, 2, {ZMMREG,MEMORY|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+30987, 548},
};

static const struct itemplate instrux_VBROADCASTI64X4[1] = {
    /*   0 : VBROADCASTI64X4 zmmreg|mask|z,mem256 [rm:t4:    evex.512.66.0f38.w1 5b /r         ] AVX512,FUTURE */
        /* 250(f2 fd 48) 312 001(5b) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VBROADCASTI64X4, 2, {ZMMREG,MEMORY|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+30996, 545},
};

static const struct itemplate instrux_VCMPEQ_OQPD[3] = {
    /*   0 : VCMPEQ_OQPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f.w1 c2 /r 00    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(c2) 120 001(00) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPEQ_OQPD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+4743, 544},
    /*   1 : VCMPEQ_OQPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f.w1 c2 /r 00    ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(c2) 120 001(00) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPEQ_OQPD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+4754, 544},
    /*   2 : VCMPEQ_OQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv:  evex.nds.512.66.0f.w1 c2 /r 00    ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(c2) 120 001(00) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPEQ_OQPD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+4765, 545},
};

static const struct itemplate instrux_VCMPEQ_OQPS[3] = {
    /*   0 : VCMPEQ_OQPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.0f.w0 c2 /r 00       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 08) 301 001(c2) 120 001(00) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPEQ_OQPS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+4776, 544},
    /*   1 : VCMPEQ_OQPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.0f.w0 c2 /r 00       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7c 28) 301 001(c2) 120 001(00) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCMPEQ_OQPS, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+4787, 544},
    /*   2 : VCMPEQ_OQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv:  evex.nds.512.0f.w0 c2 /r 00       ] AVX512,FUTURE */
        /* 241(f1 7c 48) 301 001(c2) 120 001(00) : EVEX,PROT,AVX512,FUTURE */
        {I_VCMPEQ_OQPS, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+4798, 545},
};

static const struct itemplate instrux_VCMPEQ_OQSD[1] = {
    /*   0 : VCMPEQ_OQSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.lig.f2.0f.w1 c2 /r 00    ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(c2) 120 001(00) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPEQ_OQSD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+4809, 546},
};

static const struct itemplate instrux_VCMPEQ_OQSS[1] = {
    /*   0 : VCMPEQ_OQSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.lig.f3.0f.w0 c2 /r 00    ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(c2) 120 001(00) : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCMPEQ_OQSS, 3, {OPMASKREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+4820, 546},
};

static const struct itemplate instrux_VCOMPRESSPD[6] = {
    /*   0 : VCOMPRESSPD mem128|mask,xmmreg [mr:t1s:   evex.128.66.0f38.w1 8a /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 fd 08) 306 001(8a) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCOMPRESSPD, 2, {MEMORY|BITS128,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+31113, 544},
    /*   1 : VCOMPRESSPD mem256|mask,ymmreg [mr:t1s:   evex.256.66.0f38.w1 8a /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 fd 28) 306 001(8a) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCOMPRESSPD, 2, {MEMORY|BITS256,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+31122, 544},
    /*   2 : VCOMPRESSPD mem512|mask,zmmreg [mr:t1s:   evex.512.66.0f38.w1 8a /r         ] AVX512,FUTURE */
        /* 250(f2 fd 48) 306 001(8a) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VCOMPRESSPD, 2, {MEMORY|BITS512,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+31131, 545},
    /*   3 : VCOMPRESSPD xmmreg|mask|z,xmmreg [mr:       evex.128.66.0f38.w1 8a /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 fd 08) 300 001(8a) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCOMPRESSPD, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+31140, 544},
    /*   4 : VCOMPRESSPD ymmreg|mask|z,ymmreg [mr:       evex.256.66.0f38.w1 8a /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 fd 28) 300 001(8a) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCOMPRESSPD, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+31149, 544},
    /*   5 : VCOMPRESSPD zmmreg|mask|z,zmmreg [mr:       evex.512.66.0f38.w1 8a /r         ] AVX512,FUTURE */
        /* 250(f2 fd 48) 300 001(8a) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VCOMPRESSPD, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+31158, 545},
};

static const struct itemplate instrux_VCOMPRESSPS[6] = {
    /*   0 : VCOMPRESSPS mem128|mask,xmmreg [mr:t1s:   evex.128.66.0f38.w0 8a /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 08) 306 001(8a) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCOMPRESSPS, 2, {MEMORY|BITS128,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+31167, 544},
    /*   1 : VCOMPRESSPS mem256|mask,ymmreg [mr:t1s:   evex.256.66.0f38.w0 8a /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 28) 306 001(8a) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCOMPRESSPS, 2, {MEMORY|BITS256,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+31176, 544},
    /*   2 : VCOMPRESSPS mem512|mask,zmmreg [mr:t1s:   evex.512.66.0f38.w0 8a /r         ] AVX512,FUTURE */
        /* 250(f2 7d 48) 306 001(8a) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VCOMPRESSPS, 2, {MEMORY|BITS512,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+31185, 545},
    /*   3 : VCOMPRESSPS xmmreg|mask|z,xmmreg [mr:       evex.128.66.0f38.w0 8a /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 08) 300 001(8a) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCOMPRESSPS, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+31194, 544},
    /*   4 : VCOMPRESSPS ymmreg|mask|z,ymmreg [mr:       evex.256.66.0f38.w0 8a /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 28) 300 001(8a) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCOMPRESSPS, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+31203, 544},
    /*   5 : VCOMPRESSPS zmmreg|mask|z,zmmreg [mr:       evex.512.66.0f38.w0 8a /r         ] AVX512,FUTURE */
        /* 250(f2 7d 48) 300 001(8a) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VCOMPRESSPS, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+31212, 545},
};

static const struct itemplate instrux_VCVTPD2QQ[3] = {
    /*   0 : VCVTPD2QQ xmmreg|mask|z,xmmrm128|b64 [rm:fv:    evex.128.66.0f.w1 7b /r           ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f1 fd 08) 301 001(7b) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VCVTPD2QQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+31329, 547},
    /*   1 : VCVTPD2QQ ymmreg|mask|z,ymmrm256|b64 [rm:fv:    evex.256.66.0f.w1 7b /r           ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f1 fd 28) 301 001(7b) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VCVTPD2QQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+31338, 547},
    /*   2 : VCVTPD2QQ zmmreg|mask|z,zmmrm512|b64|er [rm:fv:    evex.512.66.0f.w1 7b /r           ] AVX512DQ,FUTURE */
        /* 250(f1 fd 48) 301 001(7b) 110 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VCVTPD2QQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+31347, 548},
};

static const struct itemplate instrux_VCVTPD2UDQ[3] = {
    /*   0 : VCVTPD2UDQ xmmreg|mask|z,xmmrm128|b64 [rm:fv:    evex.128.0f.w1 79 /r              ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 fc 08) 301 001(79) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCVTPD2UDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+31356, 544},
    /*   1 : VCVTPD2UDQ xmmreg|mask|z,ymmrm256|b64 [rm:fv:    evex.256.0f.w1 79 /r              ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 fc 28) 301 001(79) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCVTPD2UDQ, 2, {XMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+31365, 544},
    /*   2 : VCVTPD2UDQ ymmreg|mask|z,zmmrm512|b64|er [rm:fv:    evex.512.0f.w1 79 /r              ] AVX512,FUTURE */
        /* 250(f1 fc 48) 301 001(79) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VCVTPD2UDQ, 2, {YMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+31374, 545},
};

static const struct itemplate instrux_VCVTPD2UQQ[3] = {
    /*   0 : VCVTPD2UQQ xmmreg|mask|z,xmmrm128|b64 [rm:fv:    evex.128.66.0f.w1 79 /r           ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f1 fd 08) 301 001(79) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VCVTPD2UQQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+31383, 547},
    /*   1 : VCVTPD2UQQ ymmreg|mask|z,ymmrm256|b64 [rm:fv:    evex.256.66.0f.w1 79 /r           ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f1 fd 28) 301 001(79) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VCVTPD2UQQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+31392, 547},
    /*   2 : VCVTPD2UQQ zmmreg|mask|z,zmmrm512|b64|er [rm:fv:    evex.512.66.0f.w1 79 /r           ] AVX512DQ,FUTURE */
        /* 250(f1 fd 48) 301 001(79) 110 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VCVTPD2UQQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+31401, 548},
};

static const struct itemplate instrux_VCVTPS2QQ[3] = {
    /*   0 : VCVTPS2QQ xmmreg|mask|z,xmmrm64|b32 [rm:hv:    evex.128.66.0f.w0 7b /r           ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f1 7d 08) 302 001(7b) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VCVTPS2QQ, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+31491, 547},
    /*   1 : VCVTPS2QQ ymmreg|mask|z,xmmrm128|b32 [rm:hv:    evex.256.66.0f.w0 7b /r           ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f1 7d 28) 302 001(7b) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VCVTPS2QQ, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+31500, 547},
    /*   2 : VCVTPS2QQ zmmreg|mask|z,ymmrm256|b32|er [rm:hv:    evex.512.66.0f.w0 7b /r           ] AVX512DQ,FUTURE */
        /* 250(f1 7d 48) 302 001(7b) 110 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VCVTPS2QQ, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+31509, 548},
};

static const struct itemplate instrux_VCVTPS2UDQ[3] = {
    /*   0 : VCVTPS2UDQ xmmreg|mask|z,xmmrm128|b32 [rm:fv:    evex.128.0f.w0 79 /r              ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7c 08) 301 001(79) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCVTPS2UDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+31518, 544},
    /*   1 : VCVTPS2UDQ ymmreg|mask|z,ymmrm256|b32 [rm:fv:    evex.256.0f.w0 79 /r              ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7c 28) 301 001(79) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCVTPS2UDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+31527, 544},
    /*   2 : VCVTPS2UDQ zmmreg|mask|z,zmmrm512|b32|er [rm:fv:    evex.512.0f.w0 79 /r              ] AVX512,FUTURE */
        /* 250(f1 7c 48) 301 001(79) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VCVTPS2UDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+31536, 545},
};

static const struct itemplate instrux_VCVTPS2UQQ[3] = {
    /*   0 : VCVTPS2UQQ xmmreg|mask|z,xmmrm64|b32 [rm:hv:    evex.128.66.0f.w0 79 /r           ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f1 7d 08) 302 001(79) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VCVTPS2UQQ, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+31545, 547},
    /*   1 : VCVTPS2UQQ ymmreg|mask|z,xmmrm128|b32 [rm:hv:    evex.256.66.0f.w0 79 /r           ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f1 7d 28) 302 001(79) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VCVTPS2UQQ, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+31554, 547},
    /*   2 : VCVTPS2UQQ zmmreg|mask|z,ymmrm256|b32|er [rm:hv:    evex.512.66.0f.w0 79 /r           ] AVX512DQ,FUTURE */
        /* 250(f1 7d 48) 302 001(79) 110 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VCVTPS2UQQ, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+31563, 548},
};

static const struct itemplate instrux_VCVTQQ2PD[3] = {
    /*   0 : VCVTQQ2PD xmmreg|mask|z,xmmrm128|b64 [rm:fv:    evex.128.f3.0f.w1 e6 /r           ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f1 fe 08) 301 001(e6) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VCVTQQ2PD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+31572, 547},
    /*   1 : VCVTQQ2PD ymmreg|mask|z,ymmrm256|b64 [rm:fv:    evex.256.f3.0f.w1 e6 /r           ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f1 fe 28) 301 001(e6) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VCVTQQ2PD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+31581, 547},
    /*   2 : VCVTQQ2PD zmmreg|mask|z,zmmrm512|b64|er [rm:fv:    evex.512.f3.0f.w1 e6 /r           ] AVX512DQ,FUTURE */
        /* 250(f1 fe 48) 301 001(e6) 110 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VCVTQQ2PD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+31590, 548},
};

static const struct itemplate instrux_VCVTQQ2PS[3] = {
    /*   0 : VCVTQQ2PS xmmreg|mask|z,xmmrm128|b64 [rm:fv:    evex.128.0f.w1 5b /r              ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f1 fc 08) 301 001(5b) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VCVTQQ2PS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+31599, 547},
    /*   1 : VCVTQQ2PS xmmreg|mask|z,ymmrm256|b64 [rm:fv:    evex.256.0f.w1 5b /r              ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f1 fc 28) 301 001(5b) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VCVTQQ2PS, 2, {XMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+31608, 547},
    /*   2 : VCVTQQ2PS ymmreg|mask|z,zmmrm512|b64|er [rm:fv:    evex.512.0f.w1 5b /r              ] AVX512DQ,FUTURE */
        /* 250(f1 fc 48) 301 001(5b) 110 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VCVTQQ2PS, 2, {YMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+31617, 548},
};

static const struct itemplate instrux_VCVTSD2USI[2] = {
    /*   0 : VCVTSD2USI reg32,xmmrm64|er [rm:t1f64: evex.128.f2.0f.w0 79 /r           ] AVX512,FUTURE */
        /* 250(f1 7f 08) 310 001(79) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VCVTSD2USI, 2, {REG_GPR|BITS32,RM_XMM|BITS64,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+31662, 545},
    /*   1 : VCVTSD2USI reg64,xmmrm64|er [rm:t1f64: evex.128.f2.0f.w1 79 /r           ] AVX512,FUTURE */
        /* 250(f1 ff 08) 310 001(79) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VCVTSD2USI, 2, {REG_GPR|BITS64,RM_XMM|BITS64,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+31671, 545},
};

static const struct itemplate instrux_VCVTSS2USI[2] = {
    /*   0 : VCVTSS2USI reg32,xmmrm32|er [rm:t1f32: evex.128.f3.0f.w0 79 /r           ] AVX512,FUTURE */
        /* 250(f1 7e 08) 307 001(79) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VCVTSS2USI, 2, {REG_GPR|BITS32,RM_XMM|BITS32,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+31788, 545},
    /*   1 : VCVTSS2USI reg64,xmmrm32|er [rm:t1f32: evex.128.f3.0f.w1 79 /r           ] AVX512,FUTURE */
        /* 250(f1 fe 08) 307 001(79) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VCVTSS2USI, 2, {REG_GPR|BITS64,RM_XMM|BITS32,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+31797, 545},
};

static const struct itemplate instrux_VCVTTPD2QQ[3] = {
    /*   0 : VCVTTPD2QQ xmmreg|mask|z,xmmrm128|b64 [rm:fv:    evex.128.66.0f.w1 7a /r           ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f1 fd 08) 301 001(7a) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VCVTTPD2QQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+31833, 547},
    /*   1 : VCVTTPD2QQ ymmreg|mask|z,ymmrm256|b64 [rm:fv:    evex.256.66.0f.w1 7a /r           ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f1 fd 28) 301 001(7a) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VCVTTPD2QQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+31842, 547},
    /*   2 : VCVTTPD2QQ zmmreg|mask|z,zmmrm512|b64|sae [rm:fv:    evex.512.66.0f.w1 7a /r           ] AVX512DQ,FUTURE */
        /* 250(f1 fd 48) 301 001(7a) 110 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VCVTTPD2QQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+31851, 548},
};

static const struct itemplate instrux_VCVTTPD2UDQ[3] = {
    /*   0 : VCVTTPD2UDQ xmmreg|mask|z,xmmrm128|b64 [rm:fv:    evex.128.0f.w1 78 /r              ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 fc 08) 301 001(78) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCVTTPD2UDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+31860, 544},
    /*   1 : VCVTTPD2UDQ xmmreg|mask|z,ymmrm256|b64 [rm:fv:    evex.256.0f.w1 78 /r              ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 fc 28) 301 001(78) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCVTTPD2UDQ, 2, {XMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+31869, 544},
    /*   2 : VCVTTPD2UDQ ymmreg|mask|z,zmmrm512|b64|sae [rm:fv:    evex.512.0f.w1 78 /r              ] AVX512,FUTURE */
        /* 250(f1 fc 48) 301 001(78) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VCVTTPD2UDQ, 2, {YMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+31878, 545},
};

static const struct itemplate instrux_VCVTTPD2UQQ[3] = {
    /*   0 : VCVTTPD2UQQ xmmreg|mask|z,xmmrm128|b64 [rm:fv:    evex.128.66.0f.w1 78 /r           ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f1 fd 08) 301 001(78) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VCVTTPD2UQQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+31887, 547},
    /*   1 : VCVTTPD2UQQ ymmreg|mask|z,ymmrm256|b64 [rm:fv:    evex.256.66.0f.w1 78 /r           ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f1 fd 28) 301 001(78) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VCVTTPD2UQQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+31896, 547},
    /*   2 : VCVTTPD2UQQ zmmreg|mask|z,zmmrm512|b64|sae [rm:fv:    evex.512.66.0f.w1 78 /r           ] AVX512DQ,FUTURE */
        /* 250(f1 fd 48) 301 001(78) 110 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VCVTTPD2UQQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+31905, 548},
};

static const struct itemplate instrux_VCVTTPS2QQ[3] = {
    /*   0 : VCVTTPS2QQ xmmreg|mask|z,xmmrm64|b32 [rm:hv:    evex.128.66.0f.w0 7a /r           ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f1 7d 08) 302 001(7a) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VCVTTPS2QQ, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+31941, 547},
    /*   1 : VCVTTPS2QQ ymmreg|mask|z,xmmrm128|b32 [rm:hv:    evex.256.66.0f.w0 7a /r           ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f1 7d 28) 302 001(7a) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VCVTTPS2QQ, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+31950, 547},
    /*   2 : VCVTTPS2QQ zmmreg|mask|z,ymmrm256|b32|sae [rm:hv:    evex.512.66.0f.w0 7a /r           ] AVX512DQ,FUTURE */
        /* 250(f1 7d 48) 302 001(7a) 110 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VCVTTPS2QQ, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+31959, 548},
};

static const struct itemplate instrux_VCVTTPS2UDQ[3] = {
    /*   0 : VCVTTPS2UDQ xmmreg|mask|z,xmmrm128|b32 [rm:fv:    evex.128.0f.w0 78 /r              ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7c 08) 301 001(78) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCVTTPS2UDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+31968, 544},
    /*   1 : VCVTTPS2UDQ ymmreg|mask|z,ymmrm256|b32 [rm:fv:    evex.256.0f.w0 78 /r              ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7c 28) 301 001(78) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCVTTPS2UDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+31977, 544},
    /*   2 : VCVTTPS2UDQ zmmreg|mask|z,zmmrm512|b32|sae [rm:fv:    evex.512.0f.w0 78 /r              ] AVX512,FUTURE */
        /* 250(f1 7c 48) 301 001(78) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VCVTTPS2UDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+31986, 545},
};

static const struct itemplate instrux_VCVTTPS2UQQ[3] = {
    /*   0 : VCVTTPS2UQQ xmmreg|mask|z,xmmrm64|b32 [rm:hv:    evex.128.66.0f.w0 78 /r           ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f1 7d 08) 302 001(78) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VCVTTPS2UQQ, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+31995, 547},
    /*   1 : VCVTTPS2UQQ ymmreg|mask|z,xmmrm128|b32 [rm:hv:    evex.256.66.0f.w0 78 /r           ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f1 7d 28) 302 001(78) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VCVTTPS2UQQ, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+32004, 547},
    /*   2 : VCVTTPS2UQQ zmmreg|mask|z,ymmrm256|b32|sae [rm:hv:    evex.512.66.0f.w0 78 /r           ] AVX512DQ,FUTURE */
        /* 250(f1 7d 48) 302 001(78) 110 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VCVTTPS2UQQ, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+32013, 548},
};

static const struct itemplate instrux_VCVTTSD2USI[2] = {
    /*   0 : VCVTTSD2USI reg32,xmmrm64|sae [rm:t1f64: evex.128.f2.0f.w0 78 /r           ] AVX512,FUTURE */
        /* 250(f1 7f 08) 310 001(78) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VCVTTSD2USI, 2, {REG_GPR|BITS32,RM_XMM|BITS64,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+32040, 545},
    /*   1 : VCVTTSD2USI reg64,xmmrm64|sae [rm:t1f64: evex.128.f2.0f.w1 78 /r           ] AVX512,FUTURE */
        /* 250(f1 ff 08) 310 001(78) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VCVTTSD2USI, 2, {REG_GPR|BITS64,RM_XMM|BITS64,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+32049, 545},
};

static const struct itemplate instrux_VCVTTSS2USI[2] = {
    /*   0 : VCVTTSS2USI reg32,xmmrm32|sae [rm:t1f32: evex.128.f3.0f.w0 78 /r           ] AVX512,FUTURE */
        /* 250(f1 7e 08) 307 001(78) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VCVTTSS2USI, 2, {REG_GPR|BITS32,RM_XMM|BITS32,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+32076, 545},
    /*   1 : VCVTTSS2USI reg64,xmmrm32|sae [rm:t1f32: evex.128.f3.0f.w1 78 /r           ] AVX512,FUTURE */
        /* 250(f1 fe 08) 307 001(78) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VCVTTSS2USI, 2, {REG_GPR|BITS64,RM_XMM|BITS32,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+32085, 545},
};

static const struct itemplate instrux_VCVTUDQ2PD[3] = {
    /*   0 : VCVTUDQ2PD xmmreg|mask|z,xmmrm64|b32 [rm:hv:    evex.128.f3.0f.w0 7a /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7e 08) 302 001(7a) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCVTUDQ2PD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+32094, 544},
    /*   1 : VCVTUDQ2PD ymmreg|mask|z,xmmrm128|b32 [rm:hv:    evex.256.f3.0f.w0 7a /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7e 28) 302 001(7a) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCVTUDQ2PD, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+32103, 544},
    /*   2 : VCVTUDQ2PD zmmreg|mask|z,ymmrm256|b32|er [rm:hv:    evex.512.f3.0f.w0 7a /r           ] AVX512,FUTURE */
        /* 250(f1 7e 48) 302 001(7a) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VCVTUDQ2PD, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+32112, 545},
};

static const struct itemplate instrux_VCVTUDQ2PS[3] = {
    /*   0 : VCVTUDQ2PS xmmreg|mask|z,xmmrm128|b32 [rm:fv:    evex.128.f2.0f.w0 7a /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7f 08) 301 001(7a) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCVTUDQ2PS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+32121, 544},
    /*   1 : VCVTUDQ2PS ymmreg|mask|z,ymmrm256|b32 [rm:fv:    evex.256.f2.0f.w0 7a /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7f 28) 301 001(7a) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VCVTUDQ2PS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+32130, 544},
    /*   2 : VCVTUDQ2PS zmmreg|mask|z,zmmrm512|b32|er [rm:fv:    evex.512.f2.0f.w0 7a /r           ] AVX512,FUTURE */
        /* 250(f1 7f 48) 301 001(7a) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VCVTUDQ2PS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+32139, 545},
};

static const struct itemplate instrux_VCVTUQQ2PD[3] = {
    /*   0 : VCVTUQQ2PD xmmreg|mask|z,xmmrm128|b64 [rm:fv:    evex.128.f3.0f.w1 7a /r           ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f1 fe 08) 301 001(7a) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VCVTUQQ2PD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+32148, 547},
    /*   1 : VCVTUQQ2PD ymmreg|mask|z,ymmrm256|b64 [rm:fv:    evex.256.f3.0f.w1 7a /r           ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f1 fe 28) 301 001(7a) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VCVTUQQ2PD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+32157, 547},
    /*   2 : VCVTUQQ2PD zmmreg|mask|z,zmmrm512|b64|er [rm:fv:    evex.512.f3.0f.w1 7a /r           ] AVX512DQ,FUTURE */
        /* 250(f1 fe 48) 301 001(7a) 110 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VCVTUQQ2PD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+32166, 548},
};

static const struct itemplate instrux_VCVTUQQ2PS[3] = {
    /*   0 : VCVTUQQ2PS xmmreg|mask|z,xmmrm128|b64 [rm:fv:    evex.128.f2.0f.w1 7a /r           ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f1 ff 08) 301 001(7a) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VCVTUQQ2PS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+32175, 547},
    /*   1 : VCVTUQQ2PS xmmreg|mask|z,ymmrm256|b64 [rm:fv:    evex.256.f2.0f.w1 7a /r           ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f1 ff 28) 301 001(7a) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VCVTUQQ2PS, 2, {XMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+32184, 547},
    /*   2 : VCVTUQQ2PS ymmreg|mask|z,zmmrm512|b64|er [rm:fv:    evex.512.f2.0f.w1 7a /r           ] AVX512DQ,FUTURE */
        /* 250(f1 ff 48) 301 001(7a) 110 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VCVTUQQ2PS, 2, {YMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+32193, 548},
};

static const struct itemplate instrux_VCVTUSI2SD[2] = {
    /*   0 : VCVTUSI2SD xmmreg,xmmreg|er,rm32 [rvm:t1s:  evex.nds.lig.f2.0f.w0 7b /r       ] AVX512,FUTURE */
        /* 241(f1 7f 08) 306 001(7b) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCVTUSI2SD, 3, {XMMREG,XMMREG,RM_GPR|BITS32,0,0}, {0,ER,0,0,0}, nasm_bytecodes+32202, 546},
    /*   1 : VCVTUSI2SD xmmreg,xmmreg|er,rm64 [rvm:t1s:  evex.nds.lig.f2.0f.w1 7b /r       ] AVX512,FUTURE */
        /* 241(f1 ff 08) 306 001(7b) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCVTUSI2SD, 3, {XMMREG,XMMREG,RM_GPR|BITS64,0,0}, {0,ER,0,0,0}, nasm_bytecodes+32211, 546},
};

static const struct itemplate instrux_VCVTUSI2SS[3] = {
    /*   0 : VCVTUSI2SS xmmreg,xmmreg|er,rm32 [rvm:t1s:  evex.nds.lig.f3.0f.w0 7b /r       ] AVX512,FUTURE */
        /* 241(f1 7e 08) 306 001(7b) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCVTUSI2SS, 3, {XMMREG,XMMREG,RM_GPR|BITS32,0,0}, {0,ER,0,0,0}, nasm_bytecodes+32220, 546},
    /*   1 : VCVTUSI2SS xmmreg,xmmreg|er,rm64 [rvm:t1s:  evex.nds.lig.f3.0f.w1 7b /r       ] AVX512,FUTURE */
        /* 241(f1 fe 08) 306 001(7b) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VCVTUSI2SS, 3, {XMMREG,XMMREG,RM_GPR|BITS64,0,0}, {0,ER,0,0,0}, nasm_bytecodes+32229, 546},
    /*   2 : VCVTUSI2SS xmmreg,xmmreg|er,rm64|er [rvm:t1s:  evex.nds.lig.f3.map5.w1 7b /r     ] AVX512FP16,FUTURE */
        /* 241(f5 fe 08) 306 001(7b) 120 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTUSI2SS, 3, {XMMREG,XMMREG,RM_GPR|BITS64,0,0}, {0,ER,ER,0,0}, nasm_bytecodes+46845, 568},
};

static const struct itemplate instrux_VDBPSADBW[6] = {
    /*   0 : VDBPSADBW xmmreg|mask|z,xmmreg*,xmmrm128,imm8 [rvmi:fvm: evex.nds.128.66.0f3a.w0 42 /r ib  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 08) 303 001(42) 120 023 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VDBPSADBW, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18363, 550},
    /*   1 : VDBPSADBW xmmreg|mask|z,xmmrm128,imm8 [r+vmi:fvm: evex.nds.128.66.0f3a.w0 42 /r ib  ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f3 7d 08) 303 001(42) 110 022 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VDBPSADBW, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18373, 550},
    /*   2 : VDBPSADBW ymmreg|mask|z,ymmreg*,ymmrm256,imm8 [rvmi:fvm: evex.nds.256.66.0f3a.w0 42 /r ib  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 28) 303 001(42) 120 023 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VDBPSADBW, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18383, 550},
    /*   3 : VDBPSADBW ymmreg|mask|z,ymmrm256,imm8 [r+vmi:fvm: evex.nds.256.66.0f3a.w0 42 /r ib  ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f3 7d 28) 303 001(42) 110 022 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VDBPSADBW, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18393, 550},
    /*   4 : VDBPSADBW zmmreg|mask|z,zmmreg*,zmmrm512,imm8 [rvmi:fvm: evex.nds.512.66.0f3a.w0 42 /r ib  ] AVX512BW,FUTURE */
        /* 241(f3 7d 48) 303 001(42) 120 023 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VDBPSADBW, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18403, 551},
    /*   5 : VDBPSADBW zmmreg|mask|z,zmmrm512,imm8 [r+vmi:fvm: evex.nds.512.66.0f3a.w0 42 /r ib  ] ND,AVX512BW,FUTURE */
        /* 240(f3 7d 48) 303 001(42) 110 022 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VDBPSADBW, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18413, 551},
};

static const struct itemplate instrux_VEXP2PD[1] = {
    /*   0 : VEXP2PD zmmreg|mask|z,zmmrm512|b64|sae [rm:fv:    evex.512.66.0f38.w1 c8 /r         ] AVX512ER,FUTURE */
        /* 250(f2 fd 48) 301 001(c8) 110 : EVEX,PROT,AVX512ER,FUTURE */
        {I_VEXP2PD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+32382, 552},
};

static const struct itemplate instrux_VEXP2PS[1] = {
    /*   0 : VEXP2PS zmmreg|mask|z,zmmrm512|b32|sae [rm:fv:    evex.512.66.0f38.w0 c8 /r         ] AVX512ER,FUTURE */
        /* 250(f2 7d 48) 301 001(c8) 110 : EVEX,PROT,AVX512ER,FUTURE */
        {I_VEXP2PS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+32391, 552},
};

static const struct itemplate instrux_VEXPANDPD[6] = {
    /*   0 : VEXPANDPD xmmreg|mask|z,mem128 [rm:t1s:   evex.128.66.0f38.w1 88 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 fd 08) 306 001(88) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VEXPANDPD, 2, {XMMREG,MEMORY|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+32400, 544},
    /*   1 : VEXPANDPD ymmreg|mask|z,mem256 [rm:t1s:   evex.256.66.0f38.w1 88 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 fd 28) 306 001(88) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VEXPANDPD, 2, {YMMREG,MEMORY|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+32409, 544},
    /*   2 : VEXPANDPD zmmreg|mask|z,mem512 [rm:t1s:   evex.512.66.0f38.w1 88 /r         ] AVX512,FUTURE */
        /* 250(f2 fd 48) 306 001(88) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VEXPANDPD, 2, {ZMMREG,MEMORY|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+32418, 545},
    /*   3 : VEXPANDPD xmmreg|mask|z,xmmreg [rm:t1s:   evex.128.66.0f38.w1 88 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 fd 08) 306 001(88) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VEXPANDPD, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+32400, 544},
    /*   4 : VEXPANDPD ymmreg|mask|z,ymmreg [rm:t1s:   evex.256.66.0f38.w1 88 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 fd 28) 306 001(88) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VEXPANDPD, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+32409, 544},
    /*   5 : VEXPANDPD zmmreg|mask|z,zmmreg [rm:t1s:   evex.512.66.0f38.w1 88 /r         ] AVX512,FUTURE */
        /* 250(f2 fd 48) 306 001(88) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VEXPANDPD, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+32418, 545},
};

static const struct itemplate instrux_VEXPANDPS[6] = {
    /*   0 : VEXPANDPS xmmreg|mask|z,mem128 [rm:t1s:   evex.128.66.0f38.w0 88 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 08) 306 001(88) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VEXPANDPS, 2, {XMMREG,MEMORY|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+32427, 544},
    /*   1 : VEXPANDPS ymmreg|mask|z,mem256 [rm:t1s:   evex.256.66.0f38.w0 88 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 28) 306 001(88) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VEXPANDPS, 2, {YMMREG,MEMORY|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+32436, 544},
    /*   2 : VEXPANDPS zmmreg|mask|z,mem512 [rm:t1s:   evex.512.66.0f38.w0 88 /r         ] AVX512,FUTURE */
        /* 250(f2 7d 48) 306 001(88) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VEXPANDPS, 2, {ZMMREG,MEMORY|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+32445, 545},
    /*   3 : VEXPANDPS xmmreg|mask|z,xmmreg [rm:t1s:   evex.128.66.0f38.w0 88 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 08) 306 001(88) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VEXPANDPS, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+32427, 544},
    /*   4 : VEXPANDPS ymmreg|mask|z,ymmreg [rm:t1s:   evex.256.66.0f38.w0 88 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 28) 306 001(88) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VEXPANDPS, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+32436, 544},
    /*   5 : VEXPANDPS zmmreg|mask|z,zmmreg [rm:t1s:   evex.512.66.0f38.w0 88 /r         ] AVX512,FUTURE */
        /* 250(f2 7d 48) 306 001(88) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VEXPANDPS, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+32445, 545},
};

static const struct itemplate instrux_VEXTRACTF32X4[4] = {
    /*   0 : VEXTRACTF32X4 xmmreg|mask|z,ymmreg,imm8 [mri:      evex.256.66.0f3a.w0 19 /r ib      ] AVX512,AVX512VL,FUTURE */
        /* 250(f3 7d 28) 300 001(19) 101 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VEXTRACTF32X4, 3, {XMMREG,YMMREG,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18423, 544},
    /*   1 : VEXTRACTF32X4 xmmreg|mask|z,zmmreg,imm8 [mri:      evex.512.66.0f3a.w0 19 /r ib      ] AVX512,FUTURE */
        /* 250(f3 7d 48) 300 001(19) 101 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VEXTRACTF32X4, 3, {XMMREG,ZMMREG,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18433, 545},
    /*   2 : VEXTRACTF32X4 mem128|mask,ymmreg,imm8 [mri:t4:   evex.256.66.0f3a.w0 19 /r ib      ] AVX512,AVX512VL,FUTURE */
        /* 250(f3 7d 28) 312 001(19) 101 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VEXTRACTF32X4, 3, {MEMORY|BITS128,YMMREG,IMM_NORMAL|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+18443, 544},
    /*   3 : VEXTRACTF32X4 mem128|mask,zmmreg,imm8 [mri:t4:   evex.512.66.0f3a.w0 19 /r ib      ] AVX512,FUTURE */
        /* 250(f3 7d 48) 312 001(19) 101 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VEXTRACTF32X4, 3, {MEMORY|BITS128,ZMMREG,IMM_NORMAL|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+18453, 545},
};

static const struct itemplate instrux_VEXTRACTF32X8[2] = {
    /*   0 : VEXTRACTF32X8 ymmreg|mask|z,zmmreg,imm8 [mri:      evex.512.66.0f3a.w0 1b /r ib      ] AVX512DQ,FUTURE */
        /* 250(f3 7d 48) 300 001(1b) 101 022 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VEXTRACTF32X8, 3, {YMMREG,ZMMREG,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18463, 548},
    /*   1 : VEXTRACTF32X8 mem256|mask,zmmreg,imm8 [mri:t8:   evex.512.66.0f3a.w0 1b /r ib      ] AVX512DQ,FUTURE */
        /* 250(f3 7d 48) 313 001(1b) 101 022 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VEXTRACTF32X8, 3, {MEMORY|BITS256,ZMMREG,IMM_NORMAL|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+18473, 548},
};

static const struct itemplate instrux_VEXTRACTF64X2[4] = {
    /*   0 : VEXTRACTF64X2 xmmreg|mask|z,ymmreg,imm8 [mri:      evex.256.66.0f3a.w1 19 /r ib      ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f3 fd 28) 300 001(19) 101 022 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VEXTRACTF64X2, 3, {XMMREG,YMMREG,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18483, 547},
    /*   1 : VEXTRACTF64X2 xmmreg|mask|z,zmmreg,imm8 [mri:      evex.512.66.0f3a.w1 19 /r ib      ] AVX512DQ,FUTURE */
        /* 250(f3 fd 48) 300 001(19) 101 022 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VEXTRACTF64X2, 3, {XMMREG,ZMMREG,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18493, 548},
    /*   2 : VEXTRACTF64X2 mem128|mask,ymmreg,imm8 [mri:t2:   evex.256.66.0f3a.w1 19 /r ib      ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f3 fd 28) 311 001(19) 101 022 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VEXTRACTF64X2, 3, {MEMORY|BITS128,YMMREG,IMM_NORMAL|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+18503, 547},
    /*   3 : VEXTRACTF64X2 mem128|mask,zmmreg,imm8 [mri:t2:   evex.512.66.0f3a.w1 19 /r ib      ] AVX512DQ,FUTURE */
        /* 250(f3 fd 48) 311 001(19) 101 022 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VEXTRACTF64X2, 3, {MEMORY|BITS128,ZMMREG,IMM_NORMAL|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+18513, 548},
};

static const struct itemplate instrux_VEXTRACTF64X4[2] = {
    /*   0 : VEXTRACTF64X4 ymmreg|mask|z,zmmreg,imm8 [mri:      evex.512.66.0f3a.w1 1b /r ib      ] AVX512,FUTURE */
        /* 250(f3 fd 48) 300 001(1b) 101 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VEXTRACTF64X4, 3, {YMMREG,ZMMREG,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18523, 545},
    /*   1 : VEXTRACTF64X4 mem256|mask,zmmreg,imm8 [mri:t4:   evex.512.66.0f3a.w1 1b /r ib      ] AVX512,FUTURE */
        /* 250(f3 fd 48) 312 001(1b) 101 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VEXTRACTF64X4, 3, {MEMORY|BITS256,ZMMREG,IMM_NORMAL|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+18533, 545},
};

static const struct itemplate instrux_VEXTRACTI32X4[4] = {
    /*   0 : VEXTRACTI32X4 xmmreg|mask|z,ymmreg,imm8 [mri:      evex.256.66.0f3a.w0 39 /r ib      ] AVX512,AVX512VL,FUTURE */
        /* 250(f3 7d 28) 300 001(39) 101 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VEXTRACTI32X4, 3, {XMMREG,YMMREG,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18543, 544},
    /*   1 : VEXTRACTI32X4 xmmreg|mask|z,zmmreg,imm8 [mri:      evex.512.66.0f3a.w0 39 /r ib      ] AVX512,FUTURE */
        /* 250(f3 7d 48) 300 001(39) 101 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VEXTRACTI32X4, 3, {XMMREG,ZMMREG,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18553, 545},
    /*   2 : VEXTRACTI32X4 mem128|mask,ymmreg,imm8 [mri:t4:   evex.256.66.0f3a.w0 39 /r ib      ] AVX512,AVX512VL,FUTURE */
        /* 250(f3 7d 28) 312 001(39) 101 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VEXTRACTI32X4, 3, {MEMORY|BITS128,YMMREG,IMM_NORMAL|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+18563, 544},
    /*   3 : VEXTRACTI32X4 mem128|mask,zmmreg,imm8 [mri:t4:   evex.512.66.0f3a.w0 39 /r ib      ] AVX512,FUTURE */
        /* 250(f3 7d 48) 312 001(39) 101 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VEXTRACTI32X4, 3, {MEMORY|BITS128,ZMMREG,IMM_NORMAL|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+18573, 545},
};

static const struct itemplate instrux_VEXTRACTI32X8[2] = {
    /*   0 : VEXTRACTI32X8 ymmreg|mask|z,zmmreg,imm8 [mri:      evex.512.66.0f3a.w0 3b /r ib      ] AVX512DQ,FUTURE */
        /* 250(f3 7d 48) 300 001(3b) 101 022 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VEXTRACTI32X8, 3, {YMMREG,ZMMREG,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18583, 548},
    /*   1 : VEXTRACTI32X8 mem256|mask,zmmreg,imm8 [mri:t8:   evex.512.66.0f3a.w0 3b /r ib      ] AVX512DQ,FUTURE */
        /* 250(f3 7d 48) 313 001(3b) 101 022 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VEXTRACTI32X8, 3, {MEMORY|BITS256,ZMMREG,IMM_NORMAL|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+18593, 548},
};

static const struct itemplate instrux_VEXTRACTI64X2[4] = {
    /*   0 : VEXTRACTI64X2 xmmreg|mask|z,ymmreg,imm8 [mri:      evex.256.66.0f3a.w1 39 /r ib      ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f3 fd 28) 300 001(39) 101 022 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VEXTRACTI64X2, 3, {XMMREG,YMMREG,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18603, 547},
    /*   1 : VEXTRACTI64X2 xmmreg|mask|z,zmmreg,imm8 [mri:      evex.512.66.0f3a.w1 39 /r ib      ] AVX512DQ,FUTURE */
        /* 250(f3 fd 48) 300 001(39) 101 022 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VEXTRACTI64X2, 3, {XMMREG,ZMMREG,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18613, 548},
    /*   2 : VEXTRACTI64X2 mem128|mask,ymmreg,imm8 [mri:t2:   evex.256.66.0f3a.w1 39 /r ib      ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f3 fd 28) 311 001(39) 101 022 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VEXTRACTI64X2, 3, {MEMORY|BITS128,YMMREG,IMM_NORMAL|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+18623, 547},
    /*   3 : VEXTRACTI64X2 mem128|mask,zmmreg,imm8 [mri:t2:   evex.512.66.0f3a.w1 39 /r ib      ] AVX512DQ,FUTURE */
        /* 250(f3 fd 48) 311 001(39) 101 022 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VEXTRACTI64X2, 3, {MEMORY|BITS128,ZMMREG,IMM_NORMAL|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+18633, 548},
};

static const struct itemplate instrux_VEXTRACTI64X4[2] = {
    /*   0 : VEXTRACTI64X4 ymmreg|mask|z,zmmreg,imm8 [mri:      evex.512.66.0f3a.w1 3b /r ib      ] AVX512,FUTURE */
        /* 250(f3 fd 48) 300 001(3b) 101 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VEXTRACTI64X4, 3, {YMMREG,ZMMREG,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18643, 545},
    /*   1 : VEXTRACTI64X4 mem256|mask,zmmreg,imm8 [mri:t4:   evex.512.66.0f3a.w1 3b /r ib      ] AVX512,FUTURE */
        /* 250(f3 fd 48) 312 001(3b) 101 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VEXTRACTI64X4, 3, {MEMORY|BITS256,ZMMREG,IMM_NORMAL|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+18653, 545},
};

static const struct itemplate instrux_VFIXUPIMMPD[6] = {
    /*   0 : VFIXUPIMMPD xmmreg|mask|z,xmmreg*,xmmrm128|b64,imm8 [rvmi:fv:  evex.nds.128.66.0f3a.w1 54 /r ib  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 08) 301 001(54) 120 023 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFIXUPIMMPD, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18673, 544},
    /*   1 : VFIXUPIMMPD xmmreg|mask|z,xmmrm128|b64,imm8 [r+vmi:fv:  evex.nds.128.66.0f3a.w1 54 /r ib  ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f3 fd 08) 301 001(54) 110 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFIXUPIMMPD, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+18683, 544},
    /*   2 : VFIXUPIMMPD ymmreg|mask|z,ymmreg*,ymmrm256|b64,imm8 [rvmi:fv:  evex.nds.256.66.0f3a.w1 54 /r ib  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 28) 301 001(54) 120 023 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFIXUPIMMPD, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18693, 544},
    /*   3 : VFIXUPIMMPD ymmreg|mask|z,ymmrm256|b64,imm8 [r+vmi:fv:  evex.nds.256.66.0f3a.w1 54 /r ib  ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f3 fd 28) 301 001(54) 110 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFIXUPIMMPD, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+18703, 544},
    /*   4 : VFIXUPIMMPD zmmreg|mask|z,zmmreg*,zmmrm512|b64|sae,imm8 [rvmi:fv:  evex.nds.512.66.0f3a.w1 54 /r ib  ] AVX512,FUTURE */
        /* 241(f3 fd 48) 301 001(54) 120 023 : EVEX,PROT,AVX512,FUTURE */
        {I_VFIXUPIMMPD, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B64|SAE,0,0}, nasm_bytecodes+18713, 545},
    /*   5 : VFIXUPIMMPD zmmreg|mask|z,zmmrm512|b64|sae,imm8 [r+vmi:fv:  evex.nds.512.66.0f3a.w1 54 /r ib  ] ND,AVX512,FUTURE */
        /* 240(f3 fd 48) 301 001(54) 110 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VFIXUPIMMPD, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+18723, 545},
};

static const struct itemplate instrux_VFIXUPIMMPS[6] = {
    /*   0 : VFIXUPIMMPS xmmreg|mask|z,xmmreg*,xmmrm128|b32,imm8 [rvmi:fv:  evex.nds.128.66.0f3a.w0 54 /r ib  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 08) 301 001(54) 120 023 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFIXUPIMMPS, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18733, 544},
    /*   1 : VFIXUPIMMPS xmmreg|mask|z,xmmrm128|b32,imm8 [r+vmi:fv:  evex.nds.128.66.0f3a.w0 54 /r ib  ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f3 7d 08) 301 001(54) 110 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFIXUPIMMPS, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+18743, 544},
    /*   2 : VFIXUPIMMPS ymmreg|mask|z,ymmreg*,ymmrm256|b32,imm8 [rvmi:fv:  evex.nds.256.66.0f3a.w0 54 /r ib  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 28) 301 001(54) 120 023 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFIXUPIMMPS, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18753, 544},
    /*   3 : VFIXUPIMMPS ymmreg|mask|z,ymmrm256|b32,imm8 [r+vmi:fv:  evex.nds.256.66.0f3a.w0 54 /r ib  ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f3 7d 28) 301 001(54) 110 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VFIXUPIMMPS, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+18763, 544},
    /*   4 : VFIXUPIMMPS zmmreg|mask|z,zmmreg*,zmmrm512|b32|sae,imm8 [rvmi:fv:  evex.nds.512.66.0f3a.w0 54 /r ib  ] AVX512,FUTURE */
        /* 241(f3 7d 48) 301 001(54) 120 023 : EVEX,PROT,AVX512,FUTURE */
        {I_VFIXUPIMMPS, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B32|SAE,0,0}, nasm_bytecodes+18773, 545},
    /*   5 : VFIXUPIMMPS zmmreg|mask|z,zmmrm512|b32|sae,imm8 [r+vmi:fv:  evex.nds.512.66.0f3a.w0 54 /r ib  ] ND,AVX512,FUTURE */
        /* 240(f3 7d 48) 301 001(54) 110 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VFIXUPIMMPS, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+18783, 545},
};

static const struct itemplate instrux_VFIXUPIMMSD[2] = {
    /*   0 : VFIXUPIMMSD xmmreg|mask|z,xmmreg*,xmmrm64|sae,imm8 [rvmi:t1s: evex.nds.lig.66.0f3a.w1 55 /r ib  ] AVX512,FUTURE */
        /* 241(f3 fd 08) 306 001(55) 120 023 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VFIXUPIMMSD, 4, {XMMREG,XMMREG,RM_XMM|BITS64,IMM_NORMAL|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+18793, 546},
    /*   1 : VFIXUPIMMSD xmmreg|mask|z,xmmrm64|sae,imm8 [r+vmi:t1s: evex.nds.lig.66.0f3a.w1 55 /r ib  ] ND,AVX512,FUTURE */
        /* 240(f3 fd 08) 306 001(55) 110 022 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VFIXUPIMMSD, 3, {XMMREG,RM_XMM|BITS64,IMM_NORMAL|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+18803, 546},
};

static const struct itemplate instrux_VFIXUPIMMSS[2] = {
    /*   0 : VFIXUPIMMSS xmmreg|mask|z,xmmreg*,xmmrm32|sae,imm8 [rvmi:t1s: evex.nds.lig.66.0f3a.w0 55 /r ib  ] AVX512,FUTURE */
        /* 241(f3 7d 08) 306 001(55) 120 023 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VFIXUPIMMSS, 4, {XMMREG,XMMREG,RM_XMM|BITS32,IMM_NORMAL|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+18813, 546},
    /*   1 : VFIXUPIMMSS xmmreg|mask|z,xmmrm32|sae,imm8 [r+vmi:t1s: evex.nds.lig.66.0f3a.w0 55 /r ib  ] ND,AVX512,FUTURE */
        /* 240(f3 7d 08) 306 001(55) 110 022 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VFIXUPIMMSS, 3, {XMMREG,RM_XMM|BITS32,IMM_NORMAL|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+18823, 546},
};

static const struct itemplate instrux_VFPCLASSPD[3] = {
    /*   0 : VFPCLASSPD kreg|mask,xmmrm128|b64,imm8 [rmi:fv:   evex.128.66.0f3a.w1 66 /r ib      ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f3 fd 08) 301 001(66) 110 022 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VFPCLASSPD, 3, {OPMASKREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK,B64,0,0,0}, nasm_bytecodes+18833, 547},
    /*   1 : VFPCLASSPD kreg|mask,ymmrm256|b64,imm8 [rmi:fv:   evex.256.66.0f3a.w1 66 /r ib      ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f3 fd 28) 301 001(66) 110 022 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VFPCLASSPD, 3, {OPMASKREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK,B64,0,0,0}, nasm_bytecodes+18843, 547},
    /*   2 : VFPCLASSPD kreg|mask,zmmrm512|b64,imm8 [rmi:fv:   evex.512.66.0f3a.w1 66 /r ib      ] AVX512DQ,FUTURE */
        /* 250(f3 fd 48) 301 001(66) 110 022 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VFPCLASSPD, 3, {OPMASKREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK,B64,0,0,0}, nasm_bytecodes+18853, 548},
};

static const struct itemplate instrux_VFPCLASSPS[3] = {
    /*   0 : VFPCLASSPS kreg|mask,xmmrm128|b32,imm8 [rmi:fv:   evex.128.66.0f3a.w0 66 /r ib      ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f3 7d 08) 301 001(66) 110 022 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VFPCLASSPS, 3, {OPMASKREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK,B32,0,0,0}, nasm_bytecodes+18863, 547},
    /*   1 : VFPCLASSPS kreg|mask,ymmrm256|b32,imm8 [rmi:fv:   evex.256.66.0f3a.w0 66 /r ib      ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f3 7d 28) 301 001(66) 110 022 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VFPCLASSPS, 3, {OPMASKREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK,B32,0,0,0}, nasm_bytecodes+18873, 547},
    /*   2 : VFPCLASSPS kreg|mask,zmmrm512|b32,imm8 [rmi:fv:   evex.512.66.0f3a.w0 66 /r ib      ] AVX512DQ,FUTURE */
        /* 250(f3 7d 48) 301 001(66) 110 022 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VFPCLASSPS, 3, {OPMASKREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK,B32,0,0,0}, nasm_bytecodes+18883, 548},
};

static const struct itemplate instrux_VFPCLASSSD[1] = {
    /*   0 : VFPCLASSSD kreg|mask,xmmrm64,imm8 [rmi:t1s:  evex.lig.66.0f3a.w1 67 /r ib      ] AVX512DQ,FUTURE */
        /* 250(f3 fd 08) 306 001(67) 110 022 : LIG,EVEX,PROT,AVX512DQ,FUTURE */
        {I_VFPCLASSSD, 3, {OPMASKREG,RM_XMM|BITS64,IMM_NORMAL|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+18893, 554},
};

static const struct itemplate instrux_VFPCLASSSS[1] = {
    /*   0 : VFPCLASSSS kreg|mask,xmmrm32,imm8 [rmi:t1s:  evex.lig.66.0f3a.w0 67 /r ib      ] AVX512DQ,FUTURE */
        /* 250(f3 7d 08) 306 001(67) 110 022 : LIG,EVEX,PROT,AVX512DQ,FUTURE */
        {I_VFPCLASSSS, 3, {OPMASKREG,RM_XMM|BITS32,IMM_NORMAL|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+18903, 554},
};

static const struct itemplate instrux_VGATHERPF0DPD[1] = {
    /*   0 : VGATHERPF0DPD ymem64|mask [m:t1s:    vsiby evex.512.66.0f38.w1 c6 /1   ] AVX512PF,FUTURE */
        /* 375 250(f2 fd 48) 306 001(c6) 201 : EVEX,PROT,AVX512PF,FUTURE */
        {I_VGATHERPF0DPD, 1, {YMEM|BITS64,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+18973, 555},
};

static const struct itemplate instrux_VGATHERPF0DPS[1] = {
    /*   0 : VGATHERPF0DPS zmem32|mask [m:t1s:    vsibz evex.512.66.0f38.w0 c6 /1   ] AVX512PF,FUTURE */
        /* 376 250(f2 7d 48) 306 001(c6) 201 : EVEX,PROT,AVX512PF,FUTURE */
        {I_VGATHERPF0DPS, 1, {ZMEM|BITS32,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+18983, 555},
};

static const struct itemplate instrux_VGATHERPF0QPD[1] = {
    /*   0 : VGATHERPF0QPD zmem64|mask [m:t1s:    vsibz evex.512.66.0f38.w1 c7 /1   ] AVX512PF,FUTURE */
        /* 376 250(f2 fd 48) 306 001(c7) 201 : EVEX,PROT,AVX512PF,FUTURE */
        {I_VGATHERPF0QPD, 1, {ZMEM|BITS64,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+18993, 555},
};

static const struct itemplate instrux_VGATHERPF0QPS[1] = {
    /*   0 : VGATHERPF0QPS zmem32|mask [m:t1s:    vsibz evex.512.66.0f38.w0 c7 /1   ] AVX512PF,FUTURE */
        /* 376 250(f2 7d 48) 306 001(c7) 201 : EVEX,PROT,AVX512PF,FUTURE */
        {I_VGATHERPF0QPS, 1, {ZMEM|BITS32,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+19003, 555},
};

static const struct itemplate instrux_VGATHERPF1DPD[1] = {
    /*   0 : VGATHERPF1DPD ymem64|mask [m:t1s:    vsiby evex.512.66.0f38.w1 c6 /2   ] AVX512PF,FUTURE */
        /* 375 250(f2 fd 48) 306 001(c6) 202 : EVEX,PROT,AVX512PF,FUTURE */
        {I_VGATHERPF1DPD, 1, {YMEM|BITS64,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+19013, 555},
};

static const struct itemplate instrux_VGATHERPF1DPS[1] = {
    /*   0 : VGATHERPF1DPS zmem32|mask [m:t1s:    vsibz evex.512.66.0f38.w0 c6 /2   ] AVX512PF,FUTURE */
        /* 376 250(f2 7d 48) 306 001(c6) 202 : EVEX,PROT,AVX512PF,FUTURE */
        {I_VGATHERPF1DPS, 1, {ZMEM|BITS32,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+19023, 555},
};

static const struct itemplate instrux_VGATHERPF1QPD[1] = {
    /*   0 : VGATHERPF1QPD zmem64|mask [m:t1s:    vsibz evex.512.66.0f38.w1 c7 /2   ] AVX512PF,FUTURE */
        /* 376 250(f2 fd 48) 306 001(c7) 202 : EVEX,PROT,AVX512PF,FUTURE */
        {I_VGATHERPF1QPD, 1, {ZMEM|BITS64,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+19033, 555},
};

static const struct itemplate instrux_VGATHERPF1QPS[1] = {
    /*   0 : VGATHERPF1QPS zmem32|mask [m:t1s:    vsibz evex.512.66.0f38.w0 c7 /2   ] AVX512PF,FUTURE */
        /* 376 250(f2 7d 48) 306 001(c7) 202 : EVEX,PROT,AVX512PF,FUTURE */
        {I_VGATHERPF1QPS, 1, {ZMEM|BITS32,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+19043, 555},
};

static const struct itemplate instrux_VGETEXPPD[3] = {
    /*   0 : VGETEXPPD xmmreg|mask|z,xmmrm128|b64 [rm:fv:    evex.128.66.0f38.w1 42 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 fd 08) 301 001(42) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VGETEXPPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+33642, 544},
    /*   1 : VGETEXPPD ymmreg|mask|z,ymmrm256|b64 [rm:fv:    evex.256.66.0f38.w1 42 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 fd 28) 301 001(42) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VGETEXPPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+33651, 544},
    /*   2 : VGETEXPPD zmmreg|mask|z,zmmrm512|b64|sae [rm:fv:    evex.512.66.0f38.w1 42 /r         ] AVX512,FUTURE */
        /* 250(f2 fd 48) 301 001(42) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VGETEXPPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+33660, 545},
};

static const struct itemplate instrux_VGETEXPPS[3] = {
    /*   0 : VGETEXPPS xmmreg|mask|z,xmmrm128|b32 [rm:fv:    evex.128.66.0f38.w0 42 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 08) 301 001(42) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VGETEXPPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+33669, 544},
    /*   1 : VGETEXPPS ymmreg|mask|z,ymmrm256|b32 [rm:fv:    evex.256.66.0f38.w0 42 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 28) 301 001(42) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VGETEXPPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+33678, 544},
    /*   2 : VGETEXPPS zmmreg|mask|z,zmmrm512|b32|sae [rm:fv:    evex.512.66.0f38.w0 42 /r         ] AVX512,FUTURE */
        /* 250(f2 7d 48) 301 001(42) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VGETEXPPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+33687, 545},
};

static const struct itemplate instrux_VGETEXPSD[1] = {
    /*   0 : VGETEXPSD xmmreg|mask|z,xmmreg,xmmrm64|sae [rvm:t1s:  evex.nds.lig.66.0f38.w1 43 /r     ] AVX512,FUTURE */
        /* 241(f2 fd 08) 306 001(43) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VGETEXPSD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+33696, 546},
};

static const struct itemplate instrux_VGETEXPSS[1] = {
    /*   0 : VGETEXPSS xmmreg|mask|z,xmmreg,xmmrm32|sae [rvm:t1s:  evex.nds.lig.66.0f38.w0 43 /r     ] AVX512,FUTURE */
        /* 241(f2 7d 08) 306 001(43) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VGETEXPSS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+33705, 546},
};

static const struct itemplate instrux_VGETMANTPD[3] = {
    /*   0 : VGETMANTPD xmmreg|mask|z,xmmrm128|b64,imm8 [rmi:fv:   evex.128.66.0f3a.w1 26 /r ib      ] AVX512,AVX512VL,FUTURE */
        /* 250(f3 fd 08) 301 001(26) 110 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VGETMANTPD, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+19113, 544},
    /*   1 : VGETMANTPD ymmreg|mask|z,ymmrm256|b64,imm8 [rmi:fv:   evex.256.66.0f3a.w1 26 /r ib      ] AVX512,AVX512VL,FUTURE */
        /* 250(f3 fd 28) 301 001(26) 110 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VGETMANTPD, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+19123, 544},
    /*   2 : VGETMANTPD zmmreg|mask|z,zmmrm512|b64|sae,imm8 [rmi:fv:   evex.512.66.0f3a.w1 26 /r ib      ] AVX512,FUTURE */
        /* 250(f3 fd 48) 301 001(26) 110 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VGETMANTPD, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+19133, 545},
};

static const struct itemplate instrux_VGETMANTPS[3] = {
    /*   0 : VGETMANTPS xmmreg|mask|z,xmmrm128|b32,imm8 [rmi:fv:   evex.128.66.0f3a.w0 26 /r ib      ] AVX512,AVX512VL,FUTURE */
        /* 250(f3 7d 08) 301 001(26) 110 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VGETMANTPS, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+19143, 544},
    /*   1 : VGETMANTPS ymmreg|mask|z,ymmrm256|b32,imm8 [rmi:fv:   evex.256.66.0f3a.w0 26 /r ib      ] AVX512,AVX512VL,FUTURE */
        /* 250(f3 7d 28) 301 001(26) 110 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VGETMANTPS, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+19153, 544},
    /*   2 : VGETMANTPS zmmreg|mask|z,zmmrm512|b32|sae,imm8 [rmi:fv:   evex.512.66.0f3a.w0 26 /r ib      ] AVX512,FUTURE */
        /* 250(f3 7d 48) 301 001(26) 110 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VGETMANTPS, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+19163, 545},
};

static const struct itemplate instrux_VGETMANTSD[1] = {
    /*   0 : VGETMANTSD xmmreg|mask|z,xmmreg,xmmrm64|sae,imm8 [rvmi:t1s: evex.nds.lig.66.0f3a.w1 27 /r ib  ] AVX512,FUTURE */
        /* 241(f3 fd 08) 306 001(27) 120 023 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VGETMANTSD, 4, {XMMREG,XMMREG,RM_XMM|BITS64,IMM_NORMAL|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+19173, 546},
};

static const struct itemplate instrux_VGETMANTSS[1] = {
    /*   0 : VGETMANTSS xmmreg|mask|z,xmmreg,xmmrm32|sae,imm8 [rvmi:t1s: evex.nds.lig.66.0f3a.w0 27 /r ib  ] AVX512,FUTURE */
        /* 241(f3 7d 08) 306 001(27) 120 023 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VGETMANTSS, 4, {XMMREG,XMMREG,RM_XMM|BITS32,IMM_NORMAL|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+19183, 546},
};

static const struct itemplate instrux_VINSERTF32X4[4] = {
    /*   0 : VINSERTF32X4 ymmreg|mask|z,ymmreg*,xmmrm128,imm8 [rvmi:t4:  evex.nds.256.66.0f3a.w0 18 /r ib  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 28) 312 001(18) 120 023 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VINSERTF32X4, 4, {YMMREG,YMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19193, 544},
    /*   1 : VINSERTF32X4 ymmreg|mask|z,xmmrm128,imm8 [r+vmi:t4:  evex.nds.256.66.0f3a.w0 18 /r ib  ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f3 7d 28) 312 001(18) 110 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VINSERTF32X4, 3, {YMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19203, 544},
    /*   2 : VINSERTF32X4 zmmreg|mask|z,zmmreg*,xmmrm128,imm8 [rvmi:t4:  evex.nds.512.66.0f3a.w0 18 /r ib  ] AVX512,FUTURE */
        /* 241(f3 7d 48) 312 001(18) 120 023 : EVEX,PROT,AVX512,FUTURE */
        {I_VINSERTF32X4, 4, {ZMMREG,ZMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19213, 545},
    /*   3 : VINSERTF32X4 zmmreg|mask|z,xmmrm128,imm8 [r+vmi:t4:  evex.nds.512.66.0f3a.w0 18 /r ib  ] ND,AVX512,FUTURE */
        /* 240(f3 7d 48) 312 001(18) 110 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VINSERTF32X4, 3, {ZMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19223, 545},
};

static const struct itemplate instrux_VINSERTF32X8[2] = {
    /*   0 : VINSERTF32X8 zmmreg|mask|z,zmmreg*,ymmrm256,imm8 [rvmi:t8:  evex.nds.512.66.0f3a.w0 1a /r ib  ] AVX512DQ,FUTURE */
        /* 241(f3 7d 48) 313 001(1a) 120 023 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VINSERTF32X8, 4, {ZMMREG,ZMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19233, 548},
    /*   1 : VINSERTF32X8 zmmreg|mask|z,ymmrm256,imm8 [r+vmi:t8:  evex.nds.512.66.0f3a.w0 1a /r ib  ] ND,AVX512DQ,FUTURE */
        /* 240(f3 7d 48) 313 001(1a) 110 022 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VINSERTF32X8, 3, {ZMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19243, 548},
};

static const struct itemplate instrux_VINSERTF64X2[4] = {
    /*   0 : VINSERTF64X2 ymmreg|mask|z,ymmreg*,xmmrm128,imm8 [rvmi:t2:  evex.nds.256.66.0f3a.w1 18 /r ib  ] AVX512VL,AVX512DQ,FUTURE */
        /* 241(f3 fd 28) 311 001(18) 120 023 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VINSERTF64X2, 4, {YMMREG,YMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19253, 547},
    /*   1 : VINSERTF64X2 ymmreg|mask|z,xmmrm128,imm8 [r+vmi:t2:  evex.nds.256.66.0f3a.w1 18 /r ib  ] ND,AVX512VL,AVX512DQ,FUTURE */
        /* 240(f3 fd 28) 311 001(18) 110 022 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VINSERTF64X2, 3, {YMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19263, 547},
    /*   2 : VINSERTF64X2 zmmreg|mask|z,zmmreg*,xmmrm128,imm8 [rvmi:t2:  evex.nds.512.66.0f3a.w1 18 /r ib  ] AVX512DQ,FUTURE */
        /* 241(f3 fd 48) 311 001(18) 120 023 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VINSERTF64X2, 4, {ZMMREG,ZMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19273, 548},
    /*   3 : VINSERTF64X2 zmmreg|mask|z,xmmrm128,imm8 [r+vmi:t2:  evex.nds.512.66.0f3a.w1 18 /r ib  ] ND,AVX512DQ,FUTURE */
        /* 240(f3 fd 48) 311 001(18) 110 022 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VINSERTF64X2, 3, {ZMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19283, 548},
};

static const struct itemplate instrux_VINSERTF64X4[2] = {
    /*   0 : VINSERTF64X4 zmmreg|mask|z,zmmreg*,ymmrm256,imm8 [rvmi:t4:  evex.nds.512.66.0f3a.w1 1a /r ib  ] AVX512,FUTURE */
        /* 241(f3 fd 48) 312 001(1a) 120 023 : EVEX,PROT,AVX512,FUTURE */
        {I_VINSERTF64X4, 4, {ZMMREG,ZMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19293, 545},
    /*   1 : VINSERTF64X4 zmmreg|mask|z,ymmrm256,imm8 [r+vmi:t4:  evex.nds.512.66.0f3a.w1 1a /r ib  ] ND,AVX512,FUTURE */
        /* 240(f3 fd 48) 312 001(1a) 110 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VINSERTF64X4, 3, {ZMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19303, 545},
};

static const struct itemplate instrux_VINSERTI32X4[4] = {
    /*   0 : VINSERTI32X4 ymmreg|mask|z,ymmreg*,xmmrm128,imm8 [rvmi:t4:  evex.nds.256.66.0f3a.w0 38 /r ib  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 28) 312 001(38) 120 023 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VINSERTI32X4, 4, {YMMREG,YMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19313, 544},
    /*   1 : VINSERTI32X4 ymmreg|mask|z,xmmrm128,imm8 [r+vmi:t4:  evex.nds.256.66.0f3a.w0 38 /r ib  ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f3 7d 28) 312 001(38) 110 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VINSERTI32X4, 3, {YMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19323, 544},
    /*   2 : VINSERTI32X4 zmmreg|mask|z,zmmreg*,xmmrm128,imm8 [rvmi:t4:  evex.nds.512.66.0f3a.w0 38 /r ib  ] AVX512,FUTURE */
        /* 241(f3 7d 48) 312 001(38) 120 023 : EVEX,PROT,AVX512,FUTURE */
        {I_VINSERTI32X4, 4, {ZMMREG,ZMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19333, 545},
    /*   3 : VINSERTI32X4 zmmreg|mask|z,xmmrm128,imm8 [r+vmi:t4:  evex.nds.512.66.0f3a.w0 38 /r ib  ] ND,AVX512,FUTURE */
        /* 240(f3 7d 48) 312 001(38) 110 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VINSERTI32X4, 3, {ZMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19343, 545},
};

static const struct itemplate instrux_VINSERTI32X8[2] = {
    /*   0 : VINSERTI32X8 zmmreg|mask|z,zmmreg*,ymmrm256,imm8 [rvmi:t8:  evex.nds.512.66.0f3a.w0 3a /r ib  ] AVX512DQ,FUTURE */
        /* 241(f3 7d 48) 313 001(3a) 120 023 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VINSERTI32X8, 4, {ZMMREG,ZMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19353, 548},
    /*   1 : VINSERTI32X8 zmmreg|mask|z,ymmrm256,imm8 [r+vmi:t8:  evex.nds.512.66.0f3a.w0 3a /r ib  ] ND,AVX512DQ,FUTURE */
        /* 240(f3 7d 48) 313 001(3a) 110 022 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VINSERTI32X8, 3, {ZMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19363, 548},
};

static const struct itemplate instrux_VINSERTI64X2[4] = {
    /*   0 : VINSERTI64X2 ymmreg|mask|z,ymmreg*,xmmrm128,imm8 [rvmi:t2:  evex.nds.256.66.0f3a.w1 38 /r ib  ] AVX512VL,AVX512DQ,FUTURE */
        /* 241(f3 fd 28) 311 001(38) 120 023 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VINSERTI64X2, 4, {YMMREG,YMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19373, 547},
    /*   1 : VINSERTI64X2 ymmreg|mask|z,xmmrm128,imm8 [r+vmi:t2:  evex.nds.256.66.0f3a.w1 38 /r ib  ] ND,AVX512VL,AVX512DQ,FUTURE */
        /* 240(f3 fd 28) 311 001(38) 110 022 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VINSERTI64X2, 3, {YMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19383, 547},
    /*   2 : VINSERTI64X2 zmmreg|mask|z,zmmreg*,xmmrm128,imm8 [rvmi:t2:  evex.nds.512.66.0f3a.w1 38 /r ib  ] AVX512DQ,FUTURE */
        /* 241(f3 fd 48) 311 001(38) 120 023 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VINSERTI64X2, 4, {ZMMREG,ZMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19393, 548},
    /*   3 : VINSERTI64X2 zmmreg|mask|z,xmmrm128,imm8 [r+vmi:t2:  evex.nds.512.66.0f3a.w1 38 /r ib  ] ND,AVX512DQ,FUTURE */
        /* 240(f3 fd 48) 311 001(38) 110 022 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VINSERTI64X2, 3, {ZMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19403, 548},
};

static const struct itemplate instrux_VINSERTI64X4[2] = {
    /*   0 : VINSERTI64X4 zmmreg|mask|z,zmmreg*,ymmrm256,imm8 [rvmi:t4:  evex.nds.512.66.0f3a.w1 3a /r ib  ] AVX512,FUTURE */
        /* 241(f3 fd 48) 312 001(3a) 120 023 : EVEX,PROT,AVX512,FUTURE */
        {I_VINSERTI64X4, 4, {ZMMREG,ZMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19413, 545},
    /*   1 : VINSERTI64X4 zmmreg|mask|z,ymmrm256,imm8 [r+vmi:t4:  evex.nds.512.66.0f3a.w1 3a /r ib  ] ND,AVX512,FUTURE */
        /* 240(f3 fd 48) 312 001(3a) 110 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VINSERTI64X4, 3, {ZMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19423, 545},
};

static const struct itemplate instrux_VMOVDQA32[6] = {
    /*   0 : VMOVDQA32 xmmreg|mask|z,xmmrm128 [rm:fvm:   evex.128.66.0f.w0 6f /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7d 08) 303 001(6f) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVDQA32, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34209, 544},
    /*   1 : VMOVDQA32 ymmreg|mask|z,ymmrm256 [rm:fvm:   evex.256.66.0f.w0 6f /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7d 28) 303 001(6f) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVDQA32, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34218, 544},
    /*   2 : VMOVDQA32 zmmreg|mask|z,zmmrm512 [rm:fvm:   evex.512.66.0f.w0 6f /r           ] AVX512,FUTURE */
        /* 250(f1 7d 48) 303 001(6f) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVDQA32, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34227, 545},
    /*   3 : VMOVDQA32 xmmrm128|mask|z,xmmreg [mr:fvm:   evex.128.66.0f.w0 7f /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7d 08) 303 001(7f) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVDQA32, 2, {RM_XMM|BITS128,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34236, 544},
    /*   4 : VMOVDQA32 ymmrm256|mask|z,ymmreg [mr:fvm:   evex.256.66.0f.w0 7f /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7d 28) 303 001(7f) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVDQA32, 2, {RM_YMM|BITS256,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34245, 544},
    /*   5 : VMOVDQA32 zmmrm512|mask|z,zmmreg [mr:fvm:   evex.512.66.0f.w0 7f /r           ] AVX512,FUTURE */
        /* 250(f1 7d 48) 303 001(7f) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVDQA32, 2, {RM_ZMM|BITS512,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34254, 545},
};

static const struct itemplate instrux_VMOVDQA64[6] = {
    /*   0 : VMOVDQA64 xmmreg|mask|z,xmmrm128 [rm:fvm:   evex.128.66.0f.w1 6f /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 fd 08) 303 001(6f) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVDQA64, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34263, 544},
    /*   1 : VMOVDQA64 ymmreg|mask|z,ymmrm256 [rm:fvm:   evex.256.66.0f.w1 6f /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 fd 28) 303 001(6f) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVDQA64, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34272, 544},
    /*   2 : VMOVDQA64 zmmreg|mask|z,zmmrm512 [rm:fvm:   evex.512.66.0f.w1 6f /r           ] AVX512,FUTURE */
        /* 250(f1 fd 48) 303 001(6f) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVDQA64, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34281, 545},
    /*   3 : VMOVDQA64 xmmrm128|mask|z,xmmreg [mr:fvm:   evex.128.66.0f.w1 7f /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 fd 08) 303 001(7f) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVDQA64, 2, {RM_XMM|BITS128,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34290, 544},
    /*   4 : VMOVDQA64 ymmrm256|mask|z,ymmreg [mr:fvm:   evex.256.66.0f.w1 7f /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 fd 28) 303 001(7f) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVDQA64, 2, {RM_YMM|BITS256,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34299, 544},
    /*   5 : VMOVDQA64 zmmrm512|mask|z,zmmreg [mr:fvm:   evex.512.66.0f.w1 7f /r           ] AVX512,FUTURE */
        /* 250(f1 fd 48) 303 001(7f) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVDQA64, 2, {RM_ZMM|BITS512,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34308, 545},
};

static const struct itemplate instrux_VMOVDQU16[6] = {
    /*   0 : VMOVDQU16 xmmreg|mask|z,xmmrm128 [rm:fvm:   evex.128.f2.0f.w1 6f /r           ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f1 ff 08) 303 001(6f) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VMOVDQU16, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34317, 550},
    /*   1 : VMOVDQU16 ymmreg|mask|z,ymmrm256 [rm:fvm:   evex.256.f2.0f.w1 6f /r           ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f1 ff 28) 303 001(6f) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VMOVDQU16, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34326, 550},
    /*   2 : VMOVDQU16 zmmreg|mask|z,zmmrm512 [rm:fvm:   evex.512.f2.0f.w1 6f /r           ] AVX512BW,FUTURE */
        /* 250(f1 ff 48) 303 001(6f) 110 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VMOVDQU16, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34335, 551},
    /*   3 : VMOVDQU16 xmmrm128|mask|z,xmmreg [mr:fvm:   evex.128.f2.0f.w1 7f /r           ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f1 ff 08) 303 001(7f) 101 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VMOVDQU16, 2, {RM_XMM|BITS128,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34344, 550},
    /*   4 : VMOVDQU16 ymmrm256|mask|z,ymmreg [mr:fvm:   evex.256.f2.0f.w1 7f /r           ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f1 ff 28) 303 001(7f) 101 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VMOVDQU16, 2, {RM_YMM|BITS256,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34353, 550},
    /*   5 : VMOVDQU16 zmmrm512|mask|z,zmmreg [mr:fvm:   evex.512.f2.0f.w1 7f /r           ] AVX512BW,FUTURE */
        /* 250(f1 ff 48) 303 001(7f) 101 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VMOVDQU16, 2, {RM_ZMM|BITS512,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34362, 551},
};

static const struct itemplate instrux_VMOVDQU32[6] = {
    /*   0 : VMOVDQU32 xmmreg|mask|z,xmmrm128 [rm:fvm:   evex.128.f3.0f.w0 6f /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7e 08) 303 001(6f) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVDQU32, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34371, 544},
    /*   1 : VMOVDQU32 ymmreg|mask|z,ymmrm256 [rm:fvm:   evex.256.f3.0f.w0 6f /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7e 28) 303 001(6f) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVDQU32, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34380, 544},
    /*   2 : VMOVDQU32 zmmreg|mask|z,zmmrm512 [rm:fvm:   evex.512.f3.0f.w0 6f /r           ] AVX512,FUTURE */
        /* 250(f1 7e 48) 303 001(6f) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVDQU32, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34389, 545},
    /*   3 : VMOVDQU32 xmmrm128|mask|z,xmmreg [mr:fvm:   evex.128.f3.0f.w0 7f /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7e 08) 303 001(7f) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVDQU32, 2, {RM_XMM|BITS128,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34398, 544},
    /*   4 : VMOVDQU32 ymmrm256|mask|z,ymmreg [mr:fvm:   evex.256.f3.0f.w0 7f /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 7e 28) 303 001(7f) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVDQU32, 2, {RM_YMM|BITS256,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34407, 544},
    /*   5 : VMOVDQU32 zmmrm512|mask|z,zmmreg [mr:fvm:   evex.512.f3.0f.w0 7f /r           ] AVX512,FUTURE */
        /* 250(f1 7e 48) 303 001(7f) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVDQU32, 2, {RM_ZMM|BITS512,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34416, 545},
};

static const struct itemplate instrux_VMOVDQU64[6] = {
    /*   0 : VMOVDQU64 xmmreg|mask|z,xmmrm128 [rm:fvm:   evex.128.f3.0f.w1 6f /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 fe 08) 303 001(6f) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVDQU64, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34425, 544},
    /*   1 : VMOVDQU64 ymmreg|mask|z,ymmrm256 [rm:fvm:   evex.256.f3.0f.w1 6f /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 fe 28) 303 001(6f) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVDQU64, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34434, 544},
    /*   2 : VMOVDQU64 zmmreg|mask|z,zmmrm512 [rm:fvm:   evex.512.f3.0f.w1 6f /r           ] AVX512,FUTURE */
        /* 250(f1 fe 48) 303 001(6f) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVDQU64, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34443, 545},
    /*   3 : VMOVDQU64 xmmrm128|mask|z,xmmreg [mr:fvm:   evex.128.f3.0f.w1 7f /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 fe 08) 303 001(7f) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVDQU64, 2, {RM_XMM|BITS128,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34452, 544},
    /*   4 : VMOVDQU64 ymmrm256|mask|z,ymmreg [mr:fvm:   evex.256.f3.0f.w1 7f /r           ] AVX512,AVX512VL,FUTURE */
        /* 250(f1 fe 28) 303 001(7f) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VMOVDQU64, 2, {RM_YMM|BITS256,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34461, 544},
    /*   5 : VMOVDQU64 zmmrm512|mask|z,zmmreg [mr:fvm:   evex.512.f3.0f.w1 7f /r           ] AVX512,FUTURE */
        /* 250(f1 fe 48) 303 001(7f) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VMOVDQU64, 2, {RM_ZMM|BITS512,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34470, 545},
};

static const struct itemplate instrux_VMOVDQU8[6] = {
    /*   0 : VMOVDQU8 xmmreg|mask|z,xmmrm128 [rm:fvm:   evex.128.f2.0f.w0 6f /r           ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f1 7f 08) 303 001(6f) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VMOVDQU8, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34479, 550},
    /*   1 : VMOVDQU8 ymmreg|mask|z,ymmrm256 [rm:fvm:   evex.256.f2.0f.w0 6f /r           ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f1 7f 28) 303 001(6f) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VMOVDQU8, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34488, 550},
    /*   2 : VMOVDQU8 zmmreg|mask|z,zmmrm512 [rm:fvm:   evex.512.f2.0f.w0 6f /r           ] AVX512BW,FUTURE */
        /* 250(f1 7f 48) 303 001(6f) 110 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VMOVDQU8, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34497, 551},
    /*   3 : VMOVDQU8 xmmrm128|mask|z,xmmreg [mr:fvm:   evex.128.f2.0f.w0 7f /r           ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f1 7f 08) 303 001(7f) 101 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VMOVDQU8, 2, {RM_XMM|BITS128,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34506, 550},
    /*   4 : VMOVDQU8 ymmrm256|mask|z,ymmreg [mr:fvm:   evex.256.f2.0f.w0 7f /r           ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f1 7f 28) 303 001(7f) 101 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VMOVDQU8, 2, {RM_YMM|BITS256,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34515, 550},
    /*   5 : VMOVDQU8 zmmrm512|mask|z,zmmreg [mr:fvm:   evex.512.f2.0f.w0 7f /r           ] AVX512BW,FUTURE */
        /* 250(f1 7f 48) 303 001(7f) 101 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VMOVDQU8, 2, {RM_ZMM|BITS512,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+34524, 551},
};

static const struct itemplate instrux_VPABSQ[3] = {
    /*   0 : VPABSQ xmmreg|mask|z,xmmrm128|b64 [rm:fv:    evex.128.66.0f38.w1 1f /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 fd 08) 301 001(1f) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPABSQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+35451, 544},
    /*   1 : VPABSQ ymmreg|mask|z,ymmrm256|b64 [rm:fv:    evex.256.66.0f38.w1 1f /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 fd 28) 301 001(1f) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPABSQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+35460, 544},
    /*   2 : VPABSQ zmmreg|mask|z,zmmrm512|b64 [rm:fv:    evex.512.66.0f38.w1 1f /r         ] AVX512,FUTURE */
        /* 250(f2 fd 48) 301 001(1f) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPABSQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+35469, 545},
};

static const struct itemplate instrux_VPANDD[6] = {
    /*   0 : VPANDD xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f.w0 db /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7d 08) 301 001(db) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPANDD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+36153, 544},
    /*   1 : VPANDD xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.nds.128.66.0f.w0 db /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 08) 301 001(db) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPANDD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+36162, 544},
    /*   2 : VPANDD ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f.w0 db /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7d 28) 301 001(db) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPANDD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+36171, 544},
    /*   3 : VPANDD ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.nds.256.66.0f.w0 db /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 28) 301 001(db) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPANDD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+36180, 544},
    /*   4 : VPANDD zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv:   evex.nds.512.66.0f.w0 db /r       ] AVX512,FUTURE */
        /* 241(f1 7d 48) 301 001(db) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPANDD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+36189, 545},
    /*   5 : VPANDD zmmreg|mask|z,zmmrm512|b32 [r+vm:fv:   evex.nds.512.66.0f.w0 db /r       ] ND,AVX512,FUTURE */
        /* 240(f1 7d 48) 301 001(db) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPANDD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+36198, 545},
};

static const struct itemplate instrux_VPANDND[6] = {
    /*   0 : VPANDND xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f.w0 df /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7d 08) 301 001(df) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPANDND, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+36207, 544},
    /*   1 : VPANDND xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.nds.128.66.0f.w0 df /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 08) 301 001(df) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPANDND, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+36216, 544},
    /*   2 : VPANDND ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f.w0 df /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7d 28) 301 001(df) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPANDND, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+36225, 544},
    /*   3 : VPANDND ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.nds.256.66.0f.w0 df /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 28) 301 001(df) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPANDND, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+36234, 544},
    /*   4 : VPANDND zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv:   evex.nds.512.66.0f.w0 df /r       ] AVX512,FUTURE */
        /* 241(f1 7d 48) 301 001(df) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPANDND, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+36243, 545},
    /*   5 : VPANDND zmmreg|mask|z,zmmrm512|b32 [r+vm:fv:   evex.nds.512.66.0f.w0 df /r       ] ND,AVX512,FUTURE */
        /* 240(f1 7d 48) 301 001(df) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPANDND, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+36252, 545},
};

static const struct itemplate instrux_VPANDNQ[6] = {
    /*   0 : VPANDNQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f.w1 df /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(df) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPANDNQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+36261, 544},
    /*   1 : VPANDNQ xmmreg|mask|z,xmmrm128|b64 [r+vm:fv:   evex.nds.128.66.0f.w1 df /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 08) 301 001(df) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPANDNQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+36270, 544},
    /*   2 : VPANDNQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f.w1 df /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(df) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPANDNQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+36279, 544},
    /*   3 : VPANDNQ ymmreg|mask|z,ymmrm256|b64 [r+vm:fv:   evex.nds.256.66.0f.w1 df /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 28) 301 001(df) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPANDNQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+36288, 544},
    /*   4 : VPANDNQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv:   evex.nds.512.66.0f.w1 df /r       ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(df) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPANDNQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+36297, 545},
    /*   5 : VPANDNQ zmmreg|mask|z,zmmrm512|b64 [r+vm:fv:   evex.nds.512.66.0f.w1 df /r       ] ND,AVX512,FUTURE */
        /* 240(f1 fd 48) 301 001(df) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPANDNQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+36306, 545},
};

static const struct itemplate instrux_VPANDQ[6] = {
    /*   0 : VPANDQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f.w1 db /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(db) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPANDQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+36315, 544},
    /*   1 : VPANDQ xmmreg|mask|z,xmmrm128|b64 [r+vm:fv:   evex.nds.128.66.0f.w1 db /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 08) 301 001(db) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPANDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+36324, 544},
    /*   2 : VPANDQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f.w1 db /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(db) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPANDQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+36333, 544},
    /*   3 : VPANDQ ymmreg|mask|z,ymmrm256|b64 [r+vm:fv:   evex.nds.256.66.0f.w1 db /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 28) 301 001(db) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPANDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+36342, 544},
    /*   4 : VPANDQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv:   evex.nds.512.66.0f.w1 db /r       ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(db) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPANDQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+36351, 545},
    /*   5 : VPANDQ zmmreg|mask|z,zmmrm512|b64 [r+vm:fv:   evex.nds.512.66.0f.w1 db /r       ] ND,AVX512,FUTURE */
        /* 240(f1 fd 48) 301 001(db) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPANDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+36360, 545},
};

static const struct itemplate instrux_VPBLENDMB[3] = {
    /*   0 : VPBLENDMB xmmreg|mask|z,xmmreg,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f38.w0 66 /r     ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f2 7d 08) 303 001(66) 120 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPBLENDMB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36477, 550},
    /*   1 : VPBLENDMB ymmreg|mask|z,ymmreg,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f38.w0 66 /r     ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f2 7d 28) 303 001(66) 120 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPBLENDMB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36486, 550},
    /*   2 : VPBLENDMB zmmreg|mask|z,zmmreg,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f38.w0 66 /r     ] AVX512BW,FUTURE */
        /* 241(f2 7d 48) 303 001(66) 120 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPBLENDMB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36495, 551},
};

static const struct itemplate instrux_VPBLENDMD[3] = {
    /*   0 : VPBLENDMD xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f38.w0 64 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 08) 301 001(64) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPBLENDMD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+36504, 544},
    /*   1 : VPBLENDMD ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f38.w0 64 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 28) 301 001(64) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPBLENDMD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+36513, 544},
    /*   2 : VPBLENDMD zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv:   evex.nds.512.66.0f38.w0 64 /r     ] AVX512,FUTURE */
        /* 241(f2 7d 48) 301 001(64) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPBLENDMD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+36522, 545},
};

static const struct itemplate instrux_VPBLENDMQ[3] = {
    /*   0 : VPBLENDMQ xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 64 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 08) 301 001(64) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPBLENDMQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+36531, 544},
    /*   1 : VPBLENDMQ ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 64 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 28) 301 001(64) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPBLENDMQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+36540, 544},
    /*   2 : VPBLENDMQ zmmreg|mask|z,zmmreg,zmmrm512|b64 [rvm:fv:   evex.nds.512.66.0f38.w1 64 /r     ] AVX512,FUTURE */
        /* 241(f2 fd 48) 301 001(64) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPBLENDMQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+36549, 545},
};

static const struct itemplate instrux_VPBLENDMW[3] = {
    /*   0 : VPBLENDMW xmmreg|mask|z,xmmreg,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f38.w1 66 /r     ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f2 fd 08) 303 001(66) 120 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPBLENDMW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36558, 550},
    /*   1 : VPBLENDMW ymmreg|mask|z,ymmreg,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f38.w1 66 /r     ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f2 fd 28) 303 001(66) 120 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPBLENDMW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36567, 550},
    /*   2 : VPBLENDMW zmmreg|mask|z,zmmreg,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f38.w1 66 /r     ] AVX512BW,FUTURE */
        /* 241(f2 fd 48) 303 001(66) 120 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPBLENDMW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+36576, 551},
};

static const struct itemplate instrux_VPBROADCASTMB2Q[3] = {
    /*   0 : VPBROADCASTMB2Q xmmreg,kreg [rm:       evex.128.f3.0f38.w1 2a /r         ] AVX512CD,AVX512VL,FUTURE */
        /* 250(f2 fe 08) 300 001(2a) 110 : EVEX,PROT,AVX512CD,AVX512VL,FUTURE */
        {I_VPBROADCASTMB2Q, 2, {XMMREG,OPMASKREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+36720, 558},
    /*   1 : VPBROADCASTMB2Q ymmreg,kreg [rm:       evex.256.f3.0f38.w1 2a /r         ] AVX512CD,AVX512VL,FUTURE */
        /* 250(f2 fe 28) 300 001(2a) 110 : EVEX,PROT,AVX512CD,AVX512VL,FUTURE */
        {I_VPBROADCASTMB2Q, 2, {YMMREG,OPMASKREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+36729, 558},
    /*   2 : VPBROADCASTMB2Q zmmreg,kreg [rm:       evex.512.f3.0f38.w1 2a /r         ] AVX512CD,FUTURE */
        /* 250(f2 fe 48) 300 001(2a) 110 : EVEX,PROT,AVX512CD,FUTURE */
        {I_VPBROADCASTMB2Q, 2, {ZMMREG,OPMASKREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+36738, 559},
};

static const struct itemplate instrux_VPBROADCASTMW2D[3] = {
    /*   0 : VPBROADCASTMW2D xmmreg,kreg [rm:       evex.128.f3.0f38.w0 3a /r         ] AVX512CD,AVX512VL,FUTURE */
        /* 250(f2 7e 08) 300 001(3a) 110 : EVEX,PROT,AVX512CD,AVX512VL,FUTURE */
        {I_VPBROADCASTMW2D, 2, {XMMREG,OPMASKREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+36747, 558},
    /*   1 : VPBROADCASTMW2D ymmreg,kreg [rm:       evex.256.f3.0f38.w0 3a /r         ] AVX512CD,AVX512VL,FUTURE */
        /* 250(f2 7e 28) 300 001(3a) 110 : EVEX,PROT,AVX512CD,AVX512VL,FUTURE */
        {I_VPBROADCASTMW2D, 2, {YMMREG,OPMASKREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+36756, 558},
    /*   2 : VPBROADCASTMW2D zmmreg,kreg [rm:       evex.512.f3.0f38.w0 3a /r         ] AVX512CD,FUTURE */
        /* 250(f2 7e 48) 300 001(3a) 110 : EVEX,PROT,AVX512CD,FUTURE */
        {I_VPBROADCASTMW2D, 2, {ZMMREG,OPMASKREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+36765, 559},
};

static const struct itemplate instrux_VPCMPEQUB[3] = {
    /*   0 : VPCMPEQUB kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w0 3e /r 00  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 08) 303 001(3e) 120 001(00) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPEQUB, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+7658, 550},
    /*   1 : VPCMPEQUB kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w0 3e /r 00  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 28) 303 001(3e) 120 001(00) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPEQUB, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+7669, 550},
    /*   2 : VPCMPEQUB kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w0 3e /r 00  ] AVX512BW,FUTURE */
        /* 241(f3 7d 48) 303 001(3e) 120 001(00) : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPEQUB, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+7680, 551},
};

static const struct itemplate instrux_VPCMPEQUD[3] = {
    /*   0 : VPCMPEQUD kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.66.0f3a.w0 1e /r 00  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 08) 301 001(1e) 120 001(00) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPEQUD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+7691, 544},
    /*   1 : VPCMPEQUD kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.66.0f3a.w0 1e /r 00  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 28) 301 001(1e) 120 001(00) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPEQUD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+7702, 544},
    /*   2 : VPCMPEQUD kreg|mask,zmmreg,zmmrm512|b32 [rvmi:fv:  evex.nds.512.66.0f3a.w0 1e /r 00  ] AVX512,FUTURE */
        /* 241(f3 7d 48) 301 001(1e) 120 001(00) : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPEQUD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+7713, 545},
};

static const struct itemplate instrux_VPCMPEQUQ[3] = {
    /*   0 : VPCMPEQUQ kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f3a.w1 1e /r 00  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 08) 301 001(1e) 120 001(00) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPEQUQ, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+7724, 544},
    /*   1 : VPCMPEQUQ kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f3a.w1 1e /r 00  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 28) 301 001(1e) 120 001(00) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPEQUQ, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+7735, 544},
    /*   2 : VPCMPEQUQ kreg|mask,zmmreg,zmmrm512|b64 [rvmi:fv:  evex.nds.512.66.0f3a.w1 1e /r 00  ] AVX512,FUTURE */
        /* 241(f3 fd 48) 301 001(1e) 120 001(00) : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPEQUQ, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+7746, 545},
};

static const struct itemplate instrux_VPCMPEQUW[3] = {
    /*   0 : VPCMPEQUW kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w1 3e /r 00  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 fd 08) 303 001(3e) 120 001(00) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPEQUW, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+7757, 550},
    /*   1 : VPCMPEQUW kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w1 3e /r 00  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 fd 28) 303 001(3e) 120 001(00) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPEQUW, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+7768, 550},
    /*   2 : VPCMPEQUW kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w1 3e /r 00  ] AVX512BW,FUTURE */
        /* 241(f3 fd 48) 303 001(3e) 120 001(00) : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPEQUW, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+7779, 551},
};

static const struct itemplate instrux_VPCMPGEB[3] = {
    /*   0 : VPCMPGEB kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w0 3f /r 05  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 08) 303 001(3f) 120 001(05) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPGEB, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+7823, 550},
    /*   1 : VPCMPGEB kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w0 3f /r 05  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 28) 303 001(3f) 120 001(05) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPGEB, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+7834, 550},
    /*   2 : VPCMPGEB kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w0 3f /r 05  ] AVX512BW,FUTURE */
        /* 241(f3 7d 48) 303 001(3f) 120 001(05) : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPGEB, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+7845, 551},
};

static const struct itemplate instrux_VPCMPGED[3] = {
    /*   0 : VPCMPGED kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.66.0f3a.w0 1f /r 05  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 08) 301 001(1f) 120 001(05) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPGED, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+7856, 544},
    /*   1 : VPCMPGED kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.66.0f3a.w0 1f /r 05  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 28) 301 001(1f) 120 001(05) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPGED, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+7867, 544},
    /*   2 : VPCMPGED kreg|mask,zmmreg,zmmrm512|b32 [rvmi:fv:  evex.nds.512.66.0f3a.w0 1f /r 05  ] AVX512,FUTURE */
        /* 241(f3 7d 48) 301 001(1f) 120 001(05) : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPGED, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+7878, 545},
};

static const struct itemplate instrux_VPCMPGEQ[3] = {
    /*   0 : VPCMPGEQ kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f3a.w1 1f /r 05  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 08) 301 001(1f) 120 001(05) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPGEQ, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+7889, 544},
    /*   1 : VPCMPGEQ kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f3a.w1 1f /r 05  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 28) 301 001(1f) 120 001(05) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPGEQ, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+7900, 544},
    /*   2 : VPCMPGEQ kreg|mask,zmmreg,zmmrm512|b64 [rvmi:fv:  evex.nds.512.66.0f3a.w1 1f /r 05  ] AVX512,FUTURE */
        /* 241(f3 fd 48) 301 001(1f) 120 001(05) : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPGEQ, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+7911, 545},
};

static const struct itemplate instrux_VPCMPGEUB[3] = {
    /*   0 : VPCMPGEUB kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w0 3e /r 05  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 08) 303 001(3e) 120 001(05) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPGEUB, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+7922, 550},
    /*   1 : VPCMPGEUB kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w0 3e /r 05  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 28) 303 001(3e) 120 001(05) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPGEUB, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+7933, 550},
    /*   2 : VPCMPGEUB kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w0 3e /r 05  ] AVX512BW,FUTURE */
        /* 241(f3 7d 48) 303 001(3e) 120 001(05) : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPGEUB, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+7944, 551},
};

static const struct itemplate instrux_VPCMPGEUD[3] = {
    /*   0 : VPCMPGEUD kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.66.0f3a.w0 1e /r 05  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 08) 301 001(1e) 120 001(05) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPGEUD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+7955, 544},
    /*   1 : VPCMPGEUD kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.66.0f3a.w0 1e /r 05  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 28) 301 001(1e) 120 001(05) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPGEUD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+7966, 544},
    /*   2 : VPCMPGEUD kreg|mask,zmmreg,zmmrm512|b32 [rvmi:fv:  evex.nds.512.66.0f3a.w0 1e /r 05  ] AVX512,FUTURE */
        /* 241(f3 7d 48) 301 001(1e) 120 001(05) : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPGEUD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+7977, 545},
};

static const struct itemplate instrux_VPCMPGEUQ[3] = {
    /*   0 : VPCMPGEUQ kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f3a.w1 1e /r 05  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 08) 301 001(1e) 120 001(05) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPGEUQ, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+7988, 544},
    /*   1 : VPCMPGEUQ kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f3a.w1 1e /r 05  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 28) 301 001(1e) 120 001(05) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPGEUQ, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+7999, 544},
    /*   2 : VPCMPGEUQ kreg|mask,zmmreg,zmmrm512|b64 [rvmi:fv:  evex.nds.512.66.0f3a.w1 1e /r 05  ] AVX512,FUTURE */
        /* 241(f3 fd 48) 301 001(1e) 120 001(05) : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPGEUQ, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+8010, 545},
};

static const struct itemplate instrux_VPCMPGEUW[3] = {
    /*   0 : VPCMPGEUW kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w1 3e /r 05  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 fd 08) 303 001(3e) 120 001(05) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPGEUW, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8021, 550},
    /*   1 : VPCMPGEUW kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w1 3e /r 05  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 fd 28) 303 001(3e) 120 001(05) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPGEUW, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8032, 550},
    /*   2 : VPCMPGEUW kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w1 3e /r 05  ] AVX512BW,FUTURE */
        /* 241(f3 fd 48) 303 001(3e) 120 001(05) : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPGEUW, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8043, 551},
};

static const struct itemplate instrux_VPCMPGEW[3] = {
    /*   0 : VPCMPGEW kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w1 3f /r 05  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 fd 08) 303 001(3f) 120 001(05) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPGEW, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8054, 550},
    /*   1 : VPCMPGEW kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w1 3f /r 05  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 fd 28) 303 001(3f) 120 001(05) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPGEW, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8065, 550},
    /*   2 : VPCMPGEW kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w1 3f /r 05  ] AVX512BW,FUTURE */
        /* 241(f3 fd 48) 303 001(3f) 120 001(05) : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPGEW, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8076, 551},
};

static const struct itemplate instrux_VPCMPGTUB[3] = {
    /*   0 : VPCMPGTUB kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w0 3e /r 06  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 08) 303 001(3e) 120 001(06) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPGTUB, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8186, 550},
    /*   1 : VPCMPGTUB kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w0 3e /r 06  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 28) 303 001(3e) 120 001(06) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPGTUB, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8197, 550},
    /*   2 : VPCMPGTUB kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w0 3e /r 06  ] AVX512BW,FUTURE */
        /* 241(f3 7d 48) 303 001(3e) 120 001(06) : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPGTUB, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8208, 551},
};

static const struct itemplate instrux_VPCMPGTUD[3] = {
    /*   0 : VPCMPGTUD kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.66.0f3a.w0 1e /r 06  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 08) 301 001(1e) 120 001(06) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPGTUD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+8219, 544},
    /*   1 : VPCMPGTUD kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.66.0f3a.w0 1e /r 06  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 28) 301 001(1e) 120 001(06) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPGTUD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+8230, 544},
    /*   2 : VPCMPGTUD kreg|mask,zmmreg,zmmrm512|b32 [rvmi:fv:  evex.nds.512.66.0f3a.w0 1e /r 06  ] AVX512,FUTURE */
        /* 241(f3 7d 48) 301 001(1e) 120 001(06) : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPGTUD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+8241, 545},
};

static const struct itemplate instrux_VPCMPGTUQ[3] = {
    /*   0 : VPCMPGTUQ kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f3a.w1 1e /r 06  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 08) 301 001(1e) 120 001(06) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPGTUQ, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+8252, 544},
    /*   1 : VPCMPGTUQ kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f3a.w1 1e /r 06  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 28) 301 001(1e) 120 001(06) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPGTUQ, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+8263, 544},
    /*   2 : VPCMPGTUQ kreg|mask,zmmreg,zmmrm512|b64 [rvmi:fv:  evex.nds.512.66.0f3a.w1 1e /r 06  ] AVX512,FUTURE */
        /* 241(f3 fd 48) 301 001(1e) 120 001(06) : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPGTUQ, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+8274, 545},
};

static const struct itemplate instrux_VPCMPGTUW[3] = {
    /*   0 : VPCMPGTUW kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w1 3e /r 06  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 fd 08) 303 001(3e) 120 001(06) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPGTUW, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8285, 550},
    /*   1 : VPCMPGTUW kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w1 3e /r 06  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 fd 28) 303 001(3e) 120 001(06) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPGTUW, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8296, 550},
    /*   2 : VPCMPGTUW kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w1 3e /r 06  ] AVX512BW,FUTURE */
        /* 241(f3 fd 48) 303 001(3e) 120 001(06) : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPGTUW, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8307, 551},
};

static const struct itemplate instrux_VPCMPLEB[3] = {
    /*   0 : VPCMPLEB kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w0 3f /r 02  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 08) 303 001(3f) 120 001(02) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPLEB, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8351, 550},
    /*   1 : VPCMPLEB kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w0 3f /r 02  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 28) 303 001(3f) 120 001(02) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPLEB, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8362, 550},
    /*   2 : VPCMPLEB kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w0 3f /r 02  ] AVX512BW,FUTURE */
        /* 241(f3 7d 48) 303 001(3f) 120 001(02) : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPLEB, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8373, 551},
};

static const struct itemplate instrux_VPCMPLED[3] = {
    /*   0 : VPCMPLED kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.66.0f3a.w0 1f /r 02  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 08) 301 001(1f) 120 001(02) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPLED, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+8384, 544},
    /*   1 : VPCMPLED kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.66.0f3a.w0 1f /r 02  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 28) 301 001(1f) 120 001(02) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPLED, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+8395, 544},
    /*   2 : VPCMPLED kreg|mask,zmmreg,zmmrm512|b32 [rvmi:fv:  evex.nds.512.66.0f3a.w0 1f /r 02  ] AVX512,FUTURE */
        /* 241(f3 7d 48) 301 001(1f) 120 001(02) : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPLED, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+8406, 545},
};

static const struct itemplate instrux_VPCMPLEQ[3] = {
    /*   0 : VPCMPLEQ kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f3a.w1 1f /r 02  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 08) 301 001(1f) 120 001(02) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPLEQ, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+8417, 544},
    /*   1 : VPCMPLEQ kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f3a.w1 1f /r 02  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 28) 301 001(1f) 120 001(02) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPLEQ, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+8428, 544},
    /*   2 : VPCMPLEQ kreg|mask,zmmreg,zmmrm512|b64 [rvmi:fv:  evex.nds.512.66.0f3a.w1 1f /r 02  ] AVX512,FUTURE */
        /* 241(f3 fd 48) 301 001(1f) 120 001(02) : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPLEQ, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+8439, 545},
};

static const struct itemplate instrux_VPCMPLEUB[3] = {
    /*   0 : VPCMPLEUB kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w0 3e /r 02  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 08) 303 001(3e) 120 001(02) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPLEUB, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8450, 550},
    /*   1 : VPCMPLEUB kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w0 3e /r 02  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 28) 303 001(3e) 120 001(02) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPLEUB, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8461, 550},
    /*   2 : VPCMPLEUB kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w0 3e /r 02  ] AVX512BW,FUTURE */
        /* 241(f3 7d 48) 303 001(3e) 120 001(02) : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPLEUB, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8472, 551},
};

static const struct itemplate instrux_VPCMPLEUD[3] = {
    /*   0 : VPCMPLEUD kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.66.0f3a.w0 1e /r 02  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 08) 301 001(1e) 120 001(02) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPLEUD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+8483, 544},
    /*   1 : VPCMPLEUD kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.66.0f3a.w0 1e /r 02  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 28) 301 001(1e) 120 001(02) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPLEUD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+8494, 544},
    /*   2 : VPCMPLEUD kreg|mask,zmmreg,zmmrm512|b32 [rvmi:fv:  evex.nds.512.66.0f3a.w0 1e /r 02  ] AVX512,FUTURE */
        /* 241(f3 7d 48) 301 001(1e) 120 001(02) : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPLEUD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+8505, 545},
};

static const struct itemplate instrux_VPCMPLEUQ[3] = {
    /*   0 : VPCMPLEUQ kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f3a.w1 1e /r 02  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 08) 301 001(1e) 120 001(02) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPLEUQ, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+8516, 544},
    /*   1 : VPCMPLEUQ kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f3a.w1 1e /r 02  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 28) 301 001(1e) 120 001(02) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPLEUQ, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+8527, 544},
    /*   2 : VPCMPLEUQ kreg|mask,zmmreg,zmmrm512|b64 [rvmi:fv:  evex.nds.512.66.0f3a.w1 1e /r 02  ] AVX512,FUTURE */
        /* 241(f3 fd 48) 301 001(1e) 120 001(02) : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPLEUQ, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+8538, 545},
};

static const struct itemplate instrux_VPCMPLEUW[3] = {
    /*   0 : VPCMPLEUW kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w1 3e /r 02  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 fd 08) 303 001(3e) 120 001(02) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPLEUW, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8549, 550},
    /*   1 : VPCMPLEUW kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w1 3e /r 02  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 fd 28) 303 001(3e) 120 001(02) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPLEUW, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8560, 550},
    /*   2 : VPCMPLEUW kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w1 3e /r 02  ] AVX512BW,FUTURE */
        /* 241(f3 fd 48) 303 001(3e) 120 001(02) : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPLEUW, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8571, 551},
};

static const struct itemplate instrux_VPCMPLEW[3] = {
    /*   0 : VPCMPLEW kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w1 3f /r 02  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 fd 08) 303 001(3f) 120 001(02) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPLEW, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8582, 550},
    /*   1 : VPCMPLEW kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w1 3f /r 02  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 fd 28) 303 001(3f) 120 001(02) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPLEW, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8593, 550},
    /*   2 : VPCMPLEW kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w1 3f /r 02  ] AVX512BW,FUTURE */
        /* 241(f3 fd 48) 303 001(3f) 120 001(02) : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPLEW, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8604, 551},
};

static const struct itemplate instrux_VPCMPLTB[3] = {
    /*   0 : VPCMPLTB kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w0 3f /r 01  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 08) 303 001(3f) 120 001(01) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPLTB, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8615, 550},
    /*   1 : VPCMPLTB kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w0 3f /r 01  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 28) 303 001(3f) 120 001(01) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPLTB, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8626, 550},
    /*   2 : VPCMPLTB kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w0 3f /r 01  ] AVX512BW,FUTURE */
        /* 241(f3 7d 48) 303 001(3f) 120 001(01) : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPLTB, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8637, 551},
};

static const struct itemplate instrux_VPCMPLTD[3] = {
    /*   0 : VPCMPLTD kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.66.0f3a.w0 1f /r 01  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 08) 301 001(1f) 120 001(01) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPLTD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+8648, 544},
    /*   1 : VPCMPLTD kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.66.0f3a.w0 1f /r 01  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 28) 301 001(1f) 120 001(01) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPLTD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+8659, 544},
    /*   2 : VPCMPLTD kreg|mask,zmmreg,zmmrm512|b32 [rvmi:fv:  evex.nds.512.66.0f3a.w0 1f /r 01  ] AVX512,FUTURE */
        /* 241(f3 7d 48) 301 001(1f) 120 001(01) : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPLTD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+8670, 545},
};

static const struct itemplate instrux_VPCMPLTQ[3] = {
    /*   0 : VPCMPLTQ kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f3a.w1 1f /r 01  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 08) 301 001(1f) 120 001(01) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPLTQ, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+8681, 544},
    /*   1 : VPCMPLTQ kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f3a.w1 1f /r 01  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 28) 301 001(1f) 120 001(01) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPLTQ, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+8692, 544},
    /*   2 : VPCMPLTQ kreg|mask,zmmreg,zmmrm512|b64 [rvmi:fv:  evex.nds.512.66.0f3a.w1 1f /r 01  ] AVX512,FUTURE */
        /* 241(f3 fd 48) 301 001(1f) 120 001(01) : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPLTQ, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+8703, 545},
};

static const struct itemplate instrux_VPCMPLTUB[3] = {
    /*   0 : VPCMPLTUB kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w0 3e /r 01  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 08) 303 001(3e) 120 001(01) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPLTUB, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8714, 550},
    /*   1 : VPCMPLTUB kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w0 3e /r 01  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 28) 303 001(3e) 120 001(01) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPLTUB, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8725, 550},
    /*   2 : VPCMPLTUB kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w0 3e /r 01  ] AVX512BW,FUTURE */
        /* 241(f3 7d 48) 303 001(3e) 120 001(01) : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPLTUB, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8736, 551},
};

static const struct itemplate instrux_VPCMPLTUD[3] = {
    /*   0 : VPCMPLTUD kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.66.0f3a.w0 1e /r 01  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 08) 301 001(1e) 120 001(01) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPLTUD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+8747, 544},
    /*   1 : VPCMPLTUD kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.66.0f3a.w0 1e /r 01  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 28) 301 001(1e) 120 001(01) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPLTUD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+8758, 544},
    /*   2 : VPCMPLTUD kreg|mask,zmmreg,zmmrm512|b32 [rvmi:fv:  evex.nds.512.66.0f3a.w0 1e /r 01  ] AVX512,FUTURE */
        /* 241(f3 7d 48) 301 001(1e) 120 001(01) : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPLTUD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+8769, 545},
};

static const struct itemplate instrux_VPCMPLTUQ[3] = {
    /*   0 : VPCMPLTUQ kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f3a.w1 1e /r 01  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 08) 301 001(1e) 120 001(01) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPLTUQ, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+8780, 544},
    /*   1 : VPCMPLTUQ kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f3a.w1 1e /r 01  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 28) 301 001(1e) 120 001(01) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPLTUQ, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+8791, 544},
    /*   2 : VPCMPLTUQ kreg|mask,zmmreg,zmmrm512|b64 [rvmi:fv:  evex.nds.512.66.0f3a.w1 1e /r 01  ] AVX512,FUTURE */
        /* 241(f3 fd 48) 301 001(1e) 120 001(01) : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPLTUQ, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+8802, 545},
};

static const struct itemplate instrux_VPCMPLTUW[3] = {
    /*   0 : VPCMPLTUW kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w1 3e /r 01  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 fd 08) 303 001(3e) 120 001(01) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPLTUW, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8813, 550},
    /*   1 : VPCMPLTUW kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w1 3e /r 01  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 fd 28) 303 001(3e) 120 001(01) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPLTUW, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8824, 550},
    /*   2 : VPCMPLTUW kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w1 3e /r 01  ] AVX512BW,FUTURE */
        /* 241(f3 fd 48) 303 001(3e) 120 001(01) : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPLTUW, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8835, 551},
};

static const struct itemplate instrux_VPCMPLTW[3] = {
    /*   0 : VPCMPLTW kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w1 3f /r 01  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 fd 08) 303 001(3f) 120 001(01) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPLTW, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8846, 550},
    /*   1 : VPCMPLTW kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w1 3f /r 01  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 fd 28) 303 001(3f) 120 001(01) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPLTW, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8857, 550},
    /*   2 : VPCMPLTW kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w1 3f /r 01  ] AVX512BW,FUTURE */
        /* 241(f3 fd 48) 303 001(3f) 120 001(01) : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPLTW, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8868, 551},
};

static const struct itemplate instrux_VPCMPNEQB[3] = {
    /*   0 : VPCMPNEQB kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w0 3f /r 04  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 08) 303 001(3f) 120 001(04) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPNEQB, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8879, 550},
    /*   1 : VPCMPNEQB kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w0 3f /r 04  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 28) 303 001(3f) 120 001(04) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPNEQB, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8890, 550},
    /*   2 : VPCMPNEQB kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w0 3f /r 04  ] AVX512BW,FUTURE */
        /* 241(f3 7d 48) 303 001(3f) 120 001(04) : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPNEQB, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8901, 551},
};

static const struct itemplate instrux_VPCMPNEQD[3] = {
    /*   0 : VPCMPNEQD kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.66.0f3a.w0 1f /r 04  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 08) 301 001(1f) 120 001(04) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPNEQD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+8912, 544},
    /*   1 : VPCMPNEQD kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.66.0f3a.w0 1f /r 04  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 28) 301 001(1f) 120 001(04) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPNEQD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+8923, 544},
    /*   2 : VPCMPNEQD kreg|mask,zmmreg,zmmrm512|b32 [rvmi:fv:  evex.nds.512.66.0f3a.w0 1f /r 04  ] AVX512,FUTURE */
        /* 241(f3 7d 48) 301 001(1f) 120 001(04) : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPNEQD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+8934, 545},
};

static const struct itemplate instrux_VPCMPNEQQ[3] = {
    /*   0 : VPCMPNEQQ kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f3a.w1 1f /r 04  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 08) 301 001(1f) 120 001(04) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPNEQQ, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+8945, 544},
    /*   1 : VPCMPNEQQ kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f3a.w1 1f /r 04  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 28) 301 001(1f) 120 001(04) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPNEQQ, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+8956, 544},
    /*   2 : VPCMPNEQQ kreg|mask,zmmreg,zmmrm512|b64 [rvmi:fv:  evex.nds.512.66.0f3a.w1 1f /r 04  ] AVX512,FUTURE */
        /* 241(f3 fd 48) 301 001(1f) 120 001(04) : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPNEQQ, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+8967, 545},
};

static const struct itemplate instrux_VPCMPNEQUB[3] = {
    /*   0 : VPCMPNEQUB kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w0 3e /r 04  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 08) 303 001(3e) 120 001(04) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPNEQUB, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8978, 550},
    /*   1 : VPCMPNEQUB kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w0 3e /r 04  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 28) 303 001(3e) 120 001(04) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPNEQUB, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8989, 550},
    /*   2 : VPCMPNEQUB kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w0 3e /r 04  ] AVX512BW,FUTURE */
        /* 241(f3 7d 48) 303 001(3e) 120 001(04) : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPNEQUB, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+9000, 551},
};

static const struct itemplate instrux_VPCMPNEQUD[3] = {
    /*   0 : VPCMPNEQUD kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.66.0f3a.w0 1e /r 04  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 08) 301 001(1e) 120 001(04) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPNEQUD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+9011, 544},
    /*   1 : VPCMPNEQUD kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.66.0f3a.w0 1e /r 04  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 28) 301 001(1e) 120 001(04) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPNEQUD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+9022, 544},
    /*   2 : VPCMPNEQUD kreg|mask,zmmreg,zmmrm512|b32 [rvmi:fv:  evex.nds.512.66.0f3a.w0 1e /r 04  ] AVX512,FUTURE */
        /* 241(f3 7d 48) 301 001(1e) 120 001(04) : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPNEQUD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+9033, 545},
};

static const struct itemplate instrux_VPCMPNEQUQ[3] = {
    /*   0 : VPCMPNEQUQ kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f3a.w1 1e /r 04  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 08) 301 001(1e) 120 001(04) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPNEQUQ, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+9044, 544},
    /*   1 : VPCMPNEQUQ kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f3a.w1 1e /r 04  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 28) 301 001(1e) 120 001(04) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPNEQUQ, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+9055, 544},
    /*   2 : VPCMPNEQUQ kreg|mask,zmmreg,zmmrm512|b64 [rvmi:fv:  evex.nds.512.66.0f3a.w1 1e /r 04  ] AVX512,FUTURE */
        /* 241(f3 fd 48) 301 001(1e) 120 001(04) : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPNEQUQ, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+9066, 545},
};

static const struct itemplate instrux_VPCMPNEQUW[3] = {
    /*   0 : VPCMPNEQUW kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w1 3e /r 04  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 fd 08) 303 001(3e) 120 001(04) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPNEQUW, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+9077, 550},
    /*   1 : VPCMPNEQUW kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w1 3e /r 04  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 fd 28) 303 001(3e) 120 001(04) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPNEQUW, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+9088, 550},
    /*   2 : VPCMPNEQUW kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w1 3e /r 04  ] AVX512BW,FUTURE */
        /* 241(f3 fd 48) 303 001(3e) 120 001(04) : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPNEQUW, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+9099, 551},
};

static const struct itemplate instrux_VPCMPNEQW[3] = {
    /*   0 : VPCMPNEQW kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w1 3f /r 04  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 fd 08) 303 001(3f) 120 001(04) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPNEQW, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+9110, 550},
    /*   1 : VPCMPNEQW kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w1 3f /r 04  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 fd 28) 303 001(3f) 120 001(04) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPNEQW, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+9121, 550},
    /*   2 : VPCMPNEQW kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w1 3f /r 04  ] AVX512BW,FUTURE */
        /* 241(f3 fd 48) 303 001(3f) 120 001(04) : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPNEQW, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+9132, 551},
};

static const struct itemplate instrux_VPCMPNGTB[3] = {
    /*   0 : VPCMPNGTB kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w0 3f /r 02  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 08) 303 001(3f) 120 001(02) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPNGTB, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8351, 550},
    /*   1 : VPCMPNGTB kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w0 3f /r 02  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 28) 303 001(3f) 120 001(02) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPNGTB, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8362, 550},
    /*   2 : VPCMPNGTB kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w0 3f /r 02  ] AVX512BW,FUTURE */
        /* 241(f3 7d 48) 303 001(3f) 120 001(02) : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPNGTB, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8373, 551},
};

static const struct itemplate instrux_VPCMPNGTD[3] = {
    /*   0 : VPCMPNGTD kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.66.0f3a.w0 1f /r 02  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 08) 301 001(1f) 120 001(02) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPNGTD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+8384, 544},
    /*   1 : VPCMPNGTD kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.66.0f3a.w0 1f /r 02  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 28) 301 001(1f) 120 001(02) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPNGTD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+8395, 544},
    /*   2 : VPCMPNGTD kreg|mask,zmmreg,zmmrm512|b32 [rvmi:fv:  evex.nds.512.66.0f3a.w0 1f /r 02  ] AVX512,FUTURE */
        /* 241(f3 7d 48) 301 001(1f) 120 001(02) : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPNGTD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+8406, 545},
};

static const struct itemplate instrux_VPCMPNGTQ[3] = {
    /*   0 : VPCMPNGTQ kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f3a.w1 1f /r 02  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 08) 301 001(1f) 120 001(02) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPNGTQ, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+8417, 544},
    /*   1 : VPCMPNGTQ kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f3a.w1 1f /r 02  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 28) 301 001(1f) 120 001(02) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPNGTQ, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+8428, 544},
    /*   2 : VPCMPNGTQ kreg|mask,zmmreg,zmmrm512|b64 [rvmi:fv:  evex.nds.512.66.0f3a.w1 1f /r 02  ] AVX512,FUTURE */
        /* 241(f3 fd 48) 301 001(1f) 120 001(02) : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPNGTQ, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+8439, 545},
};

static const struct itemplate instrux_VPCMPNGTUB[3] = {
    /*   0 : VPCMPNGTUB kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w0 3e /r 02  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 08) 303 001(3e) 120 001(02) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPNGTUB, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8450, 550},
    /*   1 : VPCMPNGTUB kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w0 3e /r 02  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 28) 303 001(3e) 120 001(02) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPNGTUB, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8461, 550},
    /*   2 : VPCMPNGTUB kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w0 3e /r 02  ] AVX512BW,FUTURE */
        /* 241(f3 7d 48) 303 001(3e) 120 001(02) : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPNGTUB, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8472, 551},
};

static const struct itemplate instrux_VPCMPNGTUD[3] = {
    /*   0 : VPCMPNGTUD kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.66.0f3a.w0 1e /r 02  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 08) 301 001(1e) 120 001(02) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPNGTUD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+8483, 544},
    /*   1 : VPCMPNGTUD kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.66.0f3a.w0 1e /r 02  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 28) 301 001(1e) 120 001(02) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPNGTUD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+8494, 544},
    /*   2 : VPCMPNGTUD kreg|mask,zmmreg,zmmrm512|b32 [rvmi:fv:  evex.nds.512.66.0f3a.w0 1e /r 02  ] AVX512,FUTURE */
        /* 241(f3 7d 48) 301 001(1e) 120 001(02) : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPNGTUD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+8505, 545},
};

static const struct itemplate instrux_VPCMPNGTUQ[3] = {
    /*   0 : VPCMPNGTUQ kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f3a.w1 1e /r 02  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 08) 301 001(1e) 120 001(02) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPNGTUQ, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+8516, 544},
    /*   1 : VPCMPNGTUQ kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f3a.w1 1e /r 02  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 28) 301 001(1e) 120 001(02) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPNGTUQ, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+8527, 544},
    /*   2 : VPCMPNGTUQ kreg|mask,zmmreg,zmmrm512|b64 [rvmi:fv:  evex.nds.512.66.0f3a.w1 1e /r 02  ] AVX512,FUTURE */
        /* 241(f3 fd 48) 301 001(1e) 120 001(02) : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPNGTUQ, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+8538, 545},
};

static const struct itemplate instrux_VPCMPNGTUW[3] = {
    /*   0 : VPCMPNGTUW kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w1 3e /r 02  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 fd 08) 303 001(3e) 120 001(02) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPNGTUW, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8549, 550},
    /*   1 : VPCMPNGTUW kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w1 3e /r 02  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 fd 28) 303 001(3e) 120 001(02) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPNGTUW, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8560, 550},
    /*   2 : VPCMPNGTUW kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w1 3e /r 02  ] AVX512BW,FUTURE */
        /* 241(f3 fd 48) 303 001(3e) 120 001(02) : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPNGTUW, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8571, 551},
};

static const struct itemplate instrux_VPCMPNGTW[3] = {
    /*   0 : VPCMPNGTW kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w1 3f /r 02  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 fd 08) 303 001(3f) 120 001(02) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPNGTW, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8582, 550},
    /*   1 : VPCMPNGTW kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w1 3f /r 02  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 fd 28) 303 001(3f) 120 001(02) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPNGTW, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8593, 550},
    /*   2 : VPCMPNGTW kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w1 3f /r 02  ] AVX512BW,FUTURE */
        /* 241(f3 fd 48) 303 001(3f) 120 001(02) : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPNGTW, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8604, 551},
};

static const struct itemplate instrux_VPCMPNLEB[3] = {
    /*   0 : VPCMPNLEB kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w0 3f /r 06  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 08) 303 001(3f) 120 001(06) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPNLEB, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8087, 550},
    /*   1 : VPCMPNLEB kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w0 3f /r 06  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 28) 303 001(3f) 120 001(06) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPNLEB, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8098, 550},
    /*   2 : VPCMPNLEB kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w0 3f /r 06  ] AVX512BW,FUTURE */
        /* 241(f3 7d 48) 303 001(3f) 120 001(06) : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPNLEB, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8109, 551},
};

static const struct itemplate instrux_VPCMPNLED[3] = {
    /*   0 : VPCMPNLED kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.66.0f3a.w0 1f /r 06  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 08) 301 001(1f) 120 001(06) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPNLED, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+8120, 544},
    /*   1 : VPCMPNLED kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.66.0f3a.w0 1f /r 06  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 28) 301 001(1f) 120 001(06) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPNLED, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+8131, 544},
    /*   2 : VPCMPNLED kreg|mask,zmmreg,zmmrm512|b32 [rvmi:fv:  evex.nds.512.66.0f3a.w0 1f /r 06  ] AVX512,FUTURE */
        /* 241(f3 7d 48) 301 001(1f) 120 001(06) : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPNLED, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+8142, 545},
};

static const struct itemplate instrux_VPCMPNLEQ[3] = {
    /*   0 : VPCMPNLEQ kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f3a.w1 1f /r 06  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 08) 301 001(1f) 120 001(06) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPNLEQ, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+8153, 544},
    /*   1 : VPCMPNLEQ kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f3a.w1 1f /r 06  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 28) 301 001(1f) 120 001(06) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPNLEQ, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+8164, 544},
    /*   2 : VPCMPNLEQ kreg|mask,zmmreg,zmmrm512|b64 [rvmi:fv:  evex.nds.512.66.0f3a.w1 1f /r 06  ] AVX512,FUTURE */
        /* 241(f3 fd 48) 301 001(1f) 120 001(06) : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPNLEQ, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+8175, 545},
};

static const struct itemplate instrux_VPCMPNLEUB[3] = {
    /*   0 : VPCMPNLEUB kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w0 3e /r 06  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 08) 303 001(3e) 120 001(06) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPNLEUB, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8186, 550},
    /*   1 : VPCMPNLEUB kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w0 3e /r 06  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 28) 303 001(3e) 120 001(06) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPNLEUB, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8197, 550},
    /*   2 : VPCMPNLEUB kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w0 3e /r 06  ] AVX512BW,FUTURE */
        /* 241(f3 7d 48) 303 001(3e) 120 001(06) : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPNLEUB, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8208, 551},
};

static const struct itemplate instrux_VPCMPNLEUD[3] = {
    /*   0 : VPCMPNLEUD kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.66.0f3a.w0 1e /r 06  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 08) 301 001(1e) 120 001(06) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPNLEUD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+8219, 544},
    /*   1 : VPCMPNLEUD kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.66.0f3a.w0 1e /r 06  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 28) 301 001(1e) 120 001(06) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPNLEUD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+8230, 544},
    /*   2 : VPCMPNLEUD kreg|mask,zmmreg,zmmrm512|b32 [rvmi:fv:  evex.nds.512.66.0f3a.w0 1e /r 06  ] AVX512,FUTURE */
        /* 241(f3 7d 48) 301 001(1e) 120 001(06) : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPNLEUD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+8241, 545},
};

static const struct itemplate instrux_VPCMPNLEUQ[3] = {
    /*   0 : VPCMPNLEUQ kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f3a.w1 1e /r 06  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 08) 301 001(1e) 120 001(06) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPNLEUQ, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+8252, 544},
    /*   1 : VPCMPNLEUQ kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f3a.w1 1e /r 06  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 28) 301 001(1e) 120 001(06) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPNLEUQ, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+8263, 544},
    /*   2 : VPCMPNLEUQ kreg|mask,zmmreg,zmmrm512|b64 [rvmi:fv:  evex.nds.512.66.0f3a.w1 1e /r 06  ] AVX512,FUTURE */
        /* 241(f3 fd 48) 301 001(1e) 120 001(06) : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPNLEUQ, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+8274, 545},
};

static const struct itemplate instrux_VPCMPNLEUW[3] = {
    /*   0 : VPCMPNLEUW kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w1 3e /r 06  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 fd 08) 303 001(3e) 120 001(06) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPNLEUW, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8285, 550},
    /*   1 : VPCMPNLEUW kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w1 3e /r 06  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 fd 28) 303 001(3e) 120 001(06) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPNLEUW, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8296, 550},
    /*   2 : VPCMPNLEUW kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w1 3e /r 06  ] AVX512BW,FUTURE */
        /* 241(f3 fd 48) 303 001(3e) 120 001(06) : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPNLEUW, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8307, 551},
};

static const struct itemplate instrux_VPCMPNLEW[3] = {
    /*   0 : VPCMPNLEW kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w1 3f /r 06  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 fd 08) 303 001(3f) 120 001(06) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPNLEW, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8318, 550},
    /*   1 : VPCMPNLEW kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w1 3f /r 06  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 fd 28) 303 001(3f) 120 001(06) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPNLEW, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8329, 550},
    /*   2 : VPCMPNLEW kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w1 3f /r 06  ] AVX512BW,FUTURE */
        /* 241(f3 fd 48) 303 001(3f) 120 001(06) : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPNLEW, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8340, 551},
};

static const struct itemplate instrux_VPCMPNLTB[3] = {
    /*   0 : VPCMPNLTB kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w0 3f /r 05  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 08) 303 001(3f) 120 001(05) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPNLTB, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+7823, 550},
    /*   1 : VPCMPNLTB kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w0 3f /r 05  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 28) 303 001(3f) 120 001(05) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPNLTB, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+7834, 550},
    /*   2 : VPCMPNLTB kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w0 3f /r 05  ] AVX512BW,FUTURE */
        /* 241(f3 7d 48) 303 001(3f) 120 001(05) : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPNLTB, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+7845, 551},
};

static const struct itemplate instrux_VPCMPNLTD[3] = {
    /*   0 : VPCMPNLTD kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.66.0f3a.w0 1f /r 05  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 08) 301 001(1f) 120 001(05) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPNLTD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+7856, 544},
    /*   1 : VPCMPNLTD kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.66.0f3a.w0 1f /r 05  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 28) 301 001(1f) 120 001(05) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPNLTD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+7867, 544},
    /*   2 : VPCMPNLTD kreg|mask,zmmreg,zmmrm512|b32 [rvmi:fv:  evex.nds.512.66.0f3a.w0 1f /r 05  ] AVX512,FUTURE */
        /* 241(f3 7d 48) 301 001(1f) 120 001(05) : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPNLTD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+7878, 545},
};

static const struct itemplate instrux_VPCMPNLTQ[3] = {
    /*   0 : VPCMPNLTQ kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f3a.w1 1f /r 05  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 08) 301 001(1f) 120 001(05) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPNLTQ, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+7889, 544},
    /*   1 : VPCMPNLTQ kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f3a.w1 1f /r 05  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 28) 301 001(1f) 120 001(05) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPNLTQ, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+7900, 544},
    /*   2 : VPCMPNLTQ kreg|mask,zmmreg,zmmrm512|b64 [rvmi:fv:  evex.nds.512.66.0f3a.w1 1f /r 05  ] AVX512,FUTURE */
        /* 241(f3 fd 48) 301 001(1f) 120 001(05) : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPNLTQ, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+7911, 545},
};

static const struct itemplate instrux_VPCMPNLTUB[3] = {
    /*   0 : VPCMPNLTUB kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w0 3e /r 05  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 08) 303 001(3e) 120 001(05) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPNLTUB, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+7922, 550},
    /*   1 : VPCMPNLTUB kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w0 3e /r 05  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 28) 303 001(3e) 120 001(05) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPNLTUB, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+7933, 550},
    /*   2 : VPCMPNLTUB kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w0 3e /r 05  ] AVX512BW,FUTURE */
        /* 241(f3 7d 48) 303 001(3e) 120 001(05) : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPNLTUB, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+7944, 551},
};

static const struct itemplate instrux_VPCMPNLTUD[3] = {
    /*   0 : VPCMPNLTUD kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv:  evex.nds.128.66.0f3a.w0 1e /r 05  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 08) 301 001(1e) 120 001(05) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPNLTUD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+7955, 544},
    /*   1 : VPCMPNLTUD kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv:  evex.nds.256.66.0f3a.w0 1e /r 05  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 28) 301 001(1e) 120 001(05) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPNLTUD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+7966, 544},
    /*   2 : VPCMPNLTUD kreg|mask,zmmreg,zmmrm512|b32 [rvmi:fv:  evex.nds.512.66.0f3a.w0 1e /r 05  ] AVX512,FUTURE */
        /* 241(f3 7d 48) 301 001(1e) 120 001(05) : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPNLTUD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+7977, 545},
};

static const struct itemplate instrux_VPCMPNLTUQ[3] = {
    /*   0 : VPCMPNLTUQ kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv:  evex.nds.128.66.0f3a.w1 1e /r 05  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 08) 301 001(1e) 120 001(05) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPNLTUQ, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+7988, 544},
    /*   1 : VPCMPNLTUQ kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv:  evex.nds.256.66.0f3a.w1 1e /r 05  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 28) 301 001(1e) 120 001(05) : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPNLTUQ, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+7999, 544},
    /*   2 : VPCMPNLTUQ kreg|mask,zmmreg,zmmrm512|b64 [rvmi:fv:  evex.nds.512.66.0f3a.w1 1e /r 05  ] AVX512,FUTURE */
        /* 241(f3 fd 48) 301 001(1e) 120 001(05) : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPNLTUQ, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+8010, 545},
};

static const struct itemplate instrux_VPCMPNLTUW[3] = {
    /*   0 : VPCMPNLTUW kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w1 3e /r 05  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 fd 08) 303 001(3e) 120 001(05) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPNLTUW, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8021, 550},
    /*   1 : VPCMPNLTUW kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w1 3e /r 05  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 fd 28) 303 001(3e) 120 001(05) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPNLTUW, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8032, 550},
    /*   2 : VPCMPNLTUW kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w1 3e /r 05  ] AVX512BW,FUTURE */
        /* 241(f3 fd 48) 303 001(3e) 120 001(05) : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPNLTUW, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8043, 551},
};

static const struct itemplate instrux_VPCMPNLTW[3] = {
    /*   0 : VPCMPNLTW kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w1 3f /r 05  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 fd 08) 303 001(3f) 120 001(05) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPNLTW, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8054, 550},
    /*   1 : VPCMPNLTW kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w1 3f /r 05  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 fd 28) 303 001(3f) 120 001(05) : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPNLTW, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8065, 550},
    /*   2 : VPCMPNLTW kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w1 3f /r 05  ] AVX512BW,FUTURE */
        /* 241(f3 fd 48) 303 001(3f) 120 001(05) : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPNLTW, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8076, 551},
};

static const struct itemplate instrux_VPCMPB[3] = {
    /*   0 : VPCMPB kreg|mask,xmmreg,xmmrm128,imm8 [rvmi:fvm: evex.nds.128.66.0f3a.w0 3f /r ib  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 08) 303 001(3f) 120 023 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPB, 4, {OPMASKREG,XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK,0,0,0,0}, nasm_bytecodes+19513, 550},
    /*   1 : VPCMPB kreg|mask,ymmreg,ymmrm256,imm8 [rvmi:fvm: evex.nds.256.66.0f3a.w0 3f /r ib  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 28) 303 001(3f) 120 023 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPB, 4, {OPMASKREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK,0,0,0,0}, nasm_bytecodes+19523, 550},
    /*   2 : VPCMPB kreg|mask,zmmreg,zmmrm512,imm8 [rvmi:fvm: evex.nds.512.66.0f3a.w0 3f /r ib  ] AVX512BW,FUTURE */
        /* 241(f3 7d 48) 303 001(3f) 120 023 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPB, 4, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, {MASK,0,0,0,0}, nasm_bytecodes+19533, 551},
};

static const struct itemplate instrux_VPCMPD[3] = {
    /*   0 : VPCMPD kreg|mask,xmmreg,xmmrm128|b32,imm8 [rvmi:fv:  evex.nds.128.66.0f3a.w0 1f /r ib  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 08) 301 001(1f) 120 023 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPD, 4, {OPMASKREG,XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK,0,B32,0,0}, nasm_bytecodes+19543, 544},
    /*   1 : VPCMPD kreg|mask,ymmreg,ymmrm256|b32,imm8 [rvmi:fv:  evex.nds.256.66.0f3a.w0 1f /r ib  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 28) 301 001(1f) 120 023 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPD, 4, {OPMASKREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK,0,B32,0,0}, nasm_bytecodes+19553, 544},
    /*   2 : VPCMPD kreg|mask,zmmreg,zmmrm512|b32,imm8 [rvmi:fv:  evex.nds.512.66.0f3a.w0 1f /r ib  ] AVX512,FUTURE */
        /* 241(f3 7d 48) 301 001(1f) 120 023 : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPD, 4, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, {MASK,0,B32,0,0}, nasm_bytecodes+19563, 545},
};

static const struct itemplate instrux_VPCMPQ[3] = {
    /*   0 : VPCMPQ kreg|mask,xmmreg,xmmrm128|b64,imm8 [rvmi:fv:  evex.nds.128.66.0f3a.w1 1f /r ib  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 08) 301 001(1f) 120 023 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPQ, 4, {OPMASKREG,XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK,0,B64,0,0}, nasm_bytecodes+19573, 544},
    /*   1 : VPCMPQ kreg|mask,ymmreg,ymmrm256|b64,imm8 [rvmi:fv:  evex.nds.256.66.0f3a.w1 1f /r ib  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 28) 301 001(1f) 120 023 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPQ, 4, {OPMASKREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK,0,B64,0,0}, nasm_bytecodes+19583, 544},
    /*   2 : VPCMPQ kreg|mask,zmmreg,zmmrm512|b64,imm8 [rvmi:fv:  evex.nds.512.66.0f3a.w1 1f /r ib  ] AVX512,FUTURE */
        /* 241(f3 fd 48) 301 001(1f) 120 023 : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPQ, 4, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, {MASK,0,B64,0,0}, nasm_bytecodes+19593, 545},
};

static const struct itemplate instrux_VPCMPUB[3] = {
    /*   0 : VPCMPUB kreg|mask,xmmreg,xmmrm128,imm8 [rvmi:fvm: evex.nds.128.66.0f3a.w0 3e /r ib  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 08) 303 001(3e) 120 023 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPUB, 4, {OPMASKREG,XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK,0,0,0,0}, nasm_bytecodes+19603, 550},
    /*   1 : VPCMPUB kreg|mask,ymmreg,ymmrm256,imm8 [rvmi:fvm: evex.nds.256.66.0f3a.w0 3e /r ib  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 7d 28) 303 001(3e) 120 023 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPUB, 4, {OPMASKREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK,0,0,0,0}, nasm_bytecodes+19613, 550},
    /*   2 : VPCMPUB kreg|mask,zmmreg,zmmrm512,imm8 [rvmi:fvm: evex.nds.512.66.0f3a.w0 3e /r ib  ] AVX512BW,FUTURE */
        /* 241(f3 7d 48) 303 001(3e) 120 023 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPUB, 4, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, {MASK,0,0,0,0}, nasm_bytecodes+19623, 551},
};

static const struct itemplate instrux_VPCMPUD[3] = {
    /*   0 : VPCMPUD kreg|mask,xmmreg,xmmrm128|b32,imm8 [rvmi:fv:  evex.nds.128.66.0f3a.w0 1e /r ib  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 08) 301 001(1e) 120 023 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPUD, 4, {OPMASKREG,XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK,0,B32,0,0}, nasm_bytecodes+19633, 544},
    /*   1 : VPCMPUD kreg|mask,ymmreg,ymmrm256|b32,imm8 [rvmi:fv:  evex.nds.256.66.0f3a.w0 1e /r ib  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 28) 301 001(1e) 120 023 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPUD, 4, {OPMASKREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK,0,B32,0,0}, nasm_bytecodes+19643, 544},
    /*   2 : VPCMPUD kreg|mask,zmmreg,zmmrm512|b32,imm8 [rvmi:fv:  evex.nds.512.66.0f3a.w0 1e /r ib  ] AVX512,FUTURE */
        /* 241(f3 7d 48) 301 001(1e) 120 023 : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPUD, 4, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, {MASK,0,B32,0,0}, nasm_bytecodes+19653, 545},
};

static const struct itemplate instrux_VPCMPUQ[3] = {
    /*   0 : VPCMPUQ kreg|mask,xmmreg,xmmrm128|b64,imm8 [rvmi:fv:  evex.nds.128.66.0f3a.w1 1e /r ib  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 08) 301 001(1e) 120 023 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPUQ, 4, {OPMASKREG,XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK,0,B64,0,0}, nasm_bytecodes+19663, 544},
    /*   1 : VPCMPUQ kreg|mask,ymmreg,ymmrm256|b64,imm8 [rvmi:fv:  evex.nds.256.66.0f3a.w1 1e /r ib  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 28) 301 001(1e) 120 023 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCMPUQ, 4, {OPMASKREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK,0,B64,0,0}, nasm_bytecodes+19673, 544},
    /*   2 : VPCMPUQ kreg|mask,zmmreg,zmmrm512|b64,imm8 [rvmi:fv:  evex.nds.512.66.0f3a.w1 1e /r ib  ] AVX512,FUTURE */
        /* 241(f3 fd 48) 301 001(1e) 120 023 : EVEX,PROT,AVX512,FUTURE */
        {I_VPCMPUQ, 4, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, {MASK,0,B64,0,0}, nasm_bytecodes+19683, 545},
};

static const struct itemplate instrux_VPCMPUW[3] = {
    /*   0 : VPCMPUW kreg|mask,xmmreg,xmmrm128,imm8 [rvmi:fvm: evex.nds.128.66.0f3a.w1 3e /r ib  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 fd 08) 303 001(3e) 120 023 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPUW, 4, {OPMASKREG,XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK,0,0,0,0}, nasm_bytecodes+19693, 550},
    /*   1 : VPCMPUW kreg|mask,ymmreg,ymmrm256,imm8 [rvmi:fvm: evex.nds.256.66.0f3a.w1 3e /r ib  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 fd 28) 303 001(3e) 120 023 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPUW, 4, {OPMASKREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK,0,0,0,0}, nasm_bytecodes+19703, 550},
    /*   2 : VPCMPUW kreg|mask,zmmreg,zmmrm512,imm8 [rvmi:fvm: evex.nds.512.66.0f3a.w1 3e /r ib  ] AVX512BW,FUTURE */
        /* 241(f3 fd 48) 303 001(3e) 120 023 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPUW, 4, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, {MASK,0,0,0,0}, nasm_bytecodes+19713, 551},
};

static const struct itemplate instrux_VPCMPW[3] = {
    /*   0 : VPCMPW kreg|mask,xmmreg,xmmrm128,imm8 [rvmi:fvm: evex.nds.128.66.0f3a.w1 3f /r ib  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 fd 08) 303 001(3f) 120 023 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPW, 4, {OPMASKREG,XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK,0,0,0,0}, nasm_bytecodes+19723, 550},
    /*   1 : VPCMPW kreg|mask,ymmreg,ymmrm256,imm8 [rvmi:fvm: evex.nds.256.66.0f3a.w1 3f /r ib  ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f3 fd 28) 303 001(3f) 120 023 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPCMPW, 4, {OPMASKREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK,0,0,0,0}, nasm_bytecodes+19733, 550},
    /*   2 : VPCMPW kreg|mask,zmmreg,zmmrm512,imm8 [rvmi:fvm: evex.nds.512.66.0f3a.w1 3f /r ib  ] AVX512BW,FUTURE */
        /* 241(f3 fd 48) 303 001(3f) 120 023 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPCMPW, 4, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, {MASK,0,0,0,0}, nasm_bytecodes+19743, 551},
};

static const struct itemplate instrux_VPCOMPRESSD[6] = {
    /*   0 : VPCOMPRESSD mem128|mask,xmmreg [mr:t1s:   evex.128.66.0f38.w0 8b /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 08) 306 001(8b) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCOMPRESSD, 2, {MEMORY|BITS128,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+37125, 544},
    /*   1 : VPCOMPRESSD mem256|mask,ymmreg [mr:t1s:   evex.256.66.0f38.w0 8b /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 28) 306 001(8b) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCOMPRESSD, 2, {MEMORY|BITS256,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+37134, 544},
    /*   2 : VPCOMPRESSD mem512|mask,zmmreg [mr:t1s:   evex.512.66.0f38.w0 8b /r         ] AVX512,FUTURE */
        /* 250(f2 7d 48) 306 001(8b) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VPCOMPRESSD, 2, {MEMORY|BITS512,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+37143, 545},
    /*   3 : VPCOMPRESSD xmmreg|mask|z,xmmreg [mr:       evex.128.66.0f38.w0 8b /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 08) 300 001(8b) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCOMPRESSD, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+37152, 544},
    /*   4 : VPCOMPRESSD ymmreg|mask|z,ymmreg [mr:       evex.256.66.0f38.w0 8b /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 28) 300 001(8b) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCOMPRESSD, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+37161, 544},
    /*   5 : VPCOMPRESSD zmmreg|mask|z,zmmreg [mr:       evex.512.66.0f38.w0 8b /r         ] AVX512,FUTURE */
        /* 250(f2 7d 48) 300 001(8b) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VPCOMPRESSD, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+37170, 545},
};

static const struct itemplate instrux_VPCOMPRESSQ[6] = {
    /*   0 : VPCOMPRESSQ mem128|mask,xmmreg [mr:t1s:   evex.128.66.0f38.w1 8b /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 fd 08) 306 001(8b) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCOMPRESSQ, 2, {MEMORY|BITS128,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+37179, 544},
    /*   1 : VPCOMPRESSQ mem256|mask,ymmreg [mr:t1s:   evex.256.66.0f38.w1 8b /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 fd 28) 306 001(8b) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCOMPRESSQ, 2, {MEMORY|BITS256,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+37188, 544},
    /*   2 : VPCOMPRESSQ mem512|mask,zmmreg [mr:t1s:   evex.512.66.0f38.w1 8b /r         ] AVX512,FUTURE */
        /* 250(f2 fd 48) 306 001(8b) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VPCOMPRESSQ, 2, {MEMORY|BITS512,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+37197, 545},
    /*   3 : VPCOMPRESSQ xmmreg|mask|z,xmmreg [mr:       evex.128.66.0f38.w1 8b /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 fd 08) 300 001(8b) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCOMPRESSQ, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+37206, 544},
    /*   4 : VPCOMPRESSQ ymmreg|mask|z,ymmreg [mr:       evex.256.66.0f38.w1 8b /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 fd 28) 300 001(8b) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPCOMPRESSQ, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+37215, 544},
    /*   5 : VPCOMPRESSQ zmmreg|mask|z,zmmreg [mr:       evex.512.66.0f38.w1 8b /r         ] AVX512,FUTURE */
        /* 250(f2 fd 48) 300 001(8b) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VPCOMPRESSQ, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+37224, 545},
};

static const struct itemplate instrux_VPCONFLICTD[3] = {
    /*   0 : VPCONFLICTD xmmreg|mask|z,xmmrm128|b32 [rm:fv:    evex.128.66.0f38.w0 c4 /r         ] AVX512CD,AVX512VL,FUTURE */
        /* 250(f2 7d 08) 301 001(c4) 110 : EVEX,PROT,AVX512CD,AVX512VL,FUTURE */
        {I_VPCONFLICTD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+37233, 558},
    /*   1 : VPCONFLICTD ymmreg|mask|z,ymmrm256|b32 [rm:fv:    evex.256.66.0f38.w0 c4 /r         ] AVX512CD,AVX512VL,FUTURE */
        /* 250(f2 7d 28) 301 001(c4) 110 : EVEX,PROT,AVX512CD,AVX512VL,FUTURE */
        {I_VPCONFLICTD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+37242, 558},
    /*   2 : VPCONFLICTD zmmreg|mask|z,zmmrm512|b32 [rm:fv:    evex.512.66.0f38.w0 c4 /r         ] AVX512CD,FUTURE */
        /* 250(f2 7d 48) 301 001(c4) 110 : EVEX,PROT,AVX512CD,FUTURE */
        {I_VPCONFLICTD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+37251, 559},
};

static const struct itemplate instrux_VPCONFLICTQ[3] = {
    /*   0 : VPCONFLICTQ xmmreg|mask|z,xmmrm128|b64 [rm:fv:    evex.128.66.0f38.w1 c4 /r         ] AVX512CD,AVX512VL,FUTURE */
        /* 250(f2 fd 08) 301 001(c4) 110 : EVEX,PROT,AVX512CD,AVX512VL,FUTURE */
        {I_VPCONFLICTQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+37260, 558},
    /*   1 : VPCONFLICTQ ymmreg|mask|z,ymmrm256|b64 [rm:fv:    evex.256.66.0f38.w1 c4 /r         ] AVX512CD,AVX512VL,FUTURE */
        /* 250(f2 fd 28) 301 001(c4) 110 : EVEX,PROT,AVX512CD,AVX512VL,FUTURE */
        {I_VPCONFLICTQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+37269, 558},
    /*   2 : VPCONFLICTQ zmmreg|mask|z,zmmrm512|b64 [rm:fv:    evex.512.66.0f38.w1 c4 /r         ] AVX512CD,FUTURE */
        /* 250(f2 fd 48) 301 001(c4) 110 : EVEX,PROT,AVX512CD,FUTURE */
        {I_VPCONFLICTQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+37278, 559},
};

static const struct itemplate instrux_VPERMB[6] = {
    /*   0 : VPERMB xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f38.w0 8d /r     ] AVX512VL,AVX512VBMI,FUTURE */
        /* 241(f2 7d 08) 303 001(8d) 120 : EVEX,PROT,AVX512VL,AVX512VBMI,FUTURE */
        {I_VPERMB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+37287, 560},
    /*   1 : VPERMB xmmreg|mask|z,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f38.w0 8d /r     ] ND,AVX512VL,AVX512VBMI,FUTURE */
        /* 240(f2 7d 08) 303 001(8d) 110 : EVEX,PROT,AVX512VL,AVX512VBMI,FUTURE */
        {I_VPERMB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+37296, 560},
    /*   2 : VPERMB ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f38.w0 8d /r     ] AVX512VL,AVX512VBMI,FUTURE */
        /* 241(f2 7d 28) 303 001(8d) 120 : EVEX,PROT,AVX512VL,AVX512VBMI,FUTURE */
        {I_VPERMB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+37305, 560},
    /*   3 : VPERMB ymmreg|mask|z,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f38.w0 8d /r     ] ND,AVX512VL,AVX512VBMI,FUTURE */
        /* 240(f2 7d 28) 303 001(8d) 110 : EVEX,PROT,AVX512VL,AVX512VBMI,FUTURE */
        {I_VPERMB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+37314, 560},
    /*   4 : VPERMB zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f38.w0 8d /r     ] AVX512VBMI,FUTURE */
        /* 241(f2 7d 48) 303 001(8d) 120 : EVEX,PROT,AVX512VBMI,FUTURE */
        {I_VPERMB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+37323, 561},
    /*   5 : VPERMB zmmreg|mask|z,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f38.w0 8d /r     ] ND,AVX512VBMI,FUTURE */
        /* 240(f2 7d 48) 303 001(8d) 110 : EVEX,PROT,AVX512VBMI,FUTURE */
        {I_VPERMB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+37332, 561},
};

static const struct itemplate instrux_VPERMI2B[3] = {
    /*   0 : VPERMI2B xmmreg|mask|z,xmmreg,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f38.w0 75 /r     ] AVX512VL,AVX512VBMI,FUTURE */
        /* 241(f2 7d 08) 303 001(75) 120 : EVEX,PROT,AVX512VL,AVX512VBMI,FUTURE */
        {I_VPERMI2B, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+37377, 560},
    /*   1 : VPERMI2B ymmreg|mask|z,ymmreg,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f38.w0 75 /r     ] AVX512VL,AVX512VBMI,FUTURE */
        /* 241(f2 7d 28) 303 001(75) 120 : EVEX,PROT,AVX512VL,AVX512VBMI,FUTURE */
        {I_VPERMI2B, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+37386, 560},
    /*   2 : VPERMI2B zmmreg|mask|z,zmmreg,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f38.w0 75 /r     ] AVX512VBMI,FUTURE */
        /* 241(f2 7d 48) 303 001(75) 120 : EVEX,PROT,AVX512VBMI,FUTURE */
        {I_VPERMI2B, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+37395, 561},
};

static const struct itemplate instrux_VPERMI2D[3] = {
    /*   0 : VPERMI2D xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f38.w0 76 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 08) 301 001(76) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPERMI2D, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+37404, 544},
    /*   1 : VPERMI2D ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f38.w0 76 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 28) 301 001(76) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPERMI2D, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+37413, 544},
    /*   2 : VPERMI2D zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv:   evex.nds.512.66.0f38.w0 76 /r     ] AVX512,FUTURE */
        /* 241(f2 7d 48) 301 001(76) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPERMI2D, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+37422, 545},
};

static const struct itemplate instrux_VPERMI2PD[3] = {
    /*   0 : VPERMI2PD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 77 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 08) 301 001(77) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPERMI2PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+37431, 544},
    /*   1 : VPERMI2PD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 77 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 28) 301 001(77) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPERMI2PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+37440, 544},
    /*   2 : VPERMI2PD zmmreg|mask|z,zmmreg,zmmrm512|b64 [rvm:fv:   evex.nds.512.66.0f38.w1 77 /r     ] AVX512,FUTURE */
        /* 241(f2 fd 48) 301 001(77) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPERMI2PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+37449, 545},
};

static const struct itemplate instrux_VPERMI2PS[3] = {
    /*   0 : VPERMI2PS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f38.w0 77 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 08) 301 001(77) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPERMI2PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+37458, 544},
    /*   1 : VPERMI2PS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f38.w0 77 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 28) 301 001(77) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPERMI2PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+37467, 544},
    /*   2 : VPERMI2PS zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv:   evex.nds.512.66.0f38.w0 77 /r     ] AVX512,FUTURE */
        /* 241(f2 7d 48) 301 001(77) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPERMI2PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+37476, 545},
};

static const struct itemplate instrux_VPERMI2Q[3] = {
    /*   0 : VPERMI2Q xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 76 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 08) 301 001(76) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPERMI2Q, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+37485, 544},
    /*   1 : VPERMI2Q ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 76 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 28) 301 001(76) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPERMI2Q, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+37494, 544},
    /*   2 : VPERMI2Q zmmreg|mask|z,zmmreg,zmmrm512|b64 [rvm:fv:   evex.nds.512.66.0f38.w1 76 /r     ] AVX512,FUTURE */
        /* 241(f2 fd 48) 301 001(76) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPERMI2Q, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+37503, 545},
};

static const struct itemplate instrux_VPERMI2W[3] = {
    /*   0 : VPERMI2W xmmreg|mask|z,xmmreg,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f38.w1 75 /r     ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f2 fd 08) 303 001(75) 120 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPERMI2W, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+37512, 550},
    /*   1 : VPERMI2W ymmreg|mask|z,ymmreg,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f38.w1 75 /r     ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f2 fd 28) 303 001(75) 120 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPERMI2W, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+37521, 550},
    /*   2 : VPERMI2W zmmreg|mask|z,zmmreg,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f38.w1 75 /r     ] AVX512BW,FUTURE */
        /* 241(f2 fd 48) 303 001(75) 120 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPERMI2W, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+37530, 551},
};

static const struct itemplate instrux_VPERMT2B[3] = {
    /*   0 : VPERMT2B xmmreg|mask|z,xmmreg,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f38.w0 7d /r     ] AVX512VL,AVX512VBMI,FUTURE */
        /* 241(f2 7d 08) 303 001(7d) 120 : EVEX,PROT,AVX512VL,AVX512VBMI,FUTURE */
        {I_VPERMT2B, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+37755, 560},
    /*   1 : VPERMT2B ymmreg|mask|z,ymmreg,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f38.w0 7d /r     ] AVX512VL,AVX512VBMI,FUTURE */
        /* 241(f2 7d 28) 303 001(7d) 120 : EVEX,PROT,AVX512VL,AVX512VBMI,FUTURE */
        {I_VPERMT2B, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+37764, 560},
    /*   2 : VPERMT2B zmmreg|mask|z,zmmreg,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f38.w0 7d /r     ] AVX512VBMI,FUTURE */
        /* 241(f2 7d 48) 303 001(7d) 120 : EVEX,PROT,AVX512VBMI,FUTURE */
        {I_VPERMT2B, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+37773, 561},
};

static const struct itemplate instrux_VPERMT2D[3] = {
    /*   0 : VPERMT2D xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f38.w0 7e /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 08) 301 001(7e) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPERMT2D, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+37782, 544},
    /*   1 : VPERMT2D ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f38.w0 7e /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 28) 301 001(7e) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPERMT2D, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+37791, 544},
    /*   2 : VPERMT2D zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv:   evex.nds.512.66.0f38.w0 7e /r     ] AVX512,FUTURE */
        /* 241(f2 7d 48) 301 001(7e) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPERMT2D, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+37800, 545},
};

static const struct itemplate instrux_VPERMT2PD[3] = {
    /*   0 : VPERMT2PD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 7f /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 08) 301 001(7f) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPERMT2PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+37809, 544},
    /*   1 : VPERMT2PD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 7f /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 28) 301 001(7f) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPERMT2PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+37818, 544},
    /*   2 : VPERMT2PD zmmreg|mask|z,zmmreg,zmmrm512|b64 [rvm:fv:   evex.nds.512.66.0f38.w1 7f /r     ] AVX512,FUTURE */
        /* 241(f2 fd 48) 301 001(7f) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPERMT2PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+37827, 545},
};

static const struct itemplate instrux_VPERMT2PS[3] = {
    /*   0 : VPERMT2PS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f38.w0 7f /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 08) 301 001(7f) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPERMT2PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+37836, 544},
    /*   1 : VPERMT2PS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f38.w0 7f /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 28) 301 001(7f) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPERMT2PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+37845, 544},
    /*   2 : VPERMT2PS zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv:   evex.nds.512.66.0f38.w0 7f /r     ] AVX512,FUTURE */
        /* 241(f2 7d 48) 301 001(7f) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPERMT2PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+37854, 545},
};

static const struct itemplate instrux_VPERMT2Q[3] = {
    /*   0 : VPERMT2Q xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 7e /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 08) 301 001(7e) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPERMT2Q, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+37863, 544},
    /*   1 : VPERMT2Q ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 7e /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 28) 301 001(7e) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPERMT2Q, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+37872, 544},
    /*   2 : VPERMT2Q zmmreg|mask|z,zmmreg,zmmrm512|b64 [rvm:fv:   evex.nds.512.66.0f38.w1 7e /r     ] AVX512,FUTURE */
        /* 241(f2 fd 48) 301 001(7e) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPERMT2Q, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+37881, 545},
};

static const struct itemplate instrux_VPERMT2W[3] = {
    /*   0 : VPERMT2W xmmreg|mask|z,xmmreg,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f38.w1 7d /r     ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f2 fd 08) 303 001(7d) 120 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPERMT2W, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+37890, 550},
    /*   1 : VPERMT2W ymmreg|mask|z,ymmreg,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f38.w1 7d /r     ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f2 fd 28) 303 001(7d) 120 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPERMT2W, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+37899, 550},
    /*   2 : VPERMT2W zmmreg|mask|z,zmmreg,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f38.w1 7d /r     ] AVX512BW,FUTURE */
        /* 241(f2 fd 48) 303 001(7d) 120 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPERMT2W, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+37908, 551},
};

static const struct itemplate instrux_VPERMW[6] = {
    /*   0 : VPERMW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f38.w1 8d /r     ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f2 fd 08) 303 001(8d) 120 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPERMW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+37917, 550},
    /*   1 : VPERMW xmmreg|mask|z,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f38.w1 8d /r     ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f2 fd 08) 303 001(8d) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPERMW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+37926, 550},
    /*   2 : VPERMW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f38.w1 8d /r     ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f2 fd 28) 303 001(8d) 120 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPERMW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+37935, 550},
    /*   3 : VPERMW ymmreg|mask|z,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f38.w1 8d /r     ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f2 fd 28) 303 001(8d) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPERMW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+37944, 550},
    /*   4 : VPERMW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f38.w1 8d /r     ] AVX512BW,FUTURE */
        /* 241(f2 fd 48) 303 001(8d) 120 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPERMW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+37953, 551},
    /*   5 : VPERMW zmmreg|mask|z,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f38.w1 8d /r     ] ND,AVX512BW,FUTURE */
        /* 240(f2 fd 48) 303 001(8d) 110 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPERMW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+37962, 551},
};

static const struct itemplate instrux_VPEXPANDD[6] = {
    /*   0 : VPEXPANDD xmmreg|mask|z,mem128 [rm:t1s:   evex.128.66.0f38.w0 89 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 08) 306 001(89) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPEXPANDD, 2, {XMMREG,MEMORY|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+37971, 544},
    /*   1 : VPEXPANDD ymmreg|mask|z,mem256 [rm:t1s:   evex.256.66.0f38.w0 89 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 28) 306 001(89) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPEXPANDD, 2, {YMMREG,MEMORY|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+37980, 544},
    /*   2 : VPEXPANDD zmmreg|mask|z,mem512 [rm:t1s:   evex.512.66.0f38.w0 89 /r         ] AVX512,FUTURE */
        /* 250(f2 7d 48) 306 001(89) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPEXPANDD, 2, {ZMMREG,MEMORY|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+37989, 545},
    /*   3 : VPEXPANDD xmmreg|mask|z,xmmreg [rm:t1s:   evex.128.66.0f38.w0 89 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 08) 306 001(89) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPEXPANDD, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+37971, 544},
    /*   4 : VPEXPANDD ymmreg|mask|z,ymmreg [rm:t1s:   evex.256.66.0f38.w0 89 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 28) 306 001(89) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPEXPANDD, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+37980, 544},
    /*   5 : VPEXPANDD zmmreg|mask|z,zmmreg [rm:t1s:   evex.512.66.0f38.w0 89 /r         ] AVX512,FUTURE */
        /* 250(f2 7d 48) 306 001(89) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPEXPANDD, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+37989, 545},
};

static const struct itemplate instrux_VPEXPANDQ[6] = {
    /*   0 : VPEXPANDQ xmmreg|mask|z,mem128 [rm:t1s:   evex.128.66.0f38.w1 89 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 fd 08) 306 001(89) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPEXPANDQ, 2, {XMMREG,MEMORY|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+37998, 544},
    /*   1 : VPEXPANDQ ymmreg|mask|z,mem256 [rm:t1s:   evex.256.66.0f38.w1 89 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 fd 28) 306 001(89) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPEXPANDQ, 2, {YMMREG,MEMORY|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38007, 544},
    /*   2 : VPEXPANDQ zmmreg|mask|z,mem512 [rm:t1s:   evex.512.66.0f38.w1 89 /r         ] AVX512,FUTURE */
        /* 250(f2 fd 48) 306 001(89) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPEXPANDQ, 2, {ZMMREG,MEMORY|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38016, 545},
    /*   3 : VPEXPANDQ xmmreg|mask|z,xmmreg [rm:t1s:   evex.128.66.0f38.w1 89 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 fd 08) 306 001(89) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPEXPANDQ, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+37998, 544},
    /*   4 : VPEXPANDQ ymmreg|mask|z,ymmreg [rm:t1s:   evex.256.66.0f38.w1 89 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 fd 28) 306 001(89) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPEXPANDQ, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38007, 544},
    /*   5 : VPEXPANDQ zmmreg|mask|z,zmmreg [rm:t1s:   evex.512.66.0f38.w1 89 /r         ] AVX512,FUTURE */
        /* 250(f2 fd 48) 306 001(89) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPEXPANDQ, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+38016, 545},
};

static const struct itemplate instrux_VPLZCNTD[3] = {
    /*   0 : VPLZCNTD xmmreg|mask|z,xmmrm128|b32 [rm:fv:    evex.128.66.0f38.w0 44 /r         ] AVX512CD,AVX512VL,FUTURE */
        /* 250(f2 7d 08) 301 001(44) 110 : EVEX,PROT,AVX512CD,AVX512VL,FUTURE */
        {I_VPLZCNTD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+38025, 558},
    /*   1 : VPLZCNTD ymmreg|mask|z,ymmrm256|b32 [rm:fv:    evex.256.66.0f38.w0 44 /r         ] AVX512CD,AVX512VL,FUTURE */
        /* 250(f2 7d 28) 301 001(44) 110 : EVEX,PROT,AVX512CD,AVX512VL,FUTURE */
        {I_VPLZCNTD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+38034, 558},
    /*   2 : VPLZCNTD zmmreg|mask|z,zmmrm512|b32 [rm:fv:    evex.512.66.0f38.w0 44 /r         ] AVX512CD,FUTURE */
        /* 250(f2 7d 48) 301 001(44) 110 : EVEX,PROT,AVX512CD,FUTURE */
        {I_VPLZCNTD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+38043, 559},
};

static const struct itemplate instrux_VPLZCNTQ[3] = {
    /*   0 : VPLZCNTQ xmmreg|mask|z,xmmrm128|b64 [rm:fv:    evex.128.66.0f38.w1 44 /r         ] AVX512CD,AVX512VL,FUTURE */
        /* 250(f2 fd 08) 301 001(44) 110 : EVEX,PROT,AVX512CD,AVX512VL,FUTURE */
        {I_VPLZCNTQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+38052, 558},
    /*   1 : VPLZCNTQ ymmreg|mask|z,ymmrm256|b64 [rm:fv:    evex.256.66.0f38.w1 44 /r         ] AVX512CD,AVX512VL,FUTURE */
        /* 250(f2 fd 28) 301 001(44) 110 : EVEX,PROT,AVX512CD,AVX512VL,FUTURE */
        {I_VPLZCNTQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+38061, 558},
    /*   2 : VPLZCNTQ zmmreg|mask|z,zmmrm512|b64 [rm:fv:    evex.512.66.0f38.w1 44 /r         ] AVX512CD,FUTURE */
        /* 250(f2 fd 48) 301 001(44) 110 : EVEX,PROT,AVX512CD,FUTURE */
        {I_VPLZCNTQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+38070, 559},
};

static const struct itemplate instrux_VPMAXSQ[6] = {
    /*   0 : VPMAXSQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 3d /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 08) 301 001(3d) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMAXSQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+38349, 544},
    /*   1 : VPMAXSQ xmmreg|mask|z,xmmrm128|b64 [r+vm:fv:   evex.nds.128.66.0f38.w1 3d /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 fd 08) 301 001(3d) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMAXSQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+38358, 544},
    /*   2 : VPMAXSQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 3d /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 28) 301 001(3d) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMAXSQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+38367, 544},
    /*   3 : VPMAXSQ ymmreg|mask|z,ymmrm256|b64 [r+vm:fv:   evex.nds.256.66.0f38.w1 3d /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 fd 28) 301 001(3d) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMAXSQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+38376, 544},
    /*   4 : VPMAXSQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv:   evex.nds.512.66.0f38.w1 3d /r     ] AVX512,FUTURE */
        /* 241(f2 fd 48) 301 001(3d) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMAXSQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+38385, 545},
    /*   5 : VPMAXSQ zmmreg|mask|z,zmmrm512|b64 [r+vm:fv:   evex.nds.512.66.0f38.w1 3d /r     ] ND,AVX512,FUTURE */
        /* 240(f2 fd 48) 301 001(3d) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMAXSQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+38394, 545},
};

static const struct itemplate instrux_VPMAXUQ[6] = {
    /*   0 : VPMAXUQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 3f /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 08) 301 001(3f) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMAXUQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+38565, 544},
    /*   1 : VPMAXUQ xmmreg|mask|z,xmmrm128|b64 [r+vm:fv:   evex.nds.128.66.0f38.w1 3f /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 fd 08) 301 001(3f) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMAXUQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+38574, 544},
    /*   2 : VPMAXUQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 3f /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 28) 301 001(3f) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMAXUQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+38583, 544},
    /*   3 : VPMAXUQ ymmreg|mask|z,ymmrm256|b64 [r+vm:fv:   evex.nds.256.66.0f38.w1 3f /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 fd 28) 301 001(3f) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMAXUQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+38592, 544},
    /*   4 : VPMAXUQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv:   evex.nds.512.66.0f38.w1 3f /r     ] AVX512,FUTURE */
        /* 241(f2 fd 48) 301 001(3f) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMAXUQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+38601, 545},
    /*   5 : VPMAXUQ zmmreg|mask|z,zmmrm512|b64 [r+vm:fv:   evex.nds.512.66.0f38.w1 3f /r     ] ND,AVX512,FUTURE */
        /* 240(f2 fd 48) 301 001(3f) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMAXUQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+38610, 545},
};

static const struct itemplate instrux_VPMINSQ[6] = {
    /*   0 : VPMINSQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 39 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 08) 301 001(39) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMINSQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+38781, 544},
    /*   1 : VPMINSQ xmmreg|mask|z,xmmrm128|b64 [r+vm:fv:   evex.nds.128.66.0f38.w1 39 /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 fd 08) 301 001(39) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMINSQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+38790, 544},
    /*   2 : VPMINSQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 39 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 28) 301 001(39) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMINSQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+38799, 544},
    /*   3 : VPMINSQ ymmreg|mask|z,ymmrm256|b64 [r+vm:fv:   evex.nds.256.66.0f38.w1 39 /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 fd 28) 301 001(39) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMINSQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+38808, 544},
    /*   4 : VPMINSQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv:   evex.nds.512.66.0f38.w1 39 /r     ] AVX512,FUTURE */
        /* 241(f2 fd 48) 301 001(39) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMINSQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+38817, 545},
    /*   5 : VPMINSQ zmmreg|mask|z,zmmrm512|b64 [r+vm:fv:   evex.nds.512.66.0f38.w1 39 /r     ] ND,AVX512,FUTURE */
        /* 240(f2 fd 48) 301 001(39) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMINSQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+38826, 545},
};

static const struct itemplate instrux_VPMINUQ[6] = {
    /*   0 : VPMINUQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 3b /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 08) 301 001(3b) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMINUQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+38997, 544},
    /*   1 : VPMINUQ xmmreg|mask|z,xmmrm128|b64 [r+vm:fv:   evex.nds.128.66.0f38.w1 3b /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 fd 08) 301 001(3b) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMINUQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+39006, 544},
    /*   2 : VPMINUQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 3b /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 28) 301 001(3b) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMINUQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+39015, 544},
    /*   3 : VPMINUQ ymmreg|mask|z,ymmrm256|b64 [r+vm:fv:   evex.nds.256.66.0f38.w1 3b /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 fd 28) 301 001(3b) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMINUQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+39024, 544},
    /*   4 : VPMINUQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv:   evex.nds.512.66.0f38.w1 3b /r     ] AVX512,FUTURE */
        /* 241(f2 fd 48) 301 001(3b) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMINUQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+39033, 545},
    /*   5 : VPMINUQ zmmreg|mask|z,zmmrm512|b64 [r+vm:fv:   evex.nds.512.66.0f38.w1 3b /r     ] ND,AVX512,FUTURE */
        /* 240(f2 fd 48) 301 001(3b) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMINUQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+39042, 545},
};

static const struct itemplate instrux_VPMOVB2M[3] = {
    /*   0 : VPMOVB2M kreg,xmmreg [rm:       evex.128.f3.0f38.w0 29 /r         ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7e 08) 300 001(29) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMOVB2M, 2, {OPMASKREG,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+39105, 550},
    /*   1 : VPMOVB2M kreg,ymmreg [rm:       evex.256.f3.0f38.w0 29 /r         ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7e 28) 300 001(29) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMOVB2M, 2, {OPMASKREG,YMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+39114, 550},
    /*   2 : VPMOVB2M kreg,zmmreg [rm:       evex.512.f3.0f38.w0 29 /r         ] AVX512BW,FUTURE */
        /* 250(f2 7e 48) 300 001(29) 110 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPMOVB2M, 2, {OPMASKREG,ZMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+39123, 551},
};

static const struct itemplate instrux_VPMOVD2M[3] = {
    /*   0 : VPMOVD2M kreg,xmmreg [rm:       evex.128.f3.0f38.w0 39 /r         ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f2 7e 08) 300 001(39) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VPMOVD2M, 2, {OPMASKREG,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+39132, 547},
    /*   1 : VPMOVD2M kreg,ymmreg [rm:       evex.256.f3.0f38.w0 39 /r         ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f2 7e 28) 300 001(39) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VPMOVD2M, 2, {OPMASKREG,YMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+39141, 547},
    /*   2 : VPMOVD2M kreg,zmmreg [rm:       evex.512.f3.0f38.w0 39 /r         ] AVX512DQ,FUTURE */
        /* 250(f2 7e 48) 300 001(39) 110 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VPMOVD2M, 2, {OPMASKREG,ZMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+39150, 548},
};

static const struct itemplate instrux_VPMOVDB[6] = {
    /*   0 : VPMOVDB xmmreg|mask|z,xmmreg [mr:       evex.128.f3.0f38.w0 31 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 08) 300 001(31) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVDB, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39159, 544},
    /*   1 : VPMOVDB xmmreg|mask|z,ymmreg [mr:       evex.256.f3.0f38.w0 31 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 28) 300 001(31) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVDB, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39168, 544},
    /*   2 : VPMOVDB xmmreg|mask|z,zmmreg [mr:       evex.512.f3.0f38.w0 31 /r         ] AVX512,FUTURE */
        /* 250(f2 7e 48) 300 001(31) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMOVDB, 2, {XMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39177, 545},
    /*   3 : VPMOVDB mem32|mask,xmmreg [mr:qvm:   evex.128.f3.0f38.w0 31 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 08) 315 001(31) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVDB, 2, {MEMORY|BITS32,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+39186, 544},
    /*   4 : VPMOVDB mem64|mask,ymmreg [mr:qvm:   evex.256.f3.0f38.w0 31 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 28) 315 001(31) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVDB, 2, {MEMORY|BITS64,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+39195, 544},
    /*   5 : VPMOVDB mem128|mask,zmmreg [mr:qvm:   evex.512.f3.0f38.w0 31 /r         ] AVX512,FUTURE */
        /* 250(f2 7e 48) 315 001(31) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMOVDB, 2, {MEMORY|BITS128,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+39204, 545},
};

static const struct itemplate instrux_VPMOVDW[6] = {
    /*   0 : VPMOVDW xmmreg|mask|z,xmmreg [mr:       evex.128.f3.0f38.w0 33 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 08) 300 001(33) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVDW, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39213, 544},
    /*   1 : VPMOVDW xmmreg|mask|z,ymmreg [mr:       evex.256.f3.0f38.w0 33 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 28) 300 001(33) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVDW, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39222, 544},
    /*   2 : VPMOVDW ymmreg|mask|z,zmmreg [mr:       evex.512.f3.0f38.w0 33 /r         ] AVX512,FUTURE */
        /* 250(f2 7e 48) 300 001(33) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMOVDW, 2, {YMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39231, 545},
    /*   3 : VPMOVDW mem64|mask,xmmreg [mr:hvm:   evex.128.f3.0f38.w0 33 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 08) 314 001(33) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVDW, 2, {MEMORY|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+39240, 544},
    /*   4 : VPMOVDW mem128|mask,ymmreg [mr:hvm:   evex.256.f3.0f38.w0 33 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 28) 314 001(33) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVDW, 2, {MEMORY|BITS128,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+39249, 544},
    /*   5 : VPMOVDW mem256|mask,zmmreg [mr:hvm:   evex.512.f3.0f38.w0 33 /r         ] AVX512,FUTURE */
        /* 250(f2 7e 48) 314 001(33) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMOVDW, 2, {MEMORY|BITS256,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+39258, 545},
};

static const struct itemplate instrux_VPMOVM2B[3] = {
    /*   0 : VPMOVM2B xmmreg,kreg [rm:       evex.128.f3.0f38.w0 28 /r         ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7e 08) 300 001(28) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMOVM2B, 2, {XMMREG,OPMASKREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+39267, 550},
    /*   1 : VPMOVM2B ymmreg,kreg [rm:       evex.256.f3.0f38.w0 28 /r         ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7e 28) 300 001(28) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMOVM2B, 2, {YMMREG,OPMASKREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+39276, 550},
    /*   2 : VPMOVM2B zmmreg,kreg [rm:       evex.512.f3.0f38.w0 28 /r         ] AVX512BW,FUTURE */
        /* 250(f2 7e 48) 300 001(28) 110 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPMOVM2B, 2, {ZMMREG,OPMASKREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+39285, 551},
};

static const struct itemplate instrux_VPMOVM2D[3] = {
    /*   0 : VPMOVM2D xmmreg,kreg [rm:       evex.128.f3.0f38.w0 38 /r         ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f2 7e 08) 300 001(38) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VPMOVM2D, 2, {XMMREG,OPMASKREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+39294, 547},
    /*   1 : VPMOVM2D ymmreg,kreg [rm:       evex.256.f3.0f38.w0 38 /r         ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f2 7e 28) 300 001(38) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VPMOVM2D, 2, {YMMREG,OPMASKREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+39303, 547},
    /*   2 : VPMOVM2D zmmreg,kreg [rm:       evex.512.f3.0f38.w0 38 /r         ] AVX512DQ,FUTURE */
        /* 250(f2 7e 48) 300 001(38) 110 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VPMOVM2D, 2, {ZMMREG,OPMASKREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+39312, 548},
};

static const struct itemplate instrux_VPMOVM2Q[3] = {
    /*   0 : VPMOVM2Q xmmreg,kreg [rm:       evex.128.f3.0f38.w1 38 /r         ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f2 fe 08) 300 001(38) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VPMOVM2Q, 2, {XMMREG,OPMASKREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+39321, 547},
    /*   1 : VPMOVM2Q ymmreg,kreg [rm:       evex.256.f3.0f38.w1 38 /r         ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f2 fe 28) 300 001(38) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VPMOVM2Q, 2, {YMMREG,OPMASKREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+39330, 547},
    /*   2 : VPMOVM2Q zmmreg,kreg [rm:       evex.512.f3.0f38.w1 38 /r         ] AVX512DQ,FUTURE */
        /* 250(f2 fe 48) 300 001(38) 110 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VPMOVM2Q, 2, {ZMMREG,OPMASKREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+39339, 548},
};

static const struct itemplate instrux_VPMOVM2W[3] = {
    /*   0 : VPMOVM2W xmmreg,kreg [rm:       evex.128.f3.0f38.w1 28 /r         ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 fe 08) 300 001(28) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMOVM2W, 2, {XMMREG,OPMASKREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+39348, 550},
    /*   1 : VPMOVM2W ymmreg,kreg [rm:       evex.256.f3.0f38.w1 28 /r         ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 fe 28) 300 001(28) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMOVM2W, 2, {YMMREG,OPMASKREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+39357, 550},
    /*   2 : VPMOVM2W zmmreg,kreg [rm:       evex.512.f3.0f38.w1 28 /r         ] AVX512BW,FUTURE */
        /* 250(f2 fe 48) 300 001(28) 110 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPMOVM2W, 2, {ZMMREG,OPMASKREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+39366, 551},
};

static const struct itemplate instrux_VPMOVQ2M[3] = {
    /*   0 : VPMOVQ2M kreg,xmmreg [rm:       evex.128.f3.0f38.w1 39 /r         ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f2 fe 08) 300 001(39) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VPMOVQ2M, 2, {OPMASKREG,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+39375, 547},
    /*   1 : VPMOVQ2M kreg,ymmreg [rm:       evex.256.f3.0f38.w1 39 /r         ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f2 fe 28) 300 001(39) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VPMOVQ2M, 2, {OPMASKREG,YMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+39384, 547},
    /*   2 : VPMOVQ2M kreg,zmmreg [rm:       evex.512.f3.0f38.w1 39 /r         ] AVX512DQ,FUTURE */
        /* 250(f2 fe 48) 300 001(39) 110 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VPMOVQ2M, 2, {OPMASKREG,ZMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+39393, 548},
};

static const struct itemplate instrux_VPMOVQB[6] = {
    /*   0 : VPMOVQB xmmreg|mask|z,xmmreg [mr:       evex.128.f3.0f38.w0 32 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 08) 300 001(32) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVQB, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39402, 544},
    /*   1 : VPMOVQB xmmreg|mask|z,ymmreg [mr:       evex.256.f3.0f38.w0 32 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 28) 300 001(32) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVQB, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39411, 544},
    /*   2 : VPMOVQB xmmreg|mask|z,zmmreg [mr:       evex.512.f3.0f38.w0 32 /r         ] AVX512,FUTURE */
        /* 250(f2 7e 48) 300 001(32) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMOVQB, 2, {XMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39420, 545},
    /*   3 : VPMOVQB mem16|mask,xmmreg [mr:ovm:   evex.128.f3.0f38.w0 32 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 08) 316 001(32) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVQB, 2, {MEMORY|BITS16,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+39429, 544},
    /*   4 : VPMOVQB mem32|mask,ymmreg [mr:ovm:   evex.256.f3.0f38.w0 32 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 28) 316 001(32) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVQB, 2, {MEMORY|BITS32,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+39438, 544},
    /*   5 : VPMOVQB mem64|mask,zmmreg [mr:ovm:   evex.512.f3.0f38.w0 32 /r         ] AVX512,FUTURE */
        /* 250(f2 7e 48) 316 001(32) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMOVQB, 2, {MEMORY|BITS64,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+39447, 545},
};

static const struct itemplate instrux_VPMOVQD[6] = {
    /*   0 : VPMOVQD xmmreg|mask|z,xmmreg [mr:       evex.128.f3.0f38.w0 35 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 08) 300 001(35) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVQD, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39456, 544},
    /*   1 : VPMOVQD xmmreg|mask|z,ymmreg [mr:       evex.256.f3.0f38.w0 35 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 28) 300 001(35) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVQD, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39465, 544},
    /*   2 : VPMOVQD ymmreg|mask|z,zmmreg [mr:       evex.512.f3.0f38.w0 35 /r         ] AVX512,FUTURE */
        /* 250(f2 7e 48) 300 001(35) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMOVQD, 2, {YMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39474, 545},
    /*   3 : VPMOVQD mem64|mask,xmmreg [mr:hvm:   evex.128.f3.0f38.w0 35 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 08) 314 001(35) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVQD, 2, {MEMORY|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+39483, 544},
    /*   4 : VPMOVQD mem128|mask,ymmreg [mr:hvm:   evex.256.f3.0f38.w0 35 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 28) 314 001(35) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVQD, 2, {MEMORY|BITS128,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+39492, 544},
    /*   5 : VPMOVQD mem256|mask,zmmreg [mr:hvm:   evex.512.f3.0f38.w0 35 /r         ] AVX512,FUTURE */
        /* 250(f2 7e 48) 314 001(35) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMOVQD, 2, {MEMORY|BITS256,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+39501, 545},
};

static const struct itemplate instrux_VPMOVQW[6] = {
    /*   0 : VPMOVQW xmmreg|mask|z,xmmreg [mr:       evex.128.f3.0f38.w0 34 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 08) 300 001(34) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVQW, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39510, 544},
    /*   1 : VPMOVQW xmmreg|mask|z,ymmreg [mr:       evex.256.f3.0f38.w0 34 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 28) 300 001(34) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVQW, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39519, 544},
    /*   2 : VPMOVQW xmmreg|mask|z,zmmreg [mr:       evex.512.f3.0f38.w0 34 /r         ] AVX512,FUTURE */
        /* 250(f2 7e 48) 300 001(34) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMOVQW, 2, {XMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39528, 545},
    /*   3 : VPMOVQW mem32|mask,xmmreg [mr:qvm:   evex.128.f3.0f38.w0 34 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 08) 315 001(34) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVQW, 2, {MEMORY|BITS32,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+39537, 544},
    /*   4 : VPMOVQW mem64|mask,ymmreg [mr:qvm:   evex.256.f3.0f38.w0 34 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 28) 315 001(34) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVQW, 2, {MEMORY|BITS64,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+39546, 544},
    /*   5 : VPMOVQW mem128|mask,zmmreg [mr:qvm:   evex.512.f3.0f38.w0 34 /r         ] AVX512,FUTURE */
        /* 250(f2 7e 48) 315 001(34) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMOVQW, 2, {MEMORY|BITS128,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+39555, 545},
};

static const struct itemplate instrux_VPMOVSDB[6] = {
    /*   0 : VPMOVSDB xmmreg|mask|z,xmmreg [mr:       evex.128.f3.0f38.w0 21 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 08) 300 001(21) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVSDB, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39564, 544},
    /*   1 : VPMOVSDB xmmreg|mask|z,ymmreg [mr:       evex.256.f3.0f38.w0 21 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 28) 300 001(21) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVSDB, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39573, 544},
    /*   2 : VPMOVSDB xmmreg|mask|z,zmmreg [mr:       evex.512.f3.0f38.w0 21 /r         ] AVX512,FUTURE */
        /* 250(f2 7e 48) 300 001(21) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMOVSDB, 2, {XMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39582, 545},
    /*   3 : VPMOVSDB mem32|mask,xmmreg [mr:qvm:   evex.128.f3.0f38.w0 21 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 08) 315 001(21) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVSDB, 2, {MEMORY|BITS32,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+39591, 544},
    /*   4 : VPMOVSDB mem64|mask,ymmreg [mr:qvm:   evex.256.f3.0f38.w0 21 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 28) 315 001(21) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVSDB, 2, {MEMORY|BITS64,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+39600, 544},
    /*   5 : VPMOVSDB mem128|mask,zmmreg [mr:qvm:   evex.512.f3.0f38.w0 21 /r         ] AVX512,FUTURE */
        /* 250(f2 7e 48) 315 001(21) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMOVSDB, 2, {MEMORY|BITS128,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+39609, 545},
};

static const struct itemplate instrux_VPMOVSDW[6] = {
    /*   0 : VPMOVSDW xmmreg|mask|z,xmmreg [mr:       evex.128.f3.0f38.w0 23 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 08) 300 001(23) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVSDW, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39618, 544},
    /*   1 : VPMOVSDW xmmreg|mask|z,ymmreg [mr:       evex.256.f3.0f38.w0 23 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 28) 300 001(23) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVSDW, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39627, 544},
    /*   2 : VPMOVSDW ymmreg|mask|z,zmmreg [mr:       evex.512.f3.0f38.w0 23 /r         ] AVX512,FUTURE */
        /* 250(f2 7e 48) 300 001(23) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMOVSDW, 2, {YMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39636, 545},
    /*   3 : VPMOVSDW mem64|mask,xmmreg [mr:hvm:   evex.128.f3.0f38.w0 23 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 08) 314 001(23) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVSDW, 2, {MEMORY|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+39645, 544},
    /*   4 : VPMOVSDW mem128|mask,ymmreg [mr:hvm:   evex.256.f3.0f38.w0 23 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 28) 314 001(23) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVSDW, 2, {MEMORY|BITS128,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+39654, 544},
    /*   5 : VPMOVSDW mem256|mask,zmmreg [mr:hvm:   evex.512.f3.0f38.w0 23 /r         ] AVX512,FUTURE */
        /* 250(f2 7e 48) 314 001(23) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMOVSDW, 2, {MEMORY|BITS256,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+39663, 545},
};

static const struct itemplate instrux_VPMOVSQB[6] = {
    /*   0 : VPMOVSQB xmmreg|mask|z,xmmreg [mr:       evex.128.f3.0f38.w0 22 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 08) 300 001(22) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVSQB, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39672, 544},
    /*   1 : VPMOVSQB xmmreg|mask|z,ymmreg [mr:       evex.256.f3.0f38.w0 22 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 28) 300 001(22) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVSQB, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39681, 544},
    /*   2 : VPMOVSQB xmmreg|mask|z,zmmreg [mr:       evex.512.f3.0f38.w0 22 /r         ] AVX512,FUTURE */
        /* 250(f2 7e 48) 300 001(22) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMOVSQB, 2, {XMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39690, 545},
    /*   3 : VPMOVSQB mem16|mask,xmmreg [mr:ovm:   evex.128.f3.0f38.w0 22 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 08) 316 001(22) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVSQB, 2, {MEMORY|BITS16,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+39699, 544},
    /*   4 : VPMOVSQB mem32|mask,ymmreg [mr:ovm:   evex.256.f3.0f38.w0 22 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 28) 316 001(22) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVSQB, 2, {MEMORY|BITS32,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+39708, 544},
    /*   5 : VPMOVSQB mem64|mask,zmmreg [mr:ovm:   evex.512.f3.0f38.w0 22 /r         ] AVX512,FUTURE */
        /* 250(f2 7e 48) 316 001(22) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMOVSQB, 2, {MEMORY|BITS64,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+39717, 545},
};

static const struct itemplate instrux_VPMOVSQD[6] = {
    /*   0 : VPMOVSQD xmmreg|mask|z,xmmreg [mr:       evex.128.f3.0f38.w0 25 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 08) 300 001(25) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVSQD, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39726, 544},
    /*   1 : VPMOVSQD xmmreg|mask|z,ymmreg [mr:       evex.256.f3.0f38.w0 25 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 28) 300 001(25) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVSQD, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39735, 544},
    /*   2 : VPMOVSQD ymmreg|mask|z,zmmreg [mr:       evex.512.f3.0f38.w0 25 /r         ] AVX512,FUTURE */
        /* 250(f2 7e 48) 300 001(25) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMOVSQD, 2, {YMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39744, 545},
    /*   3 : VPMOVSQD mem64|mask,xmmreg [mr:hvm:   evex.128.f3.0f38.w0 25 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 08) 314 001(25) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVSQD, 2, {MEMORY|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+39753, 544},
    /*   4 : VPMOVSQD mem128|mask,ymmreg [mr:hvm:   evex.256.f3.0f38.w0 25 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 28) 314 001(25) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVSQD, 2, {MEMORY|BITS128,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+39762, 544},
    /*   5 : VPMOVSQD mem256|mask,zmmreg [mr:hvm:   evex.512.f3.0f38.w0 25 /r         ] AVX512,FUTURE */
        /* 250(f2 7e 48) 314 001(25) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMOVSQD, 2, {MEMORY|BITS256,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+39771, 545},
};

static const struct itemplate instrux_VPMOVSQW[6] = {
    /*   0 : VPMOVSQW xmmreg|mask|z,xmmreg [mr:       evex.128.f3.0f38.w0 24 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 08) 300 001(24) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVSQW, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39780, 544},
    /*   1 : VPMOVSQW xmmreg|mask|z,ymmreg [mr:       evex.256.f3.0f38.w0 24 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 28) 300 001(24) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVSQW, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39789, 544},
    /*   2 : VPMOVSQW xmmreg|mask|z,zmmreg [mr:       evex.512.f3.0f38.w0 24 /r         ] AVX512,FUTURE */
        /* 250(f2 7e 48) 300 001(24) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMOVSQW, 2, {XMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39798, 545},
    /*   3 : VPMOVSQW mem32|mask,xmmreg [mr:qvm:   evex.128.f3.0f38.w0 24 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 08) 315 001(24) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVSQW, 2, {MEMORY|BITS32,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+39807, 544},
    /*   4 : VPMOVSQW mem64|mask,ymmreg [mr:qvm:   evex.256.f3.0f38.w0 24 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 28) 315 001(24) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVSQW, 2, {MEMORY|BITS64,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+39816, 544},
    /*   5 : VPMOVSQW mem128|mask,zmmreg [mr:qvm:   evex.512.f3.0f38.w0 24 /r         ] AVX512,FUTURE */
        /* 250(f2 7e 48) 315 001(24) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMOVSQW, 2, {MEMORY|BITS128,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+39825, 545},
};

static const struct itemplate instrux_VPMOVSWB[6] = {
    /*   0 : VPMOVSWB xmmreg|mask|z,xmmreg [mr:       evex.128.f3.0f38.w0 20 /r         ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7e 08) 300 001(20) 101 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMOVSWB, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39834, 550},
    /*   1 : VPMOVSWB xmmreg|mask|z,ymmreg [mr:       evex.256.f3.0f38.w0 20 /r         ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7e 28) 300 001(20) 101 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMOVSWB, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39843, 550},
    /*   2 : VPMOVSWB ymmreg|mask|z,zmmreg [mr:       evex.512.f3.0f38.w0 20 /r         ] AVX512BW,FUTURE */
        /* 250(f2 7e 48) 300 001(20) 101 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPMOVSWB, 2, {YMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+39852, 551},
    /*   3 : VPMOVSWB mem64|mask,xmmreg [mr:hvm:   evex.128.f3.0f38.w0 20 /r         ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7e 08) 314 001(20) 101 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMOVSWB, 2, {MEMORY|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+39861, 550},
    /*   4 : VPMOVSWB mem128|mask,ymmreg [mr:hvm:   evex.256.f3.0f38.w0 20 /r         ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7e 28) 314 001(20) 101 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMOVSWB, 2, {MEMORY|BITS128,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+39870, 550},
    /*   5 : VPMOVSWB mem256|mask,zmmreg [mr:hvm:   evex.512.f3.0f38.w0 20 /r         ] AVX512BW,FUTURE */
        /* 250(f2 7e 48) 314 001(20) 101 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPMOVSWB, 2, {MEMORY|BITS256,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+39879, 551},
};

static const struct itemplate instrux_VPMOVUSDB[6] = {
    /*   0 : VPMOVUSDB xmmreg|mask|z,xmmreg [mr:       evex.128.f3.0f38.w0 11 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 08) 300 001(11) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVUSDB, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40050, 544},
    /*   1 : VPMOVUSDB xmmreg|mask|z,ymmreg [mr:       evex.256.f3.0f38.w0 11 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 28) 300 001(11) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVUSDB, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40059, 544},
    /*   2 : VPMOVUSDB xmmreg|mask|z,zmmreg [mr:       evex.512.f3.0f38.w0 11 /r         ] AVX512,FUTURE */
        /* 250(f2 7e 48) 300 001(11) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMOVUSDB, 2, {XMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40068, 545},
    /*   3 : VPMOVUSDB mem32|mask,xmmreg [mr:qvm:   evex.128.f3.0f38.w0 11 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 08) 315 001(11) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVUSDB, 2, {MEMORY|BITS32,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+40077, 544},
    /*   4 : VPMOVUSDB mem64|mask,ymmreg [mr:qvm:   evex.256.f3.0f38.w0 11 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 28) 315 001(11) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVUSDB, 2, {MEMORY|BITS64,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+40086, 544},
    /*   5 : VPMOVUSDB mem128|mask,zmmreg [mr:qvm:   evex.512.f3.0f38.w0 11 /r         ] AVX512,FUTURE */
        /* 250(f2 7e 48) 315 001(11) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMOVUSDB, 2, {MEMORY|BITS128,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+40095, 545},
};

static const struct itemplate instrux_VPMOVUSDW[6] = {
    /*   0 : VPMOVUSDW xmmreg|mask|z,xmmreg [mr:       evex.128.f3.0f38.w0 13 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 08) 300 001(13) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVUSDW, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40104, 544},
    /*   1 : VPMOVUSDW xmmreg|mask|z,ymmreg [mr:       evex.256.f3.0f38.w0 13 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 28) 300 001(13) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVUSDW, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40113, 544},
    /*   2 : VPMOVUSDW ymmreg|mask|z,zmmreg [mr:       evex.512.f3.0f38.w0 13 /r         ] AVX512,FUTURE */
        /* 250(f2 7e 48) 300 001(13) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMOVUSDW, 2, {YMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40122, 545},
    /*   3 : VPMOVUSDW mem64|mask,xmmreg [mr:hvm:   evex.128.f3.0f38.w0 13 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 08) 314 001(13) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVUSDW, 2, {MEMORY|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+40131, 544},
    /*   4 : VPMOVUSDW mem128|mask,ymmreg [mr:hvm:   evex.256.f3.0f38.w0 13 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 28) 314 001(13) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVUSDW, 2, {MEMORY|BITS128,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+40140, 544},
    /*   5 : VPMOVUSDW mem256|mask,zmmreg [mr:hvm:   evex.512.f3.0f38.w0 13 /r         ] AVX512,FUTURE */
        /* 250(f2 7e 48) 314 001(13) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMOVUSDW, 2, {MEMORY|BITS256,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+40149, 545},
};

static const struct itemplate instrux_VPMOVUSQB[6] = {
    /*   0 : VPMOVUSQB xmmreg|mask|z,xmmreg [mr:       evex.128.f3.0f38.w0 12 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 08) 300 001(12) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVUSQB, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40158, 544},
    /*   1 : VPMOVUSQB xmmreg|mask|z,ymmreg [mr:       evex.256.f3.0f38.w0 12 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 28) 300 001(12) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVUSQB, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40167, 544},
    /*   2 : VPMOVUSQB xmmreg|mask|z,zmmreg [mr:       evex.512.f3.0f38.w0 12 /r         ] AVX512,FUTURE */
        /* 250(f2 7e 48) 300 001(12) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMOVUSQB, 2, {XMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40176, 545},
    /*   3 : VPMOVUSQB mem16|mask,xmmreg [mr:ovm:   evex.128.f3.0f38.w0 12 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 08) 316 001(12) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVUSQB, 2, {MEMORY|BITS16,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+40185, 544},
    /*   4 : VPMOVUSQB mem32|mask,ymmreg [mr:ovm:   evex.256.f3.0f38.w0 12 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 28) 316 001(12) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVUSQB, 2, {MEMORY|BITS32,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+40194, 544},
    /*   5 : VPMOVUSQB mem64|mask,zmmreg [mr:ovm:   evex.512.f3.0f38.w0 12 /r         ] AVX512,FUTURE */
        /* 250(f2 7e 48) 316 001(12) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMOVUSQB, 2, {MEMORY|BITS64,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+40203, 545},
};

static const struct itemplate instrux_VPMOVUSQD[6] = {
    /*   0 : VPMOVUSQD xmmreg|mask|z,xmmreg [mr:       evex.128.f3.0f38.w0 15 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 08) 300 001(15) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVUSQD, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40212, 544},
    /*   1 : VPMOVUSQD xmmreg|mask|z,ymmreg [mr:       evex.256.f3.0f38.w0 15 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 28) 300 001(15) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVUSQD, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40221, 544},
    /*   2 : VPMOVUSQD ymmreg|mask|z,zmmreg [mr:       evex.512.f3.0f38.w0 15 /r         ] AVX512,FUTURE */
        /* 250(f2 7e 48) 300 001(15) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMOVUSQD, 2, {YMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40230, 545},
    /*   3 : VPMOVUSQD mem64|mask,xmmreg [mr:hvm:   evex.128.f3.0f38.w0 15 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 08) 314 001(15) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVUSQD, 2, {MEMORY|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+40239, 544},
    /*   4 : VPMOVUSQD mem128|mask,ymmreg [mr:hvm:   evex.256.f3.0f38.w0 15 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 28) 314 001(15) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVUSQD, 2, {MEMORY|BITS128,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+40248, 544},
    /*   5 : VPMOVUSQD mem256|mask,zmmreg [mr:hvm:   evex.512.f3.0f38.w0 15 /r         ] AVX512,FUTURE */
        /* 250(f2 7e 48) 314 001(15) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMOVUSQD, 2, {MEMORY|BITS256,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+40257, 545},
};

static const struct itemplate instrux_VPMOVUSQW[6] = {
    /*   0 : VPMOVUSQW xmmreg|mask|z,xmmreg [mr:       evex.128.f3.0f38.w0 14 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 08) 300 001(14) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVUSQW, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40266, 544},
    /*   1 : VPMOVUSQW xmmreg|mask|z,ymmreg [mr:       evex.256.f3.0f38.w0 14 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 28) 300 001(14) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVUSQW, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40275, 544},
    /*   2 : VPMOVUSQW xmmreg|mask|z,zmmreg [mr:       evex.512.f3.0f38.w0 14 /r         ] AVX512,FUTURE */
        /* 250(f2 7e 48) 300 001(14) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMOVUSQW, 2, {XMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40284, 545},
    /*   3 : VPMOVUSQW mem32|mask,xmmreg [mr:qvm:   evex.128.f3.0f38.w0 14 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 08) 315 001(14) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVUSQW, 2, {MEMORY|BITS32,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+40293, 544},
    /*   4 : VPMOVUSQW mem64|mask,ymmreg [mr:qvm:   evex.256.f3.0f38.w0 14 /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7e 28) 315 001(14) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPMOVUSQW, 2, {MEMORY|BITS64,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+40302, 544},
    /*   5 : VPMOVUSQW mem128|mask,zmmreg [mr:qvm:   evex.512.f3.0f38.w0 14 /r         ] AVX512,FUTURE */
        /* 250(f2 7e 48) 315 001(14) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VPMOVUSQW, 2, {MEMORY|BITS128,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+40311, 545},
};

static const struct itemplate instrux_VPMOVUSWB[6] = {
    /*   0 : VPMOVUSWB xmmreg|mask|z,xmmreg [mr:       evex.128.f3.0f38.w0 10 /r         ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7e 08) 300 001(10) 101 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMOVUSWB, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40320, 550},
    /*   1 : VPMOVUSWB xmmreg|mask|z,ymmreg [mr:       evex.256.f3.0f38.w0 10 /r         ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7e 28) 300 001(10) 101 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMOVUSWB, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40329, 550},
    /*   2 : VPMOVUSWB ymmreg|mask|z,zmmreg [mr:       evex.512.f3.0f38.w0 10 /r         ] AVX512BW,FUTURE */
        /* 250(f2 7e 48) 300 001(10) 101 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPMOVUSWB, 2, {YMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40338, 551},
    /*   3 : VPMOVUSWB mem64|mask,xmmreg [mr:hvm:   evex.128.f3.0f38.w0 10 /r         ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7e 08) 314 001(10) 101 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMOVUSWB, 2, {MEMORY|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+40347, 550},
    /*   4 : VPMOVUSWB mem128|mask,ymmreg [mr:hvm:   evex.256.f3.0f38.w0 10 /r         ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7e 28) 314 001(10) 101 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMOVUSWB, 2, {MEMORY|BITS128,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+40356, 550},
    /*   5 : VPMOVUSWB mem256|mask,zmmreg [mr:hvm:   evex.512.f3.0f38.w0 10 /r         ] AVX512BW,FUTURE */
        /* 250(f2 7e 48) 314 001(10) 101 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPMOVUSWB, 2, {MEMORY|BITS256,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+40365, 551},
};

static const struct itemplate instrux_VPMOVW2M[3] = {
    /*   0 : VPMOVW2M kreg,xmmreg [rm:       evex.128.f3.0f38.w1 29 /r         ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 fe 08) 300 001(29) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMOVW2M, 2, {OPMASKREG,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+40374, 550},
    /*   1 : VPMOVW2M kreg,ymmreg [rm:       evex.256.f3.0f38.w1 29 /r         ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 fe 28) 300 001(29) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMOVW2M, 2, {OPMASKREG,YMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+40383, 550},
    /*   2 : VPMOVW2M kreg,zmmreg [rm:       evex.512.f3.0f38.w1 29 /r         ] AVX512BW,FUTURE */
        /* 250(f2 fe 48) 300 001(29) 110 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPMOVW2M, 2, {OPMASKREG,ZMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+40392, 551},
};

static const struct itemplate instrux_VPMOVWB[6] = {
    /*   0 : VPMOVWB xmmreg|mask|z,xmmreg [mr:       evex.128.f3.0f38.w0 30 /r         ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7e 08) 300 001(30) 101 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMOVWB, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40401, 550},
    /*   1 : VPMOVWB xmmreg|mask|z,ymmreg [mr:       evex.256.f3.0f38.w0 30 /r         ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7e 28) 300 001(30) 101 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMOVWB, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40410, 550},
    /*   2 : VPMOVWB ymmreg|mask|z,zmmreg [mr:       evex.512.f3.0f38.w0 30 /r         ] AVX512BW,FUTURE */
        /* 250(f2 7e 48) 300 001(30) 101 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPMOVWB, 2, {YMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+40419, 551},
    /*   3 : VPMOVWB mem64|mask,xmmreg [mr:hvm:   evex.128.f3.0f38.w0 30 /r         ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7e 08) 314 001(30) 101 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMOVWB, 2, {MEMORY|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+40428, 550},
    /*   4 : VPMOVWB mem128|mask,ymmreg [mr:hvm:   evex.256.f3.0f38.w0 30 /r         ] AVX512VL,AVX512BW,FUTURE */
        /* 250(f2 7e 28) 314 001(30) 101 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPMOVWB, 2, {MEMORY|BITS128,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+40437, 550},
    /*   5 : VPMOVWB mem256|mask,zmmreg [mr:hvm:   evex.512.f3.0f38.w0 30 /r         ] AVX512BW,FUTURE */
        /* 250(f2 7e 48) 314 001(30) 101 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPMOVWB, 2, {MEMORY|BITS256,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+40446, 551},
};

static const struct itemplate instrux_VPMULLQ[6] = {
    /*   0 : VPMULLQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 40 /r     ] AVX512VL,AVX512DQ,FUTURE */
        /* 241(f2 fd 08) 301 001(40) 120 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VPMULLQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+40887, 547},
    /*   1 : VPMULLQ xmmreg|mask|z,xmmrm128|b64 [r+vm:fv:   evex.nds.128.66.0f38.w1 40 /r     ] ND,AVX512VL,AVX512DQ,FUTURE */
        /* 240(f2 fd 08) 301 001(40) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VPMULLQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+40896, 547},
    /*   2 : VPMULLQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 40 /r     ] AVX512VL,AVX512DQ,FUTURE */
        /* 241(f2 fd 28) 301 001(40) 120 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VPMULLQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+40905, 547},
    /*   3 : VPMULLQ ymmreg|mask|z,ymmrm256|b64 [r+vm:fv:   evex.nds.256.66.0f38.w1 40 /r     ] ND,AVX512VL,AVX512DQ,FUTURE */
        /* 240(f2 fd 28) 301 001(40) 110 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VPMULLQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+40914, 547},
    /*   4 : VPMULLQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv:   evex.nds.512.66.0f38.w1 40 /r     ] AVX512DQ,FUTURE */
        /* 241(f2 fd 48) 301 001(40) 120 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VPMULLQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+40923, 548},
    /*   5 : VPMULLQ zmmreg|mask|z,zmmrm512|b64 [r+vm:fv:   evex.nds.512.66.0f38.w1 40 /r     ] ND,AVX512DQ,FUTURE */
        /* 240(f2 fd 48) 301 001(40) 110 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VPMULLQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+40932, 548},
};

static const struct itemplate instrux_VPMULTISHIFTQB[6] = {
    /*   0 : VPMULTISHIFTQB xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 83 /r     ] AVX512VL,AVX512VBMI,FUTURE */
        /* 241(f2 fd 08) 301 001(83) 120 : EVEX,PROT,AVX512VL,AVX512VBMI,FUTURE */
        {I_VPMULTISHIFTQB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+40995, 560},
    /*   1 : VPMULTISHIFTQB xmmreg|mask|z,xmmrm128|b64 [r+vm:fv:   evex.nds.128.66.0f38.w1 83 /r     ] ND,AVX512VL,AVX512VBMI,FUTURE */
        /* 240(f2 fd 08) 301 001(83) 110 : EVEX,PROT,AVX512VL,AVX512VBMI,FUTURE */
        {I_VPMULTISHIFTQB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+41004, 560},
    /*   2 : VPMULTISHIFTQB ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 83 /r     ] AVX512VL,AVX512VBMI,FUTURE */
        /* 241(f2 fd 28) 301 001(83) 120 : EVEX,PROT,AVX512VL,AVX512VBMI,FUTURE */
        {I_VPMULTISHIFTQB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+41013, 560},
    /*   3 : VPMULTISHIFTQB ymmreg|mask|z,ymmrm256|b64 [r+vm:fv:   evex.nds.256.66.0f38.w1 83 /r     ] ND,AVX512VL,AVX512VBMI,FUTURE */
        /* 240(f2 fd 28) 301 001(83) 110 : EVEX,PROT,AVX512VL,AVX512VBMI,FUTURE */
        {I_VPMULTISHIFTQB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+41022, 560},
    /*   4 : VPMULTISHIFTQB zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv:   evex.nds.512.66.0f38.w1 83 /r     ] AVX512VBMI,FUTURE */
        /* 241(f2 fd 48) 301 001(83) 120 : EVEX,PROT,AVX512VBMI,FUTURE */
        {I_VPMULTISHIFTQB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+41031, 561},
    /*   5 : VPMULTISHIFTQB zmmreg|mask|z,zmmrm512|b64 [r+vm:fv:   evex.nds.512.66.0f38.w1 83 /r     ] ND,AVX512VBMI,FUTURE */
        /* 240(f2 fd 48) 301 001(83) 110 : EVEX,PROT,AVX512VBMI,FUTURE */
        {I_VPMULTISHIFTQB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+41040, 561},
};

static const struct itemplate instrux_VPORD[6] = {
    /*   0 : VPORD xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f.w0 eb /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7d 08) 301 001(eb) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPORD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+41103, 544},
    /*   1 : VPORD xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.nds.128.66.0f.w0 eb /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 08) 301 001(eb) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPORD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+41112, 544},
    /*   2 : VPORD ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f.w0 eb /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7d 28) 301 001(eb) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPORD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+41121, 544},
    /*   3 : VPORD ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.nds.256.66.0f.w0 eb /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 28) 301 001(eb) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPORD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+41130, 544},
    /*   4 : VPORD zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv:   evex.nds.512.66.0f.w0 eb /r       ] AVX512,FUTURE */
        /* 241(f1 7d 48) 301 001(eb) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPORD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+41139, 545},
    /*   5 : VPORD zmmreg|mask|z,zmmrm512|b32 [r+vm:fv:   evex.nds.512.66.0f.w0 eb /r       ] ND,AVX512,FUTURE */
        /* 240(f1 7d 48) 301 001(eb) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPORD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+41148, 545},
};

static const struct itemplate instrux_VPORQ[6] = {
    /*   0 : VPORQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f.w1 eb /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(eb) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPORQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+41157, 544},
    /*   1 : VPORQ xmmreg|mask|z,xmmrm128|b64 [r+vm:fv:   evex.nds.128.66.0f.w1 eb /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 08) 301 001(eb) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPORQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+41166, 544},
    /*   2 : VPORQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f.w1 eb /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(eb) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPORQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+41175, 544},
    /*   3 : VPORQ ymmreg|mask|z,ymmrm256|b64 [r+vm:fv:   evex.nds.256.66.0f.w1 eb /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 28) 301 001(eb) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPORQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+41184, 544},
    /*   4 : VPORQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv:   evex.nds.512.66.0f.w1 eb /r       ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(eb) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPORQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+41193, 545},
    /*   5 : VPORQ zmmreg|mask|z,zmmrm512|b64 [r+vm:fv:   evex.nds.512.66.0f.w1 eb /r       ] ND,AVX512,FUTURE */
        /* 240(f1 fd 48) 301 001(eb) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPORQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+41202, 545},
};

static const struct itemplate instrux_VPROLD[6] = {
    /*   0 : VPROLD xmmreg|mask|z,xmmrm128|b32*,imm8 [vmi:fv:   evex.nds.128.66.0f.w0 72 /1 ib    ] AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 08) 301 001(72) 211 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPROLD, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20103, 544},
    /*   1 : VPROLD xmmreg|mask|z,imm8 [v+mi:fv:   evex.nds.128.66.0f.w0 72 /1 ib    ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 08) 301 001(72) 201 021 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPROLD, 2, {XMMREG,IMM_NORMAL|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20113, 544},
    /*   2 : VPROLD ymmreg|mask|z,ymmrm256|b32*,imm8 [vmi:fv:   evex.nds.256.66.0f.w0 72 /1 ib    ] AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 28) 301 001(72) 211 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPROLD, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20123, 544},
    /*   3 : VPROLD ymmreg|mask|z,imm8 [v+mi:fv:   evex.nds.256.66.0f.w0 72 /1 ib    ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 28) 301 001(72) 201 021 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPROLD, 2, {YMMREG,IMM_NORMAL|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20133, 544},
    /*   4 : VPROLD zmmreg|mask|z,zmmrm512|b32*,imm8 [vmi:fv:   evex.nds.512.66.0f.w0 72 /1 ib    ] AVX512,FUTURE */
        /* 240(f1 7d 48) 301 001(72) 211 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VPROLD, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20143, 545},
    /*   5 : VPROLD zmmreg|mask|z,imm8 [v+mi:fv:   evex.nds.512.66.0f.w0 72 /1 ib    ] ND,AVX512,FUTURE */
        /* 240(f1 7d 48) 301 001(72) 201 021 : EVEX,PROT,AVX512,FUTURE */
        {I_VPROLD, 2, {ZMMREG,IMM_NORMAL|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20153, 545},
};

static const struct itemplate instrux_VPROLQ[6] = {
    /*   0 : VPROLQ xmmreg|mask|z,xmmrm128|b64*,imm8 [vmi:fv:   evex.nds.128.66.0f.w1 72 /1 ib    ] AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 08) 301 001(72) 211 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPROLQ, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+20163, 544},
    /*   1 : VPROLQ xmmreg|mask|z,imm8 [v+mi:fv:   evex.nds.128.66.0f.w1 72 /1 ib    ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 08) 301 001(72) 201 021 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPROLQ, 2, {XMMREG,IMM_NORMAL|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20173, 544},
    /*   2 : VPROLQ ymmreg|mask|z,ymmrm256|b64*,imm8 [vmi:fv:   evex.nds.256.66.0f.w1 72 /1 ib    ] AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 28) 301 001(72) 211 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPROLQ, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+20183, 544},
    /*   3 : VPROLQ ymmreg|mask|z,imm8 [v+mi:fv:   evex.nds.256.66.0f.w1 72 /1 ib    ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 28) 301 001(72) 201 021 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPROLQ, 2, {YMMREG,IMM_NORMAL|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20193, 544},
    /*   4 : VPROLQ zmmreg|mask|z,zmmrm512|b64*,imm8 [vmi:fv:   evex.nds.512.66.0f.w1 72 /1 ib    ] AVX512,FUTURE */
        /* 240(f1 fd 48) 301 001(72) 211 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VPROLQ, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+20203, 545},
    /*   5 : VPROLQ zmmreg|mask|z,imm8 [v+mi:fv:   evex.nds.512.66.0f.w1 72 /1 ib    ] ND,AVX512,FUTURE */
        /* 240(f1 fd 48) 301 001(72) 201 021 : EVEX,PROT,AVX512,FUTURE */
        {I_VPROLQ, 2, {ZMMREG,IMM_NORMAL|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20213, 545},
};

static const struct itemplate instrux_VPROLVD[6] = {
    /*   0 : VPROLVD xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f38.w0 15 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 08) 301 001(15) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPROLVD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+41211, 544},
    /*   1 : VPROLVD xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.nds.128.66.0f38.w0 15 /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 7d 08) 301 001(15) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPROLVD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+41220, 544},
    /*   2 : VPROLVD ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f38.w0 15 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 28) 301 001(15) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPROLVD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+41229, 544},
    /*   3 : VPROLVD ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.nds.256.66.0f38.w0 15 /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 7d 28) 301 001(15) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPROLVD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+41238, 544},
    /*   4 : VPROLVD zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv:   evex.nds.512.66.0f38.w0 15 /r     ] AVX512,FUTURE */
        /* 241(f2 7d 48) 301 001(15) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPROLVD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+41247, 545},
    /*   5 : VPROLVD zmmreg|mask|z,zmmrm512|b32 [r+vm:fv:   evex.nds.512.66.0f38.w0 15 /r     ] ND,AVX512,FUTURE */
        /* 240(f2 7d 48) 301 001(15) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPROLVD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+41256, 545},
};

static const struct itemplate instrux_VPROLVQ[6] = {
    /*   0 : VPROLVQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 15 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 08) 301 001(15) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPROLVQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+41265, 544},
    /*   1 : VPROLVQ xmmreg|mask|z,xmmrm128|b64 [r+vm:fv:   evex.nds.128.66.0f38.w1 15 /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 fd 08) 301 001(15) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPROLVQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+41274, 544},
    /*   2 : VPROLVQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 15 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 28) 301 001(15) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPROLVQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+41283, 544},
    /*   3 : VPROLVQ ymmreg|mask|z,ymmrm256|b64 [r+vm:fv:   evex.nds.256.66.0f38.w1 15 /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 fd 28) 301 001(15) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPROLVQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+41292, 544},
    /*   4 : VPROLVQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv:   evex.nds.512.66.0f38.w1 15 /r     ] AVX512,FUTURE */
        /* 241(f2 fd 48) 301 001(15) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPROLVQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+41301, 545},
    /*   5 : VPROLVQ zmmreg|mask|z,zmmrm512|b64 [r+vm:fv:   evex.nds.512.66.0f38.w1 15 /r     ] ND,AVX512,FUTURE */
        /* 240(f2 fd 48) 301 001(15) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPROLVQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+41310, 545},
};

static const struct itemplate instrux_VPRORD[6] = {
    /*   0 : VPRORD xmmreg|mask|z,xmmrm128|b32*,imm8 [vmi:fv:   evex.nds.128.66.0f.w0 72 /0 ib    ] AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 08) 301 001(72) 210 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPRORD, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20223, 544},
    /*   1 : VPRORD xmmreg|mask|z,imm8 [v+mi:fv:   evex.nds.128.66.0f.w0 72 /0 ib    ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 08) 301 001(72) 200 021 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPRORD, 2, {XMMREG,IMM_NORMAL|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20233, 544},
    /*   2 : VPRORD ymmreg|mask|z,ymmrm256|b32*,imm8 [vmi:fv:   evex.nds.256.66.0f.w0 72 /0 ib    ] AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 28) 301 001(72) 210 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPRORD, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20243, 544},
    /*   3 : VPRORD ymmreg|mask|z,imm8 [v+mi:fv:   evex.nds.256.66.0f.w0 72 /0 ib    ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 28) 301 001(72) 200 021 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPRORD, 2, {YMMREG,IMM_NORMAL|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20253, 544},
    /*   4 : VPRORD zmmreg|mask|z,zmmrm512|b32*,imm8 [vmi:fv:   evex.nds.512.66.0f.w0 72 /0 ib    ] AVX512,FUTURE */
        /* 240(f1 7d 48) 301 001(72) 210 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VPRORD, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20263, 545},
    /*   5 : VPRORD zmmreg|mask|z,imm8 [v+mi:fv:   evex.nds.512.66.0f.w0 72 /0 ib    ] ND,AVX512,FUTURE */
        /* 240(f1 7d 48) 301 001(72) 200 021 : EVEX,PROT,AVX512,FUTURE */
        {I_VPRORD, 2, {ZMMREG,IMM_NORMAL|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20273, 545},
};

static const struct itemplate instrux_VPRORQ[6] = {
    /*   0 : VPRORQ xmmreg|mask|z,xmmrm128|b64*,imm8 [vmi:fv:   evex.nds.128.66.0f.w1 72 /0 ib    ] AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 08) 301 001(72) 210 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPRORQ, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+20283, 544},
    /*   1 : VPRORQ xmmreg|mask|z,imm8 [v+mi:fv:   evex.nds.128.66.0f.w1 72 /0 ib    ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 08) 301 001(72) 200 021 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPRORQ, 2, {XMMREG,IMM_NORMAL|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20293, 544},
    /*   2 : VPRORQ ymmreg|mask|z,ymmrm256|b64*,imm8 [vmi:fv:   evex.nds.256.66.0f.w1 72 /0 ib    ] AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 28) 301 001(72) 210 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPRORQ, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+20303, 544},
    /*   3 : VPRORQ ymmreg|mask|z,imm8 [v+mi:fv:   evex.nds.256.66.0f.w1 72 /0 ib    ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 28) 301 001(72) 200 021 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPRORQ, 2, {YMMREG,IMM_NORMAL|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20313, 544},
    /*   4 : VPRORQ zmmreg|mask|z,zmmrm512|b64*,imm8 [vmi:fv:   evex.nds.512.66.0f.w1 72 /0 ib    ] AVX512,FUTURE */
        /* 240(f1 fd 48) 301 001(72) 210 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VPRORQ, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+20323, 545},
    /*   5 : VPRORQ zmmreg|mask|z,imm8 [v+mi:fv:   evex.nds.512.66.0f.w1 72 /0 ib    ] ND,AVX512,FUTURE */
        /* 240(f1 fd 48) 301 001(72) 200 021 : EVEX,PROT,AVX512,FUTURE */
        {I_VPRORQ, 2, {ZMMREG,IMM_NORMAL|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20333, 545},
};

static const struct itemplate instrux_VPRORVD[6] = {
    /*   0 : VPRORVD xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f38.w0 14 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 08) 301 001(14) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPRORVD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+41319, 544},
    /*   1 : VPRORVD xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.nds.128.66.0f38.w0 14 /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 7d 08) 301 001(14) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPRORVD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+41328, 544},
    /*   2 : VPRORVD ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f38.w0 14 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 28) 301 001(14) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPRORVD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+41337, 544},
    /*   3 : VPRORVD ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.nds.256.66.0f38.w0 14 /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 7d 28) 301 001(14) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPRORVD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+41346, 544},
    /*   4 : VPRORVD zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv:   evex.nds.512.66.0f38.w0 14 /r     ] AVX512,FUTURE */
        /* 241(f2 7d 48) 301 001(14) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPRORVD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+41355, 545},
    /*   5 : VPRORVD zmmreg|mask|z,zmmrm512|b32 [r+vm:fv:   evex.nds.512.66.0f38.w0 14 /r     ] ND,AVX512,FUTURE */
        /* 240(f2 7d 48) 301 001(14) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPRORVD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+41364, 545},
};

static const struct itemplate instrux_VPRORVQ[6] = {
    /*   0 : VPRORVQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 14 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 08) 301 001(14) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPRORVQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+41373, 544},
    /*   1 : VPRORVQ xmmreg|mask|z,xmmrm128|b64 [r+vm:fv:   evex.nds.128.66.0f38.w1 14 /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 fd 08) 301 001(14) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPRORVQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+41382, 544},
    /*   2 : VPRORVQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 14 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 28) 301 001(14) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPRORVQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+41391, 544},
    /*   3 : VPRORVQ ymmreg|mask|z,ymmrm256|b64 [r+vm:fv:   evex.nds.256.66.0f38.w1 14 /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 fd 28) 301 001(14) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPRORVQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+41400, 544},
    /*   4 : VPRORVQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv:   evex.nds.512.66.0f38.w1 14 /r     ] AVX512,FUTURE */
        /* 241(f2 fd 48) 301 001(14) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPRORVQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+41409, 545},
    /*   5 : VPRORVQ zmmreg|mask|z,zmmrm512|b64 [r+vm:fv:   evex.nds.512.66.0f38.w1 14 /r     ] ND,AVX512,FUTURE */
        /* 240(f2 fd 48) 301 001(14) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPRORVQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+41418, 545},
};

static const struct itemplate instrux_VPSCATTERDD[3] = {
    /*   0 : VPSCATTERDD xmem32|mask,xmmreg [mr:t1s:   vsibx evex.128.66.0f38.w0 a0 /r   ] AVX512,AVX512VL,FUTURE */
        /* 374 250(f2 7d 08) 306 001(a0) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSCATTERDD, 2, {XMEM|BITS32,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+20343, 544},
    /*   1 : VPSCATTERDD ymem32|mask,ymmreg [mr:t1s:   vsiby evex.256.66.0f38.w0 a0 /r   ] AVX512,AVX512VL,FUTURE */
        /* 375 250(f2 7d 28) 306 001(a0) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSCATTERDD, 2, {YMEM|BITS32,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+20353, 544},
    /*   2 : VPSCATTERDD zmem32|mask,zmmreg [mr:t1s:   vsibz evex.512.66.0f38.w0 a0 /r   ] AVX512,FUTURE */
        /* 376 250(f2 7d 48) 306 001(a0) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSCATTERDD, 2, {ZMEM|BITS32,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+20363, 545},
};

static const struct itemplate instrux_VPSCATTERDQ[3] = {
    /*   0 : VPSCATTERDQ xmem64|mask,xmmreg [mr:t1s:   vsibx evex.128.66.0f38.w1 a0 /r   ] AVX512,AVX512VL,FUTURE */
        /* 374 250(f2 fd 08) 306 001(a0) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSCATTERDQ, 2, {XMEM|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+20373, 544},
    /*   1 : VPSCATTERDQ xmem64|mask,ymmreg [mr:t1s:   vsibx evex.256.66.0f38.w1 a0 /r   ] AVX512,AVX512VL,FUTURE */
        /* 374 250(f2 fd 28) 306 001(a0) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSCATTERDQ, 2, {XMEM|BITS64,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+20383, 544},
    /*   2 : VPSCATTERDQ ymem64|mask,zmmreg [mr:t1s:   vsiby evex.512.66.0f38.w1 a0 /r   ] AVX512,FUTURE */
        /* 375 250(f2 fd 48) 306 001(a0) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSCATTERDQ, 2, {YMEM|BITS64,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+20393, 545},
};

static const struct itemplate instrux_VPSCATTERQD[3] = {
    /*   0 : VPSCATTERQD xmem32|mask,xmmreg [mr:t1s:   vsibx evex.128.66.0f38.w0 a1 /r   ] AVX512,AVX512VL,FUTURE */
        /* 374 250(f2 7d 08) 306 001(a1) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSCATTERQD, 2, {XMEM|BITS32,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+20403, 544},
    /*   1 : VPSCATTERQD ymem32|mask,xmmreg [mr:t1s:   vsiby evex.256.66.0f38.w0 a1 /r   ] AVX512,AVX512VL,FUTURE */
        /* 375 250(f2 7d 28) 306 001(a1) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSCATTERQD, 2, {YMEM|BITS32,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+20413, 544},
    /*   2 : VPSCATTERQD zmem32|mask,ymmreg [mr:t1s:   vsibz evex.512.66.0f38.w0 a1 /r   ] AVX512,FUTURE */
        /* 376 250(f2 7d 48) 306 001(a1) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSCATTERQD, 2, {ZMEM|BITS32,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+20423, 545},
};

static const struct itemplate instrux_VPSCATTERQQ[3] = {
    /*   0 : VPSCATTERQQ xmem64|mask,xmmreg [mr:t1s:   vsibx evex.128.66.0f38.w1 a1 /r   ] AVX512,AVX512VL,FUTURE */
        /* 374 250(f2 fd 08) 306 001(a1) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSCATTERQQ, 2, {XMEM|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+20433, 544},
    /*   1 : VPSCATTERQQ ymem64|mask,ymmreg [mr:t1s:   vsiby evex.256.66.0f38.w1 a1 /r   ] AVX512,AVX512VL,FUTURE */
        /* 375 250(f2 fd 28) 306 001(a1) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSCATTERQQ, 2, {YMEM|BITS64,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+20443, 544},
    /*   2 : VPSCATTERQQ zmem64|mask,zmmreg [mr:t1s:   vsibz evex.512.66.0f38.w1 a1 /r   ] AVX512,FUTURE */
        /* 376 250(f2 fd 48) 306 001(a1) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSCATTERQQ, 2, {ZMEM|BITS64,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+20453, 545},
};

static const struct itemplate instrux_VPSLLVW[6] = {
    /*   0 : VPSLLVW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f38.w1 12 /r     ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f2 fd 08) 303 001(12) 120 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSLLVW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41751, 550},
    /*   1 : VPSLLVW xmmreg|mask|z,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f38.w1 12 /r     ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f2 fd 08) 303 001(12) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSLLVW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41760, 550},
    /*   2 : VPSLLVW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f38.w1 12 /r     ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f2 fd 28) 303 001(12) 120 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSLLVW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41769, 550},
    /*   3 : VPSLLVW ymmreg|mask|z,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f38.w1 12 /r     ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f2 fd 28) 303 001(12) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSLLVW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41778, 550},
    /*   4 : VPSLLVW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f38.w1 12 /r     ] AVX512BW,FUTURE */
        /* 241(f2 fd 48) 303 001(12) 120 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPSLLVW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41787, 551},
    /*   5 : VPSLLVW zmmreg|mask|z,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f38.w1 12 /r     ] ND,AVX512BW,FUTURE */
        /* 240(f2 fd 48) 303 001(12) 110 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPSLLVW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41796, 551},
};

static const struct itemplate instrux_VPSRAQ[12] = {
    /*   0 : VPSRAQ xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:m128: evex.nds.128.66.0f.w1 e2 /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 317 001(e2) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRAQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41913, 544},
    /*   1 : VPSRAQ xmmreg|mask|z,xmmrm128 [r+vm:m128: evex.nds.128.66.0f.w1 e2 /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 08) 317 001(e2) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRAQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41922, 544},
    /*   2 : VPSRAQ ymmreg|mask|z,ymmreg*,xmmrm128 [rvm:m128: evex.nds.256.66.0f.w1 e2 /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 317 001(e2) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRAQ, 3, {YMMREG,YMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41931, 544},
    /*   3 : VPSRAQ ymmreg|mask|z,xmmrm128 [r+vm:m128: evex.nds.256.66.0f.w1 e2 /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 28) 317 001(e2) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRAQ, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41940, 544},
    /*   4 : VPSRAQ zmmreg|mask|z,zmmreg*,xmmrm128 [rvm:m128: evex.nds.512.66.0f.w1 e2 /r       ] AVX512,FUTURE */
        /* 241(f1 fd 48) 317 001(e2) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSRAQ, 3, {ZMMREG,ZMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41949, 545},
    /*   5 : VPSRAQ zmmreg|mask|z,xmmrm128 [r+vm:m128: evex.nds.512.66.0f.w1 e2 /r       ] ND,AVX512,FUTURE */
        /* 240(f1 fd 48) 317 001(e2) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSRAQ, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+41958, 545},
    /*   6 : VPSRAQ xmmreg|mask|z,xmmrm128|b64*,imm8 [vmi:fv:   evex.nds.128.66.0f.w1 72 /4 ib    ] AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 08) 301 001(72) 214 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRAQ, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+20853, 544},
    /*   7 : VPSRAQ xmmreg|mask|z,imm8 [v+mi:fv:   evex.nds.128.66.0f.w1 72 /4 ib    ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 08) 301 001(72) 204 021 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRAQ, 2, {XMMREG,IMM_NORMAL|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20863, 544},
    /*   8 : VPSRAQ ymmreg|mask|z,ymmrm256|b64*,imm8 [vmi:fv:   evex.nds.256.66.0f.w1 72 /4 ib    ] AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 28) 301 001(72) 214 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRAQ, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+20873, 544},
    /*   9 : VPSRAQ ymmreg|mask|z,imm8 [v+mi:fv:   evex.nds.256.66.0f.w1 72 /4 ib    ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 28) 301 001(72) 204 021 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRAQ, 2, {YMMREG,IMM_NORMAL|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20883, 544},
    /*  10 : VPSRAQ zmmreg|mask|z,zmmrm512|b64*,imm8 [vmi:fv:   evex.nds.512.66.0f.w1 72 /4 ib    ] AVX512,FUTURE */
        /* 240(f1 fd 48) 301 001(72) 214 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSRAQ, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+20893, 545},
    /*  11 : VPSRAQ zmmreg|mask|z,imm8 [v+mi:fv:   evex.nds.512.66.0f.w1 72 /4 ib    ] ND,AVX512,FUTURE */
        /* 240(f1 fd 48) 301 001(72) 204 021 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSRAQ, 2, {ZMMREG,IMM_NORMAL|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20903, 545},
};

static const struct itemplate instrux_VPSRAVQ[6] = {
    /*   0 : VPSRAVQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 46 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 08) 301 001(46) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRAVQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+42021, 544},
    /*   1 : VPSRAVQ xmmreg|mask|z,xmmrm128|b64 [r+vm:fv:   evex.nds.128.66.0f38.w1 46 /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 fd 08) 301 001(46) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRAVQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+42030, 544},
    /*   2 : VPSRAVQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 46 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 28) 301 001(46) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRAVQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+42039, 544},
    /*   3 : VPSRAVQ ymmreg|mask|z,ymmrm256|b64 [r+vm:fv:   evex.nds.256.66.0f38.w1 46 /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 fd 28) 301 001(46) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPSRAVQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+42048, 544},
    /*   4 : VPSRAVQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv:   evex.nds.512.66.0f38.w1 46 /r     ] AVX512,FUTURE */
        /* 241(f2 fd 48) 301 001(46) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSRAVQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+42057, 545},
    /*   5 : VPSRAVQ zmmreg|mask|z,zmmrm512|b64 [r+vm:fv:   evex.nds.512.66.0f38.w1 46 /r     ] ND,AVX512,FUTURE */
        /* 240(f2 fd 48) 301 001(46) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPSRAVQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+42066, 545},
};

static const struct itemplate instrux_VPSRAVW[6] = {
    /*   0 : VPSRAVW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f38.w1 11 /r     ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f2 fd 08) 303 001(11) 120 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSRAVW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42075, 550},
    /*   1 : VPSRAVW xmmreg|mask|z,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f38.w1 11 /r     ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f2 fd 08) 303 001(11) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSRAVW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42084, 550},
    /*   2 : VPSRAVW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f38.w1 11 /r     ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f2 fd 28) 303 001(11) 120 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSRAVW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42093, 550},
    /*   3 : VPSRAVW ymmreg|mask|z,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f38.w1 11 /r     ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f2 fd 28) 303 001(11) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSRAVW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42102, 550},
    /*   4 : VPSRAVW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f38.w1 11 /r     ] AVX512BW,FUTURE */
        /* 241(f2 fd 48) 303 001(11) 120 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPSRAVW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42111, 551},
    /*   5 : VPSRAVW zmmreg|mask|z,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f38.w1 11 /r     ] ND,AVX512BW,FUTURE */
        /* 240(f2 fd 48) 303 001(11) 110 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPSRAVW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42120, 551},
};

static const struct itemplate instrux_VPSRLVW[6] = {
    /*   0 : VPSRLVW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f38.w1 10 /r     ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f2 fd 08) 303 001(10) 120 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSRLVW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42399, 550},
    /*   1 : VPSRLVW xmmreg|mask|z,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f38.w1 10 /r     ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f2 fd 08) 303 001(10) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSRLVW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42408, 550},
    /*   2 : VPSRLVW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f38.w1 10 /r     ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f2 fd 28) 303 001(10) 120 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSRLVW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42417, 550},
    /*   3 : VPSRLVW ymmreg|mask|z,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f38.w1 10 /r     ] ND,AVX512VL,AVX512BW,FUTURE */
        /* 240(f2 fd 28) 303 001(10) 110 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPSRLVW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42426, 550},
    /*   4 : VPSRLVW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f38.w1 10 /r     ] AVX512BW,FUTURE */
        /* 241(f2 fd 48) 303 001(10) 120 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPSRLVW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42435, 551},
    /*   5 : VPSRLVW zmmreg|mask|z,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f38.w1 10 /r     ] ND,AVX512BW,FUTURE */
        /* 240(f2 fd 48) 303 001(10) 110 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPSRLVW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+42444, 551},
};

static const struct itemplate instrux_VPTERNLOGD[3] = {
    /*   0 : VPTERNLOGD xmmreg|mask|z,xmmreg,xmmrm128|b32,imm8 [rvmi:fv:  evex.nds.128.66.0f3a.w0 25 /r ib  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 08) 301 001(25) 120 023 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPTERNLOGD, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+21213, 544},
    /*   1 : VPTERNLOGD ymmreg|mask|z,ymmreg,ymmrm256|b32,imm8 [rvmi:fv:  evex.nds.256.66.0f3a.w0 25 /r ib  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 28) 301 001(25) 120 023 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPTERNLOGD, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+21223, 544},
    /*   2 : VPTERNLOGD zmmreg|mask|z,zmmreg,zmmrm512|b32,imm8 [rvmi:fv:  evex.nds.512.66.0f3a.w0 25 /r ib  ] AVX512,FUTURE */
        /* 241(f3 7d 48) 301 001(25) 120 023 : EVEX,PROT,AVX512,FUTURE */
        {I_VPTERNLOGD, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+21233, 545},
};

static const struct itemplate instrux_VPTERNLOGQ[3] = {
    /*   0 : VPTERNLOGQ xmmreg|mask|z,xmmreg,xmmrm128|b64,imm8 [rvmi:fv:  evex.nds.128.66.0f3a.w1 25 /r ib  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 08) 301 001(25) 120 023 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPTERNLOGQ, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+21243, 544},
    /*   1 : VPTERNLOGQ ymmreg|mask|z,ymmreg,ymmrm256|b64,imm8 [rvmi:fv:  evex.nds.256.66.0f3a.w1 25 /r ib  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 28) 301 001(25) 120 023 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPTERNLOGQ, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+21253, 544},
    /*   2 : VPTERNLOGQ zmmreg|mask|z,zmmreg,zmmrm512|b64,imm8 [rvmi:fv:  evex.nds.512.66.0f3a.w1 25 /r ib  ] AVX512,FUTURE */
        /* 241(f3 fd 48) 301 001(25) 120 023 : EVEX,PROT,AVX512,FUTURE */
        {I_VPTERNLOGQ, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+21263, 545},
};

static const struct itemplate instrux_VPTESTMB[3] = {
    /*   0 : VPTESTMB kreg|mask,xmmreg,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f38.w0 26 /r     ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f2 7d 08) 303 001(26) 120 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPTESTMB, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+42939, 550},
    /*   1 : VPTESTMB kreg|mask,ymmreg,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f38.w0 26 /r     ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f2 7d 28) 303 001(26) 120 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPTESTMB, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+42948, 550},
    /*   2 : VPTESTMB kreg|mask,zmmreg,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f38.w0 26 /r     ] AVX512BW,FUTURE */
        /* 241(f2 7d 48) 303 001(26) 120 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPTESTMB, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+42957, 551},
};

static const struct itemplate instrux_VPTESTMD[3] = {
    /*   0 : VPTESTMD kreg|mask,xmmreg,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f38.w0 27 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 08) 301 001(27) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPTESTMD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+42966, 544},
    /*   1 : VPTESTMD kreg|mask,ymmreg,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f38.w0 27 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 28) 301 001(27) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPTESTMD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+42975, 544},
    /*   2 : VPTESTMD kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv:   evex.nds.512.66.0f38.w0 27 /r     ] AVX512,FUTURE */
        /* 241(f2 7d 48) 301 001(27) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPTESTMD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+42984, 545},
};

static const struct itemplate instrux_VPTESTMQ[3] = {
    /*   0 : VPTESTMQ kreg|mask,xmmreg,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 27 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 08) 301 001(27) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPTESTMQ, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+42993, 544},
    /*   1 : VPTESTMQ kreg|mask,ymmreg,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 27 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 28) 301 001(27) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPTESTMQ, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+43002, 544},
    /*   2 : VPTESTMQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv:   evex.nds.512.66.0f38.w1 27 /r     ] AVX512,FUTURE */
        /* 241(f2 fd 48) 301 001(27) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPTESTMQ, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+43011, 545},
};

static const struct itemplate instrux_VPTESTMW[3] = {
    /*   0 : VPTESTMW kreg|mask,xmmreg,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f38.w1 26 /r     ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f2 fd 08) 303 001(26) 120 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPTESTMW, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+43020, 550},
    /*   1 : VPTESTMW kreg|mask,ymmreg,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f38.w1 26 /r     ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f2 fd 28) 303 001(26) 120 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPTESTMW, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+43029, 550},
    /*   2 : VPTESTMW kreg|mask,zmmreg,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f38.w1 26 /r     ] AVX512BW,FUTURE */
        /* 241(f2 fd 48) 303 001(26) 120 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPTESTMW, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+43038, 551},
};

static const struct itemplate instrux_VPTESTNMB[3] = {
    /*   0 : VPTESTNMB kreg|mask,xmmreg,xmmrm128 [rvm:fvm:  evex.nds.128.f3.0f38.w0 26 /r     ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f2 7e 08) 303 001(26) 120 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPTESTNMB, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+43047, 550},
    /*   1 : VPTESTNMB kreg|mask,ymmreg,ymmrm256 [rvm:fvm:  evex.nds.256.f3.0f38.w0 26 /r     ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f2 7e 28) 303 001(26) 120 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPTESTNMB, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+43056, 550},
    /*   2 : VPTESTNMB kreg|mask,zmmreg,zmmrm512 [rvm:fvm:  evex.nds.512.f3.0f38.w0 26 /r     ] AVX512BW,FUTURE */
        /* 241(f2 7e 48) 303 001(26) 120 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPTESTNMB, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+43065, 551},
};

static const struct itemplate instrux_VPTESTNMD[3] = {
    /*   0 : VPTESTNMD kreg|mask,xmmreg,xmmrm128|b32 [rvm:fv:   evex.nds.128.f3.0f38.w0 27 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7e 08) 301 001(27) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPTESTNMD, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+43074, 544},
    /*   1 : VPTESTNMD kreg|mask,ymmreg,ymmrm256|b32 [rvm:fv:   evex.nds.256.f3.0f38.w0 27 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7e 28) 301 001(27) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPTESTNMD, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+43083, 544},
    /*   2 : VPTESTNMD kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv:   evex.nds.512.f3.0f38.w0 27 /r     ] AVX512,FUTURE */
        /* 241(f2 7e 48) 301 001(27) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPTESTNMD, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+43092, 545},
};

static const struct itemplate instrux_VPTESTNMQ[3] = {
    /*   0 : VPTESTNMQ kreg|mask,xmmreg,xmmrm128|b64 [rvm:fv:   evex.nds.128.f3.0f38.w1 27 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fe 08) 301 001(27) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPTESTNMQ, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+43101, 544},
    /*   1 : VPTESTNMQ kreg|mask,ymmreg,ymmrm256|b64 [rvm:fv:   evex.nds.256.f3.0f38.w1 27 /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fe 28) 301 001(27) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPTESTNMQ, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+43110, 544},
    /*   2 : VPTESTNMQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv:   evex.nds.512.f3.0f38.w1 27 /r     ] AVX512,FUTURE */
        /* 241(f2 fe 48) 301 001(27) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPTESTNMQ, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+43119, 545},
};

static const struct itemplate instrux_VPTESTNMW[3] = {
    /*   0 : VPTESTNMW kreg|mask,xmmreg,xmmrm128 [rvm:fvm:  evex.nds.128.f3.0f38.w1 26 /r     ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f2 fe 08) 303 001(26) 120 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPTESTNMW, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+43128, 550},
    /*   1 : VPTESTNMW kreg|mask,ymmreg,ymmrm256 [rvm:fvm:  evex.nds.256.f3.0f38.w1 26 /r     ] AVX512VL,AVX512BW,FUTURE */
        /* 241(f2 fe 28) 303 001(26) 120 : EVEX,PROT,AVX512VL,AVX512BW,FUTURE */
        {I_VPTESTNMW, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+43137, 550},
    /*   2 : VPTESTNMW kreg|mask,zmmreg,zmmrm512 [rvm:fvm:  evex.nds.512.f3.0f38.w1 26 /r     ] AVX512BW,FUTURE */
        /* 241(f2 fe 48) 303 001(26) 120 : EVEX,PROT,AVX512BW,FUTURE */
        {I_VPTESTNMW, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+43146, 551},
};

static const struct itemplate instrux_VPXORD[6] = {
    /*   0 : VPXORD xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f.w0 ef /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7d 08) 301 001(ef) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPXORD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+43587, 544},
    /*   1 : VPXORD xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.nds.128.66.0f.w0 ef /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 08) 301 001(ef) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPXORD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+43596, 544},
    /*   2 : VPXORD ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f.w0 ef /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 7d 28) 301 001(ef) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPXORD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+43605, 544},
    /*   3 : VPXORD ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.nds.256.66.0f.w0 ef /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 7d 28) 301 001(ef) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPXORD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+43614, 544},
    /*   4 : VPXORD zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv:   evex.nds.512.66.0f.w0 ef /r       ] AVX512,FUTURE */
        /* 241(f1 7d 48) 301 001(ef) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPXORD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+43623, 545},
    /*   5 : VPXORD zmmreg|mask|z,zmmrm512|b32 [r+vm:fv:   evex.nds.512.66.0f.w0 ef /r       ] ND,AVX512,FUTURE */
        /* 240(f1 7d 48) 301 001(ef) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPXORD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+43632, 545},
};

static const struct itemplate instrux_VPXORQ[6] = {
    /*   0 : VPXORQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f.w1 ef /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 08) 301 001(ef) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPXORQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+43641, 544},
    /*   1 : VPXORQ xmmreg|mask|z,xmmrm128|b64 [r+vm:fv:   evex.nds.128.66.0f.w1 ef /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 08) 301 001(ef) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPXORQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+43650, 544},
    /*   2 : VPXORQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f.w1 ef /r       ] AVX512,AVX512VL,FUTURE */
        /* 241(f1 fd 28) 301 001(ef) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPXORQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+43659, 544},
    /*   3 : VPXORQ ymmreg|mask|z,ymmrm256|b64 [r+vm:fv:   evex.nds.256.66.0f.w1 ef /r       ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f1 fd 28) 301 001(ef) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VPXORQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+43668, 544},
    /*   4 : VPXORQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv:   evex.nds.512.66.0f.w1 ef /r       ] AVX512,FUTURE */
        /* 241(f1 fd 48) 301 001(ef) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VPXORQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+43677, 545},
    /*   5 : VPXORQ zmmreg|mask|z,zmmrm512|b64 [r+vm:fv:   evex.nds.512.66.0f.w1 ef /r       ] ND,AVX512,FUTURE */
        /* 240(f1 fd 48) 301 001(ef) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VPXORQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+43686, 545},
};

static const struct itemplate instrux_VRANGEPD[6] = {
    /*   0 : VRANGEPD xmmreg|mask|z,xmmreg*,xmmrm128|b64,imm8 [rvmi:fv:  evex.nds.128.66.0f3a.w1 50 /r ib  ] AVX512VL,AVX512DQ,FUTURE */
        /* 241(f3 fd 08) 301 001(50) 120 023 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VRANGEPD, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+21273, 547},
    /*   1 : VRANGEPD xmmreg|mask|z,xmmrm128|b64,imm8 [r+vmi:fv:  evex.nds.128.66.0f3a.w1 50 /r ib  ] ND,AVX512VL,AVX512DQ,FUTURE */
        /* 240(f3 fd 08) 301 001(50) 110 022 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VRANGEPD, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+21283, 547},
    /*   2 : VRANGEPD ymmreg|mask|z,ymmreg*,ymmrm256|b64,imm8 [rvmi:fv:  evex.nds.256.66.0f3a.w1 50 /r ib  ] AVX512VL,AVX512DQ,FUTURE */
        /* 241(f3 fd 28) 301 001(50) 120 023 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VRANGEPD, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+21293, 547},
    /*   3 : VRANGEPD ymmreg|mask|z,ymmrm256|b64,imm8 [r+vmi:fv:  evex.nds.256.66.0f3a.w1 50 /r ib  ] ND,AVX512VL,AVX512DQ,FUTURE */
        /* 240(f3 fd 28) 301 001(50) 110 022 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VRANGEPD, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+21303, 547},
    /*   4 : VRANGEPD zmmreg|mask|z,zmmreg*,zmmrm512|b64|sae,imm8 [rvmi:fv:  evex.nds.512.66.0f3a.w1 50 /r ib  ] AVX512DQ,FUTURE */
        /* 241(f3 fd 48) 301 001(50) 120 023 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VRANGEPD, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B64|SAE,0,0}, nasm_bytecodes+21313, 548},
    /*   5 : VRANGEPD zmmreg|mask|z,zmmrm512|b64|sae,imm8 [r+vmi:fv:  evex.nds.512.66.0f3a.w1 50 /r ib  ] ND,AVX512DQ,FUTURE */
        /* 240(f3 fd 48) 301 001(50) 110 022 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VRANGEPD, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+21323, 548},
};

static const struct itemplate instrux_VRANGEPS[6] = {
    /*   0 : VRANGEPS xmmreg|mask|z,xmmreg*,xmmrm128|b32,imm8 [rvmi:fv:  evex.nds.128.66.0f3a.w0 50 /r ib  ] AVX512VL,AVX512DQ,FUTURE */
        /* 241(f3 7d 08) 301 001(50) 120 023 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VRANGEPS, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+21333, 547},
    /*   1 : VRANGEPS xmmreg|mask|z,xmmrm128|b32,imm8 [r+vmi:fv:  evex.nds.128.66.0f3a.w0 50 /r ib  ] ND,AVX512VL,AVX512DQ,FUTURE */
        /* 240(f3 7d 08) 301 001(50) 110 022 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VRANGEPS, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+21343, 547},
    /*   2 : VRANGEPS ymmreg|mask|z,ymmreg*,ymmrm256|b32,imm8 [rvmi:fv:  evex.nds.256.66.0f3a.w0 50 /r ib  ] AVX512VL,AVX512DQ,FUTURE */
        /* 241(f3 7d 28) 301 001(50) 120 023 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VRANGEPS, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+21353, 547},
    /*   3 : VRANGEPS ymmreg|mask|z,ymmrm256|b32,imm8 [r+vmi:fv:  evex.nds.256.66.0f3a.w0 50 /r ib  ] ND,AVX512VL,AVX512DQ,FUTURE */
        /* 240(f3 7d 28) 301 001(50) 110 022 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VRANGEPS, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+21363, 547},
    /*   4 : VRANGEPS zmmreg|mask|z,zmmreg*,zmmrm512|b32|sae,imm8 [rvmi:fv:  evex.nds.512.66.0f3a.w0 50 /r ib  ] AVX512DQ,FUTURE */
        /* 241(f3 7d 48) 301 001(50) 120 023 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VRANGEPS, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B32|SAE,0,0}, nasm_bytecodes+21373, 548},
    /*   5 : VRANGEPS zmmreg|mask|z,zmmrm512|b32|sae,imm8 [r+vmi:fv:  evex.nds.512.66.0f3a.w0 50 /r ib  ] ND,AVX512DQ,FUTURE */
        /* 240(f3 7d 48) 301 001(50) 110 022 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VRANGEPS, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+21383, 548},
};

static const struct itemplate instrux_VRANGESD[2] = {
    /*   0 : VRANGESD xmmreg|mask|z,xmmreg*,xmmrm64|sae,imm8 [rvmi:t1s: evex.nds.lig.66.0f3a.w1 51 /r ib  ] AVX512DQ,FUTURE */
        /* 241(f3 fd 08) 306 001(51) 120 023 : LIG,EVEX,PROT,AVX512DQ,FUTURE */
        {I_VRANGESD, 4, {XMMREG,XMMREG,RM_XMM|BITS64,IMM_NORMAL|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+21393, 554},
    /*   1 : VRANGESD xmmreg|mask|z,xmmrm64|sae,imm8 [r+vmi:t1s: evex.nds.lig.66.0f3a.w1 51 /r ib  ] ND,AVX512DQ,FUTURE */
        /* 240(f3 fd 08) 306 001(51) 110 022 : LIG,EVEX,PROT,AVX512DQ,FUTURE */
        {I_VRANGESD, 3, {XMMREG,RM_XMM|BITS64,IMM_NORMAL|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+21403, 554},
};

static const struct itemplate instrux_VRANGESS[2] = {
    /*   0 : VRANGESS xmmreg|mask|z,xmmreg*,xmmrm32|sae,imm8 [rvmi:t1s: evex.nds.lig.66.0f3a.w0 51 /r ib  ] AVX512DQ,FUTURE */
        /* 241(f3 7d 08) 306 001(51) 120 023 : LIG,EVEX,PROT,AVX512DQ,FUTURE */
        {I_VRANGESS, 4, {XMMREG,XMMREG,RM_XMM|BITS32,IMM_NORMAL|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+21413, 554},
    /*   1 : VRANGESS xmmreg|mask|z,xmmrm32|sae,imm8 [r+vmi:t1s: evex.nds.lig.66.0f3a.w0 51 /r ib  ] ND,AVX512DQ,FUTURE */
        /* 240(f3 7d 08) 306 001(51) 110 022 : LIG,EVEX,PROT,AVX512DQ,FUTURE */
        {I_VRANGESS, 3, {XMMREG,RM_XMM|BITS32,IMM_NORMAL|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+21423, 554},
};

static const struct itemplate instrux_VRCP14PD[3] = {
    /*   0 : VRCP14PD xmmreg|mask|z,xmmrm128|b64 [rm:fv:    evex.128.66.0f38.w1 4c /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 fd 08) 301 001(4c) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VRCP14PD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+43695, 544},
    /*   1 : VRCP14PD ymmreg|mask|z,ymmrm256|b64 [rm:fv:    evex.256.66.0f38.w1 4c /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 fd 28) 301 001(4c) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VRCP14PD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+43704, 544},
    /*   2 : VRCP14PD zmmreg|mask|z,zmmrm512|b64 [rm:fv:    evex.512.66.0f38.w1 4c /r         ] AVX512,FUTURE */
        /* 250(f2 fd 48) 301 001(4c) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VRCP14PD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+43713, 545},
};

static const struct itemplate instrux_VRCP14PS[3] = {
    /*   0 : VRCP14PS xmmreg|mask|z,xmmrm128|b32 [rm:fv:    evex.128.66.0f38.w0 4c /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 08) 301 001(4c) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VRCP14PS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+43722, 544},
    /*   1 : VRCP14PS ymmreg|mask|z,ymmrm256|b32 [rm:fv:    evex.256.66.0f38.w0 4c /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 28) 301 001(4c) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VRCP14PS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+43731, 544},
    /*   2 : VRCP14PS zmmreg|mask|z,zmmrm512|b32 [rm:fv:    evex.512.66.0f38.w0 4c /r         ] AVX512,FUTURE */
        /* 250(f2 7d 48) 301 001(4c) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VRCP14PS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+43740, 545},
};

static const struct itemplate instrux_VRCP14SD[2] = {
    /*   0 : VRCP14SD xmmreg|mask|z,xmmreg*,xmmrm64 [rvm:t1s:  evex.nds.lig.66.0f38.w1 4d /r     ] AVX512,FUTURE */
        /* 241(f2 fd 08) 306 001(4d) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VRCP14SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+43749, 546},
    /*   1 : VRCP14SD xmmreg|mask|z,xmmrm64 [r+vm:t1s:  evex.nds.lig.66.0f38.w1 4d /r     ] ND,AVX512,FUTURE */
        /* 240(f2 fd 08) 306 001(4d) 110 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VRCP14SD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+43758, 546},
};

static const struct itemplate instrux_VRCP14SS[2] = {
    /*   0 : VRCP14SS xmmreg|mask|z,xmmreg*,xmmrm32 [rvm:t1s:  evex.nds.lig.66.0f38.w0 4d /r     ] AVX512,FUTURE */
        /* 241(f2 7d 08) 306 001(4d) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VRCP14SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+43767, 546},
    /*   1 : VRCP14SS xmmreg|mask|z,xmmrm32 [r+vm:t1s:  evex.nds.lig.66.0f38.w0 4d /r     ] ND,AVX512,FUTURE */
        /* 240(f2 7d 08) 306 001(4d) 110 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VRCP14SS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+43776, 546},
};

static const struct itemplate instrux_VRCP28PD[1] = {
    /*   0 : VRCP28PD zmmreg|mask|z,zmmrm512|b64|sae [rm:fv:    evex.512.66.0f38.w1 ca /r         ] AVX512ER,FUTURE */
        /* 250(f2 fd 48) 301 001(ca) 110 : EVEX,PROT,AVX512ER,FUTURE */
        {I_VRCP28PD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+43785, 552},
};

static const struct itemplate instrux_VRCP28PS[1] = {
    /*   0 : VRCP28PS zmmreg|mask|z,zmmrm512|b32|sae [rm:fv:    evex.512.66.0f38.w0 ca /r         ] AVX512ER,FUTURE */
        /* 250(f2 7d 48) 301 001(ca) 110 : EVEX,PROT,AVX512ER,FUTURE */
        {I_VRCP28PS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+43794, 552},
};

static const struct itemplate instrux_VRCP28SD[2] = {
    /*   0 : VRCP28SD xmmreg|mask|z,xmmreg*,xmmrm64|sae [rvm:t1s:  evex.nds.lig.66.0f38.w1 cb /r     ] AVX512ER,FUTURE */
        /* 241(f2 fd 08) 306 001(cb) 120 : LIG,EVEX,PROT,AVX512ER,FUTURE */
        {I_VRCP28SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+43803, 565},
    /*   1 : VRCP28SD xmmreg|mask|z,xmmrm64|sae [r+vm:t1s:  evex.nds.lig.66.0f38.w1 cb /r     ] ND,AVX512ER,FUTURE */
        /* 240(f2 fd 08) 306 001(cb) 110 : LIG,EVEX,PROT,AVX512ER,FUTURE */
        {I_VRCP28SD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+43812, 565},
};

static const struct itemplate instrux_VRCP28SS[2] = {
    /*   0 : VRCP28SS xmmreg|mask|z,xmmreg*,xmmrm32|sae [rvm:t1s:  evex.nds.lig.66.0f38.w0 cb /r     ] AVX512ER,FUTURE */
        /* 241(f2 7d 08) 306 001(cb) 120 : LIG,EVEX,PROT,AVX512ER,FUTURE */
        {I_VRCP28SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+43821, 565},
    /*   1 : VRCP28SS xmmreg|mask|z,xmmrm32|sae [r+vm:t1s:  evex.nds.lig.66.0f38.w0 cb /r     ] ND,AVX512ER,FUTURE */
        /* 240(f2 7d 08) 306 001(cb) 110 : LIG,EVEX,PROT,AVX512ER,FUTURE */
        {I_VRCP28SS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+43830, 565},
};

static const struct itemplate instrux_VREDUCEPD[3] = {
    /*   0 : VREDUCEPD xmmreg|mask|z,xmmrm128|b64,imm8 [rmi:fv:   evex.128.66.0f3a.w1 56 /r ib      ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f3 fd 08) 301 001(56) 110 022 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VREDUCEPD, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+21433, 547},
    /*   1 : VREDUCEPD ymmreg|mask|z,ymmrm256|b64,imm8 [rmi:fv:   evex.256.66.0f3a.w1 56 /r ib      ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f3 fd 28) 301 001(56) 110 022 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VREDUCEPD, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+21443, 547},
    /*   2 : VREDUCEPD zmmreg|mask|z,zmmrm512|b64|sae,imm8 [rmi:fv:   evex.512.66.0f3a.w1 56 /r ib      ] AVX512DQ,FUTURE */
        /* 250(f3 fd 48) 301 001(56) 110 022 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VREDUCEPD, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+21453, 548},
};

static const struct itemplate instrux_VREDUCEPS[3] = {
    /*   0 : VREDUCEPS xmmreg|mask|z,xmmrm128|b32,imm8 [rmi:fv:   evex.128.66.0f3a.w0 56 /r ib      ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f3 7d 08) 301 001(56) 110 022 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VREDUCEPS, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+21463, 547},
    /*   1 : VREDUCEPS ymmreg|mask|z,ymmrm256|b32,imm8 [rmi:fv:   evex.256.66.0f3a.w0 56 /r ib      ] AVX512VL,AVX512DQ,FUTURE */
        /* 250(f3 7d 28) 301 001(56) 110 022 : EVEX,PROT,AVX512VL,AVX512DQ,FUTURE */
        {I_VREDUCEPS, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+21473, 547},
    /*   2 : VREDUCEPS zmmreg|mask|z,zmmrm512|b32|sae,imm8 [rmi:fv:   evex.512.66.0f3a.w0 56 /r ib      ] AVX512DQ,FUTURE */
        /* 250(f3 7d 48) 301 001(56) 110 022 : EVEX,PROT,AVX512DQ,FUTURE */
        {I_VREDUCEPS, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+21483, 548},
};

static const struct itemplate instrux_VREDUCESD[2] = {
    /*   0 : VREDUCESD xmmreg|mask|z,xmmreg*,xmmrm64|sae,imm8 [rvmi:t1s: evex.nds.lig.66.0f3a.w1 57 /r ib  ] AVX512DQ,FUTURE */
        /* 241(f3 fd 08) 306 001(57) 120 023 : LIG,EVEX,PROT,AVX512DQ,FUTURE */
        {I_VREDUCESD, 4, {XMMREG,XMMREG,RM_XMM|BITS64,IMM_NORMAL|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+21493, 554},
    /*   1 : VREDUCESD xmmreg|mask|z,xmmrm64|sae,imm8 [r+vmi:t1s: evex.nds.lig.66.0f3a.w1 57 /r ib  ] ND,AVX512DQ,FUTURE */
        /* 240(f3 fd 08) 306 001(57) 110 022 : LIG,EVEX,PROT,AVX512DQ,FUTURE */
        {I_VREDUCESD, 3, {XMMREG,RM_XMM|BITS64,IMM_NORMAL|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+21503, 554},
};

static const struct itemplate instrux_VREDUCESS[2] = {
    /*   0 : VREDUCESS xmmreg|mask|z,xmmreg*,xmmrm32|sae,imm8 [rvmi:t1s: evex.nds.lig.66.0f3a.w0 57 /r ib  ] AVX512DQ,FUTURE */
        /* 241(f3 7d 08) 306 001(57) 120 023 : LIG,EVEX,PROT,AVX512DQ,FUTURE */
        {I_VREDUCESS, 4, {XMMREG,XMMREG,RM_XMM|BITS32,IMM_NORMAL|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+21513, 554},
    /*   1 : VREDUCESS xmmreg|mask|z,xmmrm32|sae,imm8 [r+vmi:t1s: evex.nds.lig.66.0f3a.w0 57 /r ib  ] ND,AVX512DQ,FUTURE */
        /* 240(f3 7d 08) 306 001(57) 110 022 : LIG,EVEX,PROT,AVX512DQ,FUTURE */
        {I_VREDUCESS, 3, {XMMREG,RM_XMM|BITS32,IMM_NORMAL|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+21523, 554},
};

static const struct itemplate instrux_VRNDSCALEPD[3] = {
    /*   0 : VRNDSCALEPD xmmreg|mask|z,xmmrm128|b64,imm8 [rmi:fv:   evex.128.66.0f3a.w1 09 /r ib      ] AVX512,AVX512VL,FUTURE */
        /* 250(f3 fd 08) 301 001(09) 110 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VRNDSCALEPD, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+21533, 544},
    /*   1 : VRNDSCALEPD ymmreg|mask|z,ymmrm256|b64,imm8 [rmi:fv:   evex.256.66.0f3a.w1 09 /r ib      ] AVX512,AVX512VL,FUTURE */
        /* 250(f3 fd 28) 301 001(09) 110 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VRNDSCALEPD, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+21543, 544},
    /*   2 : VRNDSCALEPD zmmreg|mask|z,zmmrm512|b64|sae,imm8 [rmi:fv:   evex.512.66.0f3a.w1 09 /r ib      ] AVX512,FUTURE */
        /* 250(f3 fd 48) 301 001(09) 110 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VRNDSCALEPD, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+21553, 545},
};

static const struct itemplate instrux_VRNDSCALEPH[3] = {
    /*   0 : VRNDSCALEPH xmmreg|mask|z,xmmrm128|b16,imm8 [rmi:fv:   evex.128.np.0f3a.w0 08 /r ib      ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f3 7c 08) 301 001(08) 110 022 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VRNDSCALEPH, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+21563, 566},
    /*   1 : VRNDSCALEPH ymmreg|mask|z,ymmrm256|b16,imm8 [rmi:fv:   evex.256.np.0f3a.w0 08 /r ib      ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f3 7c 28) 301 001(08) 110 022 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VRNDSCALEPH, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+21573, 566},
    /*   2 : VRNDSCALEPH zmmreg|mask|z,zmmrm512|b16|sae,imm8 [rmi:fv:   evex.512.np.0f3a.w0 08 /r ib      ] AVX512FP16,FUTURE */
        /* 250(f3 7c 48) 301 001(08) 110 022 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VRNDSCALEPH, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+21583, 567},
};

static const struct itemplate instrux_VRNDSCALEPS[3] = {
    /*   0 : VRNDSCALEPS xmmreg|mask|z,xmmrm128|b32,imm8 [rmi:fv:   evex.128.66.0f3a.w0 08 /r ib      ] AVX512,AVX512VL,FUTURE */
        /* 250(f3 7d 08) 301 001(08) 110 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VRNDSCALEPS, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+21593, 544},
    /*   1 : VRNDSCALEPS ymmreg|mask|z,ymmrm256|b32,imm8 [rmi:fv:   evex.256.66.0f3a.w0 08 /r ib      ] AVX512,AVX512VL,FUTURE */
        /* 250(f3 7d 28) 301 001(08) 110 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VRNDSCALEPS, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+21603, 544},
    /*   2 : VRNDSCALEPS zmmreg|mask|z,zmmrm512|b32|sae,imm8 [rmi:fv:   evex.512.66.0f3a.w0 08 /r ib      ] AVX512,FUTURE */
        /* 250(f3 7d 48) 301 001(08) 110 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VRNDSCALEPS, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+21613, 545},
};

static const struct itemplate instrux_VRNDSCALESD[2] = {
    /*   0 : VRNDSCALESD xmmreg|mask|z,xmmreg*,xmmrm64|sae,imm8 [rvmi:t1s: evex.nds.lig.66.0f3a.w1 0b /r ib  ] AVX512,FUTURE */
        /* 241(f3 fd 08) 306 001(0b) 120 023 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VRNDSCALESD, 4, {XMMREG,XMMREG,RM_XMM|BITS64,IMM_NORMAL|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+21623, 546},
    /*   1 : VRNDSCALESD xmmreg|mask|z,xmmrm64|sae,imm8 [r+vmi:t1s: evex.nds.lig.66.0f3a.w1 0b /r ib  ] ND,AVX512,FUTURE */
        /* 240(f3 fd 08) 306 001(0b) 110 022 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VRNDSCALESD, 3, {XMMREG,RM_XMM|BITS64,IMM_NORMAL|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+21633, 546},
};

static const struct itemplate instrux_VRNDSCALESH[2] = {
    /*   0 : VRNDSCALESH xmmreg|mask|z,xmmreg*,xmmrm16|sae,imm8 [rvmi:t1s: evex.nds.lig.np.0f3a.w0 0a /r ib  ] AVX512FP16,FUTURE */
        /* 241(f3 7c 08) 306 001(0a) 120 023 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VRNDSCALESH, 4, {XMMREG,XMMREG,RM_XMM|BITS16,IMM_NORMAL|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+21643, 568},
    /*   1 : VRNDSCALESH xmmreg|mask|z,xmmrm16|sae,imm8 [r+vmi:t1s: evex.nds.lig.np.0f3a.w0 0a /r ib  ] ND,AVX512FP16,FUTURE */
        /* 240(f3 7c 08) 306 001(0a) 110 022 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VRNDSCALESH, 3, {XMMREG,RM_XMM|BITS16,IMM_NORMAL|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+21653, 568},
};

static const struct itemplate instrux_VRNDSCALESS[2] = {
    /*   0 : VRNDSCALESS xmmreg|mask|z,xmmreg*,xmmrm32|sae,imm8 [rvmi:t1s: evex.nds.lig.66.0f3a.w0 0a /r ib  ] AVX512,FUTURE */
        /* 241(f3 7d 08) 306 001(0a) 120 023 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VRNDSCALESS, 4, {XMMREG,XMMREG,RM_XMM|BITS32,IMM_NORMAL|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+21663, 546},
    /*   1 : VRNDSCALESS xmmreg|mask|z,xmmrm32|sae,imm8 [r+vmi:t1s: evex.nds.lig.66.0f3a.w0 0a /r ib  ] ND,AVX512,FUTURE */
        /* 240(f3 7d 08) 306 001(0a) 110 022 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VRNDSCALESS, 3, {XMMREG,RM_XMM|BITS32,IMM_NORMAL|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+21673, 546},
};

static const struct itemplate instrux_VRSQRT14PD[3] = {
    /*   0 : VRSQRT14PD xmmreg|mask|z,xmmrm128|b64 [rm:fv:    evex.128.66.0f38.w1 4e /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 fd 08) 301 001(4e) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VRSQRT14PD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+43839, 544},
    /*   1 : VRSQRT14PD ymmreg|mask|z,ymmrm256|b64 [rm:fv:    evex.256.66.0f38.w1 4e /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 fd 28) 301 001(4e) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VRSQRT14PD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+43848, 544},
    /*   2 : VRSQRT14PD zmmreg|mask|z,zmmrm512|b64 [rm:fv:    evex.512.66.0f38.w1 4e /r         ] AVX512,FUTURE */
        /* 250(f2 fd 48) 301 001(4e) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VRSQRT14PD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+43857, 545},
};

static const struct itemplate instrux_VRSQRT14PS[3] = {
    /*   0 : VRSQRT14PS xmmreg|mask|z,xmmrm128|b32 [rm:fv:    evex.128.66.0f38.w0 4e /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 08) 301 001(4e) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VRSQRT14PS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+43866, 544},
    /*   1 : VRSQRT14PS ymmreg|mask|z,ymmrm256|b32 [rm:fv:    evex.256.66.0f38.w0 4e /r         ] AVX512,AVX512VL,FUTURE */
        /* 250(f2 7d 28) 301 001(4e) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VRSQRT14PS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+43875, 544},
    /*   2 : VRSQRT14PS zmmreg|mask|z,zmmrm512|b32 [rm:fv:    evex.512.66.0f38.w0 4e /r         ] AVX512,FUTURE */
        /* 250(f2 7d 48) 301 001(4e) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VRSQRT14PS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+43884, 545},
};

static const struct itemplate instrux_VRSQRT14SD[2] = {
    /*   0 : VRSQRT14SD xmmreg|mask|z,xmmreg*,xmmrm64 [rvm:t1s:  evex.nds.lig.66.0f38.w1 4f /r     ] AVX512,FUTURE */
        /* 241(f2 fd 08) 306 001(4f) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VRSQRT14SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+43893, 546},
    /*   1 : VRSQRT14SD xmmreg|mask|z,xmmrm64 [r+vm:t1s:  evex.nds.lig.66.0f38.w1 4f /r     ] ND,AVX512,FUTURE */
        /* 240(f2 fd 08) 306 001(4f) 110 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VRSQRT14SD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+43902, 546},
};

static const struct itemplate instrux_VRSQRT14SS[2] = {
    /*   0 : VRSQRT14SS xmmreg|mask|z,xmmreg*,xmmrm32 [rvm:t1s:  evex.nds.lig.66.0f38.w0 4f /r     ] AVX512,FUTURE */
        /* 241(f2 7d 08) 306 001(4f) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VRSQRT14SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+43911, 546},
    /*   1 : VRSQRT14SS xmmreg|mask|z,xmmrm32 [r+vm:t1s:  evex.nds.lig.66.0f38.w0 4f /r     ] ND,AVX512,FUTURE */
        /* 240(f2 7d 08) 306 001(4f) 110 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VRSQRT14SS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+43920, 546},
};

static const struct itemplate instrux_VRSQRT28PD[1] = {
    /*   0 : VRSQRT28PD zmmreg|mask|z,zmmrm512|b64|sae [rm:fv:    evex.512.66.0f38.w1 cc /r         ] AVX512ER,FUTURE */
        /* 250(f2 fd 48) 301 001(cc) 110 : EVEX,PROT,AVX512ER,FUTURE */
        {I_VRSQRT28PD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+43929, 552},
};

static const struct itemplate instrux_VRSQRT28PS[1] = {
    /*   0 : VRSQRT28PS zmmreg|mask|z,zmmrm512|b32|sae [rm:fv:    evex.512.66.0f38.w0 cc /r         ] AVX512ER,FUTURE */
        /* 250(f2 7d 48) 301 001(cc) 110 : EVEX,PROT,AVX512ER,FUTURE */
        {I_VRSQRT28PS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+43938, 552},
};

static const struct itemplate instrux_VRSQRT28SD[2] = {
    /*   0 : VRSQRT28SD xmmreg|mask|z,xmmreg*,xmmrm64|sae [rvm:t1s:  evex.nds.lig.66.0f38.w1 cd /r     ] AVX512ER,FUTURE */
        /* 241(f2 fd 08) 306 001(cd) 120 : LIG,EVEX,PROT,AVX512ER,FUTURE */
        {I_VRSQRT28SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+43947, 565},
    /*   1 : VRSQRT28SD xmmreg|mask|z,xmmrm64|sae [r+vm:t1s:  evex.nds.lig.66.0f38.w1 cd /r     ] ND,AVX512ER,FUTURE */
        /* 240(f2 fd 08) 306 001(cd) 110 : LIG,EVEX,PROT,AVX512ER,FUTURE */
        {I_VRSQRT28SD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+43956, 565},
};

static const struct itemplate instrux_VRSQRT28SS[2] = {
    /*   0 : VRSQRT28SS xmmreg|mask|z,xmmreg*,xmmrm32|sae [rvm:t1s:  evex.nds.lig.66.0f38.w0 cd /r     ] AVX512ER,FUTURE */
        /* 241(f2 7d 08) 306 001(cd) 120 : LIG,EVEX,PROT,AVX512ER,FUTURE */
        {I_VRSQRT28SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+43965, 565},
    /*   1 : VRSQRT28SS xmmreg|mask|z,xmmrm32|sae [r+vm:t1s:  evex.nds.lig.66.0f38.w0 cd /r     ] ND,AVX512ER,FUTURE */
        /* 240(f2 7d 08) 306 001(cd) 110 : LIG,EVEX,PROT,AVX512ER,FUTURE */
        {I_VRSQRT28SS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+43974, 565},
};

static const struct itemplate instrux_VSCALEFPD[6] = {
    /*   0 : VSCALEFPD xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv:   evex.nds.128.66.0f38.w1 2c /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 08) 301 001(2c) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSCALEFPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+43983, 544},
    /*   1 : VSCALEFPD xmmreg|mask|z,xmmrm128|b64 [r+vm:fv:   evex.nds.128.66.0f38.w1 2c /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 fd 08) 301 001(2c) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSCALEFPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+43992, 544},
    /*   2 : VSCALEFPD ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv:   evex.nds.256.66.0f38.w1 2c /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 fd 28) 301 001(2c) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSCALEFPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+44001, 544},
    /*   3 : VSCALEFPD ymmreg|mask|z,ymmrm256|b64 [r+vm:fv:   evex.nds.256.66.0f38.w1 2c /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 fd 28) 301 001(2c) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSCALEFPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+44010, 544},
    /*   4 : VSCALEFPD zmmreg|mask|z,zmmreg*,zmmrm512|b64|er [rvm:fv:   evex.nds.512.66.0f38.w1 2c /r     ] AVX512,FUTURE */
        /* 241(f2 fd 48) 301 001(2c) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VSCALEFPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+44019, 545},
    /*   5 : VSCALEFPD zmmreg|mask|z,zmmrm512|b64|er [r+vm:fv:   evex.nds.512.66.0f38.w1 2c /r     ] ND,AVX512,FUTURE */
        /* 240(f2 fd 48) 301 001(2c) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VSCALEFPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+44028, 545},
};

static const struct itemplate instrux_VSCALEFPS[6] = {
    /*   0 : VSCALEFPS xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.nds.128.66.0f38.w0 2c /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 08) 301 001(2c) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSCALEFPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+44037, 544},
    /*   1 : VSCALEFPS xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.nds.128.66.0f38.w0 2c /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 7d 08) 301 001(2c) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSCALEFPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+44046, 544},
    /*   2 : VSCALEFPS ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.nds.256.66.0f38.w0 2c /r     ] AVX512,AVX512VL,FUTURE */
        /* 241(f2 7d 28) 301 001(2c) 120 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSCALEFPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+44055, 544},
    /*   3 : VSCALEFPS ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.nds.256.66.0f38.w0 2c /r     ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f2 7d 28) 301 001(2c) 110 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSCALEFPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+44064, 544},
    /*   4 : VSCALEFPS zmmreg|mask|z,zmmreg*,zmmrm512|b32|er [rvm:fv:   evex.nds.512.66.0f38.w0 2c /r     ] AVX512,FUTURE */
        /* 241(f2 7d 48) 301 001(2c) 120 : EVEX,PROT,AVX512,FUTURE */
        {I_VSCALEFPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+44073, 545},
    /*   5 : VSCALEFPS zmmreg|mask|z,zmmrm512|b32|er [r+vm:fv:   evex.nds.512.66.0f38.w0 2c /r     ] ND,AVX512,FUTURE */
        /* 240(f2 7d 48) 301 001(2c) 110 : EVEX,PROT,AVX512,FUTURE */
        {I_VSCALEFPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+44082, 545},
};

static const struct itemplate instrux_VSCALEFSD[2] = {
    /*   0 : VSCALEFSD xmmreg|mask|z,xmmreg*,xmmrm64|er [rvm:t1s:  evex.nds.lig.66.0f38.w1 2d /r     ] AVX512,FUTURE */
        /* 241(f2 fd 08) 306 001(2d) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VSCALEFSD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+44091, 546},
    /*   1 : VSCALEFSD xmmreg|mask|z,xmmrm64|er [r+vm:t1s:  evex.nds.lig.66.0f38.w1 2d /r     ] ND,AVX512,FUTURE */
        /* 240(f2 fd 08) 306 001(2d) 110 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VSCALEFSD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+44100, 546},
};

static const struct itemplate instrux_VSCALEFSS[2] = {
    /*   0 : VSCALEFSS xmmreg|mask|z,xmmreg*,xmmrm32|er [rvm:t1s:  evex.nds.lig.66.0f38.w0 2d /r     ] AVX512,FUTURE */
        /* 241(f2 7d 08) 306 001(2d) 120 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VSCALEFSS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+44109, 546},
    /*   1 : VSCALEFSS xmmreg|mask|z,xmmrm32|er [r+vm:t1s:  evex.nds.lig.66.0f38.w0 2d /r     ] ND,AVX512,FUTURE */
        /* 240(f2 7d 08) 306 001(2d) 110 : LIG,EVEX,PROT,AVX512,FUTURE */
        {I_VSCALEFSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+44118, 546},
};

static const struct itemplate instrux_VSCATTERDPD[3] = {
    /*   0 : VSCATTERDPD xmem64|mask,xmmreg [mr:t1s:   vsibx evex.128.66.0f38.w1 a2 /r   ] AVX512,AVX512VL,FUTURE */
        /* 374 250(f2 fd 08) 306 001(a2) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSCATTERDPD, 2, {XMEM|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+21683, 544},
    /*   1 : VSCATTERDPD xmem64|mask,ymmreg [mr:t1s:   vsibx evex.256.66.0f38.w1 a2 /r   ] AVX512,AVX512VL,FUTURE */
        /* 374 250(f2 fd 28) 306 001(a2) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSCATTERDPD, 2, {XMEM|BITS64,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+21693, 544},
    /*   2 : VSCATTERDPD ymem64|mask,zmmreg [mr:t1s:   vsiby evex.512.66.0f38.w1 a2 /r   ] AVX512,FUTURE */
        /* 375 250(f2 fd 48) 306 001(a2) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VSCATTERDPD, 2, {YMEM|BITS64,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+21703, 545},
};

static const struct itemplate instrux_VSCATTERDPS[3] = {
    /*   0 : VSCATTERDPS xmem32|mask,xmmreg [mr:t1s:   vsibx evex.128.66.0f38.w0 a2 /r   ] AVX512,AVX512VL,FUTURE */
        /* 374 250(f2 7d 08) 306 001(a2) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSCATTERDPS, 2, {XMEM|BITS32,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+21713, 544},
    /*   1 : VSCATTERDPS ymem32|mask,ymmreg [mr:t1s:   vsiby evex.256.66.0f38.w0 a2 /r   ] AVX512,AVX512VL,FUTURE */
        /* 375 250(f2 7d 28) 306 001(a2) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSCATTERDPS, 2, {YMEM|BITS32,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+21723, 544},
    /*   2 : VSCATTERDPS zmem32|mask,zmmreg [mr:t1s:   vsibz evex.512.66.0f38.w0 a2 /r   ] AVX512,FUTURE */
        /* 376 250(f2 7d 48) 306 001(a2) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VSCATTERDPS, 2, {ZMEM|BITS32,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+21733, 545},
};

static const struct itemplate instrux_VSCATTERPF0DPD[1] = {
    /*   0 : VSCATTERPF0DPD ymem64|mask [m:t1s:    vsiby evex.512.66.0f38.w1 c6 /5   ] AVX512PF,FUTURE */
        /* 375 250(f2 fd 48) 306 001(c6) 205 : EVEX,PROT,AVX512PF,FUTURE */
        {I_VSCATTERPF0DPD, 1, {YMEM|BITS64,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+21743, 555},
};

static const struct itemplate instrux_VSCATTERPF0DPS[1] = {
    /*   0 : VSCATTERPF0DPS zmem32|mask [m:t1s:    vsibz evex.512.66.0f38.w0 c6 /5   ] AVX512PF,FUTURE */
        /* 376 250(f2 7d 48) 306 001(c6) 205 : EVEX,PROT,AVX512PF,FUTURE */
        {I_VSCATTERPF0DPS, 1, {ZMEM|BITS32,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+21753, 555},
};

static const struct itemplate instrux_VSCATTERPF0QPD[1] = {
    /*   0 : VSCATTERPF0QPD zmem64|mask [m:t1s:    vsibz evex.512.66.0f38.w1 c7 /5   ] AVX512PF,FUTURE */
        /* 376 250(f2 fd 48) 306 001(c7) 205 : EVEX,PROT,AVX512PF,FUTURE */
        {I_VSCATTERPF0QPD, 1, {ZMEM|BITS64,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+21763, 555},
};

static const struct itemplate instrux_VSCATTERPF0QPS[1] = {
    /*   0 : VSCATTERPF0QPS zmem32|mask [m:t1s:    vsibz evex.512.66.0f38.w0 c7 /5   ] AVX512PF,FUTURE */
        /* 376 250(f2 7d 48) 306 001(c7) 205 : EVEX,PROT,AVX512PF,FUTURE */
        {I_VSCATTERPF0QPS, 1, {ZMEM|BITS32,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+21773, 555},
};

static const struct itemplate instrux_VSCATTERPF1DPD[1] = {
    /*   0 : VSCATTERPF1DPD ymem64|mask [m:t1s:    vsiby evex.512.66.0f38.w1 c6 /6   ] AVX512PF,FUTURE */
        /* 375 250(f2 fd 48) 306 001(c6) 206 : EVEX,PROT,AVX512PF,FUTURE */
        {I_VSCATTERPF1DPD, 1, {YMEM|BITS64,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+21783, 555},
};

static const struct itemplate instrux_VSCATTERPF1DPS[1] = {
    /*   0 : VSCATTERPF1DPS zmem32|mask [m:t1s:    vsibz evex.512.66.0f38.w0 c6 /6   ] AVX512PF,FUTURE */
        /* 376 250(f2 7d 48) 306 001(c6) 206 : EVEX,PROT,AVX512PF,FUTURE */
        {I_VSCATTERPF1DPS, 1, {ZMEM|BITS32,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+21793, 555},
};

static const struct itemplate instrux_VSCATTERPF1QPD[1] = {
    /*   0 : VSCATTERPF1QPD zmem64|mask [m:t1s:    vsibz evex.512.66.0f38.w1 c7 /6   ] AVX512PF,FUTURE */
        /* 376 250(f2 fd 48) 306 001(c7) 206 : EVEX,PROT,AVX512PF,FUTURE */
        {I_VSCATTERPF1QPD, 1, {ZMEM|BITS64,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+21803, 555},
};

static const struct itemplate instrux_VSCATTERPF1QPS[1] = {
    /*   0 : VSCATTERPF1QPS zmem32|mask [m:t1s:    vsibz evex.512.66.0f38.w0 c7 /6   ] AVX512PF,FUTURE */
        /* 376 250(f2 7d 48) 306 001(c7) 206 : EVEX,PROT,AVX512PF,FUTURE */
        {I_VSCATTERPF1QPS, 1, {ZMEM|BITS32,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+21813, 555},
};

static const struct itemplate instrux_VSCATTERQPD[3] = {
    /*   0 : VSCATTERQPD xmem64|mask,xmmreg [mr:t1s:   vsibx evex.128.66.0f38.w1 a3 /r   ] AVX512,AVX512VL,FUTURE */
        /* 374 250(f2 fd 08) 306 001(a3) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSCATTERQPD, 2, {XMEM|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+21823, 544},
    /*   1 : VSCATTERQPD ymem64|mask,ymmreg [mr:t1s:   vsiby evex.256.66.0f38.w1 a3 /r   ] AVX512,AVX512VL,FUTURE */
        /* 375 250(f2 fd 28) 306 001(a3) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSCATTERQPD, 2, {YMEM|BITS64,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+21833, 544},
    /*   2 : VSCATTERQPD zmem64|mask,zmmreg [mr:t1s:   vsibz evex.512.66.0f38.w1 a3 /r   ] AVX512,FUTURE */
        /* 376 250(f2 fd 48) 306 001(a3) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VSCATTERQPD, 2, {ZMEM|BITS64,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+21843, 545},
};

static const struct itemplate instrux_VSCATTERQPS[3] = {
    /*   0 : VSCATTERQPS xmem32|mask,xmmreg [mr:t1s:   vsibx evex.128.66.0f38.w0 a3 /r   ] AVX512,AVX512VL,FUTURE */
        /* 374 250(f2 7d 08) 306 001(a3) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSCATTERQPS, 2, {XMEM|BITS32,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+21853, 544},
    /*   1 : VSCATTERQPS ymem32|mask,xmmreg [mr:t1s:   vsiby evex.256.66.0f38.w0 a3 /r   ] AVX512,AVX512VL,FUTURE */
        /* 375 250(f2 7d 28) 306 001(a3) 101 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSCATTERQPS, 2, {YMEM|BITS32,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+21863, 544},
    /*   2 : VSCATTERQPS zmem32|mask,ymmreg [mr:t1s:   vsibz evex.512.66.0f38.w0 a3 /r   ] AVX512,FUTURE */
        /* 376 250(f2 7d 48) 306 001(a3) 101 : EVEX,PROT,AVX512,FUTURE */
        {I_VSCATTERQPS, 2, {ZMEM|BITS32,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+21873, 545},
};

static const struct itemplate instrux_VSHUFF32X4[4] = {
    /*   0 : VSHUFF32X4 ymmreg|mask|z,ymmreg*,ymmrm256|b32,imm8 [rvmi:fv:  evex.nds.256.66.0f3a.w0 23 /r ib  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 28) 301 001(23) 120 023 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSHUFF32X4, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+21883, 544},
    /*   1 : VSHUFF32X4 ymmreg|mask|z,ymmrm256|b32,imm8 [r+vmi:fv:  evex.nds.256.66.0f3a.w0 23 /r ib  ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f3 7d 28) 301 001(23) 110 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSHUFF32X4, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+21893, 544},
    /*   2 : VSHUFF32X4 zmmreg|mask|z,zmmreg*,zmmrm512|b32,imm8 [rvmi:fv:  evex.nds.512.66.0f3a.w0 23 /r ib  ] AVX512,FUTURE */
        /* 241(f3 7d 48) 301 001(23) 120 023 : EVEX,PROT,AVX512,FUTURE */
        {I_VSHUFF32X4, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+21903, 545},
    /*   3 : VSHUFF32X4 zmmreg|mask|z,zmmrm512|b32,imm8 [r+vmi:fv:  evex.nds.512.66.0f3a.w0 23 /r ib  ] ND,AVX512,FUTURE */
        /* 240(f3 7d 48) 301 001(23) 110 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VSHUFF32X4, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+21913, 545},
};

static const struct itemplate instrux_VSHUFF64X2[4] = {
    /*   0 : VSHUFF64X2 ymmreg|mask|z,ymmreg*,ymmrm256|b64,imm8 [rvmi:fv:  evex.nds.256.66.0f3a.w1 23 /r ib  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 28) 301 001(23) 120 023 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSHUFF64X2, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+21923, 544},
    /*   1 : VSHUFF64X2 ymmreg|mask|z,ymmrm256|b64,imm8 [r+vmi:fv:  evex.nds.256.66.0f3a.w1 23 /r ib  ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f3 fd 28) 301 001(23) 110 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSHUFF64X2, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+21933, 544},
    /*   2 : VSHUFF64X2 zmmreg|mask|z,zmmreg*,zmmrm512|b64,imm8 [rvmi:fv:  evex.nds.512.66.0f3a.w1 23 /r ib  ] AVX512,FUTURE */
        /* 241(f3 fd 48) 301 001(23) 120 023 : EVEX,PROT,AVX512,FUTURE */
        {I_VSHUFF64X2, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+21943, 545},
    /*   3 : VSHUFF64X2 zmmreg|mask|z,zmmrm512|b64,imm8 [r+vmi:fv:  evex.nds.512.66.0f3a.w1 23 /r ib  ] ND,AVX512,FUTURE */
        /* 240(f3 fd 48) 301 001(23) 110 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VSHUFF64X2, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+21953, 545},
};

static const struct itemplate instrux_VSHUFI32X4[4] = {
    /*   0 : VSHUFI32X4 ymmreg|mask|z,ymmreg*,ymmrm256|b32,imm8 [rvmi:fv:  evex.nds.256.66.0f3a.w0 43 /r ib  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 7d 28) 301 001(43) 120 023 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSHUFI32X4, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+21963, 544},
    /*   1 : VSHUFI32X4 ymmreg|mask|z,ymmrm256|b32,imm8 [r+vmi:fv:  evex.nds.256.66.0f3a.w0 43 /r ib  ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f3 7d 28) 301 001(43) 110 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSHUFI32X4, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+21973, 544},
    /*   2 : VSHUFI32X4 zmmreg|mask|z,zmmreg*,zmmrm512|b32,imm8 [rvmi:fv:  evex.nds.512.66.0f3a.w0 43 /r ib  ] AVX512,FUTURE */
        /* 241(f3 7d 48) 301 001(43) 120 023 : EVEX,PROT,AVX512,FUTURE */
        {I_VSHUFI32X4, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+21983, 545},
    /*   3 : VSHUFI32X4 zmmreg|mask|z,zmmrm512|b32,imm8 [r+vmi:fv:  evex.nds.512.66.0f3a.w0 43 /r ib  ] ND,AVX512,FUTURE */
        /* 240(f3 7d 48) 301 001(43) 110 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VSHUFI32X4, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+21993, 545},
};

static const struct itemplate instrux_VSHUFI64X2[4] = {
    /*   0 : VSHUFI64X2 ymmreg|mask|z,ymmreg*,ymmrm256|b64,imm8 [rvmi:fv:  evex.nds.256.66.0f3a.w1 43 /r ib  ] AVX512,AVX512VL,FUTURE */
        /* 241(f3 fd 28) 301 001(43) 120 023 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSHUFI64X2, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22003, 544},
    /*   1 : VSHUFI64X2 ymmreg|mask|z,ymmrm256|b64,imm8 [r+vmi:fv:  evex.nds.256.66.0f3a.w1 43 /r ib  ] ND,AVX512,AVX512VL,FUTURE */
        /* 240(f3 fd 28) 301 001(43) 110 022 : EVEX,PROT,AVX512,AVX512VL,FUTURE */
        {I_VSHUFI64X2, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+22013, 544},
    /*   2 : VSHUFI64X2 zmmreg|mask|z,zmmreg*,zmmrm512|b64,imm8 [rvmi:fv:  evex.nds.512.66.0f3a.w1 43 /r ib  ] AVX512,FUTURE */
        /* 241(f3 fd 48) 301 001(43) 120 023 : EVEX,PROT,AVX512,FUTURE */
        {I_VSHUFI64X2, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22023, 545},
    /*   3 : VSHUFI64X2 zmmreg|mask|z,zmmrm512|b64,imm8 [r+vmi:fv:  evex.nds.512.66.0f3a.w1 43 /r ib  ] ND,AVX512,FUTURE */
        /* 240(f3 fd 48) 301 001(43) 110 022 : EVEX,PROT,AVX512,FUTURE */
        {I_VSHUFI64X2, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+22033, 545},
};

static const struct itemplate instrux_RDPKRU[1] = {
    /*   0 : RDPKRU void [          0f 01 ee                          ] LONG,PROT,PKU,X86_64 */
        /* 355 002(01 ee) : LONG,PROT,PKU,X86_64 */
        {I_RDPKRU, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70011, 569},
};

static const struct itemplate instrux_WRPKRU[1] = {
    /*   0 : WRPKRU void [          0f 01 ef                          ] LONG,PROT,PKU,X86_64 */
        /* 355 002(01 ef) : LONG,PROT,PKU,X86_64 */
        {I_WRPKRU, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70017, 569},
};

static const struct itemplate instrux_PTWRITE[2] = {
    /*   0 : PTWRITE rm32 [m:        f3 o32 0f ae /4                   ] PTWRITE,FUTURE */
        /* 333 321 355 001(ae) 204 : PTWRITE,FUTURE */
        {I_PTWRITE, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+65720, 570},
    /*   1 : PTWRITE rm64 [m:        f3 o64 0f ae /4                   ] AR0,SX,LONG,PROT,PTWRITE,X86_64 */
        /* 333 324 355 001(ae) 204 : AR0,SX,LONG,PROT,PTWRITE,X86_64 */
        {I_PTWRITE, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+65727, 571},
};

static const struct itemplate instrux_CLDEMOTE[1] = {
    /*   0 : CLDEMOTE mem [m:        np 0f 1c /0                       ] CLDEMOTE,FUTURE */
        /* 360 355 001(1c) 200 : CLDEMOTE,FUTURE */
        {I_CLDEMOTE, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+69914, 572},
};

static const struct itemplate instrux_MOVDIRI[4] = {
    /*   0 : MOVDIRI mem32,reg32 [mr:       np o32 0f38 f9 /r                 ] MOVDIRI,FUTURE */
        /* 360 321 356 001(f9) 101 : NOAPX,MOVDIRI,FUTURE */
        {I_MOVDIRI, 2, {MEMORY|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65734, 573},
    /*   1 : MOVDIRI mem64,reg64 [mr:       np o64 0f38 f9 /r                 ] LONG,PROT,MOVDIRI,X86_64 */
        /* 360 324 356 001(f9) 101 : NOAPX,LONG,PROT,MOVDIRI,X86_64 */
        {I_MOVDIRI, 2, {MEMORY|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65741, 574},
    /*   2 : MOVDIRI mem32,reg32 [mr:       evex.nd0.nf0.np.l0.m4.w0 f9 /r    ] LONG,PROT,APX,MOVDIRI,X86_64 */
        /* 250(f4 7c 08) 300 001(f9) 101 : LONG,EVEX,PROT,APX,MOVDIRI,X86_64 */
        {I_MOVDIRI, 2, {MEMORY|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44703, 575},
    /*   3 : MOVDIRI mem64,reg64 [mr:       evex.nd0.nf0.np.l0.m4.w1 f9 /r    ] LONG,PROT,APX,MOVDIRI,X86_64 */
        /* 250(f4 fc 08) 300 001(f9) 101 : LONG,EVEX,PROT,APX,MOVDIRI,X86_64 */
        {I_MOVDIRI, 2, {MEMORY|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44712, 575},
};

static const struct itemplate instrux_MOVDIR64B[4] = {
    /*   0 : MOVDIR64B reg16,mem512 [rm:       a16 66 0f38 f8 /r                 ] NOLONG,MOVDIR64B,FUTURE */
        /* 310 361 356 001(f8) 110 : NOREX,NOAPX,NOLONG,MOVDIR64B,FUTURE */
        {I_MOVDIR64B, 2, {REG_GPR|BITS16|RN_L16,MEMORY|BITS512|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65748, 576},
    /*   1 : MOVDIR64B reg32,mem512 [rm:       a32 66 0f38 f8 /r                 ] MOVDIR64B,FUTURE */
        /* 311 361 356 001(f8) 110 : NOAPX,MOVDIR64B,FUTURE */
        {I_MOVDIR64B, 2, {REG_GPR|BITS32|RN_L16,MEMORY|BITS512|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65755, 577},
    /*   2 : MOVDIR64B reg64,mem512 [rm:       a64 66 0f38 f8 /r                 ] LONG,PROT,MOVDIR64B,X86_64 */
        /* 313 361 356 001(f8) 110 : NOAPX,LONG,PROT,MOVDIR64B,X86_64 */
        {I_MOVDIR64B, 2, {REG_GPR|BITS64|RN_L16,MEMORY|BITS512|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65762, 578},
    /*   3 : MOVDIR64B reg64,mem512 [rm:       evex.nd0.nf0.66.l0.m4.w1 f8 /r    ] LONG,PROT,APX,MOVDIR64B,X86_64 */
        /* 250(f4 fd 08) 300 001(f8) 110 : LONG,EVEX,PROT,APX,MOVDIR64B,X86_64 */
        {I_MOVDIR64B, 2, {REG_GPR|BITS64,MEMORY|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+44721, 579},
};

static const struct itemplate instrux_PCONFIG[2] = {
    /*   0 : PCONFIG void [          np 0f 01 c5                       ] FL,PCONFIG,FUTURE */
        /* 360 355 002(01 c5) : FL,PCONFIG,FUTURE */
        {I_PCONFIG, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+69920, 580},
    /*   1 : PCONFIG void [          np 0f 01 c5                       ] FL,PRIV,PCONFIG,FUTURE */
        /* 360 355 002(01 c5) : FL,PRIV,PCONFIG,FUTURE */
        {I_PCONFIG, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+69920, 612},
};

static const struct itemplate instrux_PBNDKB[1] = {
    /*   0 : PBNDKB void [          np 0f 01 c7                       ] PBNDKB,FUTURE */
        /* 360 355 002(01 c7) : PBNDKB,FUTURE */
        {I_PBNDKB, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+69926, 581},
};

static const struct itemplate instrux_PREFETCHRST2[1] = {
    /*   0 : PREFETCHRST2 mem8 [m:        0f 18 /4                          ] MOVRS,FUTURE */
        /* 355 001(18) 204 : MOVRS,FUTURE */
        {I_PREFETCHRST2, 1, {MEMORY|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70119, 582},
};

static const struct itemplate instrux_GF2P8AFFINEINVQB[1] = {
    /*   0 : GF2P8AFFINEINVQB xmmreg,xmmrm128,imm8 [rmi:      66 0f3a cf /r ib                  ] SSE,GFNI,FUTURE */
        /* 361 357 001(cf) 110 022 : NOAPX,SSE,GFNI,FUTURE */
        {I_GF2P8AFFINEINVQB, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+65769, 583},
};

static const struct itemplate instrux_VGF2P8AFFINEINVQB[10] = {
    /*   0 : VGF2P8AFFINEINVQB xmmreg,xmmreg*,xmmrm128,imm8 [rvmi:     vex.nds.128.66.0f3a.w1 cf /r ib   ] AVX,GFNI,FUTURE */
        /* 261(003 201) 001(cf) 120 023 : NOAPX,VEX,AVX,GFNI,FUTURE */
        {I_VGF2P8AFFINEINVQB, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+54637, 584},
    /*   1 : VGF2P8AFFINEINVQB xmmreg,xmmrm128,imm8 [r+vmi:     vex.nds.128.66.0f3a.w1 cf /r ib   ] ND,AVX,GFNI,FUTURE */
        /* 260(003 201) 001(cf) 110 022 : NOAPX,VEX,AVX,GFNI,FUTURE */
        {I_VGF2P8AFFINEINVQB, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54645, 584},
    /*   2 : VGF2P8AFFINEINVQB ymmreg,ymmreg*,ymmrm256,imm8 [rvmi:     vex.nds.256.66.0f3a.w1 cf /r ib   ] AVX,GFNI,FUTURE */
        /* 261(003 205) 001(cf) 120 023 : NOAPX,VEX,AVX,GFNI,FUTURE */
        {I_VGF2P8AFFINEINVQB, 4, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+54653, 584},
    /*   3 : VGF2P8AFFINEINVQB ymmreg,ymmrm256,imm8 [r+vmi:     vex.nds.256.66.0f3a.w1 cf /r ib   ] ND,AVX,GFNI,FUTURE */
        /* 260(003 205) 001(cf) 110 022 : NOAPX,VEX,AVX,GFNI,FUTURE */
        {I_VGF2P8AFFINEINVQB, 3, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54661, 584},
    /*   4 : VGF2P8AFFINEINVQB xmmreg|mask|z,xmmreg*,xmmrm128|b64,imm8 [rvmi:fv:  evex.nds.128.66.0f3a.w1 cf /r ib  ] AVX512VL,GFNI,FUTURE */
        /* 241(f3 fd 08) 301 001(cf) 120 023 : EVEX,PROT,AVX512VL,GFNI,FUTURE */
        {I_VGF2P8AFFINEINVQB, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22163, 585},
    /*   5 : VGF2P8AFFINEINVQB xmmreg|mask|z,xmmrm128|b64,imm8 [r+vmi:fv:  evex.nds.128.66.0f3a.w1 cf /r ib  ] ND,AVX512VL,GFNI,FUTURE */
        /* 240(f3 fd 08) 301 001(cf) 110 022 : EVEX,PROT,AVX512VL,GFNI,FUTURE */
        {I_VGF2P8AFFINEINVQB, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+22173, 585},
    /*   6 : VGF2P8AFFINEINVQB ymmreg|mask|z,ymmreg*,ymmrm256|b64,imm8 [rvmi:fv:  evex.nds.256.66.0f3a.w1 cf /r ib  ] AVX512VL,GFNI,FUTURE */
        /* 241(f3 fd 28) 301 001(cf) 120 023 : EVEX,PROT,AVX512VL,GFNI,FUTURE */
        {I_VGF2P8AFFINEINVQB, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22183, 585},
    /*   7 : VGF2P8AFFINEINVQB ymmreg|mask|z,ymmrm256|b64,imm8 [r+vmi:fv:  evex.nds.256.66.0f3a.w1 cf /r ib  ] ND,AVX512VL,GFNI,FUTURE */
        /* 240(f3 fd 28) 301 001(cf) 110 022 : EVEX,PROT,AVX512VL,GFNI,FUTURE */
        {I_VGF2P8AFFINEINVQB, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+22193, 585},
    /*   8 : VGF2P8AFFINEINVQB zmmreg|mask|z,zmmreg*,zmmrm512|b64,imm8 [rvmi:fv:  evex.nds.512.66.0f3a.w1 cf /r ib  ] AVX512,GFNI,FUTURE */
        /* 241(f3 fd 48) 301 001(cf) 120 023 : EVEX,PROT,AVX512,GFNI,FUTURE */
        {I_VGF2P8AFFINEINVQB, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22203, 586},
    /*   9 : VGF2P8AFFINEINVQB zmmreg|mask|z,zmmrm512|b64,imm8 [r+vmi:fv:  evex.nds.512.66.0f3a.w1 cf /r ib  ] ND,AVX512,GFNI,FUTURE */
        /* 240(f3 fd 48) 301 001(cf) 110 022 : EVEX,PROT,AVX512,GFNI,FUTURE */
        {I_VGF2P8AFFINEINVQB, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+22213, 586},
};

static const struct itemplate instrux_GF2P8AFFINEQB[1] = {
    /*   0 : GF2P8AFFINEQB xmmreg,xmmrm128,imm8 [rmi:      66 0f3a ce /r ib                  ] SSE,GFNI,FUTURE */
        /* 361 357 001(ce) 110 022 : NOAPX,SSE,GFNI,FUTURE */
        {I_GF2P8AFFINEQB, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+65776, 583},
};

static const struct itemplate instrux_VGF2P8AFFINEQB[10] = {
    /*   0 : VGF2P8AFFINEQB xmmreg,xmmreg*,xmmrm128,imm8 [rvmi:     vex.nds.128.66.0f3a.w1 ce /r ib   ] AVX,GFNI,FUTURE */
        /* 261(003 201) 001(ce) 120 023 : NOAPX,VEX,AVX,GFNI,FUTURE */
        {I_VGF2P8AFFINEQB, 4, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+54669, 584},
    /*   1 : VGF2P8AFFINEQB xmmreg,xmmrm128,imm8 [r+vmi:     vex.nds.128.66.0f3a.w1 ce /r ib   ] ND,AVX,GFNI,FUTURE */
        /* 260(003 201) 001(ce) 110 022 : NOAPX,VEX,AVX,GFNI,FUTURE */
        {I_VGF2P8AFFINEQB, 3, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54677, 584},
    /*   2 : VGF2P8AFFINEQB ymmreg,ymmreg*,ymmrm256,imm8 [rvmi:     vex.nds.256.66.0f3a.w1 ce /r ib   ] AVX,GFNI,FUTURE */
        /* 261(003 205) 001(ce) 120 023 : NOAPX,VEX,AVX,GFNI,FUTURE */
        {I_VGF2P8AFFINEQB, 4, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,IMM_NORMAL|BITS8,0}, NO_DECORATOR, nasm_bytecodes+54685, 584},
    /*   3 : VGF2P8AFFINEQB ymmreg,ymmrm256,imm8 [r+vmi:     vex.nds.256.66.0f3a.w1 ce /r ib   ] ND,AVX,GFNI,FUTURE */
        /* 260(003 205) 001(ce) 110 022 : NOAPX,VEX,AVX,GFNI,FUTURE */
        {I_VGF2P8AFFINEQB, 3, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+54693, 584},
    /*   4 : VGF2P8AFFINEQB xmmreg|mask|z,xmmreg*,xmmrm128|b64,imm8 [rvmi:fv:  evex.nds.128.66.0f3a.w1 ce /r ib  ] AVX512VL,GFNI,FUTURE */
        /* 241(f3 fd 08) 301 001(ce) 120 023 : EVEX,PROT,AVX512VL,GFNI,FUTURE */
        {I_VGF2P8AFFINEQB, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22223, 585},
    /*   5 : VGF2P8AFFINEQB xmmreg|mask|z,xmmrm128|b64,imm8 [r+vmi:fv:  evex.nds.128.66.0f3a.w1 ce /r ib  ] ND,AVX512VL,GFNI,FUTURE */
        /* 240(f3 fd 08) 301 001(ce) 110 022 : EVEX,PROT,AVX512VL,GFNI,FUTURE */
        {I_VGF2P8AFFINEQB, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+22233, 585},
    /*   6 : VGF2P8AFFINEQB ymmreg|mask|z,ymmreg*,ymmrm256|b64,imm8 [rvmi:fv:  evex.nds.256.66.0f3a.w1 ce /r ib  ] AVX512VL,GFNI,FUTURE */
        /* 241(f3 fd 28) 301 001(ce) 120 023 : EVEX,PROT,AVX512VL,GFNI,FUTURE */
        {I_VGF2P8AFFINEQB, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22243, 585},
    /*   7 : VGF2P8AFFINEQB ymmreg|mask|z,ymmrm256|b64,imm8 [r+vmi:fv:  evex.nds.256.66.0f3a.w1 ce /r ib  ] ND,AVX512VL,GFNI,FUTURE */
        /* 240(f3 fd 28) 301 001(ce) 110 022 : EVEX,PROT,AVX512VL,GFNI,FUTURE */
        {I_VGF2P8AFFINEQB, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+22253, 585},
    /*   8 : VGF2P8AFFINEQB zmmreg|mask|z,zmmreg*,zmmrm512|b64,imm8 [rvmi:fv:  evex.nds.512.66.0f3a.w1 ce /r ib  ] AVX512,GFNI,FUTURE */
        /* 241(f3 fd 48) 301 001(ce) 120 023 : EVEX,PROT,AVX512,GFNI,FUTURE */
        {I_VGF2P8AFFINEQB, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22263, 586},
    /*   9 : VGF2P8AFFINEQB zmmreg|mask|z,zmmrm512|b64,imm8 [r+vmi:fv:  evex.nds.512.66.0f3a.w1 ce /r ib  ] ND,AVX512,GFNI,FUTURE */
        /* 240(f3 fd 48) 301 001(ce) 110 022 : EVEX,PROT,AVX512,GFNI,FUTURE */
        {I_VGF2P8AFFINEQB, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+22273, 586},
};

static const struct itemplate instrux_GF2P8MULB[1] = {
    /*   0 : GF2P8MULB xmmreg,xmmrm128 [rm:       66 0f38 cf /r                     ] SSE,GFNI,FUTURE */
        /* 361 356 001(cf) 110 : NOAPX,SSE,GFNI,FUTURE */
        {I_GF2P8MULB, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69932, 583},
};

static const struct itemplate instrux_VGF2P8MULB[10] = {
    /*   0 : VGF2P8MULB xmmreg,xmmreg*,xmmrm128 [rvm:      vex.nds.128.66.0f38.w0 cf /r      ] AVX,GFNI,FUTURE */
        /* 261(002 001) 001(cf) 120 : NOAPX,VEX,AVX,GFNI,FUTURE */
        {I_VGF2P8MULB, 3, {XMMREG|RN_L16,XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65783, 584},
    /*   1 : VGF2P8MULB xmmreg,xmmrm128 [r+vm:      vex.nds.128.66.0f38.w0 cf /r      ] ND,AVX,GFNI,FUTURE */
        /* 260(002 001) 001(cf) 110 : NOAPX,VEX,AVX,GFNI,FUTURE */
        {I_VGF2P8MULB, 2, {XMMREG|RN_L16,RM_XMM|BITS128|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65790, 584},
    /*   2 : VGF2P8MULB ymmreg,ymmreg*,ymmrm256 [rvm:      vex.nds.256.66.0f38.w0 cf /r      ] AVX,GFNI,FUTURE */
        /* 261(002 005) 001(cf) 120 : NOAPX,VEX,AVX,GFNI,FUTURE */
        {I_VGF2P8MULB, 3, {YMMREG|RN_L16,YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65797, 584},
    /*   3 : VGF2P8MULB ymmreg,ymmrm256 [r+vm:      vex.nds.256.66.0f38.w0 cf /r      ] ND,AVX,GFNI,FUTURE */
        /* 260(002 005) 001(cf) 110 : NOAPX,VEX,AVX,GFNI,FUTURE */
        {I_VGF2P8MULB, 2, {YMMREG|RN_L16,RM_YMM|BITS256|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65804, 584},
    /*   4 : VGF2P8MULB xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f38.w0 cf /r     ] AVX512VL,GFNI,FUTURE */
        /* 241(f2 7d 08) 303 001(cf) 120 : EVEX,PROT,AVX512VL,GFNI,FUTURE */
        {I_VGF2P8MULB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+44730, 585},
    /*   5 : VGF2P8MULB xmmreg|mask|z,xmmrm128 [r+vm:fvm:  evex.nds.128.66.0f38.w0 cf /r     ] ND,AVX512VL,GFNI,FUTURE */
        /* 240(f2 7d 08) 303 001(cf) 110 : EVEX,PROT,AVX512VL,GFNI,FUTURE */
        {I_VGF2P8MULB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+44739, 585},
    /*   6 : VGF2P8MULB ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f38.w0 cf /r     ] AVX512VL,GFNI,FUTURE */
        /* 241(f2 7d 28) 303 001(cf) 120 : EVEX,PROT,AVX512VL,GFNI,FUTURE */
        {I_VGF2P8MULB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+44748, 585},
    /*   7 : VGF2P8MULB ymmreg|mask|z,ymmrm256 [r+vm:fvm:  evex.nds.256.66.0f38.w0 cf /r     ] ND,AVX512VL,GFNI,FUTURE */
        /* 240(f2 7d 28) 303 001(cf) 110 : EVEX,PROT,AVX512VL,GFNI,FUTURE */
        {I_VGF2P8MULB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+44757, 585},
    /*   8 : VGF2P8MULB zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f38.w0 cf /r     ] AVX512,GFNI,FUTURE */
        /* 241(f2 7d 48) 303 001(cf) 120 : EVEX,PROT,AVX512,GFNI,FUTURE */
        {I_VGF2P8MULB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+44766, 586},
    /*   9 : VGF2P8MULB zmmreg|mask|z,zmmrm512 [r+vm:fvm:  evex.nds.512.66.0f38.w0 cf /r     ] ND,AVX512,GFNI,FUTURE */
        /* 240(f2 7d 48) 303 001(cf) 110 : EVEX,PROT,AVX512,GFNI,FUTURE */
        {I_VGF2P8MULB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+44775, 586},
};

static const struct itemplate instrux_VPCOMPRESSB[6] = {
    /*   0 : VPCOMPRESSB mem128|mask,xmmreg [mr:t1s8:  evex.128.66.0f38.w0 63 /r         ] AVX512VL,AVX512VBMI2,FUTURE */
        /* 250(f2 7d 08) 304 001(63) 101 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPCOMPRESSB, 2, {MEMORY|BITS128,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+44784, 587},
    /*   1 : VPCOMPRESSB mem256|mask,ymmreg [mr:t1s8:  evex.256.66.0f38.w0 63 /r         ] AVX512VL,AVX512VBMI2,FUTURE */
        /* 250(f2 7d 28) 304 001(63) 101 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPCOMPRESSB, 2, {MEMORY|BITS256,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+44793, 587},
    /*   2 : VPCOMPRESSB mem512|mask,zmmreg [mr:t1s8:  evex.512.66.0f38.w0 63 /r         ] AVX512VBMI2,FUTURE */
        /* 250(f2 7d 48) 304 001(63) 101 : EVEX,PROT,AVX512VBMI2,FUTURE */
        {I_VPCOMPRESSB, 2, {MEMORY|BITS512,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+44802, 588},
    /*   3 : VPCOMPRESSB xmmreg|mask|z,xmmreg [mr:       evex.128.66.0f38.w0 63 /r         ] AVX512VL,AVX512VBMI2,FUTURE */
        /* 250(f2 7d 08) 300 001(63) 101 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPCOMPRESSB, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+44811, 587},
    /*   4 : VPCOMPRESSB ymmreg|mask|z,ymmreg [mr:       evex.256.66.0f38.w0 63 /r         ] AVX512VL,AVX512VBMI2,FUTURE */
        /* 250(f2 7d 28) 300 001(63) 101 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPCOMPRESSB, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+44820, 587},
    /*   5 : VPCOMPRESSB zmmreg|mask|z,zmmreg [mr:       evex.512.66.0f38.w0 63 /r         ] AVX512VBMI2,FUTURE */
        /* 250(f2 7d 48) 300 001(63) 101 : EVEX,PROT,AVX512VBMI2,FUTURE */
        {I_VPCOMPRESSB, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+44829, 588},
};

static const struct itemplate instrux_VPCOMPRESSW[6] = {
    /*   0 : VPCOMPRESSW mem128|mask,xmmreg [mr:t1s16: evex.128.66.0f38.w1 63 /r         ] AVX512VL,AVX512VBMI2,FUTURE */
        /* 250(f2 fd 08) 305 001(63) 101 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPCOMPRESSW, 2, {MEMORY|BITS128,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+44838, 587},
    /*   1 : VPCOMPRESSW mem256|mask,ymmreg [mr:t1s16: evex.256.66.0f38.w1 63 /r         ] AVX512VL,AVX512VBMI2,FUTURE */
        /* 250(f2 fd 28) 305 001(63) 101 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPCOMPRESSW, 2, {MEMORY|BITS256,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+44847, 587},
    /*   2 : VPCOMPRESSW mem512|mask,zmmreg [mr:t1s16: evex.512.66.0f38.w1 63 /r         ] AVX512VBMI2,FUTURE */
        /* 250(f2 fd 48) 305 001(63) 101 : EVEX,PROT,AVX512VBMI2,FUTURE */
        {I_VPCOMPRESSW, 2, {MEMORY|BITS512,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+44856, 588},
    /*   3 : VPCOMPRESSW xmmreg|mask|z,xmmreg [mr:       evex.128.66.0f38.w1 63 /r         ] AVX512VL,AVX512VBMI2,FUTURE */
        /* 250(f2 fd 08) 300 001(63) 101 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPCOMPRESSW, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+44865, 587},
    /*   4 : VPCOMPRESSW ymmreg|mask|z,ymmreg [mr:       evex.256.66.0f38.w1 63 /r         ] AVX512VL,AVX512VBMI2,FUTURE */
        /* 250(f2 fd 28) 300 001(63) 101 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPCOMPRESSW, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+44874, 587},
    /*   5 : VPCOMPRESSW zmmreg|mask|z,zmmreg [mr:       evex.512.66.0f38.w1 63 /r         ] AVX512VBMI2,FUTURE */
        /* 250(f2 fd 48) 300 001(63) 101 : EVEX,PROT,AVX512VBMI2,FUTURE */
        {I_VPCOMPRESSW, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+44883, 588},
};

static const struct itemplate instrux_VPEXPANDB[3] = {
    /*   0 : VPEXPANDB xmmreg|mask|z,xmmrm128 [rm:t1s8:  evex.128.66.0f38.w0 62 /r         ] AVX512VL,AVX512VBMI2,FUTURE */
        /* 250(f2 7d 08) 304 001(62) 110 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPEXPANDB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+44892, 587},
    /*   1 : VPEXPANDB ymmreg|mask|z,ymmrm256 [rm:t1s8:  evex.256.66.0f38.w0 62 /r         ] AVX512VL,AVX512VBMI2,FUTURE */
        /* 250(f2 7d 28) 304 001(62) 110 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPEXPANDB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+44901, 587},
    /*   2 : VPEXPANDB zmmreg|mask|z,zmmrm512 [rm:t1s8:  evex.512.66.0f38.w0 62 /r         ] AVX512VBMI2,FUTURE */
        /* 250(f2 7d 48) 304 001(62) 110 : EVEX,PROT,AVX512VBMI2,FUTURE */
        {I_VPEXPANDB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+44910, 588},
};

static const struct itemplate instrux_VPEXPANDW[3] = {
    /*   0 : VPEXPANDW xmmreg|mask|z,xmmrm128 [rm:t1s16: evex.128.66.0f38.w1 62 /r         ] AVX512VL,AVX512VBMI2,FUTURE */
        /* 250(f2 fd 08) 305 001(62) 110 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPEXPANDW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+44919, 587},
    /*   1 : VPEXPANDW ymmreg|mask|z,ymmrm256 [rm:t1s16: evex.256.66.0f38.w1 62 /r         ] AVX512VL,AVX512VBMI2,FUTURE */
        /* 250(f2 fd 28) 305 001(62) 110 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPEXPANDW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+44928, 587},
    /*   2 : VPEXPANDW zmmreg|mask|z,zmmrm512 [rm:t1s16: evex.512.66.0f38.w1 62 /r         ] AVX512VBMI2,FUTURE */
        /* 250(f2 fd 48) 305 001(62) 110 : EVEX,PROT,AVX512VBMI2,FUTURE */
        {I_VPEXPANDW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+44937, 588},
};

static const struct itemplate instrux_VPSHLDW[6] = {
    /*   0 : VPSHLDW xmmreg|mask|z,xmmreg*,xmmrm128,imm8 [rvmi:fvm: evex.nds.128.66.0f3a.w1 70 /r ib  ] AVX512VL,AVX512VBMI2,FUTURE */
        /* 241(f3 fd 08) 303 001(70) 120 023 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHLDW, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22283, 587},
    /*   1 : VPSHLDW xmmreg|mask|z,xmmrm128,imm8 [r+vmi:fvm: evex.nds.128.66.0f3a.w1 70 /r ib  ] ND,AVX512VL,AVX512VBMI2,FUTURE */
        /* 240(f3 fd 08) 303 001(70) 110 022 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHLDW, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22293, 587},
    /*   2 : VPSHLDW ymmreg|mask|z,ymmreg*,ymmrm256,imm8 [rvmi:fvm: evex.nds.256.66.0f3a.w1 70 /r ib  ] AVX512VL,AVX512VBMI2,FUTURE */
        /* 241(f3 fd 28) 303 001(70) 120 023 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHLDW, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22303, 587},
    /*   3 : VPSHLDW ymmreg|mask|z,ymmrm256,imm8 [r+vmi:fvm: evex.nds.256.66.0f3a.w1 70 /r ib  ] ND,AVX512VL,AVX512VBMI2,FUTURE */
        /* 240(f3 fd 28) 303 001(70) 110 022 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHLDW, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22313, 587},
    /*   4 : VPSHLDW zmmreg|mask|z,zmmreg*,zmmrm512,imm8 [rvmi:fvm: evex.nds.512.66.0f3a.w1 70 /r ib  ] AVX512VBMI2,FUTURE */
        /* 241(f3 fd 48) 303 001(70) 120 023 : EVEX,PROT,AVX512VBMI2,FUTURE */
        {I_VPSHLDW, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22323, 588},
    /*   5 : VPSHLDW zmmreg|mask|z,zmmrm512,imm8 [r+vmi:fvm: evex.nds.512.66.0f3a.w1 70 /r ib  ] ND,AVX512VBMI2,FUTURE */
        /* 240(f3 fd 48) 303 001(70) 110 022 : EVEX,PROT,AVX512VBMI2,FUTURE */
        {I_VPSHLDW, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22333, 588},
};

static const struct itemplate instrux_VPSHLDD[6] = {
    /*   0 : VPSHLDD xmmreg|mask|z,xmmreg*,xmmrm128|b32,imm8 [rvmi:fv:  evex.nds.128.66.0f3a.w0 71 /r ib  ] AVX512VL,AVX512VBMI2,FUTURE */
        /* 241(f3 7d 08) 301 001(71) 120 023 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHLDD, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22343, 587},
    /*   1 : VPSHLDD xmmreg|mask|z,xmmrm128|b32,imm8 [r+vmi:fv:  evex.nds.128.66.0f3a.w0 71 /r ib  ] ND,AVX512VL,AVX512VBMI2,FUTURE */
        /* 240(f3 7d 08) 301 001(71) 110 022 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHLDD, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+22353, 587},
    /*   2 : VPSHLDD ymmreg|mask|z,ymmreg*,ymmrm256|b32,imm8 [rvmi:fv:  evex.nds.256.66.0f3a.w0 71 /r ib  ] AVX512VL,AVX512VBMI2,FUTURE */
        /* 241(f3 7d 28) 301 001(71) 120 023 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHLDD, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22363, 587},
    /*   3 : VPSHLDD ymmreg|mask|z,ymmrm256|b32,imm8 [r+vmi:fv:  evex.nds.256.66.0f3a.w0 71 /r ib  ] ND,AVX512VL,AVX512VBMI2,FUTURE */
        /* 240(f3 7d 28) 301 001(71) 110 022 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHLDD, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+22373, 587},
    /*   4 : VPSHLDD zmmreg|mask|z,zmmreg*,zmmrm512|b32,imm8 [rvmi:fv:  evex.nds.512.66.0f3a.w0 71 /r ib  ] AVX512VBMI2,FUTURE */
        /* 241(f3 7d 48) 301 001(71) 120 023 : EVEX,PROT,AVX512VBMI2,FUTURE */
        {I_VPSHLDD, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22383, 588},
    /*   5 : VPSHLDD zmmreg|mask|z,zmmrm512|b32,imm8 [r+vmi:fv:  evex.nds.512.66.0f3a.w0 71 /r ib  ] ND,AVX512VBMI2,FUTURE */
        /* 240(f3 7d 48) 301 001(71) 110 022 : EVEX,PROT,AVX512VBMI2,FUTURE */
        {I_VPSHLDD, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+22393, 588},
};

static const struct itemplate instrux_VPSHLDQ[6] = {
    /*   0 : VPSHLDQ xmmreg|mask|z,xmmreg*,xmmrm128|b64,imm8 [rvmi:fv:  evex.nds.128.66.0f3a.w1 71 /r ib  ] AVX512VL,AVX512VBMI2,FUTURE */
        /* 241(f3 fd 08) 301 001(71) 120 023 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHLDQ, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22403, 587},
    /*   1 : VPSHLDQ xmmreg|mask|z,xmmrm128|b64,imm8 [r+vmi:fv:  evex.nds.128.66.0f3a.w1 71 /r ib  ] ND,AVX512VL,AVX512VBMI2,FUTURE */
        /* 240(f3 fd 08) 301 001(71) 110 022 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHLDQ, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+22413, 587},
    /*   2 : VPSHLDQ ymmreg|mask|z,ymmreg*,ymmrm256|b64,imm8 [rvmi:fv:  evex.nds.256.66.0f3a.w1 71 /r ib  ] AVX512VL,AVX512VBMI2,FUTURE */
        /* 241(f3 fd 28) 301 001(71) 120 023 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHLDQ, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22423, 587},
    /*   3 : VPSHLDQ ymmreg|mask|z,ymmrm256|b64,imm8 [r+vmi:fv:  evex.nds.256.66.0f3a.w1 71 /r ib  ] ND,AVX512VL,AVX512VBMI2,FUTURE */
        /* 240(f3 fd 28) 301 001(71) 110 022 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHLDQ, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+22433, 587},
    /*   4 : VPSHLDQ zmmreg|mask|z,zmmreg*,zmmrm512|b64,imm8 [rvmi:fv:  evex.nds.512.66.0f3a.w1 71 /r ib  ] AVX512VBMI2,FUTURE */
        /* 241(f3 fd 48) 301 001(71) 120 023 : EVEX,PROT,AVX512VBMI2,FUTURE */
        {I_VPSHLDQ, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22443, 588},
    /*   5 : VPSHLDQ zmmreg|mask|z,zmmrm512|b64,imm8 [r+vmi:fv:  evex.nds.512.66.0f3a.w1 71 /r ib  ] ND,AVX512VBMI2,FUTURE */
        /* 240(f3 fd 48) 301 001(71) 110 022 : EVEX,PROT,AVX512VBMI2,FUTURE */
        {I_VPSHLDQ, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+22453, 588},
};

static const struct itemplate instrux_VPSHLDVW[6] = {
    /*   0 : VPSHLDVW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.dds.128.66.0f38.w1 70 /r     ] AVX512VL,AVX512VBMI2,FUTURE */
        /* 241(f2 fd 08) 303 001(70) 120 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHLDVW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+44946, 587},
    /*   1 : VPSHLDVW xmmreg|mask|z,xmmrm128 [r+vm:fvm: evex.dds.128.66.0f38.w1 70 /r     ] ND,AVX512VL,AVX512VBMI2,FUTURE */
        /* 240(f2 fd 08) 303 001(70) 110 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHLDVW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+44955, 587},
    /*   2 : VPSHLDVW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.dds.256.66.0f38.w1 70 /r     ] AVX512VL,AVX512VBMI2,FUTURE */
        /* 241(f2 fd 28) 303 001(70) 120 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHLDVW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+44964, 587},
    /*   3 : VPSHLDVW ymmreg|mask|z,ymmrm256 [r+vm:fvm: evex.dds.256.66.0f38.w1 70 /r     ] ND,AVX512VL,AVX512VBMI2,FUTURE */
        /* 240(f2 fd 28) 303 001(70) 110 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHLDVW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+44973, 587},
    /*   4 : VPSHLDVW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.dds.512.66.0f38.w1 70 /r     ] AVX512VBMI2,FUTURE */
        /* 241(f2 fd 48) 303 001(70) 120 : EVEX,PROT,AVX512VBMI2,FUTURE */
        {I_VPSHLDVW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+44982, 588},
    /*   5 : VPSHLDVW zmmreg|mask|z,zmmrm512 [r+vm:fvm: evex.dds.512.66.0f38.w1 70 /r     ] ND,AVX512VBMI2,FUTURE */
        /* 240(f2 fd 48) 303 001(70) 110 : EVEX,PROT,AVX512VBMI2,FUTURE */
        {I_VPSHLDVW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+44991, 588},
};

static const struct itemplate instrux_VPSHLDVD[6] = {
    /*   0 : VPSHLDVD xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:  evex.dds.128.66.0f38.w0 71 /r     ] AVX512VL,AVX512VBMI2,FUTURE */
        /* 241(f2 7d 08) 301 001(71) 120 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHLDVD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+45000, 587},
    /*   1 : VPSHLDVD xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:  evex.dds.128.66.0f38.w0 71 /r     ] ND,AVX512VL,AVX512VBMI2,FUTURE */
        /* 240(f2 7d 08) 301 001(71) 110 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHLDVD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+45009, 587},
    /*   2 : VPSHLDVD ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:  evex.dds.256.66.0f38.w0 71 /r     ] AVX512VL,AVX512VBMI2,FUTURE */
        /* 241(f2 7d 28) 301 001(71) 120 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHLDVD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+45018, 587},
    /*   3 : VPSHLDVD ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:  evex.dds.256.66.0f38.w0 71 /r     ] ND,AVX512VL,AVX512VBMI2,FUTURE */
        /* 240(f2 7d 28) 301 001(71) 110 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHLDVD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+45027, 587},
    /*   4 : VPSHLDVD zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv:  evex.dds.512.66.0f38.w0 71 /r     ] AVX512VBMI2,FUTURE */
        /* 241(f2 7d 48) 301 001(71) 120 : EVEX,PROT,AVX512VBMI2,FUTURE */
        {I_VPSHLDVD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+45036, 588},
    /*   5 : VPSHLDVD zmmreg|mask|z,zmmrm512|b32 [r+vm:fv:  evex.dds.512.66.0f38.w0 71 /r     ] ND,AVX512VBMI2,FUTURE */
        /* 240(f2 7d 48) 301 001(71) 110 : EVEX,PROT,AVX512VBMI2,FUTURE */
        {I_VPSHLDVD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+45045, 588},
};

static const struct itemplate instrux_VPSHLDVQ[6] = {
    /*   0 : VPSHLDVQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv:  evex.dds.128.66.0f38.w1 71 /r     ] AVX512VL,AVX512VBMI2,FUTURE */
        /* 241(f2 fd 08) 301 001(71) 120 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHLDVQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+45054, 587},
    /*   1 : VPSHLDVQ xmmreg|mask|z,xmmrm128|b64 [r+vm:fv:  evex.dds.128.66.0f38.w1 71 /r     ] ND,AVX512VL,AVX512VBMI2,FUTURE */
        /* 240(f2 fd 08) 301 001(71) 110 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHLDVQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+45063, 587},
    /*   2 : VPSHLDVQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv:  evex.dds.256.66.0f38.w1 71 /r     ] AVX512VL,AVX512VBMI2,FUTURE */
        /* 241(f2 fd 28) 301 001(71) 120 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHLDVQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+45072, 587},
    /*   3 : VPSHLDVQ ymmreg|mask|z,ymmrm256|b64 [r+vm:fv:  evex.dds.256.66.0f38.w1 71 /r     ] ND,AVX512VL,AVX512VBMI2,FUTURE */
        /* 240(f2 fd 28) 301 001(71) 110 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHLDVQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+45081, 587},
    /*   4 : VPSHLDVQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv:  evex.dds.512.66.0f38.w1 71 /r     ] AVX512VBMI2,FUTURE */
        /* 241(f2 fd 48) 301 001(71) 120 : EVEX,PROT,AVX512VBMI2,FUTURE */
        {I_VPSHLDVQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+45090, 588},
    /*   5 : VPSHLDVQ zmmreg|mask|z,zmmrm512|b64 [r+vm:fv:  evex.dds.512.66.0f38.w1 71 /r     ] ND,AVX512VBMI2,FUTURE */
        /* 240(f2 fd 48) 301 001(71) 110 : EVEX,PROT,AVX512VBMI2,FUTURE */
        {I_VPSHLDVQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+45099, 588},
};

static const struct itemplate instrux_VPSHRDW[6] = {
    /*   0 : VPSHRDW xmmreg|mask|z,xmmreg*,xmmrm128,imm8 [rvmi:fvm: evex.nds.128.66.0f3a.w1 72 /r ib  ] AVX512VL,AVX512VBMI2,FUTURE */
        /* 241(f3 fd 08) 303 001(72) 120 023 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHRDW, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22463, 587},
    /*   1 : VPSHRDW xmmreg|mask|z,xmmrm128,imm8 [r+vmi:fvm: evex.nds.128.66.0f3a.w1 72 /r ib  ] ND,AVX512VL,AVX512VBMI2,FUTURE */
        /* 240(f3 fd 08) 303 001(72) 110 022 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHRDW, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22473, 587},
    /*   2 : VPSHRDW ymmreg|mask|z,ymmreg*,ymmrm256,imm8 [rvmi:fvm: evex.nds.256.66.0f3a.w1 72 /r ib  ] AVX512VL,AVX512VBMI2,FUTURE */
        /* 241(f3 fd 28) 303 001(72) 120 023 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHRDW, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22483, 587},
    /*   3 : VPSHRDW ymmreg|mask|z,ymmrm256,imm8 [r+vmi:fvm: evex.nds.256.66.0f3a.w1 72 /r ib  ] ND,AVX512VL,AVX512VBMI2,FUTURE */
        /* 240(f3 fd 28) 303 001(72) 110 022 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHRDW, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22493, 587},
    /*   4 : VPSHRDW zmmreg|mask|z,zmmreg*,zmmrm512,imm8 [rvmi:fvm: evex.nds.512.66.0f3a.w1 72 /r ib  ] AVX512VBMI2,FUTURE */
        /* 241(f3 fd 48) 303 001(72) 120 023 : EVEX,PROT,AVX512VBMI2,FUTURE */
        {I_VPSHRDW, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22503, 588},
    /*   5 : VPSHRDW zmmreg|mask|z,zmmrm512,imm8 [r+vmi:fvm: evex.nds.512.66.0f3a.w1 72 /r ib  ] ND,AVX512VBMI2,FUTURE */
        /* 240(f3 fd 48) 303 001(72) 110 022 : EVEX,PROT,AVX512VBMI2,FUTURE */
        {I_VPSHRDW, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22513, 588},
};

static const struct itemplate instrux_VPSHRDD[6] = {
    /*   0 : VPSHRDD xmmreg|mask|z,xmmreg*,xmmrm128|b32,imm8 [rvmi:fv:  evex.nds.128.66.0f3a.w0 73 /r ib  ] AVX512VL,AVX512VBMI2,FUTURE */
        /* 241(f3 7d 08) 301 001(73) 120 023 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHRDD, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22523, 587},
    /*   1 : VPSHRDD xmmreg|mask|z,xmmrm128|b32,imm8 [r+vmi:fv:  evex.nds.128.66.0f3a.w0 73 /r ib  ] ND,AVX512VL,AVX512VBMI2,FUTURE */
        /* 240(f3 7d 08) 301 001(73) 110 022 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHRDD, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+22533, 587},
    /*   2 : VPSHRDD ymmreg|mask|z,ymmreg*,ymmrm256|b32,imm8 [rvmi:fv:  evex.nds.256.66.0f3a.w0 73 /r ib  ] AVX512VL,AVX512VBMI2,FUTURE */
        /* 241(f3 7d 28) 301 001(73) 120 023 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHRDD, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22543, 587},
    /*   3 : VPSHRDD ymmreg|mask|z,ymmrm256|b32,imm8 [r+vmi:fv:  evex.nds.256.66.0f3a.w0 73 /r ib  ] ND,AVX512VL,AVX512VBMI2,FUTURE */
        /* 240(f3 7d 28) 301 001(73) 110 022 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHRDD, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+22553, 587},
    /*   4 : VPSHRDD zmmreg|mask|z,zmmreg*,zmmrm512|b32,imm8 [rvmi:fv:  evex.nds.512.66.0f3a.w0 73 /r ib  ] AVX512VBMI2,FUTURE */
        /* 241(f3 7d 48) 301 001(73) 120 023 : EVEX,PROT,AVX512VBMI2,FUTURE */
        {I_VPSHRDD, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22563, 588},
    /*   5 : VPSHRDD zmmreg|mask|z,zmmrm512|b32,imm8 [r+vmi:fv:  evex.nds.512.66.0f3a.w0 73 /r ib  ] ND,AVX512VBMI2,FUTURE */
        /* 240(f3 7d 48) 301 001(73) 110 022 : EVEX,PROT,AVX512VBMI2,FUTURE */
        {I_VPSHRDD, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+22573, 588},
};

static const struct itemplate instrux_VPSHRDQ[6] = {
    /*   0 : VPSHRDQ xmmreg|mask|z,xmmreg*,xmmrm128|b64,imm8 [rvmi:fv:  evex.nds.128.66.0f3a.w1 73 /r ib  ] AVX512VL,AVX512VBMI2,FUTURE */
        /* 241(f3 fd 08) 301 001(73) 120 023 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHRDQ, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22583, 587},
    /*   1 : VPSHRDQ xmmreg|mask|z,xmmrm128|b64,imm8 [r+vmi:fv:  evex.nds.128.66.0f3a.w1 73 /r ib  ] ND,AVX512VL,AVX512VBMI2,FUTURE */
        /* 240(f3 fd 08) 301 001(73) 110 022 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHRDQ, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+22593, 587},
    /*   2 : VPSHRDQ ymmreg|mask|z,ymmreg*,ymmrm256|b64,imm8 [rvmi:fv:  evex.nds.256.66.0f3a.w1 73 /r ib  ] AVX512VL,AVX512VBMI2,FUTURE */
        /* 241(f3 fd 28) 301 001(73) 120 023 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHRDQ, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22603, 587},
    /*   3 : VPSHRDQ ymmreg|mask|z,ymmrm256|b64,imm8 [r+vmi:fv:  evex.nds.256.66.0f3a.w1 73 /r ib  ] ND,AVX512VL,AVX512VBMI2,FUTURE */
        /* 240(f3 fd 28) 301 001(73) 110 022 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHRDQ, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+22613, 587},
    /*   4 : VPSHRDQ zmmreg|mask|z,zmmreg*,zmmrm512|b64,imm8 [rvmi:fv:  evex.nds.512.66.0f3a.w1 73 /r ib  ] AVX512VBMI2,FUTURE */
        /* 241(f3 fd 48) 301 001(73) 120 023 : EVEX,PROT,AVX512VBMI2,FUTURE */
        {I_VPSHRDQ, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22623, 588},
    /*   5 : VPSHRDQ zmmreg|mask|z,zmmrm512|b64,imm8 [r+vmi:fv:  evex.nds.512.66.0f3a.w1 73 /r ib  ] ND,AVX512VBMI2,FUTURE */
        /* 240(f3 fd 48) 301 001(73) 110 022 : EVEX,PROT,AVX512VBMI2,FUTURE */
        {I_VPSHRDQ, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+22633, 588},
};

static const struct itemplate instrux_VPSHRDVW[6] = {
    /*   0 : VPSHRDVW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.dds.128.66.0f38.w1 72 /r     ] AVX512VL,AVX512VBMI2,FUTURE */
        /* 241(f2 fd 08) 303 001(72) 120 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHRDVW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+45108, 587},
    /*   1 : VPSHRDVW xmmreg|mask|z,xmmrm128 [r+vm:fvm: evex.dds.128.66.0f38.w1 72 /r     ] ND,AVX512VL,AVX512VBMI2,FUTURE */
        /* 240(f2 fd 08) 303 001(72) 110 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHRDVW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+45117, 587},
    /*   2 : VPSHRDVW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.dds.256.66.0f38.w1 72 /r     ] AVX512VL,AVX512VBMI2,FUTURE */
        /* 241(f2 fd 28) 303 001(72) 120 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHRDVW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+45126, 587},
    /*   3 : VPSHRDVW ymmreg|mask|z,ymmrm256 [r+vm:fvm: evex.dds.256.66.0f38.w1 72 /r     ] ND,AVX512VL,AVX512VBMI2,FUTURE */
        /* 240(f2 fd 28) 303 001(72) 110 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHRDVW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+45135, 587},
    /*   4 : VPSHRDVW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.dds.512.66.0f38.w1 72 /r     ] AVX512VBMI2,FUTURE */
        /* 241(f2 fd 48) 303 001(72) 120 : EVEX,PROT,AVX512VBMI2,FUTURE */
        {I_VPSHRDVW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+45144, 588},
    /*   5 : VPSHRDVW zmmreg|mask|z,zmmrm512 [r+vm:fvm: evex.dds.512.66.0f38.w1 72 /r     ] ND,AVX512VBMI2,FUTURE */
        /* 240(f2 fd 48) 303 001(72) 110 : EVEX,PROT,AVX512VBMI2,FUTURE */
        {I_VPSHRDVW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+45153, 588},
};

static const struct itemplate instrux_VPSHRDVD[6] = {
    /*   0 : VPSHRDVD xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:  evex.dds.128.66.0f38.w0 73 /r     ] AVX512VL,AVX512VBMI2,FUTURE */
        /* 241(f2 7d 08) 301 001(73) 120 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHRDVD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+45162, 587},
    /*   1 : VPSHRDVD xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:  evex.dds.128.66.0f38.w0 73 /r     ] ND,AVX512VL,AVX512VBMI2,FUTURE */
        /* 240(f2 7d 08) 301 001(73) 110 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHRDVD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+45171, 587},
    /*   2 : VPSHRDVD ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:  evex.dds.256.66.0f38.w0 73 /r     ] AVX512VL,AVX512VBMI2,FUTURE */
        /* 241(f2 7d 28) 301 001(73) 120 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHRDVD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+45180, 587},
    /*   3 : VPSHRDVD ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:  evex.dds.256.66.0f38.w0 73 /r     ] ND,AVX512VL,AVX512VBMI2,FUTURE */
        /* 240(f2 7d 28) 301 001(73) 110 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHRDVD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+45189, 587},
    /*   4 : VPSHRDVD zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv:  evex.dds.512.66.0f38.w0 73 /r     ] AVX512VBMI2,FUTURE */
        /* 241(f2 7d 48) 301 001(73) 120 : EVEX,PROT,AVX512VBMI2,FUTURE */
        {I_VPSHRDVD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+45198, 588},
    /*   5 : VPSHRDVD zmmreg|mask|z,zmmrm512|b32 [r+vm:fv:  evex.dds.512.66.0f38.w0 73 /r     ] ND,AVX512VBMI2,FUTURE */
        /* 240(f2 7d 48) 301 001(73) 110 : EVEX,PROT,AVX512VBMI2,FUTURE */
        {I_VPSHRDVD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+45207, 588},
};

static const struct itemplate instrux_VPSHRDVQ[6] = {
    /*   0 : VPSHRDVQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv:  evex.dds.128.66.0f38.w1 73 /r     ] AVX512VL,AVX512VBMI2,FUTURE */
        /* 241(f2 fd 08) 301 001(73) 120 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHRDVQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+45216, 587},
    /*   1 : VPSHRDVQ xmmreg|mask|z,xmmrm128|b64 [r+vm:fv:  evex.dds.128.66.0f38.w1 73 /r     ] ND,AVX512VL,AVX512VBMI2,FUTURE */
        /* 240(f2 fd 08) 301 001(73) 110 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHRDVQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+45225, 587},
    /*   2 : VPSHRDVQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv:  evex.dds.256.66.0f38.w1 73 /r     ] AVX512VL,AVX512VBMI2,FUTURE */
        /* 241(f2 fd 28) 301 001(73) 120 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHRDVQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+45234, 587},
    /*   3 : VPSHRDVQ ymmreg|mask|z,ymmrm256|b64 [r+vm:fv:  evex.dds.256.66.0f38.w1 73 /r     ] ND,AVX512VL,AVX512VBMI2,FUTURE */
        /* 240(f2 fd 28) 301 001(73) 110 : EVEX,PROT,AVX512VL,AVX512VBMI2,FUTURE */
        {I_VPSHRDVQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+45243, 587},
    /*   4 : VPSHRDVQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv:  evex.dds.512.66.0f38.w1 73 /r     ] AVX512VBMI2,FUTURE */
        /* 241(f2 fd 48) 301 001(73) 120 : EVEX,PROT,AVX512VBMI2,FUTURE */
        {I_VPSHRDVQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+45252, 588},
    /*   5 : VPSHRDVQ zmmreg|mask|z,zmmrm512|b64 [r+vm:fv:  evex.dds.512.66.0f38.w1 73 /r     ] ND,AVX512VBMI2,FUTURE */
        /* 240(f2 fd 48) 301 001(73) 110 : EVEX,PROT,AVX512VBMI2,FUTURE */
        {I_VPSHRDVQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+45261, 588},
};

static const struct itemplate instrux_VPOPCNTB[3] = {
    /*   0 : VPOPCNTB xmmreg|mask|z,xmmrm128 [rm:fvm:   evex.128.66.0f38.w0 54 /r         ] AVX512VL,AVX512BITALG,FUTURE */
        /* 250(f2 7d 08) 303 001(54) 110 : EVEX,PROT,AVX512VL,AVX512BITALG,FUTURE */
        {I_VPOPCNTB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+45486, 591},
    /*   1 : VPOPCNTB ymmreg|mask|z,ymmrm256 [rm:fvm:   evex.256.66.0f38.w0 54 /r         ] AVX512VL,AVX512BITALG,FUTURE */
        /* 250(f2 7d 28) 303 001(54) 110 : EVEX,PROT,AVX512VL,AVX512BITALG,FUTURE */
        {I_VPOPCNTB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+45495, 591},
    /*   2 : VPOPCNTB zmmreg|mask|z,zmmrm512 [rm:fvm:   evex.512.66.0f38.w0 54 /r         ] AVX512BITALG,FUTURE */
        /* 250(f2 7d 48) 303 001(54) 110 : EVEX,PROT,AVX512BITALG,FUTURE */
        {I_VPOPCNTB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+45504, 592},
};

static const struct itemplate instrux_VPOPCNTW[3] = {
    /*   0 : VPOPCNTW xmmreg|mask|z,xmmrm128 [rm:fvm:   evex.128.66.0f38.w1 54 /r         ] AVX512VL,AVX512BITALG,FUTURE */
        /* 250(f2 fd 08) 303 001(54) 110 : EVEX,PROT,AVX512VL,AVX512BITALG,FUTURE */
        {I_VPOPCNTW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+45513, 591},
    /*   1 : VPOPCNTW ymmreg|mask|z,ymmrm256 [rm:fvm:   evex.256.66.0f38.w1 54 /r         ] AVX512VL,AVX512BITALG,FUTURE */
        /* 250(f2 fd 28) 303 001(54) 110 : EVEX,PROT,AVX512VL,AVX512BITALG,FUTURE */
        {I_VPOPCNTW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+45522, 591},
    /*   2 : VPOPCNTW zmmreg|mask|z,zmmrm512 [rm:fvm:   evex.512.66.0f38.w1 54 /r         ] AVX512BITALG,FUTURE */
        /* 250(f2 fd 48) 303 001(54) 110 : EVEX,PROT,AVX512BITALG,FUTURE */
        {I_VPOPCNTW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+45531, 592},
};

static const struct itemplate instrux_VPOPCNTD[3] = {
    /*   0 : VPOPCNTD xmmreg|mask|z,xmmrm128 [rm:fv:    evex.128.66.0f38.w0 55 /r         ] AVX512VL,AVX512VPOPCNTDQ,FUTURE */
        /* 250(f2 7d 08) 301 001(55) 110 : EVEX,PROT,AVX512VL,AVX512VPOPCNTDQ,FUTURE */
        {I_VPOPCNTD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+45540, 593},
    /*   1 : VPOPCNTD ymmreg|mask|z,ymmrm256 [rm:fv:    evex.256.66.0f38.w0 55 /r         ] AVX512VL,AVX512VPOPCNTDQ,FUTURE */
        /* 250(f2 7d 28) 301 001(55) 110 : EVEX,PROT,AVX512VL,AVX512VPOPCNTDQ,FUTURE */
        {I_VPOPCNTD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+45549, 593},
    /*   2 : VPOPCNTD zmmreg|mask|z,zmmrm512 [rm:fv:    evex.512.66.0f38.w0 55 /r         ] AVX512VPOPCNTDQ,FUTURE */
        /* 250(f2 7d 48) 301 001(55) 110 : EVEX,PROT,AVX512VPOPCNTDQ,FUTURE */
        {I_VPOPCNTD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+45558, 594},
};

static const struct itemplate instrux_VPOPCNTQ[3] = {
    /*   0 : VPOPCNTQ xmmreg|mask|z,xmmrm128 [rm:fv:    evex.128.66.0f38.w1 55 /r         ] AVX512VL,AVX512VPOPCNTDQ,FUTURE */
        /* 250(f2 fd 08) 301 001(55) 110 : EVEX,PROT,AVX512VL,AVX512VPOPCNTDQ,FUTURE */
        {I_VPOPCNTQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+45567, 593},
    /*   1 : VPOPCNTQ ymmreg|mask|z,ymmrm256 [rm:fv:    evex.256.66.0f38.w1 55 /r         ] AVX512VL,AVX512VPOPCNTDQ,FUTURE */
        /* 250(f2 fd 28) 301 001(55) 110 : EVEX,PROT,AVX512VL,AVX512VPOPCNTDQ,FUTURE */
        {I_VPOPCNTQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+45576, 593},
    /*   2 : VPOPCNTQ zmmreg|mask|z,zmmrm512 [rm:fv:    evex.512.66.0f38.w1 55 /r         ] AVX512VPOPCNTDQ,FUTURE */
        /* 250(f2 fd 48) 301 001(55) 110 : EVEX,PROT,AVX512VPOPCNTDQ,FUTURE */
        {I_VPOPCNTQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+45585, 594},
};

static const struct itemplate instrux_VPSHUFBITQMB[3] = {
    /*   0 : VPSHUFBITQMB kreg|mask,xmmreg,xmmrm128 [rvm:fvm:  evex.nds.128.66.0f38.w0 8f /r     ] AVX512VL,AVX512BITALG,FUTURE */
        /* 241(f2 7d 08) 303 001(8f) 120 : EVEX,PROT,AVX512VL,AVX512BITALG,FUTURE */
        {I_VPSHUFBITQMB, 3, {OPMASKREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+45594, 591},
    /*   1 : VPSHUFBITQMB kreg|mask,ymmreg,ymmrm256 [rvm:fvm:  evex.nds.256.66.0f38.w0 8f /r     ] AVX512VL,AVX512BITALG,FUTURE */
        /* 241(f2 7d 28) 303 001(8f) 120 : EVEX,PROT,AVX512VL,AVX512BITALG,FUTURE */
        {I_VPSHUFBITQMB, 3, {OPMASKREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+45603, 591},
    /*   2 : VPSHUFBITQMB kreg|mask,zmmreg,zmmrm512 [rvm:fvm:  evex.nds.512.66.0f38.w0 8f /r     ] AVX512BITALG,FUTURE */
        /* 241(f2 7d 48) 303 001(8f) 120 : EVEX,PROT,AVX512BITALG,FUTURE */
        {I_VPSHUFBITQMB, 3, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+45612, 592},
};

static const struct itemplate instrux_V4FMADDPS[1] = {
    /*   0 : V4FMADDPS zmmreg|mask|z,zmmreg|rs4,mem [rvm:m128: evex.dds.512.f2.0f38.w0 9a /r     ] AR0-2,SO,AVX5124FMAPS,FUTURE */
        /* 241(f2 7f 48) 317 001(9a) 120 : AR0,AR1,AR2,SO,EVEX,PROT,AVX5124FMAPS,FUTURE */
        {I_V4FMADDPS, 3, {ZMMREG,ZMMREG|RS4,MEMORY,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+45621, 595},
};

static const struct itemplate instrux_V4FNMADDPS[1] = {
    /*   0 : V4FNMADDPS zmmreg|mask|z,zmmreg|rs4,mem [rvm:m128: evex.dds.512.f2.0f38.w0 aa /r     ] AR0-2,SO,AVX5124FMAPS,FUTURE */
        /* 241(f2 7f 48) 317 001(aa) 120 : AR0,AR1,AR2,SO,EVEX,PROT,AVX5124FMAPS,FUTURE */
        {I_V4FNMADDPS, 3, {ZMMREG,ZMMREG|RS4,MEMORY,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+45630, 595},
};

static const struct itemplate instrux_V4FMADDSS[1] = {
    /*   0 : V4FMADDSS zmmreg|mask|z,zmmreg|rs4,mem [rvm:m128: evex.dds.lig.f2.0f38.w0 9b /r     ] AR0-2,SO,AVX5124FMAPS,FUTURE */
        /* 241(f2 7f 08) 317 001(9b) 120 : AR0,AR1,AR2,SO,LIG,EVEX,PROT,AVX5124FMAPS,FUTURE */
        {I_V4FMADDSS, 3, {ZMMREG,ZMMREG|RS4,MEMORY,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+45639, 596},
};

static const struct itemplate instrux_V4FNMADDSS[1] = {
    /*   0 : V4FNMADDSS zmmreg|mask|z,zmmreg|rs4,mem [rvm:m128: evex.dds.lig.f2.0f38.w0 ab /r     ] AR0-2,SO,AVX5124FMAPS,FUTURE */
        /* 241(f2 7f 08) 317 001(ab) 120 : AR0,AR1,AR2,SO,LIG,EVEX,PROT,AVX5124FMAPS,FUTURE */
        {I_V4FNMADDSS, 3, {ZMMREG,ZMMREG|RS4,MEMORY,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+45648, 596},
};

static const struct itemplate instrux_V4DPWSSDS[1] = {
    /*   0 : V4DPWSSDS zmmreg|mask|z,zmmreg|rs4,mem [rvm:m128: evex.dds.512.f2.0f38.w0 53 /r     ] AR0-2,SO,AVX5124VNNIW,FUTURE */
        /* 241(f2 7f 48) 317 001(53) 120 : AR0,AR1,AR2,SO,EVEX,PROT,AVX5124VNNIW,FUTURE */
        {I_V4DPWSSDS, 3, {ZMMREG,ZMMREG|RS4,MEMORY,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+45657, 597},
};

static const struct itemplate instrux_V4DPWSSD[1] = {
    /*   0 : V4DPWSSD zmmreg|mask|z,zmmreg|rs4,mem [rvm:m128: evex.dds.512.f2.0f38.w0 52 /r     ] AR0-2,SO,AVX5124VNNIW,FUTURE */
        /* 241(f2 7f 48) 317 001(52) 120 : AR0,AR1,AR2,SO,EVEX,PROT,AVX5124VNNIW,FUTURE */
        {I_V4DPWSSD, 3, {ZMMREG,ZMMREG|RS4,MEMORY,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+45666, 597},
};

static const struct itemplate instrux_ENCLS[1] = {
    /*   0 : ENCLS void [          np 0f 01 cf                       ] SGX,FUTURE */
        /* 360 355 002(01 cf) : SGX,FUTURE */
        {I_ENCLS, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+69938, 598},
};

static const struct itemplate instrux_ENCLU[1] = {
    /*   0 : ENCLU void [          np 0f 01 d7                       ] SGX,FUTURE */
        /* 360 355 002(01 d7) : SGX,FUTURE */
        {I_ENCLU, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+69944, 598},
};

static const struct itemplate instrux_ENCLV[1] = {
    /*   0 : ENCLV void [          np 0f 01 c0                       ] SGX,FUTURE */
        /* 360 355 002(01 c0) : SGX,FUTURE */
        {I_ENCLV, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+69950, 598},
};

static const struct itemplate instrux_CLRSSBSY[1] = {
    /*   0 : CLRSSBSY mem64 [m:        f3 0f ae /6                       ] FL,CET,FUTURE */
        /* 333 355 001(ae) 206 : FL,CET,FUTURE */
        {I_CLRSSBSY, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+56943, 599},
};

static const struct itemplate instrux_ENDBR32[1] = {
    /*   0 : ENDBR32 void [          f3 0f 1e fb                       ] CET,FUTURE */
        /* 333 355 002(1e fb) : CET,FUTURE */
        {I_ENDBR32, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+69956, 600},
};

static const struct itemplate instrux_ENDBR64[1] = {
    /*   0 : ENDBR64 void [          f3 0f 1e fa                       ] CET,FUTURE */
        /* 333 355 002(1e fa) : CET,FUTURE */
        {I_ENDBR64, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+69962, 600},
};

static const struct itemplate instrux_INCSSPD[1] = {
    /*   0 : INCSSPD reg32 [m:        o32 f3 0f ae /5                   ] CET,FUTURE */
        /* 321 333 355 001(ae) 205 : CET,FUTURE */
        {I_INCSSPD, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+65811, 600},
};

static const struct itemplate instrux_INCSSPQ[1] = {
    /*   0 : INCSSPQ reg64 [m:        o64 f3 0f ae /5                   ] LONG,PROT,CET,X86_64 */
        /* 324 333 355 001(ae) 205 : LONG,PROT,CET,X86_64 */
        {I_INCSSPQ, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+65818, 601},
};

static const struct itemplate instrux_RDSSPD[1] = {
    /*   0 : RDSSPD reg32 [m:        o32 f3 0f 1e /1                   ] CET,FUTURE */
        /* 321 333 355 001(1e) 201 : CET,FUTURE */
        {I_RDSSPD, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+65825, 600},
};

static const struct itemplate instrux_RDSSPQ[1] = {
    /*   0 : RDSSPQ reg64 [m:        o64 f3 0f 1e /1                   ] LONG,PROT,CET,X86_64 */
        /* 324 333 355 001(1e) 201 : LONG,PROT,CET,X86_64 */
        {I_RDSSPQ, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+65832, 601},
};

static const struct itemplate instrux_RSTORSSP[1] = {
    /*   0 : RSTORSSP mem64 [m:        f3 0f 01 /5                       ] CET,FUTURE */
        /* 333 355 001(01) 205 : CET,FUTURE */
        {I_RSTORSSP, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+69968, 600},
};

static const struct itemplate instrux_SAVEPREVSSP[1] = {
    /*   0 : SAVEPREVSSP void [          f3 0f 01 ea                       ] CET,FUTURE */
        /* 333 355 002(01 ea) : CET,FUTURE */
        {I_SAVEPREVSSP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+69974, 600},
};

static const struct itemplate instrux_SETSSBSY[1] = {
    /*   0 : SETSSBSY void [          f3 0f 01 e8                       ] CET,FUTURE */
        /* 333 355 002(01 e8) : CET,FUTURE */
        {I_SETSSBSY, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+69980, 600},
};

static const struct itemplate instrux_WRUSSD[2] = {
    /*   0 : WRUSSD mem32,reg32 [mr:       o32 66 0f38 f5 /r                 ] CET,FUTURE */
        /* 321 361 356 001(f5) 101 : NOAPX,CET,FUTURE */
        {I_WRUSSD, 2, {MEMORY|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65839, 602},
    /*   1 : WRUSSD mem32,reg32 [mr:       evex.nf0.nd0.l0.66.m4.w0 65 /r    ] LONG,PROT,CET,APX,X86_64 */
        /* 250(f4 7d 08) 300 001(65) 101 : LONG,EVEX,PROT,CET,APX,X86_64 */
        {I_WRUSSD, 2, {MEMORY|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+45675, 603},
};

static const struct itemplate instrux_WRUSSQ[2] = {
    /*   0 : WRUSSQ mem64,reg64 [mr:       o64 66 0f38 f5 /r                 ] LONG,PROT,CET,X86_64 */
        /* 324 361 356 001(f5) 101 : NOAPX,LONG,PROT,CET,X86_64 */
        {I_WRUSSQ, 2, {MEMORY|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65846, 604},
    /*   1 : WRUSSQ mem64,reg64 [mr:       evex.nf0.nd0.l0.66.m4.w1 65 /r    ] LONG,PROT,CET,APX,X86_64 */
        /* 250(f4 fd 08) 300 001(65) 101 : LONG,EVEX,PROT,CET,APX,X86_64 */
        {I_WRUSSQ, 2, {MEMORY|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+45684, 603},
};

static const struct itemplate instrux_WRSSD[2] = {
    /*   0 : WRSSD mem32,reg32 [mr:       o32 0f38 f6 /r                    ] CET,FUTURE */
        /* 321 356 001(f6) 101 : NOAPX,CET,FUTURE */
        {I_WRSSD, 2, {MEMORY|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69986, 602},
    /*   1 : WRSSD mem32,reg32 [mr:       evex.nf0.nd0.l0.m4.w0 66 /r       ] LONG,PROT,CET,APX,X86_64 */
        /* 250(f4 7c 08) 300 001(66) 101 : LONG,EVEX,PROT,CET,APX,X86_64 */
        {I_WRSSD, 2, {MEMORY|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+45693, 603},
};

static const struct itemplate instrux_WRSSQ[2] = {
    /*   0 : WRSSQ mem64,reg64 [mr:       o64 0f38 f6 /r                    ] LONG,PROT,CET,X86_64 */
        /* 324 356 001(f6) 101 : NOAPX,LONG,PROT,CET,X86_64 */
        {I_WRSSQ, 2, {MEMORY|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+69992, 604},
    /*   1 : WRSSQ mem64,reg64 [mr:       evex.nf0.nd0.l0.m4.w1 66 /r       ] LONG,PROT,CET,APX,X86_64 */
        /* 250(f4 fc 08) 300 001(66) 101 : LONG,EVEX,PROT,CET,APX,X86_64 */
        {I_WRSSQ, 2, {MEMORY|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+45702, 603},
};

static const struct itemplate instrux_ENQCMD[5] = {
    /*   0 : ENQCMD reg16,mem512 [rm:       a16 f2 0f38 f8 /r                 ] AR0-1,SZ,NOREX,NOAPX,NOLONG,FL,ENQCMD,FUTURE */
        /* 310 332 356 001(f8) 110 : AR0,AR1,SZ,NOREX,NOAPX,NOLONG,FL,ENQCMD,FUTURE */
        {I_ENQCMD, 2, {REG_GPR|BITS16|RN_L16,MEMORY|BITS512|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65853, 605},
    /*   1 : ENQCMD reg32,mem512 [rm:       a16 f2 0f38 f8 /r                 ] ND,AR0-1,SZ,NOREX,NOAPX,NOLONG,FL,ENQCMD,FUTURE */
        /* 310 332 356 001(f8) 110 : AR0,AR1,SZ,NOREX,NOAPX,NOLONG,FL,ENQCMD,FUTURE */
        {I_ENQCMD, 2, {REG_GPR|BITS32|RN_L16,MEMORY|BITS512|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65853, 605},
    /*   2 : ENQCMD reg32,mem512 [rm:       a32 f2 0f38 f8 /r                 ] AR0-1,SZ,FL,ENQCMD,FUTURE */
        /* 311 332 356 001(f8) 110 : AR0,AR1,SZ,NOAPX,FL,ENQCMD,FUTURE */
        {I_ENQCMD, 2, {REG_GPR|BITS32|RN_L16,MEMORY|BITS512|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65860, 606},
    /*   3 : ENQCMD reg64,mem512 [rm:       a64 f2 0f38 f8 /r                 ] AR0-1,SZ,LONG,FL,PROT,ENQCMD,X86_64 */
        /* 313 332 356 001(f8) 110 : AR0,AR1,SZ,NOAPX,LONG,FL,PROT,ENQCMD,X86_64 */
        {I_ENQCMD, 2, {REG_GPR|BITS64|RN_L16,MEMORY|BITS512|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65867, 607},
    /*   4 : ENQCMD reg64,mem512 [rm:       evex.nf0.nd0.l0.f2.m4.w1 f8 /r    ] AR0-1,SZ,LONG,FL,PRIV,PROT,ENQCMD,APX,X86_64 */
        /* 250(f4 ff 08) 300 001(f8) 110 : AR0,AR1,SZ,LONG,FL,EVEX,PRIV,PROT,ENQCMD,APX,X86_64 */
        {I_ENQCMD, 2, {REG_GPR|BITS64,MEMORY|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+45711, 608},
};

static const struct itemplate instrux_ENQCMDS[5] = {
    /*   0 : ENQCMDS reg16,mem512 [rm:       a16 f3 0f38 f8 /r                 ] AR0-1,SZ,NOREX,NOAPX,NOLONG,FL,PRIV,ENQCMD,FUTURE */
        /* 310 333 356 001(f8) 110 : AR0,AR1,SZ,NOREX,NOAPX,NOLONG,FL,PRIV,ENQCMD,FUTURE */
        {I_ENQCMDS, 2, {REG_GPR|BITS16|RN_L16,MEMORY|BITS512|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65874, 609},
    /*   1 : ENQCMDS reg32,mem512 [rm:       a16 f3 0f38 f8 /r                 ] ND,AR0-1,SZ,NOREX,NOAPX,NOLONG,FL,PRIV,ENQCMD,FUTURE */
        /* 310 333 356 001(f8) 110 : AR0,AR1,SZ,NOREX,NOAPX,NOLONG,FL,PRIV,ENQCMD,FUTURE */
        {I_ENQCMDS, 2, {REG_GPR|BITS32|RN_L16,MEMORY|BITS512|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65874, 609},
    /*   2 : ENQCMDS reg32,mem512 [rm:       a32 f3 0f38 f8 /r                 ] AR0-1,SZ,FL,PRIV,ENQCMD,FUTURE */
        /* 311 333 356 001(f8) 110 : AR0,AR1,SZ,NOAPX,FL,PRIV,ENQCMD,FUTURE */
        {I_ENQCMDS, 2, {REG_GPR|BITS32|RN_L16,MEMORY|BITS512|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65881, 610},
    /*   3 : ENQCMDS reg64,mem512 [rm:       a64 f3 0f38 f8 /r                 ] AR0-1,SZ,LONG,FL,PRIV,PROT,ENQCMD,X86_64 */
        /* 313 333 356 001(f8) 110 : AR0,AR1,SZ,NOAPX,LONG,FL,PRIV,PROT,ENQCMD,X86_64 */
        {I_ENQCMDS, 2, {REG_GPR|BITS64|RN_L16,MEMORY|BITS512|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65888, 611},
    /*   4 : ENQCMDS reg64,mem512 [rm:       evex.nf0.nd0.l0.f3.m4.w1 f8 /r    ] AR0-1,SZ,LONG,FL,PRIV,PROT,ENQCMD,APX,X86_64 */
        /* 250(f4 fe 08) 300 001(f8) 110 : AR0,AR1,SZ,LONG,FL,EVEX,PRIV,PROT,ENQCMD,APX,X86_64 */
        {I_ENQCMDS, 2, {REG_GPR|BITS64,MEMORY|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+45720, 608},
};

static const struct itemplate instrux_XRESLDTRK[1] = {
    /*   0 : XRESLDTRK void [          f2 0f 01 e9                       ] TSXLDTRK,FUTURE */
        /* 332 355 002(01 e9) : TSXLDTRK,FUTURE */
        {I_XRESLDTRK, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+69998, 613},
};

static const struct itemplate instrux_XSUSLDTRK[1] = {
    /*   0 : XSUSLDTRK void [          f2 0f 01 e8                       ] TSXLDTRK,FUTURE */
        /* 332 355 002(01 e8) : TSXLDTRK,FUTURE */
        {I_XSUSLDTRK, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70004, 613},
};

static const struct itemplate instrux_VCVTNE2PS2BF16[6] = {
    /*   0 : VCVTNE2PS2BF16 xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.128.f2.0f38.w0 72 /r         ] AVX512VL,AVX512BF16,FUTURE */
        /* 241(f2 7f 08) 301 001(72) 120 : EVEX,PROT,AVX512VL,AVX512BF16,FUTURE */
        {I_VCVTNE2PS2BF16, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+45729, 614},
    /*   1 : VCVTNE2PS2BF16 xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.128.f2.0f38.w0 72 /r         ] ND,AVX512VL,AVX512BF16,FUTURE */
        /* 240(f2 7f 08) 301 001(72) 110 : EVEX,PROT,AVX512VL,AVX512BF16,FUTURE */
        {I_VCVTNE2PS2BF16, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+45738, 614},
    /*   2 : VCVTNE2PS2BF16 ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.256.f2.0f38.w0 72 /r         ] AVX512VL,AVX512BF16,FUTURE */
        /* 241(f2 7f 28) 301 001(72) 120 : EVEX,PROT,AVX512VL,AVX512BF16,FUTURE */
        {I_VCVTNE2PS2BF16, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+45747, 614},
    /*   3 : VCVTNE2PS2BF16 ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.256.f2.0f38.w0 72 /r         ] ND,AVX512VL,AVX512BF16,FUTURE */
        /* 240(f2 7f 28) 301 001(72) 110 : EVEX,PROT,AVX512VL,AVX512BF16,FUTURE */
        {I_VCVTNE2PS2BF16, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+45756, 614},
    /*   4 : VCVTNE2PS2BF16 zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv:   evex.512.f2.0f38.w0 72 /r         ] AVX512BF16,FUTURE */
        /* 241(f2 7f 48) 301 001(72) 120 : EVEX,PROT,AVX512BF16,FUTURE */
        {I_VCVTNE2PS2BF16, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+45765, 615},
    /*   5 : VCVTNE2PS2BF16 zmmreg|mask|z,zmmrm512|b32 [r+vm:fv:   evex.512.f2.0f38.w0 72 /r         ] ND,AVX512BF16,FUTURE */
        /* 240(f2 7f 48) 301 001(72) 110 : EVEX,PROT,AVX512BF16,FUTURE */
        {I_VCVTNE2PS2BF16, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+45774, 615},
};

static const struct itemplate instrux_VDPBF16PS[6] = {
    /*   0 : VDPBF16PS xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.128.f3.0f38.w0 52 /r         ] AVX512VL,AVX512BF16,FUTURE */
        /* 241(f2 7e 08) 301 001(52) 120 : EVEX,PROT,AVX512VL,AVX512BF16,FUTURE */
        {I_VDPBF16PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+45810, 614},
    /*   1 : VDPBF16PS xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.128.f3.0f38.w0 52 /r         ] ND,AVX512VL,AVX512BF16,FUTURE */
        /* 240(f2 7e 08) 301 001(52) 110 : EVEX,PROT,AVX512VL,AVX512BF16,FUTURE */
        {I_VDPBF16PS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+45819, 614},
    /*   2 : VDPBF16PS ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.256.f3.0f38.w0 52 /r         ] AVX512VL,AVX512BF16,FUTURE */
        /* 241(f2 7e 28) 301 001(52) 120 : EVEX,PROT,AVX512VL,AVX512BF16,FUTURE */
        {I_VDPBF16PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+45828, 614},
    /*   3 : VDPBF16PS ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.256.f3.0f38.w0 52 /r         ] ND,AVX512VL,AVX512BF16,FUTURE */
        /* 240(f2 7e 28) 301 001(52) 110 : EVEX,PROT,AVX512VL,AVX512BF16,FUTURE */
        {I_VDPBF16PS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+45837, 614},
    /*   4 : VDPBF16PS zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv:   evex.512.f3.0f38.w0 52 /r         ] AVX512BF16,FUTURE */
        /* 241(f2 7e 48) 301 001(52) 120 : EVEX,PROT,AVX512BF16,FUTURE */
        {I_VDPBF16PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+45846, 615},
    /*   5 : VDPBF16PS zmmreg|mask|z,zmmrm512|b32 [r+vm:fv:   evex.512.f3.0f38.w0 52 /r         ] ND,AVX512BF16,FUTURE */
        /* 240(f2 7e 48) 301 001(52) 110 : EVEX,PROT,AVX512BF16,FUTURE */
        {I_VDPBF16PS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+45855, 615},
};

static const struct itemplate instrux_VP2INTERSECTD[3] = {
    /*   0 : VP2INTERSECTD kreg|rs2,xmmreg,xmmrm128|b32 [rvm:fv:   evex.nds.128.f2.0f38.w0 68 /r     ] AVX512VL,AVX512VP2INTERSECT,FUTURE */
        /* 241(f2 7f 08) 301 001(68) 120 : EVEX,PROT,AVX512VL,AVX512VP2INTERSECT,FUTURE */
        {I_VP2INTERSECTD, 3, {OPMASKREG|RS2,XMMREG,RM_XMM|BITS128,0,0}, {0,0,B32,0,0}, nasm_bytecodes+45864, 616},
    /*   1 : VP2INTERSECTD kreg|rs2,ymmreg,ymmrm256|b32 [rvm:fv:   evex.nds.256.f2.0f38.w0 68 /r     ] AVX512VL,AVX512VP2INTERSECT,FUTURE */
        /* 241(f2 7f 28) 301 001(68) 120 : EVEX,PROT,AVX512VL,AVX512VP2INTERSECT,FUTURE */
        {I_VP2INTERSECTD, 3, {OPMASKREG|RS2,YMMREG,RM_YMM|BITS256,0,0}, {0,0,B32,0,0}, nasm_bytecodes+45873, 616},
    /*   2 : VP2INTERSECTD kreg|rs2,zmmreg,zmmrm512|b32 [rvm:fv:   evex.nds.512.f2.0f38.w0 68 /r     ] AVX512F,AVX512VP2INTERSECT,FUTURE */
        /* 241(f2 7f 48) 301 001(68) 120 : EVEX,PROT,AVX512F,AVX512VP2INTERSECT,FUTURE */
        {I_VP2INTERSECTD, 3, {OPMASKREG|RS2,ZMMREG,RM_ZMM|BITS512,0,0}, {0,0,B32,0,0}, nasm_bytecodes+45882, 617},
};

static const struct itemplate instrux_VP2INTERSECTQ[3] = {
    /*   0 : VP2INTERSECTQ kreg|rs2,xmmreg,xmmrm128|b64 [rvm:fv:   evex.nds.128.f2.0f38.w1 68 /r     ] AVX512VL,AVX512VP2INTERSECT,FUTURE */
        /* 241(f2 ff 08) 301 001(68) 120 : EVEX,PROT,AVX512VL,AVX512VP2INTERSECT,FUTURE */
        {I_VP2INTERSECTQ, 3, {OPMASKREG|RS2,XMMREG,RM_XMM|BITS128,0,0}, {0,0,B64,0,0}, nasm_bytecodes+45891, 616},
    /*   1 : VP2INTERSECTQ kreg|rs2,ymmreg,ymmrm256|b64 [rvm:fv:   evex.nds.256.f2.0f38.w1 68 /r     ] AVX512VL,AVX512VP2INTERSECT,FUTURE */
        /* 241(f2 ff 28) 301 001(68) 120 : EVEX,PROT,AVX512VL,AVX512VP2INTERSECT,FUTURE */
        {I_VP2INTERSECTQ, 3, {OPMASKREG|RS2,YMMREG,RM_YMM|BITS256,0,0}, {0,0,B64,0,0}, nasm_bytecodes+45900, 616},
    /*   2 : VP2INTERSECTQ kreg|rs2,zmmreg,zmmrm512|b64 [rvm:fv:   evex.nds.512.f2.0f38.w1 68 /r     ] AVX512F,AVX512VP2INTERSECT,FUTURE */
        /* 241(f2 ff 48) 301 001(68) 120 : EVEX,PROT,AVX512F,AVX512VP2INTERSECT,FUTURE */
        {I_VP2INTERSECTQ, 3, {OPMASKREG|RS2,ZMMREG,RM_ZMM|BITS512,0,0}, {0,0,B64,0,0}, nasm_bytecodes+45909, 617},
};

static const struct itemplate instrux_LDTILECFG[2] = {
    /*   0 : LDTILECFG mem512 [m:        vex.128.np.0f38.w0 49 /0         ] AR0,SZ,LONG,PROT,AMXTILE,X86_64 */
        /* 270(002 000) 001(49) 200 : AR0,SZ,NOAPX,LONG,VEX,PROT,AMXTILE,X86_64 */
        {I_LDTILECFG, 1, {MEMORY|BITS512|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+65895, 618},
    /*   1 : LDTILECFG mem512 [m:        evex.128.np.0f38.w0 49 /0         ] AR0,SZ,LONG,PROT,AMXTILE,X86_64,APX */
        /* 250(f2 7c 08) 300 001(49) 200 : AR0,SZ,LONG,EVEX,PROT,AMXTILE,APX,X86_64 */
        {I_LDTILECFG, 1, {MEMORY|BITS512,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45918, 619},
};

static const struct itemplate instrux_STTILECFG[2] = {
    /*   0 : STTILECFG mem512 [m:        vex.128.66.0f38.w0 49 /0         ] AR0,SZ,LONG,PROT,AMXTILE,X86_64 */
        /* 270(002 001) 001(49) 200 : AR0,SZ,NOAPX,LONG,VEX,PROT,AMXTILE,X86_64 */
        {I_STTILECFG, 1, {MEMORY|BITS512|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+65902, 618},
    /*   1 : STTILECFG mem512 [m:        evex.128.66.0f38.w0 49 /0         ] AR0,SZ,LONG,PROT,AMXTILE,X86_64,APX */
        /* 250(f2 7d 08) 300 001(49) 200 : AR0,SZ,LONG,EVEX,PROT,AMXTILE,APX,X86_64 */
        {I_STTILECFG, 1, {MEMORY|BITS512,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45927, 619},
};

static const struct itemplate instrux_TDPBF16PS[1] = {
    /*   0 : TDPBF16PS tmmreg,tmmreg,tmmreg [rmv:      vex.128.f3.0f38.w0 5c /r          ] LONG,PROT,AMXBF16,X86_64 */
        /* 262(002 002) 001(5c) 110 : NOAPX,LONG,VEX,PROT,AMXBF16,X86_64 */
        {I_TDPBF16PS, 3, {TMMREG|RN_L16,TMMREG|RN_L16,TMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65909, 620},
};

static const struct itemplate instrux_TDPFP16PS[1] = {
    /*   0 : TDPFP16PS tmmreg,tmmreg,tmmreg [rmv:      vex.128.f2.0f38.w0 5c /r          ] LONG,PROT,AMXFP16,X86_64 */
        /* 262(002 003) 001(5c) 110 : NOAPX,LONG,VEX,PROT,AMXFP16,X86_64 */
        {I_TDPFP16PS, 3, {TMMREG|RN_L16,TMMREG|RN_L16,TMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65916, 621},
};

static const struct itemplate instrux_TCMMIMFP16PS[1] = {
    /*   0 : TCMMIMFP16PS tmmreg,tmmreg,tmmreg [rmv:      vex.128.66.0f38.w0 6c /r          ] LONG,PROT,AMXCOMPLEX,X86_64 */
        /* 262(002 001) 001(6c) 110 : NOAPX,LONG,VEX,PROT,AMXCOMPLEX,X86_64 */
        {I_TCMMIMFP16PS, 3, {TMMREG|RN_L16,TMMREG|RN_L16,TMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65923, 622},
};

static const struct itemplate instrux_TCMMRLFP16PS[1] = {
    /*   0 : TCMMRLFP16PS tmmreg,tmmreg,tmmreg [rmv:      vex.128.np.0f38.w0 6c /r          ] LONG,PROT,AMXCOMPLEX,X86_64 */
        /* 262(002 000) 001(6c) 110 : NOAPX,LONG,VEX,PROT,AMXCOMPLEX,X86_64 */
        {I_TCMMRLFP16PS, 3, {TMMREG|RN_L16,TMMREG|RN_L16,TMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65930, 622},
};

static const struct itemplate instrux_TDPBSSD[1] = {
    /*   0 : TDPBSSD tmmreg,tmmreg,tmmreg [rmv:      vex.128.f2.0f38.w0 5e /r          ] LONG,PROT,AMXINT8,X86_64 */
        /* 262(002 003) 001(5e) 110 : NOAPX,LONG,VEX,PROT,AMXINT8,X86_64 */
        {I_TDPBSSD, 3, {TMMREG|RN_L16,TMMREG|RN_L16,TMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65937, 623},
};

static const struct itemplate instrux_TDPBSUD[1] = {
    /*   0 : TDPBSUD tmmreg,tmmreg,tmmreg [rmv:      vex.128.f3.0f38.w0 5e /r          ] LONG,PROT,AMXINT8,X86_64 */
        /* 262(002 002) 001(5e) 110 : NOAPX,LONG,VEX,PROT,AMXINT8,X86_64 */
        {I_TDPBSUD, 3, {TMMREG|RN_L16,TMMREG|RN_L16,TMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65944, 623},
};

static const struct itemplate instrux_TDPBUSD[1] = {
    /*   0 : TDPBUSD tmmreg,tmmreg,tmmreg [rmv:      vex.128.66.0f38.w0 5e /r          ] LONG,PROT,AMXINT8,X86_64 */
        /* 262(002 001) 001(5e) 110 : NOAPX,LONG,VEX,PROT,AMXINT8,X86_64 */
        {I_TDPBUSD, 3, {TMMREG|RN_L16,TMMREG|RN_L16,TMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65951, 623},
};

static const struct itemplate instrux_TDPBUUD[1] = {
    /*   0 : TDPBUUD tmmreg,tmmreg,tmmreg [rmv:      vex.128.np.0f38.w0 5e /r          ] LONG,PROT,AMXINT8,X86_64 */
        /* 262(002 000) 001(5e) 110 : NOAPX,LONG,VEX,PROT,AMXINT8,X86_64 */
        {I_TDPBUUD, 3, {TMMREG|RN_L16,TMMREG|RN_L16,TMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+65958, 623},
};

static const struct itemplate instrux_TILELOADD[2] = {
    /*   0 : TILELOADD tmmreg,mem [rm:       vex.128.f2.0f38.w0 4b /r         ] AR1,ANYSIZE,SIB,LONG,MIB,PROT,AMXTILE,APX,X86_64 */
        /* 270(002 003) 001(4b) 110 : AR1,ANYSIZE,NOAPX,SIB,LONG,MIB,VEX,PROT,AMXTILE,APX,X86_64 */
        {I_TILELOADD, 2, {TMMREG|RN_L16,MEMORY|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65965, 624},
    /*   1 : TILELOADD tmmreg,mem [rm:       evex.128.f2.0f38.w0 4b /r         ] AR1,ANYSIZE,SIB,LONG,MIB,PROT,AMXTILE,APX,X86_64,APX */
        /* 250(f2 7f 08) 300 001(4b) 110 : AR1,ANYSIZE,SIB,LONG,MIB,EVEX,PROT,AMXTILE,APX,X86_64 */
        {I_TILELOADD, 2, {TMMREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+45936, 625},
};

static const struct itemplate instrux_TILELOADDT1[2] = {
    /*   0 : TILELOADDT1 tmmreg,mem [rm:       vex.128.66.0f38.w0 4b /r         ] AR1,ANYSIZE,SIB,LONG,MIB,PROT,AMXTILE,APX,X86_64 */
        /* 270(002 001) 001(4b) 110 : AR1,ANYSIZE,NOAPX,SIB,LONG,MIB,VEX,PROT,AMXTILE,APX,X86_64 */
        {I_TILELOADDT1, 2, {TMMREG|RN_L16,MEMORY|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65972, 624},
    /*   1 : TILELOADDT1 tmmreg,mem [rm:       evex.128.66.0f38.w0 4b /r         ] AR1,ANYSIZE,SIB,LONG,MIB,PROT,AMXTILE,APX,X86_64,APX */
        /* 250(f2 7d 08) 300 001(4b) 110 : AR1,ANYSIZE,SIB,LONG,MIB,EVEX,PROT,AMXTILE,APX,X86_64 */
        {I_TILELOADDT1, 2, {TMMREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+45945, 625},
};

static const struct itemplate instrux_TILERELEASE[1] = {
    /*   0 : TILERELEASE void [          vex.128.np.0f38.w0 49 c0          ] LONG,PROT,AMXTILE,X86_64 */
        /* 270(002 000) 002(49 c0) : NOAPX,LONG,VEX,PROT,AMXTILE,X86_64 */
        {I_TILERELEASE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+65979, 626},
};

static const struct itemplate instrux_TILESTORED[2] = {
    /*   0 : TILESTORED mem,tmmreg [mr:       vex.128.f3.0f38.w0 4b /r         ] AR0,ANYSIZE,SIB,LONG,MIB,PROT,AMXTILE,APX,X86_64 */
        /* 270(002 002) 001(4b) 101 : AR0,ANYSIZE,NOAPX,SIB,LONG,MIB,VEX,PROT,AMXTILE,APX,X86_64 */
        {I_TILESTORED, 2, {MEMORY|RN_L16,TMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65986, 627},
    /*   1 : TILESTORED mem,tmmreg [mr:       evex.128.f3.0f38.w0 4b /r         ] AR0,ANYSIZE,SIB,LONG,MIB,PROT,AMXTILE,APX,X86_64,APX */
        /* 250(f2 7e 08) 300 001(4b) 101 : AR0,ANYSIZE,SIB,LONG,MIB,EVEX,PROT,AMXTILE,APX,X86_64 */
        {I_TILESTORED, 2, {MEMORY,TMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+45954, 628},
};

static const struct itemplate instrux_TILEZERO[1] = {
    /*   0 : TILEZERO tmmreg [r:        vex.128.f2.0f38.w0 49 /3r0        ] LONG,PROT,AMXTILE,X86_64 */
        /* 270(002 003) 001(49) 171(300) : NOAPX,LONG,VEX,PROT,AMXTILE,X86_64 */
        {I_TILEZERO, 1, {TMMREG|RN_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+54701, 626},
};

static const struct itemplate instrux_TILELOADDRS[2] = {
    /*   0 : TILELOADDRS tmmreg,mem [rm:       vex.128.f2.0f38.w0 4a /r         ] AR1,ANYSIZE,SIB,LONG,MIB,PROT,AMXTILE,AMXMOVRS,APX,X86_64,FUTURE */
        /* 270(002 003) 001(4a) 110 : AR1,ANYSIZE,NOAPX,SIB,LONG,MIB,VEX,PROT,AMXTILE,AMXMOVRS,APX,FUTURE */
        {I_TILELOADDRS, 2, {TMMREG|RN_L16,MEMORY|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+65993, 629},
    /*   1 : TILELOADDRS tmmreg,mem [rm:       evex.128.f2.0f38.w0 4a /r         ] AR1,ANYSIZE,SIB,LONG,MIB,PROT,AMXTILE,AMXMOVRS,APX,X86_64,FUTURE,APX */
        /* 250(f2 7f 08) 300 001(4a) 110 : AR1,ANYSIZE,SIB,LONG,MIB,EVEX,PROT,AMXTILE,AMXMOVRS,APX,FUTURE */
        {I_TILELOADDRS, 2, {TMMREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+45963, 630},
};

static const struct itemplate instrux_TILELOADDRST1[2] = {
    /*   0 : TILELOADDRST1 tmmreg,mem [rm:       vex.128.66.0f38.w0 4a /r         ] AR1,ANYSIZE,SIB,LONG,MIB,PROT,AMXTILE,AMXMOVRS,APX,X86_64,FUTURE */
        /* 270(002 001) 001(4a) 110 : AR1,ANYSIZE,NOAPX,SIB,LONG,MIB,VEX,PROT,AMXTILE,AMXMOVRS,APX,FUTURE */
        {I_TILELOADDRST1, 2, {TMMREG|RN_L16,MEMORY|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66000, 629},
    /*   1 : TILELOADDRST1 tmmreg,mem [rm:       evex.128.66.0f38.w0 4a /r         ] AR1,ANYSIZE,SIB,LONG,MIB,PROT,AMXTILE,AMXMOVRS,APX,X86_64,FUTURE,APX */
        /* 250(f2 7d 08) 300 001(4a) 110 : AR1,ANYSIZE,SIB,LONG,MIB,EVEX,PROT,AMXTILE,AMXMOVRS,APX,FUTURE */
        {I_TILELOADDRST1, 2, {TMMREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+45972, 630},
};

static const struct itemplate instrux_T2RPNTLVWZ0[1] = {
    /*   0 : T2RPNTLVWZ0 tmmreg,mem [rm:       vex.128.np.0f38.w0 6e /r          ] SIB,AMXTRANSPOSE,OBSOLETE,NEVER,FUTURE */
        /* 270(002 000) 001(6e) 110 : NOAPX,SIB,VEX,AMXTRANSPOSE,OBSOLETE,NEVER,FUTURE */
        {I_T2RPNTLVWZ0, 2, {TMMREG|RN_L16,MEMORY|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66007, 631},
};

static const struct itemplate instrux_T2RPNTLVWZ0T1[1] = {
    /*   0 : T2RPNTLVWZ0T1 tmmreg,mem [rm:       vex.128.np.0f38.w0 6f /r          ] SIB,AMXTRANSPOSE,OBSOLETE,NEVER,FUTURE */
        /* 270(002 000) 001(6f) 110 : NOAPX,SIB,VEX,AMXTRANSPOSE,OBSOLETE,NEVER,FUTURE */
        {I_T2RPNTLVWZ0T1, 2, {TMMREG|RN_L16,MEMORY|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66014, 631},
};

static const struct itemplate instrux_T2RPNTLVWZ1[1] = {
    /*   0 : T2RPNTLVWZ1 tmmreg,mem [rm:       vex.128.66.0f38.w0 6e /r          ] SIB,AMXTRANSPOSE,OBSOLETE,NEVER,FUTURE */
        /* 270(002 001) 001(6e) 110 : NOAPX,SIB,VEX,AMXTRANSPOSE,OBSOLETE,NEVER,FUTURE */
        {I_T2RPNTLVWZ1, 2, {TMMREG|RN_L16,MEMORY|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66021, 631},
};

static const struct itemplate instrux_T2RPNTLVWZ1T1[1] = {
    /*   0 : T2RPNTLVWZ1T1 tmmreg,mem [rm:       vex.128.66.0f38.w0 6f /r          ] SIB,AMXTRANSPOSE,OBSOLETE,NEVER,FUTURE */
        /* 270(002 001) 001(6f) 110 : NOAPX,SIB,VEX,AMXTRANSPOSE,OBSOLETE,NEVER,FUTURE */
        {I_T2RPNTLVWZ1T1, 2, {TMMREG|RN_L16,MEMORY|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66028, 631},
};

static const struct itemplate instrux_T2RPNTLVWZ0RS[1] = {
    /*   0 : T2RPNTLVWZ0RS tmmreg,mem [rm:       vex.128.np.map5.w0 f8 /r          ] SIB,AMXTRANSPOSE,OBSOLETE,NEVER,FUTURE */
        /* 270(005 000) 001(f8) 110 : NOAPX,SIB,VEX,AMXTRANSPOSE,OBSOLETE,NEVER,FUTURE */
        {I_T2RPNTLVWZ0RS, 2, {TMMREG|RN_L16,MEMORY|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66035, 631},
};

static const struct itemplate instrux_T2RPNTLVWZ0RST1[1] = {
    /*   0 : T2RPNTLVWZ0RST1 tmmreg,mem [rm:       vex.128.np.map5.w0 f9 /r          ] SIB,AMXTRANSPOSE,OBSOLETE,NEVER,FUTURE */
        /* 270(005 000) 001(f9) 110 : NOAPX,SIB,VEX,AMXTRANSPOSE,OBSOLETE,NEVER,FUTURE */
        {I_T2RPNTLVWZ0RST1, 2, {TMMREG|RN_L16,MEMORY|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66042, 631},
};

static const struct itemplate instrux_T2RPNTLVWZ1RS[1] = {
    /*   0 : T2RPNTLVWZ1RS tmmreg,mem [rm:       vex.128.66.map5.w0 f8 /r          ] SIB,AMXTRANSPOSE,OBSOLETE,NEVER,FUTURE */
        /* 270(005 001) 001(f8) 110 : NOAPX,SIB,VEX,AMXTRANSPOSE,OBSOLETE,NEVER,FUTURE */
        {I_T2RPNTLVWZ1RS, 2, {TMMREG|RN_L16,MEMORY|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66049, 631},
};

static const struct itemplate instrux_T2RPNTLVWZ1RST1[1] = {
    /*   0 : T2RPNTLVWZ1RST1 tmmreg,mem [rm:       vex.128.66.map5.w0 f9 /r          ] SIB,AMXTRANSPOSE,OBSOLETE,NEVER,FUTURE */
        /* 270(005 001) 001(f9) 110 : NOAPX,SIB,VEX,AMXTRANSPOSE,OBSOLETE,NEVER,FUTURE */
        {I_T2RPNTLVWZ1RST1, 2, {TMMREG|RN_L16,MEMORY|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66056, 631},
};

static const struct itemplate instrux_TCONJTCMMIMFP16PS[1] = {
    /*   0 : TCONJTCMMIMFP16PS tmmreg,tmmreg,tmmreg [rmv:      vex.128.np.0f38.w0 6b /r          ] AMXTRANSPOSE,OBSOLETE,NEVER,FUTURE */
        /* 262(002 000) 001(6b) 110 : NOAPX,VEX,AMXTRANSPOSE,OBSOLETE,NEVER,FUTURE */
        {I_TCONJTCMMIMFP16PS, 3, {TMMREG|RN_L16,TMMREG|RN_L16,TMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+66063, 632},
};

static const struct itemplate instrux_TCONJTFP16[1] = {
    /*   0 : TCONJTFP16 tmmreg,tmmreg [rm:       vex.128.66.0f38.w0 6b /r          ] AMXTRANSPOSE,OBSOLETE,NEVER,FUTURE */
        /* 270(002 001) 001(6b) 110 : NOAPX,VEX,AMXTRANSPOSE,OBSOLETE,NEVER,FUTURE */
        {I_TCONJTFP16, 2, {TMMREG|RN_L16,TMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66070, 632},
};

static const struct itemplate instrux_TCVTROWD2PS[2] = {
    /*   0 : TCVTROWD2PS zmmreg,tmmreg,reg32 [rmv:      evex.512.f3.0f38.w0 4a /r         ] AMXAVX512,FUTURE */
        /* 242(f2 7e 48) 300 001(4a) 110 : EVEX,PROT,AMXAVX512,FUTURE */
        {I_TCVTROWD2PS, 3, {ZMMREG,TMMREG,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+45981, 633},
    /*   1 : TCVTROWD2PS zmmreg,tmmreg,imm8 [rmi:      evex.512.f3.0f3a.w0 07 /r ib      ] AMXAVX512,FUTURE */
        /* 250(f3 7e 48) 300 001(07) 110 022 : EVEX,PROT,AMXAVX512,FUTURE */
        {I_TCVTROWD2PS, 3, {ZMMREG,TMMREG,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+22643, 633},
};

static const struct itemplate instrux_TCVTROWPS2BF16H[2] = {
    /*   0 : TCVTROWPS2BF16H zmmreg,tmmreg,reg32 [rmv:      evex.512.f2.0f38.w0 6d /r         ] AMXAVX512,FUTURE */
        /* 242(f2 7f 48) 300 001(6d) 110 : EVEX,PROT,AMXAVX512,FUTURE */
        {I_TCVTROWPS2BF16H, 3, {ZMMREG,TMMREG,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+45990, 633},
    /*   1 : TCVTROWPS2BF16H zmmreg,tmmreg,imm8 [rmi:      evex.512.f2.0f3a.w0 07 /r ib      ] AMXAVX512,FUTURE */
        /* 250(f3 7f 48) 300 001(07) 110 022 : EVEX,PROT,AMXAVX512,FUTURE */
        {I_TCVTROWPS2BF16H, 3, {ZMMREG,TMMREG,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+22653, 633},
};

static const struct itemplate instrux_TCVTROWPS2BF16L[2] = {
    /*   0 : TCVTROWPS2BF16L zmmreg,tmmreg,reg32 [rmv:      evex.512.f3.0f38.w0 6d /r         ] AMXAVX512,FUTURE */
        /* 242(f2 7e 48) 300 001(6d) 110 : EVEX,PROT,AMXAVX512,FUTURE */
        {I_TCVTROWPS2BF16L, 3, {ZMMREG,TMMREG,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+45999, 633},
    /*   1 : TCVTROWPS2BF16L zmmreg,tmmreg,imm8 [rmi:      evex.512.f3.0f3a.w0 77 /r ib      ] AMXAVX512,FUTURE */
        /* 250(f3 7e 48) 300 001(77) 110 022 : EVEX,PROT,AMXAVX512,FUTURE */
        {I_TCVTROWPS2BF16L, 3, {ZMMREG,TMMREG,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+22663, 633},
};

static const struct itemplate instrux_TCVTROWPS2PHH[2] = {
    /*   0 : TCVTROWPS2PHH zmmreg,tmmreg,reg32 [rmv:      evex.512.np.0f38.w0 6d /r         ] AMXAVX512,FUTURE */
        /* 242(f2 7c 48) 300 001(6d) 110 : EVEX,PROT,AMXAVX512,FUTURE */
        {I_TCVTROWPS2PHH, 3, {ZMMREG,TMMREG,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+46008, 633},
    /*   1 : TCVTROWPS2PHH zmmreg,tmmreg,imm8 [rmi:      evex.512.np.0f3a.w0 07 /r ib      ] AMXAVX512,FUTURE */
        /* 250(f3 7c 48) 300 001(07) 110 022 : EVEX,PROT,AMXAVX512,FUTURE */
        {I_TCVTROWPS2PHH, 3, {ZMMREG,TMMREG,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+22673, 633},
};

static const struct itemplate instrux_TCVTROWPS2PHL[2] = {
    /*   0 : TCVTROWPS2PHL zmmreg,tmmreg,reg32 [rmv:      evex.512.66.0f38.w0 6d /r         ] AMXAVX512,FUTURE */
        /* 242(f2 7d 48) 300 001(6d) 110 : EVEX,PROT,AMXAVX512,FUTURE */
        {I_TCVTROWPS2PHL, 3, {ZMMREG,TMMREG,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+46017, 633},
    /*   1 : TCVTROWPS2PHL zmmreg,tmmreg,imm8 [rmi:      evex.512.f2.0f3a.w0 77 /r ib      ] AMXAVX512,FUTURE */
        /* 250(f3 7f 48) 300 001(77) 110 022 : EVEX,PROT,AMXAVX512,FUTURE */
        {I_TCVTROWPS2PHL, 3, {ZMMREG,TMMREG,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+22683, 633},
};

static const struct itemplate instrux_TDPBF8PS[1] = {
    /*   0 : TDPBF8PS tmmreg,tmmreg,tmmreg [rmv:      vex.128.np.map5.w0 fd /r          ] AMXFP8,FUTURE */
        /* 262(005 000) 001(fd) 110 : NOAPX,VEX,AMXFP8,FUTURE */
        {I_TDPBF8PS, 3, {TMMREG|RN_L16,TMMREG|RN_L16,TMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+66077, 634},
};

static const struct itemplate instrux_TDPBHF8PS[1] = {
    /*   0 : TDPBHF8PS tmmreg,tmmreg,tmmreg [rmv:      vex.128.f2.map5.w0 fd /r          ] AMXFP8,FUTURE */
        /* 262(005 003) 001(fd) 110 : NOAPX,VEX,AMXFP8,FUTURE */
        {I_TDPBHF8PS, 3, {TMMREG|RN_L16,TMMREG|RN_L16,TMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+66084, 634},
};

static const struct itemplate instrux_TDPHBF8PS[1] = {
    /*   0 : TDPHBF8PS tmmreg,tmmreg,tmmreg [rmv:      vex.128.f3.map5.w0 fd /r          ] AMXFP8,FUTURE */
        /* 262(005 002) 001(fd) 110 : NOAPX,VEX,AMXFP8,FUTURE */
        {I_TDPHBF8PS, 3, {TMMREG|RN_L16,TMMREG|RN_L16,TMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+66091, 634},
};

static const struct itemplate instrux_TDPHF8PS[1] = {
    /*   0 : TDPHF8PS tmmreg,tmmreg,tmmreg [rmv:      vex.128.66.map5.w0 fd /r          ] AMXFP8,FUTURE */
        /* 262(005 001) 001(fd) 110 : NOAPX,VEX,AMXFP8,FUTURE */
        {I_TDPHF8PS, 3, {TMMREG|RN_L16,TMMREG|RN_L16,TMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+66098, 634},
};

static const struct itemplate instrux_TILEMOVROW[2] = {
    /*   0 : TILEMOVROW zmmreg,tmmreg,imm8 [rmi:      evex.512.66.0f3a.w0 07 /r ib      ] AMXAVX512,FUTURE */
        /* 250(f3 7d 48) 300 001(07) 110 022 : EVEX,PROT,AMXAVX512,FUTURE */
        {I_TILEMOVROW, 3, {ZMMREG,TMMREG,IMM_NORMAL|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+22693, 633},
    /*   1 : TILEMOVROW zmmreg,tmmreg,reg32 [rmv:      evex.512.66.0f38.w0 4a /r         ] AMXAVX512,FUTURE */
        /* 242(f2 7d 48) 300 001(4a) 110 : EVEX,PROT,AMXAVX512,FUTURE */
        {I_TILEMOVROW, 3, {ZMMREG,TMMREG,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+46026, 633},
};

static const struct itemplate instrux_TMMULTF32PS[1] = {
    /*   0 : TMMULTF32PS tmmreg,tmmreg,tmmreg [rmv:      vex.128.66.0f38.w0 48 /r          ] AMXTF32,FUTURE */
        /* 262(002 001) 001(48) 110 : NOAPX,VEX,AMXTF32,FUTURE */
        {I_TMMULTF32PS, 3, {TMMREG|RN_L16,TMMREG|RN_L16,TMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+66105, 635},
};

static const struct itemplate instrux_TTCMMIMFP16PS[1] = {
    /*   0 : TTCMMIMFP16PS tmmreg,tmmreg,tmmreg [rmv:      vex.128.f2.0f38.w0 6b /r          ] AMXTRANSPOSE,OBSOLETE,NEVER,FUTURE */
        /* 262(002 003) 001(6b) 110 : NOAPX,VEX,AMXTRANSPOSE,OBSOLETE,NEVER,FUTURE */
        {I_TTCMMIMFP16PS, 3, {TMMREG|RN_L16,TMMREG|RN_L16,TMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+66112, 632},
};

static const struct itemplate instrux_TTCMMRLFP16PS[1] = {
    /*   0 : TTCMMRLFP16PS tmmreg,tmmreg,tmmreg [rmv:      vex.128.f3.0f38.w0 6b /r          ] AMXTRANSPOSE,OBSOLETE,NEVER,FUTURE */
        /* 262(002 002) 001(6b) 110 : NOAPX,VEX,AMXTRANSPOSE,OBSOLETE,NEVER,FUTURE */
        {I_TTCMMRLFP16PS, 3, {TMMREG|RN_L16,TMMREG|RN_L16,TMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+66119, 632},
};

static const struct itemplate instrux_TTDPBF16PS[1] = {
    /*   0 : TTDPBF16PS tmmreg,tmmreg,tmmreg [rmv:      vex.128.f3.0f38.w0 6c /r          ] AMXTRANSPOSE,OBSOLETE,NEVER,FUTURE */
        /* 262(002 002) 001(6c) 110 : NOAPX,VEX,AMXTRANSPOSE,OBSOLETE,NEVER,FUTURE */
        {I_TTDPBF16PS, 3, {TMMREG|RN_L16,TMMREG|RN_L16,TMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+66126, 632},
};

static const struct itemplate instrux_TTDPFP16PS[1] = {
    /*   0 : TTDPFP16PS tmmreg,tmmreg,tmmreg [rmv:      vex.128.f2.0f38.w0 6c /r          ] AMXTRANSPOSE,OBSOLETE,NEVER,FUTURE */
        /* 262(002 003) 001(6c) 110 : NOAPX,VEX,AMXTRANSPOSE,OBSOLETE,NEVER,FUTURE */
        {I_TTDPFP16PS, 3, {TMMREG|RN_L16,TMMREG|RN_L16,TMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+66133, 632},
};

static const struct itemplate instrux_TTMMULTF32PS[1] = {
    /*   0 : TTMMULTF32PS tmmreg,tmmreg,tmmreg [rmv:      vex.128.np.0f38.w0 48 /r          ] AMXTRANSPOSE,OBSOLETE,NEVER,FUTURE */
        /* 262(002 000) 001(48) 110 : NOAPX,VEX,AMXTRANSPOSE,OBSOLETE,NEVER,FUTURE */
        {I_TTMMULTF32PS, 3, {TMMREG|RN_L16,TMMREG|RN_L16,TMMREG|RN_L16,0,0}, NO_DECORATOR, nasm_bytecodes+66140, 632},
};

static const struct itemplate instrux_TTRANSPOSED[1] = {
    /*   0 : TTRANSPOSED tmmreg,tmmreg [rm:       vex.128.f3.0f38.w0 5f /r          ] AMXTRANSPOSE,OBSOLETE,NEVER,FUTURE */
        /* 270(002 002) 001(5f) 110 : NOAPX,VEX,AMXTRANSPOSE,OBSOLETE,NEVER,FUTURE */
        {I_TTRANSPOSED, 2, {TMMREG|RN_L16,TMMREG|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66147, 632},
};

static const struct itemplate instrux_VADDPH[6] = {
    /*   0 : VADDPH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv:   evex.nds.128.np.map5.w0 58 /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f5 7c 08) 301 001(58) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VADDPH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+46035, 566},
    /*   1 : VADDPH xmmreg|mask|z,xmmrm128|b16 [r+vm:fv:   evex.nds.128.np.map5.w0 58 /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f5 7c 08) 301 001(58) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VADDPH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+46044, 566},
    /*   2 : VADDPH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv:   evex.nds.256.np.map5.w0 58 /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f5 7c 28) 301 001(58) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VADDPH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+46053, 566},
    /*   3 : VADDPH ymmreg|mask|z,ymmrm256|b16 [r+vm:fv:   evex.nds.256.np.map5.w0 58 /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f5 7c 28) 301 001(58) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VADDPH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+46062, 566},
    /*   4 : VADDPH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv:   evex.nds.512.np.map5.w0 58 /r     ] AVX512FP16,FUTURE */
        /* 241(f5 7c 48) 301 001(58) 120 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VADDPH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+46071, 567},
    /*   5 : VADDPH zmmreg|mask|z,zmmrm512|b16|er [r+vm:fv:   evex.nds.512.np.map5.w0 58 /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f5 7c 48) 301 001(58) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VADDPH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+46080, 567},
};

static const struct itemplate instrux_VADDSH[2] = {
    /*   0 : VADDSH xmmreg|mask|z,xmmreg*,xmmrm16|er [rvm:t1s:  evex.nds.lig.f3.map5.w0 58 /r     ] AVX512FP16,FUTURE */
        /* 241(f5 7e 08) 306 001(58) 120 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VADDSH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+46089, 568},
    /*   1 : VADDSH xmmreg|mask|z,xmmrm16|er [r+vm:t1s:  evex.nds.lig.f3.map5.w0 58 /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f5 7e 08) 306 001(58) 110 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VADDSH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+46098, 568},
};

static const struct itemplate instrux_VCMPPH[6] = {
    /*   0 : VCMPPH kreg|mask,xmmreg*,xmmrm128|b16,imm8 [rvmi:fv:  evex.nds.128.np.0f3a.w0 C2 /r ib  ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f3 7c 08) 301 001(c2) 120 023 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCMPPH, 4, {OPMASKREG,XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK,0,B16,0,0}, nasm_bytecodes+22703, 566},
    /*   1 : VCMPPH kreg|mask,xmmrm128|b16,imm8 [r+vmi:fv:  evex.nds.128.np.0f3a.w0 C2 /r ib  ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f3 7c 08) 301 001(c2) 110 022 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCMPPH, 3, {OPMASKREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK,B16,0,0,0}, nasm_bytecodes+22713, 566},
    /*   2 : VCMPPH kreg|mask,ymmreg*,ymmrm256|b16,imm8 [rvmi:fv:  evex.nds.256.np.0f3a.w0 C2 /r ib  ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f3 7c 28) 301 001(c2) 120 023 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCMPPH, 4, {OPMASKREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK,0,B16,0,0}, nasm_bytecodes+22723, 566},
    /*   3 : VCMPPH kreg|mask,ymmrm256|b16,imm8 [r+vmi:fv:  evex.nds.256.np.0f3a.w0 C2 /r ib  ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f3 7c 28) 301 001(c2) 110 022 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCMPPH, 3, {OPMASKREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK,B16,0,0,0}, nasm_bytecodes+22733, 566},
    /*   4 : VCMPPH kreg|mask,zmmreg*,zmmrm512|b16|sae,imm8 [rvmi:fv:  evex.nds.512.np.0f3a.w0 C2 /r ib  ] AVX512FP16,FUTURE */
        /* 241(f3 7c 48) 301 001(c2) 120 023 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCMPPH, 4, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, {MASK,0,B16|SAE,0,0}, nasm_bytecodes+22743, 567},
    /*   5 : VCMPPH kreg|mask,zmmrm512|b16|sae,imm8 [r+vmi:fv:  evex.nds.512.np.0f3a.w0 C2 /r ib  ] ND,AVX512FP16,FUTURE */
        /* 240(f3 7c 48) 301 001(c2) 110 022 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCMPPH, 3, {OPMASKREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK,B16|SAE,0,0,0}, nasm_bytecodes+22753, 567},
};

static const struct itemplate instrux_VCMPSH[2] = {
    /*   0 : VCMPSH kreg|mask,xmmreg*,xmmrm16|sae,imm8 [rvmi:t1s: evex.nds.lig.f3.0f3a.w0 C2 /r ib  ] AVX512FP16,FUTURE */
        /* 241(f3 7e 08) 306 001(c2) 120 023 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCMPSH, 4, {OPMASKREG,XMMREG,RM_XMM|BITS16,IMM_NORMAL|BITS8,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+22763, 568},
    /*   1 : VCMPSH kreg|mask,xmmrm16|sae,imm8 [r+vmi:t1s: evex.nds.lig.f3.0f3a.w0 C2 /r ib  ] ND,AVX512FP16,FUTURE */
        /* 240(f3 7e 08) 306 001(c2) 110 022 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCMPSH, 3, {OPMASKREG,RM_XMM|BITS16,IMM_NORMAL|BITS8,0,0}, {MASK,SAE,0,0,0}, nasm_bytecodes+22773, 568},
};

static const struct itemplate instrux_VCOMISH[1] = {
    /*   0 : VCOMISH xmmreg,xmmrm16|sae [rm:fv:    evex.lig.np.map5.w0 2F /r         ] FL,AVX512FP16,FUTURE */
        /* 250(f5 7c 08) 301 001(2f) 110 : LIG,FL,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCOMISH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+46107, 636},
};

static const struct itemplate instrux_VCVTDQ2PH[3] = {
    /*   0 : VCVTDQ2PH xmmreg|mask|z,xmmrm128|b32 [rm:fv:    evex.128.np.map5.w0 5B /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 7c 08) 301 001(5b) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTDQ2PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+46116, 566},
    /*   1 : VCVTDQ2PH ymmreg|mask|z,ymmrm256|b32 [rm:fv:    evex.256.np.map5.w0 5B /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 7c 28) 301 001(5b) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTDQ2PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+46125, 566},
    /*   2 : VCVTDQ2PH zmmreg|mask|z,zmmrm512|b32|er [rm:fv:    evex.512.np.map5.w0 5B /r         ] AVX512FP16,FUTURE */
        /* 250(f5 7c 48) 301 001(5b) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTDQ2PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+46134, 567},
};

static const struct itemplate instrux_VCVTPD2PH[3] = {
    /*   0 : VCVTPD2PH xmmreg|mask|z,xmmrm128|b64 [rm:fv:    evex.128.66.map5.w1 5A /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 fd 08) 301 001(5a) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTPD2PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+46143, 566},
    /*   1 : VCVTPD2PH ymmreg|mask|z,ymmrm256|b64 [rm:fv:    evex.256.66.map5.w1 5A /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 fd 28) 301 001(5a) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTPD2PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+46152, 566},
    /*   2 : VCVTPD2PH zmmreg|mask|z,zmmrm512|b64|er [rm:fv:    evex.512.66.map5.w1 5A /r         ] AVX512FP16,FUTURE */
        /* 250(f5 fd 48) 301 001(5a) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTPD2PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+46161, 567},
};

static const struct itemplate instrux_VCVTPH2DQ[3] = {
    /*   0 : VCVTPH2DQ xmmreg|mask|z,xmmrm64|b16 [rm:hv:    evex.128.66.map5.w0 5B /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 7d 08) 302 001(5b) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTPH2DQ, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+46170, 566},
    /*   1 : VCVTPH2DQ ymmreg|mask|z,xmmrm128|b16 [rm:hv:    evex.256.66.map5.w0 5B /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 7d 28) 302 001(5b) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTPH2DQ, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+46179, 566},
    /*   2 : VCVTPH2DQ zmmreg|mask|z,ymmrm256|b16|er [rm:hv:    evex.512.66.map5.w0 5B /r         ] AVX512FP16,FUTURE */
        /* 250(f5 7d 48) 302 001(5b) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTPH2DQ, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+46188, 567},
};

static const struct itemplate instrux_VCVTPH2PD[3] = {
    /*   0 : VCVTPH2PD xmmreg|mask|z,xmmrm32|b16 [rm:qvm:   evex.128.np.map5.w0 5A /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 7c 08) 315 001(5a) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTPH2PD, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+46197, 566},
    /*   1 : VCVTPH2PD ymmreg|mask|z,xmmrm64|b16 [rm:qvm:   evex.256.np.map5.w0 5A /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 7c 28) 315 001(5a) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTPH2PD, 2, {YMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+46206, 566},
    /*   2 : VCVTPH2PD zmmreg|mask|z,xmmrm128|b16|sae [rm:qvm:   evex.512.np.map5.w0 5A /r         ] AVX512FP16,FUTURE */
        /* 250(f5 7c 48) 315 001(5a) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTPH2PD, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+46215, 567},
};

static const struct itemplate instrux_VCVTPH2PSX[3] = {
    /*   0 : VCVTPH2PSX xmmreg|mask|z,xmmrm64|b16 [rm:hv:    evex.128.66.map6.w0 13 /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f6 7d 08) 302 001(13) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTPH2PSX, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+46224, 566},
    /*   1 : VCVTPH2PSX ymmreg|mask|z,xmmrm128|b16 [rm:hv:    evex.256.66.map6.w0 13 /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f6 7d 28) 302 001(13) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTPH2PSX, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+46233, 566},
    /*   2 : VCVTPH2PSX zmmreg|mask|z,ymmrm256|b16|sae [rm:hv:    evex.512.66.map6.w0 13 /r         ] AVX512FP16,FUTURE */
        /* 250(f6 7d 48) 302 001(13) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTPH2PSX, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+46242, 567},
};

static const struct itemplate instrux_VCVTPH2QQ[3] = {
    /*   0 : VCVTPH2QQ xmmreg|mask|z,xmmrm32|b16 [rm:qvm:   evex.128.66.map5.w0 7b /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 7d 08) 315 001(7b) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTPH2QQ, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+46251, 566},
    /*   1 : VCVTPH2QQ ymmreg|mask|z,xmmrm64|b16 [rm:qvm:   evex.256.66.map5.w0 7b /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 7d 28) 315 001(7b) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTPH2QQ, 2, {YMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+46260, 566},
    /*   2 : VCVTPH2QQ zmmreg|mask|z,xmmrm128|b16|er [rm:qvm:   evex.512.66.map5.w0 7b /r         ] AVX512FP16,FUTURE */
        /* 250(f5 7d 48) 315 001(7b) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTPH2QQ, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+46269, 567},
};

static const struct itemplate instrux_VCVTPH2UDQ[3] = {
    /*   0 : VCVTPH2UDQ xmmreg|mask|z,xmmrm32|b16 [rm:hv:    evex.128.map5.w0 79 /r            ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 7c 08) 302 001(79) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTPH2UDQ, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+46278, 566},
    /*   1 : VCVTPH2UDQ ymmreg|mask|z,xmmrm64|b16 [rm:hv:    evex.256.map5.w0 79 /r            ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 7c 28) 302 001(79) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTPH2UDQ, 2, {YMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+46287, 566},
    /*   2 : VCVTPH2UDQ zmmreg|mask|z,xmmrm128|b16|er [rm:hv:    evex.512.map5.w0 79 /r            ] AVX512FP16,FUTURE */
        /* 250(f5 7c 48) 302 001(79) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTPH2UDQ, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+46296, 567},
};

static const struct itemplate instrux_VCVTPH2UQQ[3] = {
    /*   0 : VCVTPH2UQQ xmmreg|mask|z,xmmrm32|b16 [rm:qvm:   evex.128.66.map5.w0 79 /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 7d 08) 315 001(79) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTPH2UQQ, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+46305, 566},
    /*   1 : VCVTPH2UQQ ymmreg|mask|z,xmmrm64|b16 [rm:qvm:   evex.256.66.map5.w0 79 /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 7d 28) 315 001(79) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTPH2UQQ, 2, {YMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+46314, 566},
    /*   2 : VCVTPH2UQQ zmmreg|mask|z,xmmrm128|b16|er [rm:qvm:   evex.512.66.map5.w0 79 /r         ] AVX512FP16,FUTURE */
        /* 250(f5 7d 48) 315 001(79) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTPH2UQQ, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+46323, 567},
};

static const struct itemplate instrux_VCVTPH2UW[3] = {
    /*   0 : VCVTPH2UW xmmreg|mask|z,xmmrm128|b16 [rm:fv:    evex.128.np.map5.w0 7d /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 7c 08) 301 001(7d) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTPH2UW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+46332, 566},
    /*   1 : VCVTPH2UW ymmreg|mask|z,ymmrm256|b16 [rm:fv:    evex.256.np.map5.w0 7d /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 7c 28) 301 001(7d) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTPH2UW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+46341, 566},
    /*   2 : VCVTPH2UW zmmreg|mask|z,zmmrm512|b16|er [rm:fv:    evex.512.np.map5.w0 7d /r         ] AVX512FP16,FUTURE */
        /* 250(f5 7c 48) 301 001(7d) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTPH2UW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+46350, 567},
};

static const struct itemplate instrux_VCVTPH2W[3] = {
    /*   0 : VCVTPH2W xmmreg|mask|z,xmmrm128|b16 [rm:fv:    evex.128.66.map5.w0 7d /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 7d 08) 301 001(7d) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTPH2W, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+46359, 566},
    /*   1 : VCVTPH2W ymmreg|mask|z,ymmrm256|b16 [rm:fv:    evex.256.66.map5.w0 7d /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 7d 28) 301 001(7d) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTPH2W, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+46368, 566},
    /*   2 : VCVTPH2W zmmreg|mask|z,zmmrm512|b16|er [rm:fv:    evex.512.66.map5.w0 7d /r         ] AVX512FP16,FUTURE */
        /* 250(f5 7d 48) 301 001(7d) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTPH2W, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+46377, 567},
};

static const struct itemplate instrux_VCVTPS2PHX[3] = {
    /*   0 : VCVTPS2PHX xmmreg|mask|z,xmmrm128|b32 [rm:fv:    evex.128.66.map5.w0 1d /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 7d 08) 301 001(1d) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTPS2PHX, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+46386, 566},
    /*   1 : VCVTPS2PHX xmmreg|mask|z,ymmrm256|b32 [rm:fv:    evex.256.66.map5.w0 1d /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 7d 28) 301 001(1d) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTPS2PHX, 2, {XMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+46395, 566},
    /*   2 : VCVTPS2PHX ymmreg|mask|z,zmmrm512|b32|er [rm:fv:    evex.512.66.map5.w0 1d /r         ] AVX512FP16,FUTURE */
        /* 250(f5 7d 48) 301 001(1d) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTPS2PHX, 2, {YMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+46404, 567},
};

static const struct itemplate instrux_VCVTQQ2PH[3] = {
    /*   0 : VCVTQQ2PH xmmreg|mask|z,xmmrm128|b64 [rm:fv:    evex.128.np.map5.w1 5b /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 fc 08) 301 001(5b) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTQQ2PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+46413, 566},
    /*   1 : VCVTQQ2PH ymmreg|mask|z,ymmrm256|b64 [rm:fv:    evex.256.np.map5.w1 5b /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 fc 28) 301 001(5b) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTQQ2PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+46422, 566},
    /*   2 : VCVTQQ2PH zmmreg|mask|z,zmmrm512|b64|er [rm:fv:    evex.512.np.map5.w1 5b /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 fc 48) 301 001(5b) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTQQ2PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+46431, 566},
};

static const struct itemplate instrux_VCVTSD2SH[2] = {
    /*   0 : VCVTSD2SH xmmreg|mask|z,xmmreg*,xmmrm64|er [rvm:t1s:  evex.nds.lig.f2.map5.w1 5a /r     ] AVX512FP16,FUTURE */
        /* 241(f5 ff 08) 306 001(5a) 120 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTSD2SH, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+46440, 568},
    /*   1 : VCVTSD2SH xmmreg|mask|z,xmmrm64|er [r+vm:t1s:  evex.nds.lig.f2.map5.w1 5a /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f5 ff 08) 306 001(5a) 110 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTSD2SH, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+46449, 568},
};

static const struct itemplate instrux_VCVTSH2SD[2] = {
    /*   0 : VCVTSH2SD xmmreg,xmmreg*,xmmrm16|sae [rvm:t1s:  evex.nds.lig.f3.map5.w0 5a /r     ] AVX512FP16,FUTURE */
        /* 241(f5 7e 08) 306 001(5a) 120 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTSH2SD, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {0,0,SAE,0,0}, nasm_bytecodes+46458, 568},
    /*   1 : VCVTSH2SD xmmreg,xmmrm16|sae [r+vm:t1s:  evex.nds.lig.f3.map5.w0 5a /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f5 7e 08) 306 001(5a) 110 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTSH2SD, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+46467, 568},
};

static const struct itemplate instrux_VCVTSH2SI[2] = {
    /*   0 : VCVTSH2SI reg32,xmmrm16|er [rm:t1s:   evex.lig.f3.map5.w0 2d /r         ] AVX512FP16,FUTURE */
        /* 250(f5 7e 08) 306 001(2d) 110 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTSH2SI, 2, {REG_GPR|BITS32,RM_XMM|BITS16,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+46476, 568},
    /*   1 : VCVTSH2SI reg64,xmmrm16|er [rm:t1s:   evex.lig.f3.map5.w1 2d /r         ] AVX512FP16,FUTURE */
        /* 250(f5 fe 08) 306 001(2d) 110 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTSH2SI, 2, {REG_GPR|BITS64,RM_XMM|BITS16,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+46485, 568},
};

static const struct itemplate instrux_VCVTSH2SS[2] = {
    /*   0 : VCVTSH2SS xmmreg|mask|z,xmmreg*,xmmrm16|sae [rvm:t1s:  evex.nds.lig.map6.w0 13 /r        ] AVX512FP16,FUTURE */
        /* 241(f6 7c 08) 306 001(13) 120 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTSH2SS, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+46494, 568},
    /*   1 : VCVTSH2SS xmmreg|mask|z,xmmrm16|sae [r+vm:t1s:  evex.nds.lig.map6.w0 13 /r        ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7c 08) 306 001(13) 110 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTSH2SS, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+46503, 568},
};

static const struct itemplate instrux_VCVTSH2USI[2] = {
    /*   0 : VCVTSH2USI reg32,xmmrm16|er [rm:t1s:   evex.lig.f3.map5.w0 79 /r         ] AVX512FP16,FUTURE */
        /* 250(f5 7e 08) 306 001(79) 110 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTSH2USI, 2, {REG_GPR|BITS32,RM_XMM|BITS16,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+46512, 568},
    /*   1 : VCVTSH2USI reg64,xmmrm16|er [rm:t1s:   evex.lig.f3.map5.w1 79 /r         ] AVX512FP16,FUTURE */
        /* 250(f5 fe 08) 306 001(79) 110 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTSH2USI, 2, {REG_GPR|BITS64,RM_XMM|BITS16,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+46521, 568},
};

static const struct itemplate instrux_VCVTSI2SH[4] = {
    /*   0 : VCVTSI2SH xmmreg,xmmreg*,rm32|er [rvm:t1s:  evex.nds.lig.f3.map5.w0 2a /r     ] AVX512FP16,FUTURE */
        /* 241(f5 7e 08) 306 001(2a) 120 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTSI2SH, 3, {XMMREG,XMMREG,RM_GPR|BITS32,0,0}, {0,0,ER,0,0}, nasm_bytecodes+46530, 568},
    /*   1 : VCVTSI2SH xmmreg,rm32|er [r+vm:t1s:  evex.nds.lig.f3.map5.w0 2a /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f5 7e 08) 306 001(2a) 110 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTSI2SH, 2, {XMMREG,RM_GPR|BITS32,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+46539, 568},
    /*   2 : VCVTSI2SH xmmreg,xmmreg*,rm64|er [rvm:t1s:  evex.nds.lig.f3.map5.w1 2a /r     ] AVX512FP16,FUTURE */
        /* 241(f5 fe 08) 306 001(2a) 120 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTSI2SH, 3, {XMMREG,XMMREG,RM_GPR|BITS64,0,0}, {0,0,ER,0,0}, nasm_bytecodes+46548, 568},
    /*   3 : VCVTSI2SH xmmreg,rm64|er [r+vm:t1s:  evex.nds.lig.f3.map5.w1 2a /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f5 fe 08) 306 001(2a) 110 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTSI2SH, 2, {XMMREG,RM_GPR|BITS64,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+46557, 568},
};

static const struct itemplate instrux_VCVTSS2SH[2] = {
    /*   0 : VCVTSS2SH xmmreg,xmmreg*,xmmrm32|er [rvm:t1s:  evex.nds.lig.np.map5 1d /r        ] AVX512FP16,FUTURE */
        /* 241(f5 7c 08) 306 001(1d) 120 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTSS2SH, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {0,0,ER,0,0}, nasm_bytecodes+46566, 568},
    /*   1 : VCVTSS2SH xmmreg,xmmrm32|er [r+vm:t1s:  evex.nds.lig.np.map5 1d /r        ] ND,AVX512FP16,FUTURE */
        /* 240(f5 7c 08) 306 001(1d) 110 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTSS2SH, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+46575, 568},
};

static const struct itemplate instrux_VCVTTPH2DQ[3] = {
    /*   0 : VCVTTPH2DQ xmmreg|mask|z,xmmrm64|b16 [rm:hv:    evex.128.f3.map5.w0 5b /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 7e 08) 302 001(5b) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTTPH2DQ, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+46584, 566},
    /*   1 : VCVTTPH2DQ ymmreg|mask|z,xmmrm128|b16 [rm:hv:    evex.256.f3.map5.w0 5b /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 7e 28) 302 001(5b) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTTPH2DQ, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+46593, 566},
    /*   2 : VCVTTPH2DQ zmmreg|mask|z,ymmrm256|b16|sae [rm:hv:    evex.512.f3.map5.w0 5b /r         ] AVX512FP16,FUTURE */
        /* 250(f5 7e 48) 302 001(5b) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTTPH2DQ, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+46602, 567},
};

static const struct itemplate instrux_VCVTTPH2QQ[3] = {
    /*   0 : VCVTTPH2QQ xmmreg|mask|z,xmmrm32|b16 [rm:t1s:   evex.128.66.map5.w0 7a /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 7d 08) 306 001(7a) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTTPH2QQ, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+46611, 566},
    /*   1 : VCVTTPH2QQ ymmreg|mask|z,xmmrm64|b16 [rm:t1s:   evex.256.66.map5.w0 7a /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 7d 28) 306 001(7a) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTTPH2QQ, 2, {YMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+46620, 566},
    /*   2 : VCVTTPH2QQ zmmreg|mask|z,xmmrm128|b16|sae [rm:t1s:   evex.512.66.map5.w0 7a /r         ] AVX512FP16,FUTURE */
        /* 250(f5 7d 48) 306 001(7a) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTTPH2QQ, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+46629, 567},
};

static const struct itemplate instrux_VCVTTPH2UDQ[3] = {
    /*   0 : VCVTTPH2UDQ xmmreg|mask|z,xmmrm64|b16 [rm:hv:    evex.128.np.map5.w0 78 /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 7c 08) 302 001(78) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTTPH2UDQ, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+46638, 566},
    /*   1 : VCVTTPH2UDQ ymmreg|mask|z,xmmrm128|b16 [rm:hv:    evex.256.np.map5.w0 78 /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 7c 28) 302 001(78) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTTPH2UDQ, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+46647, 566},
    /*   2 : VCVTTPH2UDQ zmmreg|mask|z,ymmrm256|b16|sae [rm:hv:    evex.512.np.map5.w0 78 /r         ] AVX512FP16,FUTURE */
        /* 250(f5 7c 48) 302 001(78) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTTPH2UDQ, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+46656, 567},
};

static const struct itemplate instrux_VCVTTPH2UQQ[3] = {
    /*   0 : VCVTTPH2UQQ xmmreg|mask|z,xmmrm32|b16 [rm:t1s:   evex.128.66.map5.w0 78 /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 7d 08) 306 001(78) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTTPH2UQQ, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+46665, 566},
    /*   1 : VCVTTPH2UQQ ymmreg|mask|z,xmmrm64|b16 [rm:t1s:   evex.256.66.map5.w0 78 /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 7d 28) 306 001(78) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTTPH2UQQ, 2, {YMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+46674, 566},
    /*   2 : VCVTTPH2UQQ zmmreg|mask|z,xmmrm128|b16|sae [rm:t1s:   evex.512.66.map5.w0 78 /r         ] AVX512FP16,FUTURE */
        /* 250(f5 7d 48) 306 001(78) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTTPH2UQQ, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+46683, 567},
};

static const struct itemplate instrux_VCVTTPH2UW[3] = {
    /*   0 : VCVTTPH2UW xmmreg|mask|z,xmmrm128|b16 [rm:fv:    evex.128.np.map5.w0 7c /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 7c 08) 301 001(7c) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTTPH2UW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+46692, 566},
    /*   1 : VCVTTPH2UW ymmreg|mask|z,ymmrm256|b16 [rm:fv:    evex.256.np.map5.w0 7c /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 7c 28) 301 001(7c) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTTPH2UW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+46701, 566},
    /*   2 : VCVTTPH2UW zmmreg|mask|z,zmmrm512|b16|sae [rm:fv:    evex.512.np.map5.w0 7c /r         ] AVX512FP16,FUTURE */
        /* 250(f5 7c 48) 301 001(7c) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTTPH2UW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+46710, 567},
};

static const struct itemplate instrux_VCVTTPH2W[3] = {
    /*   0 : VCVTTPH2W xmmreg|mask|z,xmmrm128|b16 [rm:fv:    evex.128.66.map5.w0 7c /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 7d 08) 301 001(7c) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTTPH2W, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+46719, 566},
    /*   1 : VCVTTPH2W ymmreg|mask|z,ymmrm256|b16 [rm:fv:    evex.256.66.map5.w0 7c /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 7d 28) 301 001(7c) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTTPH2W, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+46728, 566},
    /*   2 : VCVTTPH2W zmmreg|mask|z,zmmrm512|b16|sae [rm:fv:    evex.512.66.map5.w0 7c /r         ] AVX512FP16,FUTURE */
        /* 250(f5 7d 48) 301 001(7c) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTTPH2W, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+46737, 567},
};

static const struct itemplate instrux_VCVTTSH2SI[2] = {
    /*   0 : VCVTTSH2SI reg32,xmmrm16|sae [rm:t1s:   evex.lig.f3.map5.w0 2c /r         ] AVX512FP16,FUTURE */
        /* 250(f5 7e 08) 306 001(2c) 110 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTTSH2SI, 2, {REG_GPR|BITS32,RM_XMM|BITS16,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+46746, 568},
    /*   1 : VCVTTSH2SI reg64,xmmrm16|sae [rm:t1s:   evex.lig.f3.map5.w1 2c /r         ] AVX512FP16,FUTURE */
        /* 250(f5 fe 08) 306 001(2c) 110 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTTSH2SI, 2, {REG_GPR|BITS64,RM_XMM|BITS16,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+46755, 568},
};

static const struct itemplate instrux_VCVTTSH2USI[2] = {
    /*   0 : VCVTTSH2USI reg32,xmmrm16|sae [rm:t1s:   evex.lig.f3.map5.w0 78 /r         ] AVX512FP16,FUTURE */
        /* 250(f5 7e 08) 306 001(78) 110 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTTSH2USI, 2, {REG_GPR|BITS32,RM_XMM|BITS16,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+46764, 568},
    /*   1 : VCVTTSH2USI reg64,xmmrm16|sae [rm:t1s:   evex.lig.f3.map5.w1 78 /r         ] AVX512FP16,FUTURE */
        /* 250(f5 fe 08) 306 001(78) 110 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTTSH2USI, 2, {REG_GPR|BITS64,RM_XMM|BITS16,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+46773, 568},
};

static const struct itemplate instrux_VCVTUDQ2PH[3] = {
    /*   0 : VCVTUDQ2PH xmmreg|mask|z,xmmrm128|b32 [rm:fv:    evex.128.f2.map5.w0 7a /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 7f 08) 301 001(7a) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTUDQ2PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+46782, 566},
    /*   1 : VCVTUDQ2PH ymmreg|mask|z,ymmrm256|b32 [rm:fv:    evex.256.f2.map5.w0 7a /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 7f 28) 301 001(7a) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTUDQ2PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+46791, 566},
    /*   2 : VCVTUDQ2PH zmmreg|mask|z,zmmrm512|b32 [rm:fv:    evex.512.f2.map5.w0 7a /r         ] AVX512FP16,FUTURE */
        /* 250(f5 7f 48) 301 001(7a) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTUDQ2PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+46800, 567},
};

static const struct itemplate instrux_VCVTUQQ2PH[3] = {
    /*   0 : VCVTUQQ2PH xmmreg|mask|z,xmmrm128|b32 [rm:fv:    evex.128.f2.map5.w1 7a /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 ff 08) 301 001(7a) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTUQQ2PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+46809, 566},
    /*   1 : VCVTUQQ2PH ymmreg|mask|z,ymmrm256|b32 [rm:fv:    evex.256.f2.map5.w1 7a /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 ff 28) 301 001(7a) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTUQQ2PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+46818, 566},
    /*   2 : VCVTUQQ2PH zmmreg|mask|z,zmmrm512|b32 [rm:fv:    evex.512.f2.map5.w1 7a /r         ] AVX512FP16,FUTURE */
        /* 250(f5 ff 48) 301 001(7a) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTUQQ2PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+46827, 567},
};

static const struct itemplate instrux_VCVTUSI2SH[1] = {
    /*   0 : VCVTUSI2SH xmmreg,xmmreg|er,rm32|er [rvm:t1s:  evex.nds.lig.f3.map5.w0 7b /r     ] AVX512FP16,FUTURE */
        /* 241(f5 7e 08) 306 001(7b) 120 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTUSI2SH, 3, {XMMREG,XMMREG,RM_GPR|BITS32,0,0}, {0,ER,ER,0,0}, nasm_bytecodes+46836, 568},
};

static const struct itemplate instrux_VCVTUW2PH[3] = {
    /*   0 : VCVTUW2PH xmmreg|mask|z,xmmrm128|b16 [rm:fv:    evex.128.f2.map5.w0 7d /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 7f 08) 301 001(7d) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTUW2PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+46854, 566},
    /*   1 : VCVTUW2PH ymmreg|mask|z,ymmrm256|b16 [rm:fv:    evex.256.f2.map5.w0 7d /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 7f 28) 301 001(7d) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTUW2PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+46863, 566},
    /*   2 : VCVTUW2PH zmmreg|mask|z,zmmrm512|b16|er [rm:fv:    evex.512.f2.map5.w0 7d /r         ] AVX512FP16,FUTURE */
        /* 250(f5 7f 48) 301 001(7d) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTUW2PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+46872, 567},
};

static const struct itemplate instrux_VCVTW2PH[3] = {
    /*   0 : VCVTW2PH xmmreg|mask|z,xmmrm128|b16 [rm:fv:    evex.128.f3.map5.w0 7d /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 7e 08) 301 001(7d) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTW2PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+46881, 566},
    /*   1 : VCVTW2PH ymmreg|mask|z,ymmrm256|b16 [rm:fv:    evex.256.f3.map5.w0 7d /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 7e 28) 301 001(7d) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VCVTW2PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+46890, 566},
    /*   2 : VCVTW2PH zmmreg|mask|z,zmmrm512|b16|er [rm:fv:    evex.512.f3.map5.w0 7d /r         ] AVX512FP16,FUTURE */
        /* 250(f5 7e 48) 301 001(7d) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VCVTW2PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+46899, 567},
};

static const struct itemplate instrux_VDIVPH[6] = {
    /*   0 : VDIVPH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv:   evex.nds.128.np.map5 5e /r        ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f5 7c 08) 301 001(5e) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VDIVPH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+46908, 566},
    /*   1 : VDIVPH xmmreg|mask|z,xmmrm128|b16 [r+vm:fv:   evex.nds.128.np.map5 5e /r        ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f5 7c 08) 301 001(5e) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VDIVPH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+46917, 566},
    /*   2 : VDIVPH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv:   evex.nds.256.np.map5 5e /r        ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f5 7c 28) 301 001(5e) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VDIVPH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+46926, 566},
    /*   3 : VDIVPH ymmreg|mask|z,ymmrm256|b16 [r+vm:fv:   evex.nds.256.np.map5 5e /r        ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f5 7c 28) 301 001(5e) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VDIVPH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+46935, 566},
    /*   4 : VDIVPH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv:   evex.nds.512.np.map5 5e /r        ] AVX512FP16,FUTURE */
        /* 241(f5 7c 48) 301 001(5e) 120 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VDIVPH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+46944, 567},
    /*   5 : VDIVPH zmmreg|mask|z,zmmrm512|b16|er [r+vm:fv:   evex.nds.512.np.map5 5e /r        ] ND,AVX512FP16,FUTURE */
        /* 240(f5 7c 48) 301 001(5e) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VDIVPH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+46953, 567},
};

static const struct itemplate instrux_VDIVSH[2] = {
    /*   0 : VDIVSH xmmreg|mask|z,xmmreg*,xmmrm16|er [rvm:t1s:  evex.nds.lig.f3.map5 5e /r        ] AVX512FP16,FUTURE */
        /* 241(f5 7e 08) 306 001(5e) 120 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VDIVSH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+46962, 568},
    /*   1 : VDIVSH xmmreg|mask|z,xmmrm16|er [r+vm:t1s:  evex.nds.lig.f3.map5 5e /r        ] ND,AVX512FP16,FUTURE */
        /* 240(f5 7e 08) 306 001(5e) 110 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VDIVSH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+46971, 568},
};

static const struct itemplate instrux_VFCMADDCPH[6] = {
    /*   0 : VFCMADDCPH xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.nds.128.f2.map6.w0 56 /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7f 08) 301 001(56) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFCMADDCPH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+46980, 566},
    /*   1 : VFCMADDCPH xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.nds.128.f2.map6.w0 56 /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7f 08) 301 001(56) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFCMADDCPH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+46989, 566},
    /*   2 : VFCMADDCPH ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.nds.256.f2.map6.w0 56 /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7f 28) 301 001(56) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFCMADDCPH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+46998, 566},
    /*   3 : VFCMADDCPH ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.nds.256.f2.map6.w0 56 /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7f 28) 301 001(56) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFCMADDCPH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+47007, 566},
    /*   4 : VFCMADDCPH zmmreg|mask|z,zmmreg*,zmmrm512|b32|er [rvm:fv:   evex.nds.512.f2.map6.w0 56 /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7f 48) 301 001(56) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFCMADDCPH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+47016, 566},
    /*   5 : VFCMADDCPH zmmreg|mask|z,zmmrm512|b32|er [r+vm:fv:   evex.nds.512.f2.map6.w0 56 /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7f 48) 301 001(56) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFCMADDCPH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+47025, 566},
};

static const struct itemplate instrux_VFMADDCPH[6] = {
    /*   0 : VFMADDCPH xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.nds.128.f3.map6.w0 56 /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7e 08) 301 001(56) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMADDCPH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+47034, 566},
    /*   1 : VFMADDCPH xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.nds.128.f3.map6.w0 56 /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7e 08) 301 001(56) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMADDCPH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+47043, 566},
    /*   2 : VFMADDCPH ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.nds.256.f3.map6.w0 56 /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7e 28) 301 001(56) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMADDCPH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+47052, 566},
    /*   3 : VFMADDCPH ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.nds.256.f3.map6.w0 56 /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7e 28) 301 001(56) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMADDCPH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+47061, 566},
    /*   4 : VFMADDCPH zmmreg|mask|z,zmmreg*,zmmrm512|b32|er [rvm:fv:   evex.nds.512.f3.map6.w0 56 /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7e 48) 301 001(56) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMADDCPH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+47070, 566},
    /*   5 : VFMADDCPH zmmreg|mask|z,zmmrm512|b32|er [r+vm:fv:   evex.nds.512.f3.map6.w0 56 /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7e 48) 301 001(56) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMADDCPH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+47079, 566},
};

static const struct itemplate instrux_VFCMADDCSH[2] = {
    /*   0 : VFCMADDCSH xmmreg|mask|z,xmmreg*,xmmrm32|er [rvm:t1s:  evex.nds.lig.f2.map6.w0 57 /r     ] AVX512FP16,FUTURE */
        /* 241(f6 7f 08) 306 001(57) 120 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFCMADDCSH, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+47088, 568},
    /*   1 : VFCMADDCSH xmmreg|mask|z,xmmrm32|er [r+vm:t1s:  evex.nds.lig.f2.map6.w0 57 /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7f 08) 306 001(57) 110 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFCMADDCSH, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+47097, 568},
};

static const struct itemplate instrux_VFMADDCSH[2] = {
    /*   0 : VFMADDCSH xmmreg|mask|z,xmmreg*,xmmrm32|er [rvm:t1s:  evex.nds.lig.f3.map6.w0 57 /r     ] AVX512FP16,FUTURE */
        /* 241(f6 7e 08) 306 001(57) 120 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMADDCSH, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+47106, 568},
    /*   1 : VFMADDCSH xmmreg|mask|z,xmmrm32|er [r+vm:t1s:  evex.nds.lig.f3.map6.w0 57 /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7e 08) 306 001(57) 110 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMADDCSH, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+47115, 568},
};

static const struct itemplate instrux_VFCMULCPH[6] = {
    /*   0 : VFCMULCPH xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.nds.128.f2.map6.w0 d6 /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7f 08) 301 001(d6) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFCMULCPH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+47124, 566},
    /*   1 : VFCMULCPH xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.nds.128.f2.map6.w0 d6 /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7f 08) 301 001(d6) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFCMULCPH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+47133, 566},
    /*   2 : VFCMULCPH ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.nds.256.f2.map6.w0 d6 /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7f 28) 301 001(d6) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFCMULCPH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+47142, 566},
    /*   3 : VFCMULCPH ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.nds.256.f2.map6.w0 d6 /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7f 28) 301 001(d6) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFCMULCPH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+47151, 566},
    /*   4 : VFCMULCPH zmmreg|mask|z,zmmreg*,zmmrm512|b32|er [rvm:fv:   evex.nds.512.f2.map6.w0 d6 /r     ] AVX512FP16,FUTURE */
        /* 241(f6 7f 48) 301 001(d6) 120 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFCMULCPH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+47160, 567},
    /*   5 : VFCMULCPH zmmreg|mask|z,zmmrm512|b32|er [r+vm:fv:   evex.nds.512.f2.map6.w0 d6 /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7f 48) 301 001(d6) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFCMULCPH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+47169, 567},
};

static const struct itemplate instrux_VFMULCPH[6] = {
    /*   0 : VFMULCPH xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv:   evex.nds.128.f3.map6.w0 d6 /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7e 08) 301 001(d6) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMULCPH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+47178, 566},
    /*   1 : VFMULCPH xmmreg|mask|z,xmmrm128|b32 [r+vm:fv:   evex.nds.128.f3.map6.w0 d6 /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7e 08) 301 001(d6) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMULCPH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+47187, 566},
    /*   2 : VFMULCPH ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv:   evex.nds.256.f3.map6.w0 d6 /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7e 28) 301 001(d6) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMULCPH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+47196, 566},
    /*   3 : VFMULCPH ymmreg|mask|z,ymmrm256|b32 [r+vm:fv:   evex.nds.256.f3.map6.w0 d6 /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7e 28) 301 001(d6) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMULCPH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+47205, 566},
    /*   4 : VFMULCPH zmmreg|mask|z,zmmreg*,zmmrm512|b32|er [rvm:fv:   evex.nds.512.f3.map6.w0 d6 /r     ] AVX512FP16,FUTURE */
        /* 241(f6 7e 48) 301 001(d6) 120 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMULCPH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+47214, 567},
    /*   5 : VFMULCPH zmmreg|mask|z,zmmrm512|b32|er [r+vm:fv:   evex.nds.512.f3.map6.w0 d6 /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7e 48) 301 001(d6) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMULCPH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+47223, 567},
};

static const struct itemplate instrux_VFCMULCSH[2] = {
    /*   0 : VFCMULCSH xmmreg|mask|z,xmmreg*,xmmrm32|er [rvm:t1s:  evex.nds.lig.f2.map6.w0 d7 /r     ] AVX512FP16,FUTURE */
        /* 241(f6 7f 08) 306 001(d7) 120 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFCMULCSH, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+47232, 568},
    /*   1 : VFCMULCSH xmmreg|mask|z,xmmrm32|er [r+vm:t1s:  evex.nds.lig.f2.map6.w0 d7 /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7f 08) 306 001(d7) 110 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFCMULCSH, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+47241, 568},
};

static const struct itemplate instrux_VFMULCSH[2] = {
    /*   0 : VFMULCSH xmmreg|mask|z,xmmreg*,xmmrm32|er [rvm:t1s:  evex.nds.lig.f3.map6.w0 d7 /r     ] AVX512FP16,FUTURE */
        /* 241(f6 7e 08) 306 001(d7) 120 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMULCSH, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+47250, 568},
    /*   1 : VFMULCSH xmmreg|mask|z,xmmrm32|er [r+vm:t1s:  evex.nds.lig.f3.map6.w0 d7 /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7e 08) 306 001(d7) 110 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMULCSH, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+47259, 568},
};

static const struct itemplate instrux_VFMADDSUB132PH[6] = {
    /*   0 : VFMADDSUB132PH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv:   evex.nds.128.66.map6.w0 96 /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7d 08) 301 001(96) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMADDSUB132PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+47268, 566},
    /*   1 : VFMADDSUB132PH xmmreg|mask|z,xmmrm128|b16 [r+vm:fv:   evex.nds.128.66.map6.w0 96 /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7d 08) 301 001(96) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMADDSUB132PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+47277, 566},
    /*   2 : VFMADDSUB132PH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv:   evex.nds.256.66.map6.w0 96 /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7d 28) 301 001(96) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMADDSUB132PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+47286, 566},
    /*   3 : VFMADDSUB132PH ymmreg|mask|z,ymmrm256|b16 [r+vm:fv:   evex.nds.256.66.map6.w0 96 /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7d 28) 301 001(96) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMADDSUB132PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+47295, 566},
    /*   4 : VFMADDSUB132PH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv:   evex.nds.512.66.map6.w0 96 /r     ] AVX512FP16,FUTURE */
        /* 241(f6 7d 48) 301 001(96) 120 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMADDSUB132PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+47304, 567},
    /*   5 : VFMADDSUB132PH zmmreg|mask|z,zmmrm512|b16|er [r+vm:fv:   evex.nds.512.66.map6.w0 96 /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7d 48) 301 001(96) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMADDSUB132PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+47313, 567},
};

static const struct itemplate instrux_VFMADDSUB213PH[6] = {
    /*   0 : VFMADDSUB213PH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv:   evex.nds.128.66.map6.w0 a6 /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7d 08) 301 001(a6) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMADDSUB213PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+47322, 566},
    /*   1 : VFMADDSUB213PH xmmreg|mask|z,xmmrm128|b16 [r+vm:fv:   evex.nds.128.66.map6.w0 a6 /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7d 08) 301 001(a6) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMADDSUB213PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+47331, 566},
    /*   2 : VFMADDSUB213PH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv:   evex.nds.256.66.map6.w0 a6 /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7d 28) 301 001(a6) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMADDSUB213PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+47340, 566},
    /*   3 : VFMADDSUB213PH ymmreg|mask|z,ymmrm256|b16 [r+vm:fv:   evex.nds.256.66.map6.w0 a6 /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7d 28) 301 001(a6) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMADDSUB213PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+47349, 566},
    /*   4 : VFMADDSUB213PH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv:   evex.nds.512.66.map6.w0 a6 /r     ] AVX512FP16,FUTURE */
        /* 241(f6 7d 48) 301 001(a6) 120 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMADDSUB213PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+47358, 567},
    /*   5 : VFMADDSUB213PH zmmreg|mask|z,zmmrm512|b16|er [r+vm:fv:   evex.nds.512.66.map6.w0 a6 /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7d 48) 301 001(a6) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMADDSUB213PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+47367, 567},
};

static const struct itemplate instrux_VFMADDSUB231PH[6] = {
    /*   0 : VFMADDSUB231PH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv:   evex.nds.128.66.map6.w0 b6 /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7d 08) 301 001(b6) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMADDSUB231PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+47376, 566},
    /*   1 : VFMADDSUB231PH xmmreg|mask|z,xmmrm128|b16 [r+vm:fv:   evex.nds.128.66.map6.w0 b6 /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7d 08) 301 001(b6) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMADDSUB231PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+47385, 566},
    /*   2 : VFMADDSUB231PH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv:   evex.nds.256.66.map6.w0 b6 /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7d 28) 301 001(b6) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMADDSUB231PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+47394, 566},
    /*   3 : VFMADDSUB231PH ymmreg|mask|z,ymmrm256|b16 [r+vm:fv:   evex.nds.256.66.map6.w0 b6 /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7d 28) 301 001(b6) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMADDSUB231PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+47403, 566},
    /*   4 : VFMADDSUB231PH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv:   evex.nds.512.66.map6.w0 b6 /r     ] AVX512FP16,FUTURE */
        /* 241(f6 7d 48) 301 001(b6) 120 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMADDSUB231PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+47412, 567},
    /*   5 : VFMADDSUB231PH zmmreg|mask|z,zmmrm512|b16|er [r+vm:fv:   evex.nds.512.66.map6.w0 b6 /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7d 48) 301 001(b6) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMADDSUB231PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+47421, 567},
};

static const struct itemplate instrux_VFMSUBADD132PH[6] = {
    /*   0 : VFMSUBADD132PH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv:   evex.nds.128.66.map6.w0 97 /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7d 08) 301 001(97) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMSUBADD132PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+47430, 566},
    /*   1 : VFMSUBADD132PH xmmreg|mask|z,xmmrm128|b16 [r+vm:fv:   evex.nds.128.66.map6.w0 97 /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7d 08) 301 001(97) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMSUBADD132PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+47439, 566},
    /*   2 : VFMSUBADD132PH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv:   evex.nds.256.66.map6.w0 97 /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7d 28) 301 001(97) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMSUBADD132PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+47448, 566},
    /*   3 : VFMSUBADD132PH ymmreg|mask|z,ymmrm256|b16 [r+vm:fv:   evex.nds.256.66.map6.w0 97 /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7d 28) 301 001(97) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMSUBADD132PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+47457, 566},
    /*   4 : VFMSUBADD132PH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv:   evex.nds.512.66.map6.w0 97 /r     ] AVX512FP16,FUTURE */
        /* 241(f6 7d 48) 301 001(97) 120 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMSUBADD132PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+47466, 567},
    /*   5 : VFMSUBADD132PH zmmreg|mask|z,zmmrm512|b16|er [r+vm:fv:   evex.nds.512.66.map6.w0 97 /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7d 48) 301 001(97) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMSUBADD132PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+47475, 567},
};

static const struct itemplate instrux_VFMSUBADD213PH[6] = {
    /*   0 : VFMSUBADD213PH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv:   evex.nds.128.66.map6.w0 a7 /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7d 08) 301 001(a7) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMSUBADD213PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+47484, 566},
    /*   1 : VFMSUBADD213PH xmmreg|mask|z,xmmrm128|b16 [r+vm:fv:   evex.nds.128.66.map6.w0 a7 /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7d 08) 301 001(a7) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMSUBADD213PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+47493, 566},
    /*   2 : VFMSUBADD213PH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv:   evex.nds.256.66.map6.w0 a7 /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7d 28) 301 001(a7) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMSUBADD213PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+47502, 566},
    /*   3 : VFMSUBADD213PH ymmreg|mask|z,ymmrm256|b16 [r+vm:fv:   evex.nds.256.66.map6.w0 a7 /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7d 28) 301 001(a7) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMSUBADD213PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+47511, 566},
    /*   4 : VFMSUBADD213PH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv:   evex.nds.512.66.map6.w0 a7 /r     ] AVX512FP16,FUTURE */
        /* 241(f6 7d 48) 301 001(a7) 120 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMSUBADD213PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+47520, 567},
    /*   5 : VFMSUBADD213PH zmmreg|mask|z,zmmrm512|b16|er [r+vm:fv:   evex.nds.512.66.map6.w0 a7 /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7d 48) 301 001(a7) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMSUBADD213PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+47529, 567},
};

static const struct itemplate instrux_VFMSUBADD231PH[6] = {
    /*   0 : VFMSUBADD231PH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv:   evex.nds.128.66.map6.w0 b7 /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7d 08) 301 001(b7) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMSUBADD231PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+47538, 566},
    /*   1 : VFMSUBADD231PH xmmreg|mask|z,xmmrm128|b16 [r+vm:fv:   evex.nds.128.66.map6.w0 b7 /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7d 08) 301 001(b7) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMSUBADD231PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+47547, 566},
    /*   2 : VFMSUBADD231PH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv:   evex.nds.256.66.map6.w0 b7 /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7d 28) 301 001(b7) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMSUBADD231PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+47556, 566},
    /*   3 : VFMSUBADD231PH ymmreg|mask|z,ymmrm256|b16 [r+vm:fv:   evex.nds.256.66.map6.w0 b7 /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7d 28) 301 001(b7) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMSUBADD231PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+47565, 566},
    /*   4 : VFMSUBADD231PH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv:   evex.nds.512.66.map6.w0 b7 /r     ] AVX512FP16,FUTURE */
        /* 241(f6 7d 48) 301 001(b7) 120 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMSUBADD231PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+47574, 567},
    /*   5 : VFMSUBADD231PH zmmreg|mask|z,zmmrm512|b16|er [r+vm:fv:   evex.nds.512.66.map6.w0 b7 /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7d 48) 301 001(b7) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMSUBADD231PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+47583, 567},
};

static const struct itemplate instrux_VFMADD132PH[6] = {
    /*   0 : VFMADD132PH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv:   evex.nds.128.66.map6.w0 98 /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7d 08) 301 001(98) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMADD132PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+47592, 566},
    /*   1 : VFMADD132PH xmmreg|mask|z,xmmrm128|b16 [r+vm:fv:   evex.nds.128.66.map6.w0 98 /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7d 08) 301 001(98) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMADD132PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+47601, 566},
    /*   2 : VFMADD132PH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv:   evex.nds.256.66.map6.w0 98 /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7d 28) 301 001(98) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMADD132PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+47610, 566},
    /*   3 : VFMADD132PH ymmreg|mask|z,ymmrm256|b16 [r+vm:fv:   evex.nds.256.66.map6.w0 98 /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7d 28) 301 001(98) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMADD132PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+47619, 566},
    /*   4 : VFMADD132PH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv:   evex.nds.512.66.map6.w0 98 /r     ] AVX512FP16,FUTURE */
        /* 241(f6 7d 48) 301 001(98) 120 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMADD132PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+47628, 567},
    /*   5 : VFMADD132PH zmmreg|mask|z,zmmrm512|b16|er [r+vm:fv:   evex.nds.512.66.map6.w0 98 /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7d 48) 301 001(98) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMADD132PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+47637, 567},
};

static const struct itemplate instrux_VFMADD213PH[6] = {
    /*   0 : VFMADD213PH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv:   evex.nds.128.66.map6.w0 a8 /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7d 08) 301 001(a8) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMADD213PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+47646, 566},
    /*   1 : VFMADD213PH xmmreg|mask|z,xmmrm128|b16 [r+vm:fv:   evex.nds.128.66.map6.w0 a8 /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7d 08) 301 001(a8) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMADD213PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+47655, 566},
    /*   2 : VFMADD213PH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv:   evex.nds.256.66.map6.w0 a8 /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7d 28) 301 001(a8) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMADD213PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+47664, 566},
    /*   3 : VFMADD213PH ymmreg|mask|z,ymmrm256|b16 [r+vm:fv:   evex.nds.256.66.map6.w0 a8 /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7d 28) 301 001(a8) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMADD213PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+47673, 566},
    /*   4 : VFMADD213PH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv:   evex.nds.512.66.map6.w0 a8 /r     ] AVX512FP16,FUTURE */
        /* 241(f6 7d 48) 301 001(a8) 120 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMADD213PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+47682, 567},
    /*   5 : VFMADD213PH zmmreg|mask|z,zmmrm512|b16|er [r+vm:fv:   evex.nds.512.66.map6.w0 a8 /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7d 48) 301 001(a8) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMADD213PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+47691, 567},
};

static const struct itemplate instrux_VFMADD231PH[6] = {
    /*   0 : VFMADD231PH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv:   evex.nds.128.66.map6.w0 b8 /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7d 08) 301 001(b8) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMADD231PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+47700, 566},
    /*   1 : VFMADD231PH xmmreg|mask|z,xmmrm128|b16 [r+vm:fv:   evex.nds.128.66.map6.w0 b8 /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7d 08) 301 001(b8) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMADD231PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+47709, 566},
    /*   2 : VFMADD231PH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv:   evex.nds.256.66.map6.w0 b8 /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7d 28) 301 001(b8) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMADD231PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+47718, 566},
    /*   3 : VFMADD231PH ymmreg|mask|z,ymmrm256|b16 [r+vm:fv:   evex.nds.256.66.map6.w0 b8 /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7d 28) 301 001(b8) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMADD231PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+47727, 566},
    /*   4 : VFMADD231PH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv:   evex.nds.512.66.map6.w0 b8 /r     ] AVX512FP16,FUTURE */
        /* 241(f6 7d 48) 301 001(b8) 120 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMADD231PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+47736, 567},
    /*   5 : VFMADD231PH zmmreg|mask|z,zmmrm512|b16|er [r+vm:fv:   evex.nds.512.66.map6.w0 b8 /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7d 48) 301 001(b8) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMADD231PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+47745, 567},
};

static const struct itemplate instrux_VFNMADD132PH[6] = {
    /*   0 : VFNMADD132PH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv:   evex.nds.128.66.map6.w0 9c /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7d 08) 301 001(9c) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFNMADD132PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+47754, 566},
    /*   1 : VFNMADD132PH xmmreg|mask|z,xmmrm128|b16 [r+vm:fv:   evex.nds.128.66.map6.w0 9c /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7d 08) 301 001(9c) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFNMADD132PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+47763, 566},
    /*   2 : VFNMADD132PH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv:   evex.nds.256.66.map6.w0 9c /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7d 28) 301 001(9c) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFNMADD132PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+47772, 566},
    /*   3 : VFNMADD132PH ymmreg|mask|z,ymmrm256|b16 [r+vm:fv:   evex.nds.256.66.map6.w0 9c /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7d 28) 301 001(9c) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFNMADD132PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+47781, 566},
    /*   4 : VFNMADD132PH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv:   evex.nds.512.66.map6.w0 9c /r     ] AVX512FP16,FUTURE */
        /* 241(f6 7d 48) 301 001(9c) 120 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFNMADD132PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+47790, 567},
    /*   5 : VFNMADD132PH zmmreg|mask|z,zmmrm512|b16|er [r+vm:fv:   evex.nds.512.66.map6.w0 9c /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7d 48) 301 001(9c) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFNMADD132PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+47799, 567},
};

static const struct itemplate instrux_VFNMADD213PH[6] = {
    /*   0 : VFNMADD213PH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv:   evex.nds.128.66.map6.w0 ac /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7d 08) 301 001(ac) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFNMADD213PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+47808, 566},
    /*   1 : VFNMADD213PH xmmreg|mask|z,xmmrm128|b16 [r+vm:fv:   evex.nds.128.66.map6.w0 ac /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7d 08) 301 001(ac) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFNMADD213PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+47817, 566},
    /*   2 : VFNMADD213PH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv:   evex.nds.256.66.map6.w0 ac /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7d 28) 301 001(ac) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFNMADD213PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+47826, 566},
    /*   3 : VFNMADD213PH ymmreg|mask|z,ymmrm256|b16 [r+vm:fv:   evex.nds.256.66.map6.w0 ac /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7d 28) 301 001(ac) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFNMADD213PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+47835, 566},
    /*   4 : VFNMADD213PH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv:   evex.nds.512.66.map6.w0 ac /r     ] AVX512FP16,FUTURE */
        /* 241(f6 7d 48) 301 001(ac) 120 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFNMADD213PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+47844, 567},
    /*   5 : VFNMADD213PH zmmreg|mask|z,zmmrm512|b16|er [r+vm:fv:   evex.nds.512.66.map6.w0 ac /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7d 48) 301 001(ac) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFNMADD213PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+47853, 567},
};

static const struct itemplate instrux_VFNMADD231PH[6] = {
    /*   0 : VFNMADD231PH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv:   evex.nds.128.66.map6.w0 bc /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7d 08) 301 001(bc) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFNMADD231PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+47862, 566},
    /*   1 : VFNMADD231PH xmmreg|mask|z,xmmrm128|b16 [r+vm:fv:   evex.nds.128.66.map6.w0 bc /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7d 08) 301 001(bc) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFNMADD231PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+47871, 566},
    /*   2 : VFNMADD231PH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv:   evex.nds.256.66.map6.w0 bc /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7d 28) 301 001(bc) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFNMADD231PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+47880, 566},
    /*   3 : VFNMADD231PH ymmreg|mask|z,ymmrm256|b16 [r+vm:fv:   evex.nds.256.66.map6.w0 bc /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7d 28) 301 001(bc) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFNMADD231PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+47889, 566},
    /*   4 : VFNMADD231PH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv:   evex.nds.512.66.map6.w0 bc /r     ] AVX512FP16,FUTURE */
        /* 241(f6 7d 48) 301 001(bc) 120 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFNMADD231PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+47898, 567},
    /*   5 : VFNMADD231PH zmmreg|mask|z,zmmrm512|b16|er [r+vm:fv:   evex.nds.512.66.map6.w0 bc /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7d 48) 301 001(bc) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFNMADD231PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+47907, 567},
};

static const struct itemplate instrux_VFMADD132SH[2] = {
    /*   0 : VFMADD132SH xmmreg|mask|z,xmmreg*,xmmrm16|er [rvm:t1s:  evex.nds.lig.66.map6.w0 99 /r     ] AVX512FP16,FUTURE */
        /* 241(f6 7d 08) 306 001(99) 120 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMADD132SH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+47916, 568},
    /*   1 : VFMADD132SH xmmreg|mask|z,xmmrm16|er [r+vm:t1s:  evex.nds.lig.66.map6.w0 99 /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7d 08) 306 001(99) 110 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMADD132SH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+47925, 568},
};

static const struct itemplate instrux_VFMADD213SH[2] = {
    /*   0 : VFMADD213SH xmmreg|mask|z,xmmreg*,xmmrm16|er [rvm:t1s:  evex.nds.lig.66.map6.w0 a9 /r     ] AVX512FP16,FUTURE */
        /* 241(f6 7d 08) 306 001(a9) 120 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMADD213SH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+47934, 568},
    /*   1 : VFMADD213SH xmmreg|mask|z,xmmrm16|er [r+vm:t1s:  evex.nds.lig.66.map6.w0 a9 /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7d 08) 306 001(a9) 110 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMADD213SH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+47943, 568},
};

static const struct itemplate instrux_VFMADD231SH[2] = {
    /*   0 : VFMADD231SH xmmreg|mask|z,xmmreg*,xmmrm16|er [rvm:t1s:  evex.nds.lig.66.map6.w0 b9 /r     ] AVX512FP16,FUTURE */
        /* 241(f6 7d 08) 306 001(b9) 120 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMADD231SH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+47952, 568},
    /*   1 : VFMADD231SH xmmreg|mask|z,xmmrm16|er [r+vm:t1s:  evex.nds.lig.66.map6.w0 b9 /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7d 08) 306 001(b9) 110 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMADD231SH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+47961, 568},
};

static const struct itemplate instrux_VFNMADD132SH[2] = {
    /*   0 : VFNMADD132SH xmmreg|mask|z,xmmreg*,xmmrm16|er [rvm:t1s:  evex.nds.lig.66.map6.w0 9d /r     ] AVX512FP16,FUTURE */
        /* 241(f6 7d 08) 306 001(9d) 120 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFNMADD132SH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+47970, 568},
    /*   1 : VFNMADD132SH xmmreg|mask|z,xmmrm16|er [r+vm:t1s:  evex.nds.lig.66.map6.w0 9d /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7d 08) 306 001(9d) 110 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFNMADD132SH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+47979, 568},
};

static const struct itemplate instrux_VFNMADD213SH[2] = {
    /*   0 : VFNMADD213SH xmmreg|mask|z,xmmreg*,xmmrm16|er [rvm:t1s:  evex.nds.lig.66.map6.w0 ad /r     ] AVX512FP16,FUTURE */
        /* 241(f6 7d 08) 306 001(ad) 120 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFNMADD213SH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+47988, 568},
    /*   1 : VFNMADD213SH xmmreg|mask|z,xmmrm16|er [r+vm:t1s:  evex.nds.lig.66.map6.w0 ad /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7d 08) 306 001(ad) 110 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFNMADD213SH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+47997, 568},
};

static const struct itemplate instrux_VFNMADD231SH[2] = {
    /*   0 : VFNMADD231SH xmmreg|mask|z,xmmreg*,xmmrm16|er [rvm:t1s:  evex.nds.lig.66.map6.w0 bd /r     ] AVX512FP16,FUTURE */
        /* 241(f6 7d 08) 306 001(bd) 120 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFNMADD231SH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+48006, 568},
    /*   1 : VFNMADD231SH xmmreg|mask|z,xmmrm16|er [r+vm:t1s:  evex.nds.lig.66.map6.w0 bd /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7d 08) 306 001(bd) 110 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFNMADD231SH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+48015, 568},
};

static const struct itemplate instrux_VFMSUB132PH[6] = {
    /*   0 : VFMSUB132PH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv:   evex.nds.128.66.map6.w0 9a /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7d 08) 301 001(9a) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMSUB132PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+48024, 566},
    /*   1 : VFMSUB132PH xmmreg|mask|z,xmmrm128|b16 [r+vm:fv:   evex.nds.128.66.map6.w0 9a /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7d 08) 301 001(9a) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMSUB132PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+48033, 566},
    /*   2 : VFMSUB132PH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv:   evex.nds.256.66.map6.w0 9a /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7d 28) 301 001(9a) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMSUB132PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+48042, 566},
    /*   3 : VFMSUB132PH ymmreg|mask|z,ymmrm256|b16 [r+vm:fv:   evex.nds.256.66.map6.w0 9a /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7d 28) 301 001(9a) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMSUB132PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+48051, 566},
    /*   4 : VFMSUB132PH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv:   evex.nds.512.66.map6.w0 9a /r     ] AVX512FP16,FUTURE */
        /* 241(f6 7d 48) 301 001(9a) 120 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMSUB132PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+48060, 567},
    /*   5 : VFMSUB132PH zmmreg|mask|z,zmmrm512|b16|er [r+vm:fv:   evex.nds.512.66.map6.w0 9a /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7d 48) 301 001(9a) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMSUB132PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+48069, 567},
};

static const struct itemplate instrux_VFMSUB213PH[6] = {
    /*   0 : VFMSUB213PH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv:   evex.nds.128.66.map6.w0 aa /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7d 08) 301 001(aa) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMSUB213PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+48078, 566},
    /*   1 : VFMSUB213PH xmmreg|mask|z,xmmrm128|b16 [r+vm:fv:   evex.nds.128.66.map6.w0 aa /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7d 08) 301 001(aa) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMSUB213PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+48087, 566},
    /*   2 : VFMSUB213PH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv:   evex.nds.256.66.map6.w0 aa /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7d 28) 301 001(aa) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMSUB213PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+48096, 566},
    /*   3 : VFMSUB213PH ymmreg|mask|z,ymmrm256|b16 [r+vm:fv:   evex.nds.256.66.map6.w0 aa /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7d 28) 301 001(aa) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMSUB213PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+48105, 566},
    /*   4 : VFMSUB213PH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv:   evex.nds.512.66.map6.w0 aa /r     ] AVX512FP16,FUTURE */
        /* 241(f6 7d 48) 301 001(aa) 120 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMSUB213PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+48114, 567},
    /*   5 : VFMSUB213PH zmmreg|mask|z,zmmrm512|b16|er [r+vm:fv:   evex.nds.512.66.map6.w0 aa /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7d 48) 301 001(aa) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMSUB213PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+48123, 567},
};

static const struct itemplate instrux_VFMSUB231PH[6] = {
    /*   0 : VFMSUB231PH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv:   evex.nds.128.66.map6.w0 ba /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7d 08) 301 001(ba) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMSUB231PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+48132, 566},
    /*   1 : VFMSUB231PH xmmreg|mask|z,xmmrm128|b16 [r+vm:fv:   evex.nds.128.66.map6.w0 ba /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7d 08) 301 001(ba) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMSUB231PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+48141, 566},
    /*   2 : VFMSUB231PH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv:   evex.nds.256.66.map6.w0 ba /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7d 28) 301 001(ba) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMSUB231PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+48150, 566},
    /*   3 : VFMSUB231PH ymmreg|mask|z,ymmrm256|b16 [r+vm:fv:   evex.nds.256.66.map6.w0 ba /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7d 28) 301 001(ba) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFMSUB231PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+48159, 566},
    /*   4 : VFMSUB231PH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv:   evex.nds.512.66.map6.w0 ba /r     ] AVX512FP16,FUTURE */
        /* 241(f6 7d 48) 301 001(ba) 120 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMSUB231PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+48168, 567},
    /*   5 : VFMSUB231PH zmmreg|mask|z,zmmrm512|b16|er [r+vm:fv:   evex.nds.512.66.map6.w0 ba /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7d 48) 301 001(ba) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMSUB231PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+48177, 567},
};

static const struct itemplate instrux_VFNMSUB132PH[6] = {
    /*   0 : VFNMSUB132PH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv:   evex.nds.128.66.map6.w0 9e /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7d 08) 301 001(9e) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFNMSUB132PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+48186, 566},
    /*   1 : VFNMSUB132PH xmmreg|mask|z,xmmrm128|b16 [r+vm:fv:   evex.nds.128.66.map6.w0 9e /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7d 08) 301 001(9e) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFNMSUB132PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+48195, 566},
    /*   2 : VFNMSUB132PH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv:   evex.nds.256.66.map6.w0 9e /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7d 28) 301 001(9e) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFNMSUB132PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+48204, 566},
    /*   3 : VFNMSUB132PH ymmreg|mask|z,ymmrm256|b16 [r+vm:fv:   evex.nds.256.66.map6.w0 9e /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7d 28) 301 001(9e) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFNMSUB132PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+48213, 566},
    /*   4 : VFNMSUB132PH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv:   evex.nds.512.66.map6.w0 9e /r     ] AVX512FP16,FUTURE */
        /* 241(f6 7d 48) 301 001(9e) 120 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFNMSUB132PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+48222, 567},
    /*   5 : VFNMSUB132PH zmmreg|mask|z,zmmrm512|b16|er [r+vm:fv:   evex.nds.512.66.map6.w0 9e /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7d 48) 301 001(9e) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFNMSUB132PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+48231, 567},
};

static const struct itemplate instrux_VFNMSUB213PH[6] = {
    /*   0 : VFNMSUB213PH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv:   evex.nds.128.66.map6.w0 ae /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7d 08) 301 001(ae) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFNMSUB213PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+48240, 566},
    /*   1 : VFNMSUB213PH xmmreg|mask|z,xmmrm128|b16 [r+vm:fv:   evex.nds.128.66.map6.w0 ae /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7d 08) 301 001(ae) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFNMSUB213PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+48249, 566},
    /*   2 : VFNMSUB213PH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv:   evex.nds.256.66.map6.w0 ae /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7d 28) 301 001(ae) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFNMSUB213PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+48258, 566},
    /*   3 : VFNMSUB213PH ymmreg|mask|z,ymmrm256|b16 [r+vm:fv:   evex.nds.256.66.map6.w0 ae /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7d 28) 301 001(ae) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFNMSUB213PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+48267, 566},
    /*   4 : VFNMSUB213PH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv:   evex.nds.512.66.map6.w0 ae /r     ] AVX512FP16,FUTURE */
        /* 241(f6 7d 48) 301 001(ae) 120 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFNMSUB213PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+48276, 567},
    /*   5 : VFNMSUB213PH zmmreg|mask|z,zmmrm512|b16|er [r+vm:fv:   evex.nds.512.66.map6.w0 ae /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7d 48) 301 001(ae) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFNMSUB213PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+48285, 567},
};

static const struct itemplate instrux_VFNMSUB231PH[6] = {
    /*   0 : VFNMSUB231PH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv:   evex.nds.128.66.map6.w0 be /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7d 08) 301 001(be) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFNMSUB231PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+48294, 566},
    /*   1 : VFNMSUB231PH xmmreg|mask|z,xmmrm128|b16 [r+vm:fv:   evex.nds.128.66.map6.w0 be /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7d 08) 301 001(be) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFNMSUB231PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+48303, 566},
    /*   2 : VFNMSUB231PH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv:   evex.nds.256.66.map6.w0 be /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7d 28) 301 001(be) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFNMSUB231PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+48312, 566},
    /*   3 : VFNMSUB231PH ymmreg|mask|z,ymmrm256|b16 [r+vm:fv:   evex.nds.256.66.map6.w0 be /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7d 28) 301 001(be) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFNMSUB231PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+48321, 566},
    /*   4 : VFNMSUB231PH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv:   evex.nds.512.66.map6.w0 be /r     ] AVX512FP16,FUTURE */
        /* 241(f6 7d 48) 301 001(be) 120 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFNMSUB231PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+48330, 567},
    /*   5 : VFNMSUB231PH zmmreg|mask|z,zmmrm512|b16|er [r+vm:fv:   evex.nds.512.66.map6.w0 be /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7d 48) 301 001(be) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFNMSUB231PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+48339, 567},
};

static const struct itemplate instrux_VFMSUB132SH[2] = {
    /*   0 : VFMSUB132SH xmmreg|mask|z,xmmreg*,xmmrm16|er [rvm:t1s:  evex.nds.lig.66.map6.w0 9b /r     ] AVX512FP16,FUTURE */
        /* 241(f6 7d 08) 306 001(9b) 120 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMSUB132SH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+48348, 568},
    /*   1 : VFMSUB132SH xmmreg|mask|z,xmmrm16|er [r+vm:t1s:  evex.nds.lig.66.map6.w0 9b /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7d 08) 306 001(9b) 110 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMSUB132SH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+48357, 568},
};

static const struct itemplate instrux_VFMSUB213SH[2] = {
    /*   0 : VFMSUB213SH xmmreg|mask|z,xmmreg*,xmmrm16|er [rvm:t1s:  evex.nds.lig.66.map6.w0 ab /r     ] AVX512FP16,FUTURE */
        /* 241(f6 7d 08) 306 001(ab) 120 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMSUB213SH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+48366, 568},
    /*   1 : VFMSUB213SH xmmreg|mask|z,xmmrm16|er [r+vm:t1s:  evex.nds.lig.66.map6.w0 ab /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7d 08) 306 001(ab) 110 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMSUB213SH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+48375, 568},
};

static const struct itemplate instrux_VFMSUB231SH[2] = {
    /*   0 : VFMSUB231SH xmmreg|mask|z,xmmreg*,xmmrm16|er [rvm:t1s:  evex.nds.lig.66.map6.w0 bb /r     ] AVX512FP16,FUTURE */
        /* 241(f6 7d 08) 306 001(bb) 120 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMSUB231SH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+48384, 568},
    /*   1 : VFMSUB231SH xmmreg|mask|z,xmmrm16|er [r+vm:t1s:  evex.nds.lig.66.map6.w0 bb /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7d 08) 306 001(bb) 110 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFMSUB231SH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+48393, 568},
};

static const struct itemplate instrux_VFNMSUB132SH[2] = {
    /*   0 : VFNMSUB132SH xmmreg|mask|z,xmmreg*,xmmrm16|er [rvm:t1s:  evex.nds.lig.66.map6.w0 9f /r     ] AVX512FP16,FUTURE */
        /* 241(f6 7d 08) 306 001(9f) 120 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFNMSUB132SH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+48402, 568},
    /*   1 : VFNMSUB132SH xmmreg|mask|z,xmmrm16|er [r+vm:t1s:  evex.nds.lig.66.map6.w0 9f /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7d 08) 306 001(9f) 110 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFNMSUB132SH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+48411, 568},
};

static const struct itemplate instrux_VFNMSUB213SH[2] = {
    /*   0 : VFNMSUB213SH xmmreg|mask|z,xmmreg*,xmmrm16|er [rvm:t1s:  evex.nds.lig.66.map6.w0 af /r     ] AVX512FP16,FUTURE */
        /* 241(f6 7d 08) 306 001(af) 120 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFNMSUB213SH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+48420, 568},
    /*   1 : VFNMSUB213SH xmmreg|mask|z,xmmrm16|er [r+vm:t1s:  evex.nds.lig.66.map6.w0 af /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7d 08) 306 001(af) 110 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFNMSUB213SH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+48429, 568},
};

static const struct itemplate instrux_VFNMSUB231SH[2] = {
    /*   0 : VFNMSUB231SH xmmreg|mask|z,xmmreg*,xmmrm16|er [rvm:t1s:  evex.nds.lig.66.map6.w0 bf /r     ] AVX512FP16,FUTURE */
        /* 241(f6 7d 08) 306 001(bf) 120 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFNMSUB231SH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+48438, 568},
    /*   1 : VFNMSUB231SH xmmreg|mask|z,xmmrm16|er [r+vm:t1s:  evex.nds.lig.66.map6.w0 bf /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7d 08) 306 001(bf) 110 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFNMSUB231SH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+48447, 568},
};

static const struct itemplate instrux_VFPCLASSPH[3] = {
    /*   0 : VFPCLASSPH kreg|mask,xmmrm128|b16,imm8 [rmi:fv:   evex.128.np.0f3a.w0 66 /r ib      ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f3 7c 08) 301 001(66) 110 022 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFPCLASSPH, 3, {OPMASKREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK,B16,0,0,0}, nasm_bytecodes+22783, 566},
    /*   1 : VFPCLASSPH kreg|mask,ymmrm256|b16,imm8 [rmi:fv:   evex.256.np.0f3a.w0 66 /r ib      ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f3 7c 28) 301 001(66) 110 022 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VFPCLASSPH, 3, {OPMASKREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK,B16,0,0,0}, nasm_bytecodes+22793, 566},
    /*   2 : VFPCLASSPH kreg|mask,zmmrm512|b16,imm8 [rmi:fv:   evex.512.np.0f3a.w0 66 /r ib      ] AVX512FP16,FUTURE */
        /* 250(f3 7c 48) 301 001(66) 110 022 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFPCLASSPH, 3, {OPMASKREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK,B16,0,0,0}, nasm_bytecodes+22803, 567},
};

static const struct itemplate instrux_VFPCLASSSH[1] = {
    /*   0 : VFPCLASSSH kreg|mask,xmmrm16,imm8 [rmi:t1s:  evex.lig.np.0f3a.w0 67 /r ib      ] AVX512FP16,FUTURE */
        /* 250(f3 7c 08) 306 001(67) 110 022 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VFPCLASSSH, 3, {OPMASKREG,RM_XMM|BITS16,IMM_NORMAL|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+22813, 568},
};

static const struct itemplate instrux_VGETEXPPH[3] = {
    /*   0 : VGETEXPPH xmmreg|mask|z,xmmrm128|b16 [rm:fv:    evex.128.66.map6.w0 42 /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f6 7d 08) 301 001(42) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VGETEXPPH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+48456, 566},
    /*   1 : VGETEXPPH ymmreg|mask|z,ymmrm256|b16 [rm:fv:    evex.256.66.map6.w0 42 /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f6 7d 28) 301 001(42) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VGETEXPPH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+48465, 566},
    /*   2 : VGETEXPPH zmmreg|mask|z,zmmrm512|b16|sae [rm:fv:    evex.512.66.map6.w0 42 /r         ] AVX512FP16,FUTURE */
        /* 250(f6 7d 48) 301 001(42) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VGETEXPPH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+48474, 567},
};

static const struct itemplate instrux_VGETEXPSH[1] = {
    /*   0 : VGETEXPSH xmmreg|mask|z,xmmrm16|sae [rm:t1s:   evex.128.66.map6.w0 43 /r         ] AVX512FP16,FUTURE */
        /* 250(f6 7d 08) 306 001(43) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VGETEXPSH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+48483, 567},
};

static const struct itemplate instrux_VGETMANTPH[3] = {
    /*   0 : VGETMANTPH xmmreg|mask|z,xmmrm128|b16,imm8 [rmi:fv:   evex.128.np.0f3a.w0 26 /r ib      ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f3 7c 08) 301 001(26) 110 022 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VGETMANTPH, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+22823, 566},
    /*   1 : VGETMANTPH ymmreg|mask|z,ymmrm256|b16,imm8 [rmi:fv:   evex.256.np.0f3a.w0 26 /r ib      ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f3 7c 28) 301 001(26) 110 022 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VGETMANTPH, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+22833, 566},
    /*   2 : VGETMANTPH zmmreg|mask|z,zmmrm512|b16|sae,imm8 [rmi:fv:   evex.512.np.0f3a.w0 26 /r ib      ] AVX512FP16,FUTURE */
        /* 250(f3 7c 48) 301 001(26) 110 022 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VGETMANTPH, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+22843, 567},
};

static const struct itemplate instrux_VGETMANTSH[1] = {
    /*   0 : VGETMANTSH xmmreg|mask|z,xmmrm16|sae,imm8 [rmi:t1s:  evex.128.np.0f3a.w0 27 /r ib      ] AVX512FP16,FUTURE */
        /* 250(f3 7c 08) 306 001(27) 110 022 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VGETMANTSH, 3, {XMMREG,RM_XMM|BITS16,IMM_NORMAL|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+22853, 567},
};

static const struct itemplate instrux_VMAXPH[6] = {
    /*   0 : VMAXPH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv:   evex.128.np.map5.w0 5f /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f5 7c 08) 301 001(5f) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VMAXPH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+48492, 566},
    /*   1 : VMAXPH xmmreg|mask|z,xmmrm128|b16 [r+vm:fv:   evex.128.np.map5.w0 5f /r         ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f5 7c 08) 301 001(5f) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VMAXPH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+48501, 566},
    /*   2 : VMAXPH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv:   evex.256.np.map5.w0 5f /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f5 7c 28) 301 001(5f) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VMAXPH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+48510, 566},
    /*   3 : VMAXPH ymmreg|mask|z,ymmrm256|b16 [r+vm:fv:   evex.256.np.map5.w0 5f /r         ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f5 7c 28) 301 001(5f) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VMAXPH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+48519, 566},
    /*   4 : VMAXPH zmmreg|mask|z,zmmreg*,zmmrm512|b16|sae [rvm:fv:   evex.512.np.map5.w0 5f /r         ] AVX512FP16,FUTURE */
        /* 241(f5 7c 48) 301 001(5f) 120 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VMAXPH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|SAE,0,0}, nasm_bytecodes+48528, 567},
    /*   5 : VMAXPH zmmreg|mask|z,zmmrm512|b16|sae [r+vm:fv:   evex.512.np.map5.w0 5f /r         ] ND,AVX512FP16,FUTURE */
        /* 240(f5 7c 48) 301 001(5f) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VMAXPH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+48537, 567},
};

static const struct itemplate instrux_VMAXSH[1] = {
    /*   0 : VMAXSH xmmreg|mask|z,xmmreg,xmmrm16|sae [rvm:t1s:  evex.lig.f3.map5.w0 5f /r         ] AVX512FP16,FUTURE */
        /* 241(f5 7e 08) 306 001(5f) 120 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VMAXSH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+48546, 568},
};

static const struct itemplate instrux_VMINPH[6] = {
    /*   0 : VMINPH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv:   evex.128.np.map5.w0 5d /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f5 7c 08) 301 001(5d) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VMINPH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+48555, 566},
    /*   1 : VMINPH xmmreg|mask|z,xmmrm128|b16 [r+vm:fv:   evex.128.np.map5.w0 5d /r         ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f5 7c 08) 301 001(5d) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VMINPH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+48564, 566},
    /*   2 : VMINPH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv:   evex.256.np.map5.w0 5d /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f5 7c 28) 301 001(5d) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VMINPH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+48573, 566},
    /*   3 : VMINPH ymmreg|mask|z,ymmrm256|b16 [r+vm:fv:   evex.256.np.map5.w0 5d /r         ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f5 7c 28) 301 001(5d) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VMINPH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+48582, 566},
    /*   4 : VMINPH zmmreg|mask|z,zmmreg*,zmmrm512|b16|sae [rvm:fv:   evex.512.np.map5.w0 5d /r         ] AVX512FP16,FUTURE */
        /* 241(f5 7c 48) 301 001(5d) 120 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VMINPH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|SAE,0,0}, nasm_bytecodes+48591, 567},
    /*   5 : VMINPH zmmreg|mask|z,zmmrm512|b16|sae [r+vm:fv:   evex.512.np.map5.w0 5d /r         ] ND,AVX512FP16,FUTURE */
        /* 240(f5 7c 48) 301 001(5d) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VMINPH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+48600, 567},
};

static const struct itemplate instrux_VMINSH[1] = {
    /*   0 : VMINSH xmmreg|mask|z,xmmreg,xmmrm16|sae [rvm:t1s:  evex.lig.f3.map5.w0 5d /r         ] AVX512FP16,FUTURE */
        /* 241(f5 7e 08) 306 001(5d) 120 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VMINSH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+48609, 568},
};

static const struct itemplate instrux_VMOVSH[6] = {
    /*   0 : VMOVSH xmmreg|mask|z,mem16 [rm:t1s:   evex.lig.f3.map5.w0 10 /r         ] AVX512FP16,FUTURE */
        /* 250(f5 7e 08) 306 001(10) 110 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VMOVSH, 2, {XMMREG,MEMORY|BITS16,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+48618, 568},
    /*   1 : VMOVSH mem16|mask,xmmreg [mr:t1s:   evex.lig.f3.map5.w0 11 /r         ] AVX512FP16,FUTURE */
        /* 250(f5 7e 08) 306 001(11) 101 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VMOVSH, 2, {MEMORY|BITS16,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+48627, 568},
    /*   2 : VMOVSH xmmreg|mask|z,xmmreg*,xmmreg [rvm:      evex.nds.lig.f3.map5.w0 10 /r     ] AVX512FP16,FUTURE */
        /* 241(f5 7e 08) 300 001(10) 120 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VMOVSH, 3, {XMMREG,XMMREG,XMMREG,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+48636, 568},
    /*   3 : VMOVSH xmmreg|mask|z,xmmreg [r+vm:      evex.nds.lig.f3.map5.w0 10 /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f5 7e 08) 300 001(10) 110 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VMOVSH, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+48645, 568},
    /*   4 : VMOVSH xmmreg|mask|z,xmmreg*,xmmreg [rvm:      evex.nds.lig.f3.map5.w0 11 /r     ] AVX512FP16,FUTURE */
        /* 241(f5 7e 08) 300 001(11) 120 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VMOVSH, 3, {XMMREG,XMMREG,XMMREG,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+48654, 568},
    /*   5 : VMOVSH xmmreg|mask|z,xmmreg [r+vm:      evex.nds.lig.f3.map5.w0 11 /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f5 7e 08) 300 001(11) 110 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VMOVSH, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+48663, 568},
};

static const struct itemplate instrux_VMOVW[4] = {
    /*   0 : VMOVW xmmreg|mask|z,rm16 [rm:t1s:   evex.128.66.map5.wig 6e /r        ] AVX512FP16,FUTURE */
        /* 250(f5 7d 08) 306 001(6e) 110 : WIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VMOVW, 2, {XMMREG,RM_GPR|BITS16,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+48672, 637},
    /*   1 : VMOVW rm16,xmmreg [mr:t1s:   evex.128.66.map5.wig 7e /r        ] AVX512FP16,FUTURE */
        /* 250(f5 7d 08) 306 001(7e) 101 : WIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VMOVW, 2, {RM_GPR|BITS16,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+48681, 637},
    /*   2 : VMOVW xmmreg,xmmrm16 [rm:t1s:   evex.128.f3.map5.w0 6e /r         ] AVX10_2,FUTURE */
        /* 250(f5 7e 08) 306 001(6e) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VMOVW, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+51075, 645},
    /*   3 : VMOVW xmmrm16,xmmreg [mr:t1s:   evex.128.f3.map5.w0 7e /r         ] AVX10_2,FUTURE */
        /* 250(f5 7e 08) 306 001(7e) 101 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VMOVW, 2, {RM_XMM|BITS16,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+51084, 645},
};

static const struct itemplate instrux_VMULPH[6] = {
    /*   0 : VMULPH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv:   evex.nds.128.np.map5.w0 59 /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f5 7c 08) 301 001(59) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VMULPH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+48690, 566},
    /*   1 : VMULPH xmmreg|mask|z,xmmrm128|b16 [r+vm:fv:   evex.nds.128.np.map5.w0 59 /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f5 7c 08) 301 001(59) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VMULPH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+48699, 566},
    /*   2 : VMULPH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv:   evex.nds.256.np.map5.w0 59 /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f5 7c 28) 301 001(59) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VMULPH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+48708, 566},
    /*   3 : VMULPH ymmreg|mask|z,ymmrm256|b16 [r+vm:fv:   evex.nds.256.np.map5.w0 59 /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f5 7c 28) 301 001(59) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VMULPH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+48717, 566},
    /*   4 : VMULPH zmmreg|mask|z,zmmreg*,zmmrm512|b16 [rvm:fv:   evex.nds.512.np.map5.w0 59 /r     ] AVX512FP16,FUTURE */
        /* 241(f5 7c 48) 301 001(59) 120 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VMULPH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+48726, 567},
    /*   5 : VMULPH zmmreg|mask|z,zmmrm512|b16 [r+vm:fv:   evex.nds.512.np.map5.w0 59 /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f5 7c 48) 301 001(59) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VMULPH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+48735, 567},
};

static const struct itemplate instrux_VMULSH[2] = {
    /*   0 : VMULSH xmmreg|mask|z,xmmreg*,xmmrm16|er [rvm:t1s:  evex.nds.lig.f3.map5.w0 59 /r     ] AVX512FP16,FUTURE */
        /* 241(f5 7e 08) 306 001(59) 120 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VMULSH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+48744, 568},
    /*   1 : VMULSH xmmreg|mask|z,xmmrm16|er [r+vm:t1s:  evex.nds.lig.f3.map5.w0 59 /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f5 7e 08) 306 001(59) 110 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VMULSH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+48753, 568},
};

static const struct itemplate instrux_VRCPPH[6] = {
    /*   0 : VRCPPH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv:   evex.nds.128.66.map6.w0 4c /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7d 08) 301 001(4c) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VRCPPH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+48762, 566},
    /*   1 : VRCPPH xmmreg|mask|z,xmmrm128|b16 [r+vm:fv:   evex.nds.128.66.map6.w0 4c /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7d 08) 301 001(4c) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VRCPPH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+48771, 566},
    /*   2 : VRCPPH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv:   evex.nds.256.66.map6.w0 4c /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7d 28) 301 001(4c) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VRCPPH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+48780, 566},
    /*   3 : VRCPPH ymmreg|mask|z,ymmrm256|b16 [r+vm:fv:   evex.nds.256.66.map6.w0 4c /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7d 28) 301 001(4c) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VRCPPH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+48789, 566},
    /*   4 : VRCPPH zmmreg|mask|z,zmmreg*,zmmrm512|b16 [rvm:fv:   evex.nds.512.66.map6.w0 4c /r     ] AVX512FP16,FUTURE */
        /* 241(f6 7d 48) 301 001(4c) 120 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VRCPPH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+48798, 567},
    /*   5 : VRCPPH zmmreg|mask|z,zmmrm512|b16 [r+vm:fv:   evex.nds.512.66.map6.w0 4c /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7d 48) 301 001(4c) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VRCPPH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+48807, 567},
};

static const struct itemplate instrux_VRCPSH[2] = {
    /*   0 : VRCPSH xmmreg|mask|z,xmmreg*,xmmrm16|sae [rvm:t1s:  evex.nds.lig.66.map6.w0 4d /r     ] AVX512FP16,FUTURE */
        /* 241(f6 7d 08) 306 001(4d) 120 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VRCPSH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+48816, 568},
    /*   1 : VRCPSH xmmreg|mask|z,xmmrm16|sae [r+vm:t1s:  evex.nds.lig.66.map6.w0 4d /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7d 08) 306 001(4d) 110 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VRCPSH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+48825, 568},
};

static const struct itemplate instrux_VREDUCEPH[3] = {
    /*   0 : VREDUCEPH xmmreg|mask|z,xmmrm128|b16,imm8 [rmi:fv:   evex.128.np.0f3a.w0 56 /r ib      ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f3 7c 08) 301 001(56) 110 022 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VREDUCEPH, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+22863, 566},
    /*   1 : VREDUCEPH ymmreg|mask|z,ymmrm256|b16,imm8 [rmi:fv:   evex.256.np.0f3a.w0 56 /r ib      ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f3 7c 28) 301 001(56) 110 022 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VREDUCEPH, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+22873, 566},
    /*   2 : VREDUCEPH zmmreg|mask|z,zmmrm512|b16|sae,imm8 [rmi:fv:   evex.512.np.0f3a.w0 56 /r ib      ] AVX512FP16,FUTURE */
        /* 250(f3 7c 48) 301 001(56) 110 022 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VREDUCEPH, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+22883, 567},
};

static const struct itemplate instrux_VREDUCESH[2] = {
    /*   0 : VREDUCESH xmmreg|mask|z,xmmreg*,xmmrm16|sae,imm8 [rvmi:t1s: evex.nds.lig.np.0f3a.w0 57 /r ib  ] AVX512FP16,FUTURE */
        /* 241(f3 7c 08) 306 001(57) 120 023 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VREDUCESH, 4, {XMMREG,XMMREG,RM_XMM|BITS16,IMM_NORMAL|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+22893, 568},
    /*   1 : VREDUCESH xmmreg|mask|z,xmmrm16|sae,imm8 [r+vmi:t1s: evex.nds.lig.np.0f3a.w0 57 /r ib  ] ND,AVX512FP16,FUTURE */
        /* 240(f3 7c 08) 306 001(57) 110 022 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VREDUCESH, 3, {XMMREG,RM_XMM|BITS16,IMM_NORMAL|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+22903, 568},
};

static const struct itemplate instrux_VENDSCALEPH[3] = {
    /*   0 : VENDSCALEPH xmmreg|mask|z,xmmrm128|b16,imm8 [rmi:fv:   evex.128.np.0f3a.w0 08 /r ib      ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f3 7c 08) 301 001(08) 110 022 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VENDSCALEPH, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+21563, 566},
    /*   1 : VENDSCALEPH ymmreg|mask|z,ymmrm256|b16,imm8 [rmi:fv:   evex.256.np.0f3a.w0 08 /r ib      ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f3 7c 28) 301 001(08) 110 022 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VENDSCALEPH, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+21573, 566},
    /*   2 : VENDSCALEPH zmmreg|mask|z,zmmrm512|b16|sae,imm8 [rmi:fv:   evex.512.np.0f3a.w0 08 /r ib      ] AVX512FP16,FUTURE */
        /* 250(f3 7c 48) 301 001(08) 110 022 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VENDSCALEPH, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+21583, 567},
};

static const struct itemplate instrux_VENDSCALESH[2] = {
    /*   0 : VENDSCALESH xmmreg|mask|z,xmmreg*,xmmrm16|sae,imm8 [rvmi:t1s: evex.nds.lig.np.0f3a.w0 0a /r ib  ] AVX512FP16,FUTURE */
        /* 241(f3 7c 08) 306 001(0a) 120 023 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VENDSCALESH, 4, {XMMREG,XMMREG,RM_XMM|BITS16,IMM_NORMAL|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+21643, 568},
    /*   1 : VENDSCALESH xmmreg|mask|z,xmmrm16|sae,imm8 [r+vmi:t1s: evex.nds.lig.np.0f3a.w0 0a /r ib  ] ND,AVX512FP16,FUTURE */
        /* 240(f3 7c 08) 306 001(0a) 110 022 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VENDSCALESH, 3, {XMMREG,RM_XMM|BITS16,IMM_NORMAL|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+21653, 568},
};

static const struct itemplate instrux_VRSQRTPH[3] = {
    /*   0 : VRSQRTPH xmmreg|mask|z,xmmrm128|b16,imm8 [rmi:fv:   evex.128.66.map6.w0 4e /r ib      ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f6 7d 08) 301 001(4e) 110 022 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VRSQRTPH, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+22913, 566},
    /*   1 : VRSQRTPH ymmreg|mask|z,ymmrm256|b16,imm8 [rmi:fv:   evex.256.66.map6.w0 4e /r ib      ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f6 7d 28) 301 001(4e) 110 022 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VRSQRTPH, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+22923, 566},
    /*   2 : VRSQRTPH zmmreg|mask|z,zmmrm512|b16|sae,imm8 [rmi:fv:   evex.512.66.map6.w0 4e /r ib      ] AVX512FP16,FUTURE */
        /* 250(f6 7d 48) 301 001(4e) 110 022 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VRSQRTPH, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+22933, 567},
};

static const struct itemplate instrux_VRSQRTSH[2] = {
    /*   0 : VRSQRTSH xmmreg|mask|z,xmmreg*,xmmrm16|sae,imm8 [rvmi:t1s: evex.nds.lig.66.map6.w0 4f /r ib  ] AVX512FP16,FUTURE */
        /* 241(f6 7d 08) 306 001(4f) 120 023 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VRSQRTSH, 4, {XMMREG,XMMREG,RM_XMM|BITS16,IMM_NORMAL|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+22943, 568},
    /*   1 : VRSQRTSH xmmreg|mask|z,xmmrm16|sae,imm8 [r+vmi:t1s: evex.nds.lig.66.map6.w0 4f /r ib  ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7d 08) 306 001(4f) 110 022 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VRSQRTSH, 3, {XMMREG,RM_XMM|BITS16,IMM_NORMAL|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+22953, 568},
};

static const struct itemplate instrux_VSCALEFPH[6] = {
    /*   0 : VSCALEFPH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv:   evex.nds.128.66.map6.w0 2c /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7d 08) 301 001(2c) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VSCALEFPH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+48834, 566},
    /*   1 : VSCALEFPH xmmreg|mask|z,xmmrm128|b16 [r+vm:fv:   evex.nds.128.66.map6.w0 2c /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7d 08) 301 001(2c) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VSCALEFPH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+48843, 566},
    /*   2 : VSCALEFPH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv:   evex.nds.256.66.map6.w0 2c /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f6 7d 28) 301 001(2c) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VSCALEFPH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+48852, 566},
    /*   3 : VSCALEFPH ymmreg|mask|z,ymmrm256|b16 [r+vm:fv:   evex.nds.256.66.map6.w0 2c /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f6 7d 28) 301 001(2c) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VSCALEFPH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+48861, 566},
    /*   4 : VSCALEFPH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv:   evex.nds.512.66.map6.w0 2c /r     ] AVX512FP16,FUTURE */
        /* 241(f6 7d 48) 301 001(2c) 120 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VSCALEFPH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+48870, 567},
    /*   5 : VSCALEFPH zmmreg|mask|z,zmmrm512|b16|er [r+vm:fv:   evex.nds.512.66.map6.w0 2c /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7d 48) 301 001(2c) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VSCALEFPH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+48879, 567},
};

static const struct itemplate instrux_VSCALEFSH[2] = {
    /*   0 : VSCALEFSH xmmreg|mask|z,xmmreg*,xmmrm16|er [rvm:t1s:  evex.nds.lig.66.map6.w0 2d /r     ] AVX512FP16,FUTURE */
        /* 241(f6 7d 08) 306 001(2d) 120 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VSCALEFSH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+48888, 568},
    /*   1 : VSCALEFSH xmmreg|mask|z,xmmrm16|er [r+vm:t1s:  evex.nds.lig.66.map6.w0 2d /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f6 7d 08) 306 001(2d) 110 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VSCALEFSH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+48897, 568},
};

static const struct itemplate instrux_VSQRTPH[3] = {
    /*   0 : VSQRTPH xmmreg|mask|z,xmmrm128|b16 [rm:fv:    evex.128.np.map5.w0 51 /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 7c 08) 301 001(51) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VSQRTPH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+48906, 566},
    /*   1 : VSQRTPH ymmreg|mask|z,ymmrm256|b16 [rm:fv:    evex.256.np.map5.w0 51 /r         ] AVX512VL,AVX512FP16,FUTURE */
        /* 250(f5 7c 28) 301 001(51) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VSQRTPH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+48915, 566},
    /*   2 : VSQRTPH zmmreg|mask|z,zmmrm512|b16|er [rm:fv:    evex.512.np.map5.w0 51 /r         ] AVX512FP16,FUTURE */
        /* 250(f5 7c 48) 301 001(51) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VSQRTPH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+48924, 567},
};

static const struct itemplate instrux_VSQRTSH[2] = {
    /*   0 : VSQRTSH xmmreg|mask|z,xmmreg*,xmmrm16|er [rvm:t1s:  evex.nds.lig.f3.map5.w0 51 /r     ] AVX512FP16,FUTURE */
        /* 241(f5 7e 08) 306 001(51) 120 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VSQRTSH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+48933, 568},
    /*   1 : VSQRTSH xmmreg|mask|z,xmmrm16|er [r+vm:t1s:  evex.nds.lig.f3.map5.w0 51 /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f5 7e 08) 306 001(51) 110 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VSQRTSH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+48942, 568},
};

static const struct itemplate instrux_VSUBPH[6] = {
    /*   0 : VSUBPH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv:   evex.nds.128.np.map5.w0 5c /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f5 7c 08) 301 001(5c) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VSUBPH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+48951, 566},
    /*   1 : VSUBPH xmmreg|mask|z,xmmrm128|b16 [r+vm:fv:   evex.nds.128.np.map5.w0 5c /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f5 7c 08) 301 001(5c) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VSUBPH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+48960, 566},
    /*   2 : VSUBPH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv:   evex.nds.256.np.map5.w0 5c /r     ] AVX512VL,AVX512FP16,FUTURE */
        /* 241(f5 7c 28) 301 001(5c) 120 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VSUBPH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+48969, 566},
    /*   3 : VSUBPH ymmreg|mask|z,ymmrm256|b16 [r+vm:fv:   evex.nds.256.np.map5.w0 5c /r     ] ND,AVX512VL,AVX512FP16,FUTURE */
        /* 240(f5 7c 28) 301 001(5c) 110 : EVEX,PROT,AVX512VL,AVX512FP16,FUTURE */
        {I_VSUBPH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+48978, 566},
    /*   4 : VSUBPH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv:   evex.nds.512.np.map5.w0 5c /r     ] AVX512FP16,FUTURE */
        /* 241(f5 7c 48) 301 001(5c) 120 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VSUBPH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+48987, 567},
    /*   5 : VSUBPH zmmreg|mask|z,zmmrm512|b16|er [r+vm:fv:   evex.nds.512.np.map5.w0 5c /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f5 7c 48) 301 001(5c) 110 : EVEX,PROT,AVX512FP16,FUTURE */
        {I_VSUBPH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+48996, 567},
};

static const struct itemplate instrux_VSUBSH[2] = {
    /*   0 : VSUBSH xmmreg|mask|z,xmmreg*,xmmrm16|er [rvm:t1s:  evex.nds.lig.f3.map5.w0 5c /r     ] AVX512FP16,FUTURE */
        /* 241(f5 7e 08) 306 001(5c) 120 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VSUBSH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+49005, 568},
    /*   1 : VSUBSH xmmreg|mask|z,xmmrm16|er [r+vm:t1s:  evex.nds.lig.f3.map5.w0 5c /r     ] ND,AVX512FP16,FUTURE */
        /* 240(f5 7e 08) 306 001(5c) 110 : LIG,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VSUBSH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+49014, 568},
};

static const struct itemplate instrux_VUCOMISH[1] = {
    /*   0 : VUCOMISH xmmreg,xmmrm16|sae [rm:t1s:   evex.lig.np.map5.w0 2e /r         ] FL,AVX512FP16,FUTURE */
        /* 250(f5 7c 08) 306 001(2e) 110 : LIG,FL,EVEX,PROT,AVX512FP16,FUTURE */
        {I_VUCOMISH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+49023, 636},
};

static const struct itemplate instrux_AADD[4] = {
    /*   0 : AADD mem32,reg32 [mr:       o32 np 0f38 fc /r                 ] AR0-1,SQ,LONG,PROT,RAOINT,X86_64 */
        /* 321 360 356 001(fc) 101 : AR0,AR1,SQ,NOAPX,LONG,PROT,RAOINT,X86_64 */
        {I_AADD, 2, {MEMORY|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66154, 638},
    /*   1 : AADD mem64,reg64 [mr:       o64 np 0f38 fc /r                 ] AR0-1,SQ,LONG,PROT,RAOINT,X86_64 */
        /* 324 360 356 001(fc) 101 : AR0,AR1,SQ,NOAPX,LONG,PROT,RAOINT,X86_64 */
        {I_AADD, 2, {MEMORY|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66161, 638},
    /*   2 : AADD mem32,reg32 [mr:       evex.nf0.nd0.l0.np.m4.o32 fc /r   ] AR0-1,SQ,LONG,PROT,RAOINT,APX,X86_64 */
        /* 250(f4 7c 08) 300 321 001(fc) 101 : AR0,AR1,SQ,WW,LONG,EVEX,PROT,RAOINT,APX,X86_64 */
        {I_AADD, 2, {MEMORY|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+22963, 639},
    /*   3 : AADD mem64,reg64 [mr:       evex.nf0.nd0.l0.np.m4.o64 fc /r   ] AR0-1,SQ,LONG,PROT,RAOINT,APX,X86_64 */
        /* 250(f4 fc 08) 300 324 001(fc) 101 : AR0,AR1,SQ,WW,LONG,EVEX,PROT,RAOINT,APX,X86_64 */
        {I_AADD, 2, {MEMORY|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+22973, 639},
};

static const struct itemplate instrux_AAND[4] = {
    /*   0 : AAND mem32,reg32 [mr:       o32 66 0f38 fc /r                 ] AR0-1,SQ,LONG,PROT,RAOINT,X86_64 */
        /* 321 361 356 001(fc) 101 : AR0,AR1,SQ,NOAPX,LONG,PROT,RAOINT,X86_64 */
        {I_AAND, 2, {MEMORY|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66168, 638},
    /*   1 : AAND mem64,reg64 [mr:       o64 66 0f38 fc /r                 ] AR0-1,SQ,LONG,PROT,RAOINT,X86_64 */
        /* 324 361 356 001(fc) 101 : AR0,AR1,SQ,NOAPX,LONG,PROT,RAOINT,X86_64 */
        {I_AAND, 2, {MEMORY|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66175, 638},
    /*   2 : AAND mem32,reg32 [mr:       evex.nf0.nd0.l0.66.m4.o32 fc /r   ] AR0-1,SQ,LONG,PROT,RAOINT,APX,X86_64 */
        /* 250(f4 7d 08) 300 321 001(fc) 101 : AR0,AR1,SQ,WW,LONG,EVEX,PROT,RAOINT,APX,X86_64 */
        {I_AAND, 2, {MEMORY|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+22983, 639},
    /*   3 : AAND mem64,reg64 [mr:       evex.nf0.nd0.l0.66.m4.o64 fc /r   ] AR0-1,SQ,LONG,PROT,RAOINT,APX,X86_64 */
        /* 250(f4 fd 08) 300 324 001(fc) 101 : AR0,AR1,SQ,WW,LONG,EVEX,PROT,RAOINT,APX,X86_64 */
        {I_AAND, 2, {MEMORY|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+22993, 639},
};

static const struct itemplate instrux_AOR[4] = {
    /*   0 : AOR mem32,reg32 [mr:       o32 f2 0f38 fc /r                 ] AR0-1,SQ,LONG,PROT,RAOINT,X86_64 */
        /* 321 332 356 001(fc) 101 : AR0,AR1,SQ,NOAPX,LONG,PROT,RAOINT,X86_64 */
        {I_AOR, 2, {MEMORY|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66182, 638},
    /*   1 : AOR mem64,reg64 [mr:       o64 f2 0f38 fc /r                 ] AR0-1,SQ,LONG,PROT,RAOINT,X86_64 */
        /* 324 332 356 001(fc) 101 : AR0,AR1,SQ,NOAPX,LONG,PROT,RAOINT,X86_64 */
        {I_AOR, 2, {MEMORY|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66189, 638},
    /*   2 : AOR mem32,reg32 [mr:       evex.nf0.nd0.l0.f2.m4.o32 fc /r   ] AR0-1,SQ,LONG,PROT,RAOINT,APX,X86_64 */
        /* 250(f4 7f 08) 300 321 001(fc) 101 : AR0,AR1,SQ,WW,LONG,EVEX,PROT,RAOINT,APX,X86_64 */
        {I_AOR, 2, {MEMORY|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+23003, 639},
    /*   3 : AOR mem64,reg64 [mr:       evex.nf0.nd0.l0.f2.m4.o64 fc /r   ] AR0-1,SQ,LONG,PROT,RAOINT,APX,X86_64 */
        /* 250(f4 ff 08) 300 324 001(fc) 101 : AR0,AR1,SQ,WW,LONG,EVEX,PROT,RAOINT,APX,X86_64 */
        {I_AOR, 2, {MEMORY|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+23013, 639},
};

static const struct itemplate instrux_AXOR[4] = {
    /*   0 : AXOR mem32,reg32 [mr:       o32 f3 0f38 fc /r                 ] AR0-1,SQ,LONG,PROT,RAOINT,X86_64 */
        /* 321 333 356 001(fc) 101 : AR0,AR1,SQ,NOAPX,LONG,PROT,RAOINT,X86_64 */
        {I_AXOR, 2, {MEMORY|BITS32|RN_L16,REG_GPR|BITS32|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66196, 638},
    /*   1 : AXOR mem64,reg64 [mr:       o64 f3 0f38 fc /r                 ] AR0-1,SQ,LONG,PROT,RAOINT,X86_64 */
        /* 324 333 356 001(fc) 101 : AR0,AR1,SQ,NOAPX,LONG,PROT,RAOINT,X86_64 */
        {I_AXOR, 2, {MEMORY|BITS64|RN_L16,REG_GPR|BITS64|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66203, 638},
    /*   2 : AXOR mem32,reg32 [mr:       evex.nf0.nd0.l0.f3.m4.o32 fc /r   ] AR0-1,SQ,LONG,PROT,RAOINT,APX,X86_64 */
        /* 250(f4 7e 08) 300 321 001(fc) 101 : AR0,AR1,SQ,WW,LONG,EVEX,PROT,RAOINT,APX,X86_64 */
        {I_AXOR, 2, {MEMORY|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+23023, 639},
    /*   3 : AXOR mem64,reg64 [mr:       evex.nf0.nd0.l0.f3.m4.o64 fc /r   ] AR0-1,SQ,LONG,PROT,RAOINT,APX,X86_64 */
        /* 250(f4 fe 08) 300 324 001(fc) 101 : AR0,AR1,SQ,WW,LONG,EVEX,PROT,RAOINT,APX,X86_64 */
        {I_AXOR, 2, {MEMORY|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+23033, 639},
};

static const struct itemplate instrux_CLUI[1] = {
    /*   0 : CLUI void [          f3 0f 01 ee                       ] LONG,PROT,UINTR,X86_64 */
        /* 333 355 002(01 ee) : LONG,PROT,UINTR,X86_64 */
        {I_CLUI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70010, 640},
};

static const struct itemplate instrux_SENDUIPI[1] = {
    /*   0 : SENDUIPI reg64 [m:        o64nw f3 0f c7 /6                 ] LONG,PROT,UINTR,X86_64 */
        /* 323 333 355 001(c7) 206 : NWSIZE,LONG,PROT,UINTR,X86_64 */
        {I_SENDUIPI, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66210, 641},
};

static const struct itemplate instrux_STUI[1] = {
    /*   0 : STUI void [          f3 0f 01 ef                       ] LONG,PROT,UINTR,X86_64 */
        /* 333 355 002(01 ef) : LONG,PROT,UINTR,X86_64 */
        {I_STUI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70016, 640},
};

static const struct itemplate instrux_TESTUI[1] = {
    /*   0 : TESTUI void [          f3 0f 01 ed                       ] LONG,FL,PROT,UINTR,X86_64 */
        /* 333 355 002(01 ed) : LONG,FL,PROT,UINTR,X86_64 */
        {I_TESTUI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70022, 642},
};

static const struct itemplate instrux_UIRET[1] = {
    /*   0 : UIRET void [          f3 0f 01 ec                       ] LONG,FL,PROT,UINTR,X86_64 */
        /* 333 355 002(01 ec) : LONG,FL,PROT,UINTR,X86_64 */
        {I_UIRET, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70028, 642},
};

static const struct itemplate instrux_HRESET[2] = {
    /*   0 : HRESET imm,reg_eax [i-:       f3 0f3a f0 c0 ib                  ] AR0-1,SB,PRIV,HRESET,FUTURE */
        /* 333 357 002(f0 c0) 020 : AR0,AR1,SB,NOAPX,PRIV,HRESET,FUTURE */
        {I_HRESET, 2, {IMM_NORMAL,REG_EAX|RN_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+66217, 643},
    /*   1 : HRESET imm [i:        f3 0f3a f0 c0 ib                  ] ND,AR0,SB,PRIV,HRESET,FUTURE */
        /* 333 357 002(f0 c0) 020 : AR0,SB,NOAPX,PRIV,HRESET,FUTURE */
        {I_HRESET, 1, {IMM_NORMAL,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66217, 644},
};

static const struct itemplate instrux_VADDBF16[3] = {
    /*   0 : VADDBF16 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv:   evex.128.66.map5.w0 58 /r         ] AVX10_2,FUTURE */
        /* 241(f5 7d 08) 301 001(58) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VADDBF16, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49032, 645},
    /*   1 : VADDBF16 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv:   evex.256.66.map5.w0 58 /r         ] AVX10_2,FUTURE */
        /* 241(f5 7d 28) 301 001(58) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VADDBF16, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49041, 645},
    /*   2 : VADDBF16 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv:   evex.512.66.map5.w0 58 /r         ] AVX10_2,FUTURE */
        /* 241(f5 7d 48) 301 001(58) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VADDBF16, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49050, 645},
};

static const struct itemplate instrux_VCMPBF16[3] = {
    /*   0 : VCMPBF16 kreg|mask,xmmreg,xmmrm128|b16,imm8 [rvmi:fv:  evex.128.f2.0f3a.w0 c2 /r ib      ] AVX10_2,FUTURE */
        /* 241(f3 7f 08) 301 001(c2) 120 023 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCMPBF16, 4, {OPMASKREG,XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK,0,B16,0,0}, nasm_bytecodes+23043, 645},
    /*   1 : VCMPBF16 kreg|mask,ymmreg,ymmrm256|b16,imm8 [rvmi:fv:  evex.256.f2.0f3a.w0 c2 /r ib      ] AVX10_2,FUTURE */
        /* 241(f3 7f 28) 301 001(c2) 120 023 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCMPBF16, 4, {OPMASKREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK,0,B16,0,0}, nasm_bytecodes+23053, 645},
    /*   2 : VCMPBF16 kreg|mask,zmmreg,zmmrm512|b16,imm8 [rvmi:fv:  evex.512.f2.0f3a.w0 c2 /r ib      ] AVX10_2,FUTURE */
        /* 241(f3 7f 48) 301 001(c2) 120 023 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCMPBF16, 4, {OPMASKREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, {MASK,0,B16,0,0}, nasm_bytecodes+23063, 645},
};

static const struct itemplate instrux_VCOMISBF16[1] = {
    /*   0 : VCOMISBF16 xmmreg,xmmrm16 [rm:t1s:   evex.lig.66.map5.w0 2f /r         ] AVX10_2,FUTURE */
        /* 250(f5 7d 08) 306 001(2f) 110 : LIG,EVEX,PROT,AVX10_2,FUTURE */
        {I_VCOMISBF16, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+49059, 646},
};

static const struct itemplate instrux_VDIVBF16[3] = {
    /*   0 : VDIVBF16 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv:   evex.128.66.map5.w0 5e /r         ] AVX10_2,FUTURE */
        /* 241(f5 7d 08) 301 001(5e) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VDIVBF16, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49068, 645},
    /*   1 : VDIVBF16 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv:   evex.256.66.map5.w0 5e /r         ] AVX10_2,FUTURE */
        /* 241(f5 7d 28) 301 001(5e) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VDIVBF16, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49077, 645},
    /*   2 : VDIVBF16 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv:   evex.512.66.map5.w0 5e /r         ] AVX10_2,FUTURE */
        /* 241(f5 7d 48) 301 001(5e) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VDIVBF16, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49086, 645},
};

static const struct itemplate instrux_VFMADD132BF16[3] = {
    /*   0 : VFMADD132BF16 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv:   evex.128.np.map6.w0 98 /r         ] AVX10_2,FUTURE */
        /* 241(f6 7c 08) 301 001(98) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VFMADD132BF16, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49095, 645},
    /*   1 : VFMADD132BF16 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv:   evex.256.np.map6.w0 98 /r         ] AVX10_2,FUTURE */
        /* 241(f6 7c 28) 301 001(98) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VFMADD132BF16, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49104, 645},
    /*   2 : VFMADD132BF16 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv:   evex.512.np.map6.w0 98 /r         ] AVX10_2,FUTURE */
        /* 241(f6 7c 48) 301 001(98) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VFMADD132BF16, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49113, 645},
};

static const struct itemplate instrux_VFMADD213BF16[3] = {
    /*   0 : VFMADD213BF16 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv:   evex.128.np.map6.w0 a8 /r         ] AVX10_2,FUTURE */
        /* 241(f6 7c 08) 301 001(a8) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VFMADD213BF16, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49122, 645},
    /*   1 : VFMADD213BF16 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv:   evex.256.np.map6.w0 a8 /r         ] AVX10_2,FUTURE */
        /* 241(f6 7c 28) 301 001(a8) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VFMADD213BF16, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49131, 645},
    /*   2 : VFMADD213BF16 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv:   evex.512.np.map6.w0 a8 /r         ] AVX10_2,FUTURE */
        /* 241(f6 7c 48) 301 001(a8) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VFMADD213BF16, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49140, 645},
};

static const struct itemplate instrux_VFMADD231BF16[3] = {
    /*   0 : VFMADD231BF16 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv:   evex.128.np.map6.w0 b8 /r         ] AVX10_2,FUTURE */
        /* 241(f6 7c 08) 301 001(b8) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VFMADD231BF16, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49149, 645},
    /*   1 : VFMADD231BF16 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv:   evex.256.np.map6.w0 b8 /r         ] AVX10_2,FUTURE */
        /* 241(f6 7c 28) 301 001(b8) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VFMADD231BF16, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49158, 645},
    /*   2 : VFMADD231BF16 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv:   evex.512.np.map6.w0 b8 /r         ] AVX10_2,FUTURE */
        /* 241(f6 7c 48) 301 001(b8) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VFMADD231BF16, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49167, 645},
};

static const struct itemplate instrux_VFMSUB132BF16[3] = {
    /*   0 : VFMSUB132BF16 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv:   evex.128.np.map6.w0 9a /r         ] AVX10_2,FUTURE */
        /* 241(f6 7c 08) 301 001(9a) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VFMSUB132BF16, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49176, 645},
    /*   1 : VFMSUB132BF16 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv:   evex.256.np.map6.w0 9a /r         ] AVX10_2,FUTURE */
        /* 241(f6 7c 28) 301 001(9a) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VFMSUB132BF16, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49185, 645},
    /*   2 : VFMSUB132BF16 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv:   evex.512.np.map6.w0 9a /r         ] AVX10_2,FUTURE */
        /* 241(f6 7c 48) 301 001(9a) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VFMSUB132BF16, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49194, 645},
};

static const struct itemplate instrux_VFMSUB213BF16[3] = {
    /*   0 : VFMSUB213BF16 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv:   evex.128.np.map6.w0 aa /r         ] AVX10_2,FUTURE */
        /* 241(f6 7c 08) 301 001(aa) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VFMSUB213BF16, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49203, 645},
    /*   1 : VFMSUB213BF16 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv:   evex.256.np.map6.w0 aa /r         ] AVX10_2,FUTURE */
        /* 241(f6 7c 28) 301 001(aa) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VFMSUB213BF16, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49212, 645},
    /*   2 : VFMSUB213BF16 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv:   evex.512.np.map6.w0 aa /r         ] AVX10_2,FUTURE */
        /* 241(f6 7c 48) 301 001(aa) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VFMSUB213BF16, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49221, 645},
};

static const struct itemplate instrux_VFMSUB231BF16[3] = {
    /*   0 : VFMSUB231BF16 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv:   evex.128.np.map6.w0 ba /r         ] AVX10_2,FUTURE */
        /* 241(f6 7c 08) 301 001(ba) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VFMSUB231BF16, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49230, 645},
    /*   1 : VFMSUB231BF16 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv:   evex.256.np.map6.w0 ba /r         ] AVX10_2,FUTURE */
        /* 241(f6 7c 28) 301 001(ba) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VFMSUB231BF16, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49239, 645},
    /*   2 : VFMSUB231BF16 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv:   evex.512.np.map6.w0 ba /r         ] AVX10_2,FUTURE */
        /* 241(f6 7c 48) 301 001(ba) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VFMSUB231BF16, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49248, 645},
};

static const struct itemplate instrux_VFNMADD132BF16[3] = {
    /*   0 : VFNMADD132BF16 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv:   evex.128.np.map6.w0 9c /r         ] AVX10_2,FUTURE */
        /* 241(f6 7c 08) 301 001(9c) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VFNMADD132BF16, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49257, 645},
    /*   1 : VFNMADD132BF16 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv:   evex.256.np.map6.w0 9c /r         ] AVX10_2,FUTURE */
        /* 241(f6 7c 28) 301 001(9c) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VFNMADD132BF16, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49266, 645},
    /*   2 : VFNMADD132BF16 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv:   evex.512.np.map6.w0 9c /r         ] AVX10_2,FUTURE */
        /* 241(f6 7c 48) 301 001(9c) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VFNMADD132BF16, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49275, 645},
};

static const struct itemplate instrux_VFNMADD213BF16[3] = {
    /*   0 : VFNMADD213BF16 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv:   evex.128.np.map6.w0 ac /r         ] AVX10_2,FUTURE */
        /* 241(f6 7c 08) 301 001(ac) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VFNMADD213BF16, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49284, 645},
    /*   1 : VFNMADD213BF16 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv:   evex.256.np.map6.w0 ac /r         ] AVX10_2,FUTURE */
        /* 241(f6 7c 28) 301 001(ac) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VFNMADD213BF16, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49293, 645},
    /*   2 : VFNMADD213BF16 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv:   evex.512.np.map6.w0 ac /r         ] AVX10_2,FUTURE */
        /* 241(f6 7c 48) 301 001(ac) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VFNMADD213BF16, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49302, 645},
};

static const struct itemplate instrux_VFNMADD231BF16[3] = {
    /*   0 : VFNMADD231BF16 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv:   evex.128.np.map6.w0 bc /r         ] AVX10_2,FUTURE */
        /* 241(f6 7c 08) 301 001(bc) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VFNMADD231BF16, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49311, 645},
    /*   1 : VFNMADD231BF16 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv:   evex.256.np.map6.w0 bc /r         ] AVX10_2,FUTURE */
        /* 241(f6 7c 28) 301 001(bc) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VFNMADD231BF16, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49320, 645},
    /*   2 : VFNMADD231BF16 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv:   evex.512.np.map6.w0 bc /r         ] AVX10_2,FUTURE */
        /* 241(f6 7c 48) 301 001(bc) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VFNMADD231BF16, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49329, 645},
};

static const struct itemplate instrux_VFNMSUB132BF16[3] = {
    /*   0 : VFNMSUB132BF16 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv:   evex.128.np.map6.w0 9e /r         ] AVX10_2,FUTURE */
        /* 241(f6 7c 08) 301 001(9e) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VFNMSUB132BF16, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49338, 645},
    /*   1 : VFNMSUB132BF16 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv:   evex.256.np.map6.w0 9e /r         ] AVX10_2,FUTURE */
        /* 241(f6 7c 28) 301 001(9e) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VFNMSUB132BF16, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49347, 645},
    /*   2 : VFNMSUB132BF16 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv:   evex.512.np.map6.w0 9e /r         ] AVX10_2,FUTURE */
        /* 241(f6 7c 48) 301 001(9e) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VFNMSUB132BF16, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49356, 645},
};

static const struct itemplate instrux_VFNMSUB213BF16[3] = {
    /*   0 : VFNMSUB213BF16 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv:   evex.128.np.map6.w0 ae /r         ] AVX10_2,FUTURE */
        /* 241(f6 7c 08) 301 001(ae) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VFNMSUB213BF16, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49365, 645},
    /*   1 : VFNMSUB213BF16 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv:   evex.256.np.map6.w0 ae /r         ] AVX10_2,FUTURE */
        /* 241(f6 7c 28) 301 001(ae) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VFNMSUB213BF16, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49374, 645},
    /*   2 : VFNMSUB213BF16 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv:   evex.512.np.map6.w0 ae /r         ] AVX10_2,FUTURE */
        /* 241(f6 7c 48) 301 001(ae) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VFNMSUB213BF16, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49383, 645},
};

static const struct itemplate instrux_VFNMSUB231BF16[3] = {
    /*   0 : VFNMSUB231BF16 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv:   evex.128.np.map6.w0 be /r         ] AVX10_2,FUTURE */
        /* 241(f6 7c 08) 301 001(be) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VFNMSUB231BF16, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49392, 645},
    /*   1 : VFNMSUB231BF16 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv:   evex.256.np.map6.w0 be /r         ] AVX10_2,FUTURE */
        /* 241(f6 7c 28) 301 001(be) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VFNMSUB231BF16, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49401, 645},
    /*   2 : VFNMSUB231BF16 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv:   evex.512.np.map6.w0 be /r         ] AVX10_2,FUTURE */
        /* 241(f6 7c 48) 301 001(be) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VFNMSUB231BF16, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49410, 645},
};

static const struct itemplate instrux_VFPCLASSBF16[3] = {
    /*   0 : VFPCLASSBF16 kreg|mask,xmmrm128|b16,imm8 [rmi:fv:   evex.128.f2.0f3a.w0 66 /r ib      ] AVX10_2,FUTURE */
        /* 250(f3 7f 08) 301 001(66) 110 022 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VFPCLASSBF16, 3, {OPMASKREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK,B16,0,0,0}, nasm_bytecodes+23073, 645},
    /*   1 : VFPCLASSBF16 kreg|mask,ymmrm256|b16,imm8 [rmi:fv:   evex.256.f2.0f3a.w0 66 /r ib      ] AVX10_2,FUTURE */
        /* 250(f3 7f 28) 301 001(66) 110 022 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VFPCLASSBF16, 3, {OPMASKREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK,B16,0,0,0}, nasm_bytecodes+23083, 645},
    /*   2 : VFPCLASSBF16 kreg|mask,zmmrm512|b16,imm8 [rmi:fv:   evex.512.f2.0f3a.w0 66 /r ib      ] AVX10_2,FUTURE */
        /* 250(f3 7f 48) 301 001(66) 110 022 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VFPCLASSBF16, 3, {OPMASKREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK,B16,0,0,0}, nasm_bytecodes+23093, 645},
};

static const struct itemplate instrux_VGETEXPBF16[3] = {
    /*   0 : VGETEXPBF16 xmmreg|mask|z,xmmrm128|b16 [rm:fv:    evex.128.np.map6.w0 42 /r         ] AVX10_2,FUTURE */
        /* 250(f6 7c 08) 301 001(42) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VGETEXPBF16, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+49419, 645},
    /*   1 : VGETEXPBF16 ymmreg|mask|z,ymmrm256|b16 [rm:fv:    evex.256.np.map6.w0 42 /r         ] AVX10_2,FUTURE */
        /* 250(f6 7c 28) 301 001(42) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VGETEXPBF16, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+49428, 645},
    /*   2 : VGETEXPBF16 zmmreg|mask|z,zmmrm512|b16 [rm:fv:    evex.512.np.map6.w0 42 /r         ] AVX10_2,FUTURE */
        /* 250(f6 7c 48) 301 001(42) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VGETEXPBF16, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+49437, 645},
};

static const struct itemplate instrux_VGETMANTBF16[3] = {
    /*   0 : VGETMANTBF16 xmmreg|mask|z,xmmrm128|b16,imm8 [rmi:fv:   evex.128.f2.0f3a.w0 26 /r ib      ] AVX10_2,FUTURE */
        /* 250(f3 7f 08) 301 001(26) 110 022 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VGETMANTBF16, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+23103, 645},
    /*   1 : VGETMANTBF16 ymmreg|mask|z,ymmrm256|b16,imm8 [rmi:fv:   evex.256.f2.0f3a.w0 26 /r ib      ] AVX10_2,FUTURE */
        /* 250(f3 7f 28) 301 001(26) 110 022 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VGETMANTBF16, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+23113, 645},
    /*   2 : VGETMANTBF16 zmmreg|mask|z,zmmrm512|b16,imm8 [rmi:fv:   evex.512.f2.0f3a.w0 26 /r ib      ] AVX10_2,FUTURE */
        /* 250(f3 7f 48) 301 001(26) 110 022 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VGETMANTBF16, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+23123, 645},
};

static const struct itemplate instrux_VMAXBF16[3] = {
    /*   0 : VMAXBF16 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv:   evex.128.66.map5.w0 5f /r         ] AVX10_2,FUTURE */
        /* 241(f5 7d 08) 301 001(5f) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VMAXBF16, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49446, 645},
    /*   1 : VMAXBF16 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv:   evex.256.66.map5.w0 5f /r         ] AVX10_2,FUTURE */
        /* 241(f5 7d 28) 301 001(5f) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VMAXBF16, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49455, 645},
    /*   2 : VMAXBF16 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv:   evex.512.66.map5.w0 5f /r         ] AVX10_2,FUTURE */
        /* 241(f5 7d 48) 301 001(5f) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VMAXBF16, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49464, 645},
};

static const struct itemplate instrux_VMINBF16[3] = {
    /*   0 : VMINBF16 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv:   evex.128.66.map5.w0 5d /r         ] AVX10_2,FUTURE */
        /* 241(f5 7d 08) 301 001(5d) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VMINBF16, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49473, 645},
    /*   1 : VMINBF16 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv:   evex.256.66.map5.w0 5d /r         ] AVX10_2,FUTURE */
        /* 241(f5 7d 28) 301 001(5d) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VMINBF16, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49482, 645},
    /*   2 : VMINBF16 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv:   evex.512.66.map5.w0 5d /r         ] AVX10_2,FUTURE */
        /* 241(f5 7d 48) 301 001(5d) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VMINBF16, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49491, 645},
};

static const struct itemplate instrux_VMULBF16[3] = {
    /*   0 : VMULBF16 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv:   evex.128.66.map5.w0 59 /r         ] AVX10_2,FUTURE */
        /* 241(f5 7d 08) 301 001(59) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VMULBF16, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49500, 645},
    /*   1 : VMULBF16 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv:   evex.256.66.map5.w0 59 /r         ] AVX10_2,FUTURE */
        /* 241(f5 7d 28) 301 001(59) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VMULBF16, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49509, 645},
    /*   2 : VMULBF16 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv:   evex.512.66.map5.w0 59 /r         ] AVX10_2,FUTURE */
        /* 241(f5 7d 48) 301 001(59) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VMULBF16, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49518, 645},
};

static const struct itemplate instrux_VRCPBF16[3] = {
    /*   0 : VRCPBF16 xmmreg|mask|z,xmmrm128|b16 [rm:fv:    evex.128.np.map6.w0 4c /r         ] AVX10_2,FUTURE */
        /* 250(f6 7c 08) 301 001(4c) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VRCPBF16, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+49527, 645},
    /*   1 : VRCPBF16 ymmreg|mask|z,ymmrm256|b16 [rm:fv:    evex.256.np.map6.w0 4c /r         ] AVX10_2,FUTURE */
        /* 250(f6 7c 28) 301 001(4c) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VRCPBF16, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+49536, 645},
    /*   2 : VRCPBF16 zmmreg|mask|z,zmmrm512|b16 [rm:fv:    evex.512.np.map6.w0 4c /r         ] AVX10_2,FUTURE */
        /* 250(f6 7c 48) 301 001(4c) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VRCPBF16, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+49545, 645},
};

static const struct itemplate instrux_VREDUCEBF16[3] = {
    /*   0 : VREDUCEBF16 xmmreg|mask|z,xmmrm128|b16,imm8 [rmi:fv:   evex.128.f2.0f3a.w0 56 /r ib      ] AVX10_2,FUTURE */
        /* 250(f3 7f 08) 301 001(56) 110 022 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VREDUCEBF16, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+23133, 645},
    /*   1 : VREDUCEBF16 ymmreg|mask|z,ymmrm256|b16,imm8 [rmi:fv:   evex.256.f2.0f3a.w0 56 /r ib      ] AVX10_2,FUTURE */
        /* 250(f3 7f 28) 301 001(56) 110 022 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VREDUCEBF16, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+23143, 645},
    /*   2 : VREDUCEBF16 zmmreg|mask|z,zmmrm512|b16,imm8 [rmi:fv:   evex.512.f2.0f3a.w0 56 /r ib      ] AVX10_2,FUTURE */
        /* 250(f3 7f 48) 301 001(56) 110 022 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VREDUCEBF16, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+23153, 645},
};

static const struct itemplate instrux_VRNDSCALEBF16[3] = {
    /*   0 : VRNDSCALEBF16 xmmreg|mask|z,xmmrm128|b16,imm8 [rmi:fv:   evex.128.f2.0f3a.w0 08 /r ib      ] AVX10_2,FUTURE */
        /* 250(f3 7f 08) 301 001(08) 110 022 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VRNDSCALEBF16, 3, {XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+23163, 645},
    /*   1 : VRNDSCALEBF16 ymmreg|mask|z,ymmrm256|b16,imm8 [rmi:fv:   evex.256.f2.0f3a.w0 08 /r ib      ] AVX10_2,FUTURE */
        /* 250(f3 7f 28) 301 001(08) 110 022 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VRNDSCALEBF16, 3, {YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+23173, 645},
    /*   2 : VRNDSCALEBF16 zmmreg|mask|z,zmmrm512|b16,imm8 [rmi:fv:   evex.512.f2.0f3a.w0 08 /r ib      ] AVX10_2,FUTURE */
        /* 250(f3 7f 48) 301 001(08) 110 022 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VRNDSCALEBF16, 3, {ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+23183, 645},
};

static const struct itemplate instrux_VRSQRTBF16[3] = {
    /*   0 : VRSQRTBF16 xmmreg|mask|z,xmmrm128|b16 [rm:fv:    evex.128.np.map6.w0 4e /r         ] AVX10_2,FUTURE */
        /* 250(f6 7c 08) 301 001(4e) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VRSQRTBF16, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+49554, 645},
    /*   1 : VRSQRTBF16 ymmreg|mask|z,ymmrm256|b16 [rm:fv:    evex.256.np.map6.w0 4e /r         ] AVX10_2,FUTURE */
        /* 250(f6 7c 28) 301 001(4e) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VRSQRTBF16, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+49563, 645},
    /*   2 : VRSQRTBF16 zmmreg|mask|z,zmmrm512|b16 [rm:fv:    evex.512.np.map6.w0 4e /r         ] AVX10_2,FUTURE */
        /* 250(f6 7c 48) 301 001(4e) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VRSQRTBF16, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+49572, 645},
};

static const struct itemplate instrux_VSCALEFBF16[3] = {
    /*   0 : VSCALEFBF16 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv:   evex.128.np.map6.w0 2c /r         ] AVX10_2,FUTURE */
        /* 241(f6 7c 08) 301 001(2c) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VSCALEFBF16, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49581, 645},
    /*   1 : VSCALEFBF16 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv:   evex.256.np.map6.w0 2c /r         ] AVX10_2,FUTURE */
        /* 241(f6 7c 28) 301 001(2c) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VSCALEFBF16, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49590, 645},
    /*   2 : VSCALEFBF16 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv:   evex.512.np.map6.w0 2c /r         ] AVX10_2,FUTURE */
        /* 241(f6 7c 48) 301 001(2c) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VSCALEFBF16, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49599, 645},
};

static const struct itemplate instrux_VSQRTBF16[3] = {
    /*   0 : VSQRTBF16 xmmreg|mask|z,xmmrm128|b16 [rm:fv:    evex.128.66.map5.w0 51 /r         ] AVX10_2,FUTURE */
        /* 250(f5 7d 08) 301 001(51) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VSQRTBF16, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+49608, 645},
    /*   1 : VSQRTBF16 ymmreg|mask|z,ymmrm256|b16 [rm:fv:    evex.256.66.map5.w0 51 /r         ] AVX10_2,FUTURE */
        /* 250(f5 7d 28) 301 001(51) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VSQRTBF16, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+49617, 645},
    /*   2 : VSQRTBF16 zmmreg|mask|z,zmmrm512|b16 [rm:fv:    evex.512.66.map5.w0 51 /r         ] AVX10_2,FUTURE */
        /* 250(f5 7d 48) 301 001(51) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VSQRTBF16, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+49626, 645},
};

static const struct itemplate instrux_VSUBBF16[3] = {
    /*   0 : VSUBBF16 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv:   evex.128.66.map5.w0 5c /r         ] AVX10_2,FUTURE */
        /* 241(f5 7d 08) 301 001(5c) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VSUBBF16, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49635, 645},
    /*   1 : VSUBBF16 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv:   evex.256.66.map5.w0 5c /r         ] AVX10_2,FUTURE */
        /* 241(f5 7d 28) 301 001(5c) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VSUBBF16, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49644, 645},
    /*   2 : VSUBBF16 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv:   evex.512.66.map5.w0 5c /r         ] AVX10_2,FUTURE */
        /* 241(f5 7d 48) 301 001(5c) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VSUBBF16, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49653, 645},
};

static const struct itemplate instrux_VCOMXSD[1] = {
    /*   0 : VCOMXSD xmmreg,xmmrm64|sae [rm:t1s:   evex.lig.f2.0f.w1 2f /r           ] AVX10_2,FUTURE */
        /* 250(f1 ff 08) 306 001(2f) 110 : LIG,EVEX,PROT,AVX10_2,FUTURE */
        {I_VCOMXSD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+49662, 646},
};

static const struct itemplate instrux_VCOMXSH[1] = {
    /*   0 : VCOMXSH xmmreg,xmmrm16|sae [rm:t1s:   evex.lig.f3.map5.w0 2f /r         ] AVX10_2,FUTURE */
        /* 250(f5 7e 08) 306 001(2f) 110 : LIG,EVEX,PROT,AVX10_2,FUTURE */
        {I_VCOMXSH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+49671, 646},
};

static const struct itemplate instrux_VCOMXSS[1] = {
    /*   0 : VCOMXSS xmmreg,xmmrm32|sae [rm:t1s:   evex.lig.f3.0f.w0 2f /r           ] AVX10_2,FUTURE */
        /* 250(f1 7e 08) 306 001(2f) 110 : LIG,EVEX,PROT,AVX10_2,FUTURE */
        {I_VCOMXSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+49680, 646},
};

static const struct itemplate instrux_VUCOMXSD[1] = {
    /*   0 : VUCOMXSD xmmreg,xmmrm64|sae [rm:t1s:   evex.lig.f2.0f.w1 2e /r           ] AVX10_2,FUTURE */
        /* 250(f1 ff 08) 306 001(2e) 110 : LIG,EVEX,PROT,AVX10_2,FUTURE */
        {I_VUCOMXSD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+49689, 646},
};

static const struct itemplate instrux_VUCOMXSH[1] = {
    /*   0 : VUCOMXSH xmmreg,xmmrm16|sae [rm:t1s:   evex.lig.f3.map5.w0 2e /r         ] AVX10_2,FUTURE */
        /* 250(f5 7e 08) 306 001(2e) 110 : LIG,EVEX,PROT,AVX10_2,FUTURE */
        {I_VUCOMXSH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+49698, 646},
};

static const struct itemplate instrux_VUCOMXSS[1] = {
    /*   0 : VUCOMXSS xmmreg,xmmrm32|sae [rm:t1s:   evex.lig.f3.0f.w0 2e /r           ] AVX10_2,FUTURE */
        /* 250(f1 7e 08) 306 001(2e) 110 : LIG,EVEX,PROT,AVX10_2,FUTURE */
        {I_VUCOMXSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+49707, 646},
};

static const struct itemplate instrux_VCVT2PH2BF8[3] = {
    /*   0 : VCVT2PH2BF8 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv:   evex.128.f2.0f38.w0 74 /r         ] AVX10_2,FUTURE */
        /* 241(f2 7f 08) 301 001(74) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVT2PH2BF8, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49716, 645},
    /*   1 : VCVT2PH2BF8 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv:   evex.256.f2.0f38.w0 74 /r         ] AVX10_2,FUTURE */
        /* 241(f2 7f 28) 301 001(74) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVT2PH2BF8, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49725, 645},
    /*   2 : VCVT2PH2BF8 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv:   evex.512.f2.0f38.w0 74 /r         ] AVX10_2,FUTURE */
        /* 241(f2 7f 48) 301 001(74) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVT2PH2BF8, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49734, 645},
};

static const struct itemplate instrux_VCVT2PH2BF8S[3] = {
    /*   0 : VCVT2PH2BF8S xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv:   evex.128.f2.map5.w0 74 /r         ] AVX10_2,FUTURE */
        /* 241(f5 7f 08) 301 001(74) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVT2PH2BF8S, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49743, 645},
    /*   1 : VCVT2PH2BF8S ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv:   evex.256.f2.map5.w0 74 /r         ] AVX10_2,FUTURE */
        /* 241(f5 7f 28) 301 001(74) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVT2PH2BF8S, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49752, 645},
    /*   2 : VCVT2PH2BF8S zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv:   evex.512.f2.map5.w0 74 /r         ] AVX10_2,FUTURE */
        /* 241(f5 7f 48) 301 001(74) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVT2PH2BF8S, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49761, 645},
};

static const struct itemplate instrux_VCVT2PH2HF8[3] = {
    /*   0 : VCVT2PH2HF8 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv:   evex.128.f2.map5.w0 18 /r         ] AVX10_2,FUTURE */
        /* 241(f5 7f 08) 301 001(18) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVT2PH2HF8, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49770, 645},
    /*   1 : VCVT2PH2HF8 ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv:   evex.256.f2.map5.w0 18 /r         ] AVX10_2,FUTURE */
        /* 241(f5 7f 28) 301 001(18) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVT2PH2HF8, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49779, 645},
    /*   2 : VCVT2PH2HF8 zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv:   evex.512.f2.map5.w0 18 /r         ] AVX10_2,FUTURE */
        /* 241(f5 7f 48) 301 001(18) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVT2PH2HF8, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49788, 645},
};

static const struct itemplate instrux_VCVT2PH2HF8S[3] = {
    /*   0 : VCVT2PH2HF8S xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv:   evex.128.f2.map5.w0 1b /r         ] AVX10_2,FUTURE */
        /* 241(f5 7f 08) 301 001(1b) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVT2PH2HF8S, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49797, 645},
    /*   1 : VCVT2PH2HF8S ymmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv:   evex.256.f2.map5.w0 1b /r         ] AVX10_2,FUTURE */
        /* 241(f5 7f 28) 301 001(1b) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVT2PH2HF8S, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49806, 645},
    /*   2 : VCVT2PH2HF8S zmmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv:   evex.512.f2.map5.w0 1b /r         ] AVX10_2,FUTURE */
        /* 241(f5 7f 48) 301 001(1b) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVT2PH2HF8S, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49815, 645},
};

static const struct itemplate instrux_VCVTPH2BF8[3] = {
    /*   0 : VCVTPH2BF8 xmmreg|mask|z,xmmrm128|b16 [rm:fv:    evex.128.f3.0f38.w0 74 /r         ] AVX10_2,FUTURE */
        /* 250(f2 7e 08) 301 001(74) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTPH2BF8, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+49824, 645},
    /*   1 : VCVTPH2BF8 ymmreg|mask|z,ymmrm256|b16 [rm:fv:    evex.256.f3.0f38.w0 74 /r         ] AVX10_2,FUTURE */
        /* 250(f2 7e 28) 301 001(74) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTPH2BF8, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+49833, 645},
    /*   2 : VCVTPH2BF8 zmmreg|mask|z,zmmrm512|b16 [rm:fv:    evex.512.f3.0f38.w0 74 /r         ] AVX10_2,FUTURE */
        /* 250(f2 7e 48) 301 001(74) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTPH2BF8, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+49842, 645},
};

static const struct itemplate instrux_VCVTPH2BF8S[3] = {
    /*   0 : VCVTPH2BF8S xmmreg|mask|z,xmmrm128|b16 [rm:fv:    evex.128.f3.map5.w0 74 /r         ] AVX10_2,FUTURE */
        /* 250(f5 7e 08) 301 001(74) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTPH2BF8S, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+49851, 645},
    /*   1 : VCVTPH2BF8S ymmreg|mask|z,ymmrm256|b16 [rm:fv:    evex.256.f3.map5.w0 74 /r         ] AVX10_2,FUTURE */
        /* 250(f5 7e 28) 301 001(74) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTPH2BF8S, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+49860, 645},
    /*   2 : VCVTPH2BF8S zmmreg|mask|z,zmmrm512|b16 [rm:fv:    evex.512.f3.map5.w0 74 /r         ] AVX10_2,FUTURE */
        /* 250(f5 7e 48) 301 001(74) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTPH2BF8S, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+49869, 645},
};

static const struct itemplate instrux_VCVTPH2HF8[3] = {
    /*   0 : VCVTPH2HF8 xmmreg|mask|z,xmmrm128|b16 [rm:fv:    evex.128.f3.map5.w0 18 /r         ] AVX10_2,FUTURE */
        /* 250(f5 7e 08) 301 001(18) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTPH2HF8, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+49878, 645},
    /*   1 : VCVTPH2HF8 ymmreg|mask|z,ymmrm256|b16 [rm:fv:    evex.256.f3.map5.w0 18 /r         ] AVX10_2,FUTURE */
        /* 250(f5 7e 28) 301 001(18) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTPH2HF8, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+49887, 645},
    /*   2 : VCVTPH2HF8 zmmreg|mask|z,zmmrm512|b16 [rm:fv:    evex.512.f3.map5.w0 18 /r         ] AVX10_2,FUTURE */
        /* 250(f5 7e 48) 301 001(18) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTPH2HF8, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+49896, 645},
};

static const struct itemplate instrux_VCVTPH2HF8S[3] = {
    /*   0 : VCVTPH2HF8S xmmreg|mask|z,xmmrm128|b16 [rm:fv:    evex.128.f3.map5.w0 1b /r         ] AVX10_2,FUTURE */
        /* 250(f5 7e 08) 301 001(1b) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTPH2HF8S, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+49905, 645},
    /*   1 : VCVTPH2HF8S ymmreg|mask|z,ymmrm256|b16 [rm:fv:    evex.256.f3.map5.w0 1b /r         ] AVX10_2,FUTURE */
        /* 250(f5 7e 28) 301 001(1b) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTPH2HF8S, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+49914, 645},
    /*   2 : VCVTPH2HF8S zmmreg|mask|z,zmmrm512|b16 [rm:fv:    evex.512.f3.map5.w0 1b /r         ] AVX10_2,FUTURE */
        /* 250(f5 7e 48) 301 001(1b) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTPH2HF8S, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+49923, 645},
};

static const struct itemplate instrux_VCVT2PS2PHX[3] = {
    /*   0 : VCVT2PS2PHX xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv:   evex.128.66.0f38.w0 67 /r         ] AVX10_2,FUTURE */
        /* 241(f2 7d 08) 301 001(67) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVT2PS2PHX, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+49932, 645},
    /*   1 : VCVT2PS2PHX ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv:   evex.256.66.0f38.w0 67 /r         ] AVX10_2,FUTURE */
        /* 241(f2 7d 28) 301 001(67) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVT2PS2PHX, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+49941, 645},
    /*   2 : VCVT2PS2PHX zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv:   evex.512.66.0f38.w0 67 /r         ] AVX10_2,FUTURE */
        /* 241(f2 7d 48) 301 001(67) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVT2PS2PHX, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+49950, 645},
};

static const struct itemplate instrux_VCVTBIASPH2BF8[3] = {
    /*   0 : VCVTBIASPH2BF8 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv:   evex.128.np.0f38.w0 74 /r         ] AVX10_2,FUTURE */
        /* 241(f2 7c 08) 301 001(74) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTBIASPH2BF8, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49959, 645},
    /*   1 : VCVTBIASPH2BF8 xmmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv:   evex.256.np.0f38.w0 74 /r         ] AVX10_2,FUTURE */
        /* 241(f2 7c 28) 301 001(74) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTBIASPH2BF8, 3, {XMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49968, 645},
    /*   2 : VCVTBIASPH2BF8 ymmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv:   evex.512.np.0f38.w0 74 /r         ] AVX10_2,FUTURE */
        /* 241(f2 7c 48) 301 001(74) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTBIASPH2BF8, 3, {YMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49977, 645},
};

static const struct itemplate instrux_VCVTBIASPH2BF8S[3] = {
    /*   0 : VCVTBIASPH2BF8S xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv:   evex.128.np.map5.w0 74 /r         ] AVX10_2,FUTURE */
        /* 241(f5 7c 08) 301 001(74) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTBIASPH2BF8S, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49986, 645},
    /*   1 : VCVTBIASPH2BF8S xmmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv:   evex.256.np.map5.w0 74 /r         ] AVX10_2,FUTURE */
        /* 241(f5 7c 28) 301 001(74) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTBIASPH2BF8S, 3, {XMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+49995, 645},
    /*   2 : VCVTBIASPH2BF8S ymmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv:   evex.512.np.map5.w0 74 /r         ] AVX10_2,FUTURE */
        /* 241(f5 7c 48) 301 001(74) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTBIASPH2BF8S, 3, {YMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+50004, 645},
};

static const struct itemplate instrux_VCVTBIASPH2HF8[3] = {
    /*   0 : VCVTBIASPH2HF8 xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv:   evex.128.np.map5.w0 18 /r         ] AVX10_2,FUTURE */
        /* 241(f5 7c 08) 301 001(18) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTBIASPH2HF8, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+50013, 645},
    /*   1 : VCVTBIASPH2HF8 xmmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv:   evex.256.np.map5.w0 18 /r         ] AVX10_2,FUTURE */
        /* 241(f5 7c 28) 301 001(18) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTBIASPH2HF8, 3, {XMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+50022, 645},
    /*   2 : VCVTBIASPH2HF8 ymmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv:   evex.512.np.map5.w0 18 /r         ] AVX10_2,FUTURE */
        /* 241(f5 7c 48) 301 001(18) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTBIASPH2HF8, 3, {YMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+50031, 645},
};

static const struct itemplate instrux_VCVTBIASPH2HF8S[3] = {
    /*   0 : VCVTBIASPH2HF8S xmmreg|mask|z,xmmreg,xmmrm128|b16 [rvm:fv:   evex.128.np.map5.w0 1b /r         ] AVX10_2,FUTURE */
        /* 241(f5 7c 08) 301 001(1b) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTBIASPH2HF8S, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+50040, 645},
    /*   1 : VCVTBIASPH2HF8S xmmreg|mask|z,ymmreg,ymmrm256|b16 [rvm:fv:   evex.256.np.map5.w0 1b /r         ] AVX10_2,FUTURE */
        /* 241(f5 7c 28) 301 001(1b) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTBIASPH2HF8S, 3, {XMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+50049, 645},
    /*   2 : VCVTBIASPH2HF8S ymmreg|mask|z,zmmreg,zmmrm512|b16 [rvm:fv:   evex.512.np.map5.w0 1b /r         ] AVX10_2,FUTURE */
        /* 241(f5 7c 48) 301 001(1b) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTBIASPH2HF8S, 3, {YMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+50058, 645},
};

static const struct itemplate instrux_VCVTHF82PH[3] = {
    /*   0 : VCVTHF82PH xmmreg|mask|z,xmmrm64 [rm:hv:    evex.128.f2.map5.w0 1e /r         ] AVX10_2,FUTURE */
        /* 250(f5 7f 08) 302 001(1e) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTHF82PH, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+50067, 645},
    /*   1 : VCVTHF82PH ymmreg|mask|z,xmmrm128 [rm:hv:    evex.256.f2.map5.w0 1e /r         ] AVX10_2,FUTURE */
        /* 250(f5 7f 28) 302 001(1e) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTHF82PH, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+50076, 645},
    /*   2 : VCVTHF82PH zmmreg|mask|z,ymmrm256 [rm:hv:    evex.512.f2.map5.w0 1e /r         ] AVX10_2,FUTURE */
        /* 250(f5 7f 48) 302 001(1e) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTHF82PH, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+50085, 645},
};

static const struct itemplate instrux_VDPPHPS[3] = {
    /*   0 : VDPPHPS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv:   evex.128.np.0f38.w0 52 /r         ] AVX10_2,FUTURE */
        /* 241(f2 7c 08) 301 001(52) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VDPPHPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+50094, 645},
    /*   1 : VDPPHPS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv:   evex.256.np.0f38.w0 52 /r         ] AVX10_2,FUTURE */
        /* 241(f2 7c 28) 301 001(52) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VDPPHPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+50103, 645},
    /*   2 : VDPPHPS zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv:   evex.512.np.0f38.w0 52 /r         ] AVX10_2,FUTURE */
        /* 241(f2 7c 48) 301 001(52) 120 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VDPPHPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+50112, 645},
};

static const struct itemplate instrux_VMINMAXBF16[3] = {
    /*   0 : VMINMAXBF16 xmmreg|mask|z,xmmreg,xmmrm128|b16,imm8 [rvmi:fv:  evex.128.f2.0f3a.w0 52 /r ib      ] AVX10_2,FUTURE */
        /* 241(f3 7f 08) 301 001(52) 120 023 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VMINMAXBF16, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+23223, 645},
    /*   1 : VMINMAXBF16 ymmreg|mask|z,ymmreg,ymmrm256|b16,imm8 [rvmi:fv:  evex.256.f2.0f3a.w0 52 /r ib      ] AVX10_2,FUTURE */
        /* 241(f3 7f 28) 301 001(52) 120 023 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VMINMAXBF16, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+23233, 645},
    /*   2 : VMINMAXBF16 zmmreg|mask|z,zmmreg,zmmrm512|b16,imm8 [rvmi:fv:  evex.512.f2.0f3a.w0 52 /r ib      ] AVX10_2,FUTURE */
        /* 241(f3 7f 48) 301 001(52) 120 023 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VMINMAXBF16, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+23243, 645},
};

static const struct itemplate instrux_VMINMAXPD[3] = {
    /*   0 : VMINMAXPD xmmreg|mask|z,xmmreg,xmmrm128|b64,imm8 [rvmi:fv:  evex.128.66.0f3a.w1 52 /r ib      ] AVX10_2,FUTURE */
        /* 241(f3 fd 08) 301 001(52) 120 023 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VMINMAXPD, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+23253, 645},
    /*   1 : VMINMAXPD ymmreg|mask|z,ymmreg,ymmrm256|b64,imm8 [rvmi:fv:  evex.256.66.0f3a.w1 52 /r ib      ] AVX10_2,FUTURE */
        /* 241(f3 fd 28) 301 001(52) 120 023 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VMINMAXPD, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+23263, 645},
    /*   2 : VMINMAXPD zmmreg|mask|z,zmmreg,zmmrm512|b64|sae,imm8 [rvmi:fv:  evex.512.66.0f3a.w1 52 /r ib      ] AVX10_2,FUTURE */
        /* 241(f3 fd 48) 301 001(52) 120 023 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VMINMAXPD, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B64|SAE,0,0}, nasm_bytecodes+23273, 645},
};

static const struct itemplate instrux_VMINMAXPH[3] = {
    /*   0 : VMINMAXPH xmmreg|mask|z,xmmreg,xmmrm128|b16,imm8 [rvmi:fv:  evex.128.np.0f3a.w0 52 /r ib      ] AVX10_2,FUTURE */
        /* 241(f3 7c 08) 301 001(52) 120 023 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VMINMAXPH, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+23283, 645},
    /*   1 : VMINMAXPH ymmreg|mask|z,ymmreg,ymmrm256|b16,imm8 [rvmi:fv:  evex.256.np.0f3a.w0 52 /r ib      ] AVX10_2,FUTURE */
        /* 241(f3 7c 28) 301 001(52) 120 023 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VMINMAXPH, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+23293, 645},
    /*   2 : VMINMAXPH zmmreg|mask|z,zmmreg,zmmrm512|b16|sae,imm8 [rvmi:fv:  evex.512.np.0f3a.w0 52 /r ib      ] AVX10_2,FUTURE */
        /* 241(f3 7c 48) 301 001(52) 120 023 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VMINMAXPH, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B16|SAE,0,0}, nasm_bytecodes+23303, 645},
};

static const struct itemplate instrux_VMINMAXPS[3] = {
    /*   0 : VMINMAXPS xmmreg|mask|z,xmmreg,xmmrm128|b32,imm8 [rvmi:fv:  evex.128.66.0f3a.w0 52 /r ib      ] AVX10_2,FUTURE */
        /* 241(f3 7d 08) 301 001(52) 120 023 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VMINMAXPS, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+23313, 645},
    /*   1 : VMINMAXPS ymmreg|mask|z,ymmreg,ymmrm256|b32,imm8 [rvmi:fv:  evex.256.66.0f3a.w0 52 /r ib      ] AVX10_2,FUTURE */
        /* 241(f3 7d 28) 301 001(52) 120 023 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VMINMAXPS, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+23323, 645},
    /*   2 : VMINMAXPS zmmreg|mask|z,zmmreg,zmmrm512|b32|sae,imm8 [rvmi:fv:  evex.512.66.0f3a.w0 52 /r ib      ] AVX10_2,FUTURE */
        /* 241(f3 7d 48) 301 001(52) 120 023 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VMINMAXPS, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMM_NORMAL|BITS8,0}, {MASK|Z,0,B32|SAE,0,0}, nasm_bytecodes+23333, 645},
};

static const struct itemplate instrux_VMINMAXSD[1] = {
    /*   0 : VMINMAXSD xmmreg|mask|z,xmmreg,xmmrm64|sae,imm8 [rvmi:t1s: evex.lig.66.0f3a.w1 53 /r ib      ] AVX10_2,FUTURE */
        /* 241(f3 fd 08) 306 001(53) 120 023 : LIG,EVEX,PROT,AVX10_2,FUTURE */
        {I_VMINMAXSD, 4, {XMMREG,XMMREG,RM_XMM|BITS64,IMM_NORMAL|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+23343, 646},
};

static const struct itemplate instrux_VMINMAXSH[1] = {
    /*   0 : VMINMAXSH xmmreg|mask|z,xmmreg,xmmrm16|sae,imm8 [rvmi:t1s: evex.lig.np.0f3a.w0 53 /r ib      ] AVX10_2,FUTURE */
        /* 241(f3 7c 08) 306 001(53) 120 023 : LIG,EVEX,PROT,AVX10_2,FUTURE */
        {I_VMINMAXSH, 4, {XMMREG,XMMREG,RM_XMM|BITS16,IMM_NORMAL|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+23353, 646},
};

static const struct itemplate instrux_VMINMAXSS[1] = {
    /*   0 : VMINMAXSS xmmreg|mask|z,xmmreg,xmmrm32|sae,imm8 [rvmi:t1s: evex.lig.66.0f3a.w0 53 /r ib      ] AVX10_2,FUTURE */
        /* 241(f3 7d 08) 306 001(53) 120 023 : LIG,EVEX,PROT,AVX10_2,FUTURE */
        {I_VMINMAXSS, 4, {XMMREG,XMMREG,RM_XMM|BITS32,IMM_NORMAL|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+23363, 646},
};

static const struct itemplate instrux_VCVTBF162IBS[3] = {
    /*   0 : VCVTBF162IBS xmmreg|mask|z,xmmrm128|b16 [rm:fv:    evex.128.f2.map5.w0 69 /r         ] AVX10_2,FUTURE */
        /* 250(f5 7f 08) 301 001(69) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTBF162IBS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+50445, 645},
    /*   1 : VCVTBF162IBS ymmreg|mask|z,ymmrm256|b16 [rm:fv:    evex.256.f2.map5.w0 69 /r         ] AVX10_2,FUTURE */
        /* 250(f5 7f 28) 301 001(69) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTBF162IBS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+50454, 645},
    /*   2 : VCVTBF162IBS zmmreg|mask|z,zmmrm512|b16 [rm:fv:    evex.512.f2.map5.w0 69 /r         ] AVX10_2,FUTURE */
        /* 250(f5 7f 48) 301 001(69) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTBF162IBS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+50463, 645},
};

static const struct itemplate instrux_VCVTBF162IUBS[3] = {
    /*   0 : VCVTBF162IUBS xmmreg|mask|z,xmmrm128|b16 [rm:fv:    evex.128.f2.map5.w0 6b /r         ] AVX10_2,FUTURE */
        /* 250(f5 7f 08) 301 001(6b) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTBF162IUBS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+50472, 645},
    /*   1 : VCVTBF162IUBS ymmreg|mask|z,ymmrm256|b16 [rm:fv:    evex.256.f2.map5.w0 6b /r         ] AVX10_2,FUTURE */
        /* 250(f5 7f 28) 301 001(6b) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTBF162IUBS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+50481, 645},
    /*   2 : VCVTBF162IUBS zmmreg|mask|z,zmmrm512|b16 [rm:fv:    evex.512.f2.map5.w0 6b /r         ] AVX10_2,FUTURE */
        /* 250(f5 7f 48) 301 001(6b) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTBF162IUBS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+50490, 645},
};

static const struct itemplate instrux_VCVTTBF162IBS[3] = {
    /*   0 : VCVTTBF162IBS xmmreg|mask|z,xmmrm128|b16 [rm:fv:    evex.128.f2.map5.w0 68 /r         ] AVX10_2,FUTURE */
        /* 250(f5 7f 08) 301 001(68) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTBF162IBS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+50499, 645},
    /*   1 : VCVTTBF162IBS ymmreg|mask|z,ymmrm256|b16 [rm:fv:    evex.256.f2.map5.w0 68 /r         ] AVX10_2,FUTURE */
        /* 250(f5 7f 28) 301 001(68) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTBF162IBS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+50508, 645},
    /*   2 : VCVTTBF162IBS zmmreg|mask|z,zmmrm512|b16 [rm:fv:    evex.512.f2.map5.w0 68 /r         ] AVX10_2,FUTURE */
        /* 250(f5 7f 48) 301 001(68) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTBF162IBS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+50517, 645},
};

static const struct itemplate instrux_VCVTTBF162IUBS[3] = {
    /*   0 : VCVTTBF162IUBS xmmreg|mask|z,xmmrm128|b16 [rm:fv:    evex.128.f2.map5.w0 6a /r         ] AVX10_2,FUTURE */
        /* 250(f5 7f 08) 301 001(6a) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTBF162IUBS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+50526, 645},
    /*   1 : VCVTTBF162IUBS ymmreg|mask|z,ymmrm256|b16 [rm:fv:    evex.256.f2.map5.w0 6a /r         ] AVX10_2,FUTURE */
        /* 250(f5 7f 28) 301 001(6a) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTBF162IUBS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+50535, 645},
    /*   2 : VCVTTBF162IUBS zmmreg|mask|z,zmmrm512|b16 [rm:fv:    evex.512.f2.map5.w0 6a /r         ] AVX10_2,FUTURE */
        /* 250(f5 7f 48) 301 001(6a) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTBF162IUBS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+50544, 645},
};

static const struct itemplate instrux_VCVTTPD2DQS[3] = {
    /*   0 : VCVTTPD2DQS xmmreg|mask|z,xmmrm128|b64 [rm:fv:    evex.128.np.map5.w1 6d /r         ] AVX10_2,FUTURE */
        /* 250(f5 fc 08) 301 001(6d) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTPD2DQS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+50553, 645},
    /*   1 : VCVTTPD2DQS xmmreg|mask|z,ymmrm256|b64 [rm:fv:    evex.256.np.map5.w1 6d /r         ] AVX10_2,FUTURE */
        /* 250(f5 fc 28) 301 001(6d) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTPD2DQS, 2, {XMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+50562, 645},
    /*   2 : VCVTTPD2DQS ymmreg|mask|z,zmmrm512|b64|sae [rm:fv:    evex.512.np.map5.w1 6d /r         ] AVX10_2,FUTURE */
        /* 250(f5 fc 48) 301 001(6d) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTPD2DQS, 2, {YMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+50571, 645},
};

static const struct itemplate instrux_VCVTTPD2QQS[3] = {
    /*   0 : VCVTTPD2QQS xmmreg|mask|z,xmmrm128|b64 [rm:fv:    evex.128.66.map5.w1 6d /r         ] AVX10_2,FUTURE */
        /* 250(f5 fd 08) 301 001(6d) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTPD2QQS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+50580, 645},
    /*   1 : VCVTTPD2QQS ymmreg|mask|z,ymmrm256|b64 [rm:fv:    evex.256.66.map5.w1 6d /r         ] AVX10_2,FUTURE */
        /* 250(f5 fd 28) 301 001(6d) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTPD2QQS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+50589, 645},
    /*   2 : VCVTTPD2QQS zmmreg|mask|z,zmmrm512|b64|sae [rm:fv:    evex.512.66.map5.w1 6d /r         ] AVX10_2,FUTURE */
        /* 250(f5 fd 48) 301 001(6d) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTPD2QQS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+50598, 645},
};

static const struct itemplate instrux_VCVTTPD2UDQS[3] = {
    /*   0 : VCVTTPD2UDQS xmmreg|mask|z,xmmrm128|b64 [rm:fv:    evex.128.np.map5.w1 6c /r         ] AVX10_2,FUTURE */
        /* 250(f5 fc 08) 301 001(6c) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTPD2UDQS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+50607, 645},
    /*   1 : VCVTTPD2UDQS xmmreg|mask|z,ymmrm256|b64 [rm:fv:    evex.256.np.map5.w1 6c /r         ] AVX10_2,FUTURE */
        /* 250(f5 fc 28) 301 001(6c) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTPD2UDQS, 2, {XMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+50616, 645},
    /*   2 : VCVTTPD2UDQS ymmreg|mask|z,zmmrm512|b64|sae [rm:fv:    evex.512.np.map5.w1 6c /r         ] AVX10_2,FUTURE */
        /* 250(f5 fc 48) 301 001(6c) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTPD2UDQS, 2, {YMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+50625, 645},
};

static const struct itemplate instrux_VCVTTPD2UQQS[3] = {
    /*   0 : VCVTTPD2UQQS xmmreg|mask|z,xmmrm128|b64 [rm:fv:    evex.128.66.map5.w1 6c /r         ] AVX10_2,FUTURE */
        /* 250(f5 fd 08) 301 001(6c) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTPD2UQQS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+50634, 645},
    /*   1 : VCVTTPD2UQQS ymmreg|mask|z,ymmrm256|b64 [rm:fv:    evex.256.66.map5.w1 6c /r         ] AVX10_2,FUTURE */
        /* 250(f5 fd 28) 301 001(6c) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTPD2UQQS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+50643, 645},
    /*   2 : VCVTTPD2UQQS zmmreg|mask|z,zmmrm512|b64|sae [rm:fv:    evex.512.66.map5.w1 6c /r         ] AVX10_2,FUTURE */
        /* 250(f5 fd 48) 301 001(6c) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTPD2UQQS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+50652, 645},
};

static const struct itemplate instrux_VCVTPH2IBS[3] = {
    /*   0 : VCVTPH2IBS xmmreg|mask|z,xmmrm128|b16 [rm:fv:    evex.128.np.map5.w0 69 /r         ] AVX10_2,FUTURE */
        /* 250(f5 7c 08) 301 001(69) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTPH2IBS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+50661, 645},
    /*   1 : VCVTPH2IBS ymmreg|mask|z,ymmrm256|b16 [rm:fv:    evex.256.np.map5.w0 69 /r         ] AVX10_2,FUTURE */
        /* 250(f5 7c 28) 301 001(69) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTPH2IBS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+50670, 645},
    /*   2 : VCVTPH2IBS zmmreg|mask|z,zmmrm512|b16|er [rm:fv:    evex.512.np.map5.w0 69 /r         ] AVX10_2,FUTURE */
        /* 250(f5 7c 48) 301 001(69) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTPH2IBS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+50679, 645},
};

static const struct itemplate instrux_VCVTPH2IUBS[3] = {
    /*   0 : VCVTPH2IUBS xmmreg|mask|z,xmmrm128|b16 [rm:fv:    evex.128.np.map5.w0 6b /r         ] AVX10_2,FUTURE */
        /* 250(f5 7c 08) 301 001(6b) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTPH2IUBS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+50688, 645},
    /*   1 : VCVTPH2IUBS ymmreg|mask|z,ymmrm256|b16 [rm:fv:    evex.256.np.map5.w0 6b /r         ] AVX10_2,FUTURE */
        /* 250(f5 7c 28) 301 001(6b) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTPH2IUBS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+50697, 645},
    /*   2 : VCVTPH2IUBS zmmreg|mask|z,zmmrm512|b16|er [rm:fv:    evex.512.np.map5.w0 6b /r         ] AVX10_2,FUTURE */
        /* 250(f5 7c 48) 301 001(6b) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTPH2IUBS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+50706, 645},
};

static const struct itemplate instrux_VCVTTPH2IBS[3] = {
    /*   0 : VCVTTPH2IBS xmmreg|mask|z,xmmrm128|b16 [rm:fv:    evex.128.np.map5.w0 68 /r         ] AVX10_2,FUTURE */
        /* 250(f5 7c 08) 301 001(68) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTPH2IBS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+50715, 645},
    /*   1 : VCVTTPH2IBS ymmreg|mask|z,ymmrm256|b16 [rm:fv:    evex.256.np.map5.w0 68 /r         ] AVX10_2,FUTURE */
        /* 250(f5 7c 28) 301 001(68) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTPH2IBS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+50724, 645},
    /*   2 : VCVTTPH2IBS zmmreg|mask|z,zmmrm512|b16|sae [rm:fv:    evex.512.np.map5.w0 68 /r         ] AVX10_2,FUTURE */
        /* 250(f5 7c 48) 301 001(68) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTPH2IBS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+50733, 645},
};

static const struct itemplate instrux_VCVTTPH2IUBS[3] = {
    /*   0 : VCVTTPH2IUBS xmmreg|mask|z,xmmrm128|b16 [rm:fv:    evex.128.np.map5.w0 6a /r         ] AVX10_2,FUTURE */
        /* 250(f5 7c 08) 301 001(6a) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTPH2IUBS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+50742, 645},
    /*   1 : VCVTTPH2IUBS ymmreg|mask|z,ymmrm256|b16 [rm:fv:    evex.256.np.map5.w0 6a /r         ] AVX10_2,FUTURE */
        /* 250(f5 7c 28) 301 001(6a) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTPH2IUBS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+50751, 645},
    /*   2 : VCVTTPH2IUBS zmmreg|mask|z,zmmrm512|b16|sae [rm:fv:    evex.512.np.map5.w0 6a /r         ] AVX10_2,FUTURE */
        /* 250(f5 7c 48) 301 001(6a) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTPH2IUBS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+50760, 645},
};

static const struct itemplate instrux_VCVTTPS2DQS[3] = {
    /*   0 : VCVTTPS2DQS xmmreg|mask|z,xmmrm128|b32 [rm:fv:    evex.128.np.map5.w0 6d /r         ] AVX10_2,FUTURE */
        /* 250(f5 7c 08) 301 001(6d) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTPS2DQS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+50769, 645},
    /*   1 : VCVTTPS2DQS ymmreg|mask|z,ymmrm256|b32 [rm:fv:    evex.256.np.map5.w0 6d /r         ] AVX10_2,FUTURE */
        /* 250(f5 7c 28) 301 001(6d) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTPS2DQS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+50778, 645},
    /*   2 : VCVTTPS2DQS zmmreg|mask|z,zmmrm512|b32|sae [rm:fv:    evex.512.np.map5.w0 6d /r         ] AVX10_2,FUTURE */
        /* 250(f5 7c 48) 301 001(6d) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTPS2DQS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+50787, 645},
};

static const struct itemplate instrux_VCVTPS2IBS[3] = {
    /*   0 : VCVTPS2IBS xmmreg|mask|z,xmmrm128|b32 [rm:fv:    evex.128.66.map5.w0 69 /r         ] AVX10_2,FUTURE */
        /* 250(f5 7d 08) 301 001(69) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTPS2IBS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+50796, 645},
    /*   1 : VCVTPS2IBS ymmreg|mask|z,ymmrm256|b32 [rm:fv:    evex.256.66.map5.w0 69 /r         ] AVX10_2,FUTURE */
        /* 250(f5 7d 28) 301 001(69) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTPS2IBS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+50805, 645},
    /*   2 : VCVTPS2IBS zmmreg|mask|z,zmmrm512|b32|er [rm:fv:    evex.512.66.map5.w0 69 /r         ] AVX10_2,FUTURE */
        /* 250(f5 7d 48) 301 001(69) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTPS2IBS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+50814, 645},
};

static const struct itemplate instrux_VCVTPS2IUBS[3] = {
    /*   0 : VCVTPS2IUBS xmmreg|mask|z,xmmrm128|b32 [rm:fv:    evex.128.66.map5.w0 6b /r         ] AVX10_2,FUTURE */
        /* 250(f5 7d 08) 301 001(6b) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTPS2IUBS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+50823, 645},
    /*   1 : VCVTPS2IUBS ymmreg|mask|z,ymmrm256|b32 [rm:fv:    evex.256.66.map5.w0 6b /r         ] AVX10_2,FUTURE */
        /* 250(f5 7d 28) 301 001(6b) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTPS2IUBS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+50832, 645},
    /*   2 : VCVTPS2IUBS zmmreg|mask|z,zmmrm512|b32|er [rm:fv:    evex.512.66.map5.w0 6b /r         ] AVX10_2,FUTURE */
        /* 250(f5 7d 48) 301 001(6b) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTPS2IUBS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+50841, 645},
};

static const struct itemplate instrux_VCVTTPS2IBS[3] = {
    /*   0 : VCVTTPS2IBS xmmreg|mask|z,xmmrm128|b32 [rm:fv:    evex.128.66.map5.w0 68 /r         ] AVX10_2,FUTURE */
        /* 250(f5 7d 08) 301 001(68) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTPS2IBS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+50850, 645},
    /*   1 : VCVTTPS2IBS ymmreg|mask|z,ymmrm256|b32 [rm:fv:    evex.256.66.map5.w0 68 /r         ] AVX10_2,FUTURE */
        /* 250(f5 7d 28) 301 001(68) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTPS2IBS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+50859, 645},
    /*   2 : VCVTTPS2IBS zmmreg|mask|z,zmmrm512|b32|sae [rm:fv:    evex.512.66.map5.w0 68 /r         ] AVX10_2,FUTURE */
        /* 250(f5 7d 48) 301 001(68) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTPS2IBS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+50868, 645},
};

static const struct itemplate instrux_VCVTTPS2IUBS[3] = {
    /*   0 : VCVTTPS2IUBS xmmreg|mask|z,xmmrm128|b32 [rm:fv:    evex.128.66.map5.w0 6a /r         ] AVX10_2,FUTURE */
        /* 250(f5 7d 08) 301 001(6a) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTPS2IUBS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+50877, 645},
    /*   1 : VCVTTPS2IUBS ymmreg|mask|z,ymmrm256|b32 [rm:fv:    evex.256.66.map5.w0 6a /r         ] AVX10_2,FUTURE */
        /* 250(f5 7d 28) 301 001(6a) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTPS2IUBS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+50886, 645},
    /*   2 : VCVTTPS2IUBS zmmreg|mask|z,zmmrm512|b32|sae [rm:fv:    evex.512.66.map5.w0 6a /r         ] AVX10_2,FUTURE */
        /* 250(f5 7d 48) 301 001(6a) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTPS2IUBS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+50895, 645},
};

static const struct itemplate instrux_VCVTTPS2QQS[3] = {
    /*   0 : VCVTTPS2QQS xmmreg|mask|z,xmmrm64|b32 [rm:hv:    evex.128.66.map5.w0 6d /r         ] AVX10_2,FUTURE */
        /* 250(f5 7d 08) 302 001(6d) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTPS2QQS, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+50904, 645},
    /*   1 : VCVTTPS2QQS ymmreg|mask|z,xmmrm128|b32 [rm:hv:    evex.256.66.map5.w0 6d /r         ] AVX10_2,FUTURE */
        /* 250(f5 7d 28) 302 001(6d) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTPS2QQS, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+50913, 645},
    /*   2 : VCVTTPS2QQS zmmreg|mask|z,ymmrm256|b32|sae [rm:hv:    evex.512.66.map5.w0 6d /r         ] AVX10_2,FUTURE */
        /* 250(f5 7d 48) 302 001(6d) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTPS2QQS, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+50922, 645},
};

static const struct itemplate instrux_VCVTTPS2UDQS[3] = {
    /*   0 : VCVTTPS2UDQS xmmreg|mask|z,xmmrm128|b32 [rm:fv:    evex.128.np.map5.w0 6c /r         ] AVX10_2,FUTURE */
        /* 250(f5 7c 08) 301 001(6c) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTPS2UDQS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+50931, 645},
    /*   1 : VCVTTPS2UDQS ymmreg|mask|z,ymmrm256|b32 [rm:fv:    evex.256.np.map5.w0 6c /r         ] AVX10_2,FUTURE */
        /* 250(f5 7c 28) 301 001(6c) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTPS2UDQS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+50940, 645},
    /*   2 : VCVTTPS2UDQS zmmreg|mask|z,zmmrm512|b32|sae [rm:fv:    evex.512.np.map5.w0 6c /r         ] AVX10_2,FUTURE */
        /* 250(f5 7c 48) 301 001(6c) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTPS2UDQS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+50949, 645},
};

static const struct itemplate instrux_VCVTTPS2UQQS[3] = {
    /*   0 : VCVTTPS2UQQS xmmreg|mask|z,xmmrm64|b32 [rm:hv:    evex.128.66.map5.w0 6c /r         ] AVX10_2,FUTURE */
        /* 250(f5 7d 08) 302 001(6c) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTPS2UQQS, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+50958, 645},
    /*   1 : VCVTTPS2UQQS ymmreg|mask|z,xmmrm128|b32 [rm:hv:    evex.256.66.map5.w0 6c /r         ] AVX10_2,FUTURE */
        /* 250(f5 7d 28) 302 001(6c) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTPS2UQQS, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+50967, 645},
    /*   2 : VCVTTPS2UQQS zmmreg|mask|z,ymmrm256|b32|sae [rm:hv:    evex.512.66.map5.w0 6c /r         ] AVX10_2,FUTURE */
        /* 250(f5 7d 48) 302 001(6c) 110 : EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTPS2UQQS, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+50976, 645},
};

static const struct itemplate instrux_VCVTTSD2SIS[2] = {
    /*   0 : VCVTTSD2SIS reg32,xmmrm64|sae [rm:t1s:   evex.lig.f2.map5.w0 6d /r         ] AVX10_2,FUTURE */
        /* 250(f5 7f 08) 306 001(6d) 110 : LIG,EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTSD2SIS, 2, {REG_GPR|BITS32,RM_XMM|BITS64,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+50985, 646},
    /*   1 : VCVTTSD2SIS reg64,xmmrm64|sae [rm:t1s:   evex.lig.f2.map5.w1 6d /r         ] LONG,PROT,AVX10_2,X86_64 */
        /* 250(f5 ff 08) 306 001(6d) 110 : LIG,LONG,EVEX,PROT,AVX10_2,X86_64 */
        {I_VCVTTSD2SIS, 2, {REG_GPR|BITS64,RM_XMM|BITS64,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+50994, 648},
};

static const struct itemplate instrux_VCVTTSD2USIS[2] = {
    /*   0 : VCVTTSD2USIS reg32,xmmrm64|sae [rm:t1s:   evex.lig.f2.map5.w0 6c /r         ] AVX10_2,FUTURE */
        /* 250(f5 7f 08) 306 001(6c) 110 : LIG,EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTSD2USIS, 2, {REG_GPR|BITS32,RM_XMM|BITS64,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+51003, 646},
    /*   1 : VCVTTSD2USIS reg64,xmmrm64|sae [rm:t1s:   evex.lig.f2.map5.w1 6c /r         ] LONG,PROT,AVX10_2,X86_64 */
        /* 250(f5 ff 08) 306 001(6c) 110 : LIG,LONG,EVEX,PROT,AVX10_2,X86_64 */
        {I_VCVTTSD2USIS, 2, {REG_GPR|BITS64,RM_XMM|BITS64,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+51012, 648},
};

static const struct itemplate instrux_VCVTTSS2SIS[2] = {
    /*   0 : VCVTTSS2SIS reg32,xmmrm32|sae [rm:t1s:   evex.lig.f3.map5.w0 6d /r         ] AVX10_2,FUTURE */
        /* 250(f5 7e 08) 306 001(6d) 110 : LIG,EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTSS2SIS, 2, {REG_GPR|BITS32,RM_XMM|BITS32,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+51021, 646},
    /*   1 : VCVTTSS2SIS reg64,xmmrm32|sae [rm:t1s:   evex.lig.f3.map5.w1 6d /r         ] LONG,PROT,AVX10_2,X86_64 */
        /* 250(f5 fe 08) 306 001(6d) 110 : LIG,LONG,EVEX,PROT,AVX10_2,X86_64 */
        {I_VCVTTSS2SIS, 2, {REG_GPR|BITS64,RM_XMM|BITS32,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+51030, 648},
};

static const struct itemplate instrux_VCVTTSS2USIS[2] = {
    /*   0 : VCVTTSS2USIS reg32,xmmrm32|sae [rm:t1s:   evex.lig.f3.map5.w0 6c /r         ] AVX10_2,FUTURE */
        /* 250(f5 7e 08) 306 001(6c) 110 : LIG,EVEX,PROT,AVX10_2,FUTURE */
        {I_VCVTTSS2USIS, 2, {REG_GPR|BITS32,RM_XMM|BITS32,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+51039, 646},
    /*   1 : VCVTTSS2USIS reg64,xmmrm32|sae [rm:t1s:   evex.lig.f3.map5.w1 6c /r         ] LONG,PROT,AVX10_2,X86_64 */
        /* 250(f5 fe 08) 306 001(6c) 110 : LIG,LONG,EVEX,PROT,AVX10_2,X86_64 */
        {I_VCVTTSS2USIS, 2, {REG_GPR|BITS64,RM_XMM|BITS32,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+51048, 648},
};

static const struct itemplate instrux_HINT_NOP[3] = {
    /*   0 : HINT_NOP imm,reg16,rm16 [irm:      o16 0f ibn /r                     ] ND,SM1-2,FL,UNDOC,P6 */
        /* 320 355 300 121 : SM1,SM2,FL,UNDOC,P6 */
        {I_HINT_NOP, 3, {IMM_NORMAL,REG_GPR|BITS16,RM_GPR|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+72418, 651},
    /*   1 : HINT_NOP imm,reg32,rm32 [irm:      o32 0f ibn /r                     ] ND,SM1-2,FL,UNDOC,P6 */
        /* 321 355 300 121 : SM1,SM2,FL,UNDOC,P6 */
        {I_HINT_NOP, 3, {IMM_NORMAL,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+72423, 651},
    /*   2 : HINT_NOP imm,reg64,rm64 [irm:      o64 0f ibn /r                     ] ND,SM1-2,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 300 121 : SM1,SM2,LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP, 3, {IMM_NORMAL,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+72428, 652},
};

static const struct itemplate instrux_HINT_NOP0[3] = {
    /*   0 : HINT_NOP0 rm16 [m:        o16 0f 18 /0                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(18) 200 : FL,UNDOC,P6 */
        {I_HINT_NOP0, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70034, 653},
    /*   1 : HINT_NOP0 rm32 [m:        o32 0f 18 /0                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(18) 200 : FL,UNDOC,P6 */
        {I_HINT_NOP0, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70040, 653},
    /*   2 : HINT_NOP0 rm64 [m:        o64 0f 18 /0                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(18) 200 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP0, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70046, 654},
};

static const struct itemplate instrux_HINT_NOP1[3] = {
    /*   0 : HINT_NOP1 rm16 [m:        o16 0f 18 /1                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(18) 201 : FL,UNDOC,P6 */
        {I_HINT_NOP1, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70052, 653},
    /*   1 : HINT_NOP1 rm32 [m:        o32 0f 18 /1                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(18) 201 : FL,UNDOC,P6 */
        {I_HINT_NOP1, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70058, 653},
    /*   2 : HINT_NOP1 rm64 [m:        o64 0f 18 /1                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(18) 201 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP1, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70064, 654},
};

static const struct itemplate instrux_HINT_NOP2[3] = {
    /*   0 : HINT_NOP2 rm16 [m:        o16 0f 18 /2                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(18) 202 : FL,UNDOC,P6 */
        {I_HINT_NOP2, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70070, 653},
    /*   1 : HINT_NOP2 rm32 [m:        o32 0f 18 /2                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(18) 202 : FL,UNDOC,P6 */
        {I_HINT_NOP2, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70076, 653},
    /*   2 : HINT_NOP2 rm64 [m:        o64 0f 18 /2                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(18) 202 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP2, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70082, 654},
};

static const struct itemplate instrux_HINT_NOP3[3] = {
    /*   0 : HINT_NOP3 rm16 [m:        o16 0f 18 /3                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(18) 203 : FL,UNDOC,P6 */
        {I_HINT_NOP3, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70088, 653},
    /*   1 : HINT_NOP3 rm32 [m:        o32 0f 18 /3                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(18) 203 : FL,UNDOC,P6 */
        {I_HINT_NOP3, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70094, 653},
    /*   2 : HINT_NOP3 rm64 [m:        o64 0f 18 /3                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(18) 203 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP3, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70100, 654},
};

static const struct itemplate instrux_HINT_NOP4[3] = {
    /*   0 : HINT_NOP4 rm16 [m:        o16 0f 18 /4                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(18) 204 : FL,UNDOC,P6 */
        {I_HINT_NOP4, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70106, 653},
    /*   1 : HINT_NOP4 rm32 [m:        o32 0f 18 /4                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(18) 204 : FL,UNDOC,P6 */
        {I_HINT_NOP4, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70112, 653},
    /*   2 : HINT_NOP4 rm64 [m:        o64 0f 18 /4                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(18) 204 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP4, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70118, 654},
};

static const struct itemplate instrux_HINT_NOP5[3] = {
    /*   0 : HINT_NOP5 rm16 [m:        o16 0f 18 /5                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(18) 205 : FL,UNDOC,P6 */
        {I_HINT_NOP5, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70124, 653},
    /*   1 : HINT_NOP5 rm32 [m:        o32 0f 18 /5                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(18) 205 : FL,UNDOC,P6 */
        {I_HINT_NOP5, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70130, 653},
    /*   2 : HINT_NOP5 rm64 [m:        o64 0f 18 /5                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(18) 205 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP5, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70136, 654},
};

static const struct itemplate instrux_HINT_NOP6[3] = {
    /*   0 : HINT_NOP6 rm16 [m:        o16 0f 18 /6                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(18) 206 : FL,UNDOC,P6 */
        {I_HINT_NOP6, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70142, 653},
    /*   1 : HINT_NOP6 rm32 [m:        o32 0f 18 /6                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(18) 206 : FL,UNDOC,P6 */
        {I_HINT_NOP6, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70148, 653},
    /*   2 : HINT_NOP6 rm64 [m:        o64 0f 18 /6                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(18) 206 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP6, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70154, 654},
};

static const struct itemplate instrux_HINT_NOP7[3] = {
    /*   0 : HINT_NOP7 rm16 [m:        o16 0f 18 /7                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(18) 207 : FL,UNDOC,P6 */
        {I_HINT_NOP7, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70160, 653},
    /*   1 : HINT_NOP7 rm32 [m:        o32 0f 18 /7                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(18) 207 : FL,UNDOC,P6 */
        {I_HINT_NOP7, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70166, 653},
    /*   2 : HINT_NOP7 rm64 [m:        o64 0f 18 /7                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(18) 207 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP7, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70172, 654},
};

static const struct itemplate instrux_HINT_NOP8[3] = {
    /*   0 : HINT_NOP8 rm16 [m:        o16 0f 19 /0                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(19) 200 : FL,UNDOC,P6 */
        {I_HINT_NOP8, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70178, 653},
    /*   1 : HINT_NOP8 rm32 [m:        o32 0f 19 /0                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(19) 200 : FL,UNDOC,P6 */
        {I_HINT_NOP8, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70184, 653},
    /*   2 : HINT_NOP8 rm64 [m:        o64 0f 19 /0                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(19) 200 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP8, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70190, 654},
};

static const struct itemplate instrux_HINT_NOP9[3] = {
    /*   0 : HINT_NOP9 rm16 [m:        o16 0f 19 /1                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(19) 201 : FL,UNDOC,P6 */
        {I_HINT_NOP9, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70196, 653},
    /*   1 : HINT_NOP9 rm32 [m:        o32 0f 19 /1                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(19) 201 : FL,UNDOC,P6 */
        {I_HINT_NOP9, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70202, 653},
    /*   2 : HINT_NOP9 rm64 [m:        o64 0f 19 /1                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(19) 201 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP9, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70208, 654},
};

static const struct itemplate instrux_HINT_NOP10[3] = {
    /*   0 : HINT_NOP10 rm16 [m:        o16 0f 19 /2                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(19) 202 : FL,UNDOC,P6 */
        {I_HINT_NOP10, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70214, 653},
    /*   1 : HINT_NOP10 rm32 [m:        o32 0f 19 /2                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(19) 202 : FL,UNDOC,P6 */
        {I_HINT_NOP10, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70220, 653},
    /*   2 : HINT_NOP10 rm64 [m:        o64 0f 19 /2                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(19) 202 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP10, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70226, 654},
};

static const struct itemplate instrux_HINT_NOP11[3] = {
    /*   0 : HINT_NOP11 rm16 [m:        o16 0f 19 /3                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(19) 203 : FL,UNDOC,P6 */
        {I_HINT_NOP11, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70232, 653},
    /*   1 : HINT_NOP11 rm32 [m:        o32 0f 19 /3                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(19) 203 : FL,UNDOC,P6 */
        {I_HINT_NOP11, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70238, 653},
    /*   2 : HINT_NOP11 rm64 [m:        o64 0f 19 /3                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(19) 203 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP11, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70244, 654},
};

static const struct itemplate instrux_HINT_NOP12[3] = {
    /*   0 : HINT_NOP12 rm16 [m:        o16 0f 19 /4                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(19) 204 : FL,UNDOC,P6 */
        {I_HINT_NOP12, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70250, 653},
    /*   1 : HINT_NOP12 rm32 [m:        o32 0f 19 /4                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(19) 204 : FL,UNDOC,P6 */
        {I_HINT_NOP12, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70256, 653},
    /*   2 : HINT_NOP12 rm64 [m:        o64 0f 19 /4                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(19) 204 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP12, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70262, 654},
};

static const struct itemplate instrux_HINT_NOP13[3] = {
    /*   0 : HINT_NOP13 rm16 [m:        o16 0f 19 /5                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(19) 205 : FL,UNDOC,P6 */
        {I_HINT_NOP13, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70268, 653},
    /*   1 : HINT_NOP13 rm32 [m:        o32 0f 19 /5                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(19) 205 : FL,UNDOC,P6 */
        {I_HINT_NOP13, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70274, 653},
    /*   2 : HINT_NOP13 rm64 [m:        o64 0f 19 /5                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(19) 205 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP13, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70280, 654},
};

static const struct itemplate instrux_HINT_NOP14[3] = {
    /*   0 : HINT_NOP14 rm16 [m:        o16 0f 19 /6                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(19) 206 : FL,UNDOC,P6 */
        {I_HINT_NOP14, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70286, 653},
    /*   1 : HINT_NOP14 rm32 [m:        o32 0f 19 /6                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(19) 206 : FL,UNDOC,P6 */
        {I_HINT_NOP14, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70292, 653},
    /*   2 : HINT_NOP14 rm64 [m:        o64 0f 19 /6                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(19) 206 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP14, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70298, 654},
};

static const struct itemplate instrux_HINT_NOP15[3] = {
    /*   0 : HINT_NOP15 rm16 [m:        o16 0f 19 /7                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(19) 207 : FL,UNDOC,P6 */
        {I_HINT_NOP15, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70304, 653},
    /*   1 : HINT_NOP15 rm32 [m:        o32 0f 19 /7                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(19) 207 : FL,UNDOC,P6 */
        {I_HINT_NOP15, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70310, 653},
    /*   2 : HINT_NOP15 rm64 [m:        o64 0f 19 /7                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(19) 207 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP15, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70316, 654},
};

static const struct itemplate instrux_HINT_NOP16[3] = {
    /*   0 : HINT_NOP16 rm16 [m:        o16 0f 1a /0                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1a) 200 : FL,UNDOC,P6 */
        {I_HINT_NOP16, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70322, 653},
    /*   1 : HINT_NOP16 rm32 [m:        o32 0f 1a /0                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1a) 200 : FL,UNDOC,P6 */
        {I_HINT_NOP16, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70328, 653},
    /*   2 : HINT_NOP16 rm64 [m:        o64 0f 1a /0                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1a) 200 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP16, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70334, 654},
};

static const struct itemplate instrux_HINT_NOP17[3] = {
    /*   0 : HINT_NOP17 rm16 [m:        o16 0f 1a /1                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1a) 201 : FL,UNDOC,P6 */
        {I_HINT_NOP17, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70340, 653},
    /*   1 : HINT_NOP17 rm32 [m:        o32 0f 1a /1                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1a) 201 : FL,UNDOC,P6 */
        {I_HINT_NOP17, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70346, 653},
    /*   2 : HINT_NOP17 rm64 [m:        o64 0f 1a /1                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1a) 201 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP17, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70352, 654},
};

static const struct itemplate instrux_HINT_NOP18[3] = {
    /*   0 : HINT_NOP18 rm16 [m:        o16 0f 1a /2                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1a) 202 : FL,UNDOC,P6 */
        {I_HINT_NOP18, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70358, 653},
    /*   1 : HINT_NOP18 rm32 [m:        o32 0f 1a /2                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1a) 202 : FL,UNDOC,P6 */
        {I_HINT_NOP18, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70364, 653},
    /*   2 : HINT_NOP18 rm64 [m:        o64 0f 1a /2                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1a) 202 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP18, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70370, 654},
};

static const struct itemplate instrux_HINT_NOP19[3] = {
    /*   0 : HINT_NOP19 rm16 [m:        o16 0f 1a /3                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1a) 203 : FL,UNDOC,P6 */
        {I_HINT_NOP19, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70376, 653},
    /*   1 : HINT_NOP19 rm32 [m:        o32 0f 1a /3                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1a) 203 : FL,UNDOC,P6 */
        {I_HINT_NOP19, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70382, 653},
    /*   2 : HINT_NOP19 rm64 [m:        o64 0f 1a /3                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1a) 203 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP19, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70388, 654},
};

static const struct itemplate instrux_HINT_NOP20[3] = {
    /*   0 : HINT_NOP20 rm16 [m:        o16 0f 1a /4                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1a) 204 : FL,UNDOC,P6 */
        {I_HINT_NOP20, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70394, 653},
    /*   1 : HINT_NOP20 rm32 [m:        o32 0f 1a /4                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1a) 204 : FL,UNDOC,P6 */
        {I_HINT_NOP20, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70400, 653},
    /*   2 : HINT_NOP20 rm64 [m:        o64 0f 1a /4                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1a) 204 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP20, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70406, 654},
};

static const struct itemplate instrux_HINT_NOP21[3] = {
    /*   0 : HINT_NOP21 rm16 [m:        o16 0f 1a /5                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1a) 205 : FL,UNDOC,P6 */
        {I_HINT_NOP21, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70412, 653},
    /*   1 : HINT_NOP21 rm32 [m:        o32 0f 1a /5                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1a) 205 : FL,UNDOC,P6 */
        {I_HINT_NOP21, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70418, 653},
    /*   2 : HINT_NOP21 rm64 [m:        o64 0f 1a /5                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1a) 205 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP21, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70424, 654},
};

static const struct itemplate instrux_HINT_NOP22[3] = {
    /*   0 : HINT_NOP22 rm16 [m:        o16 0f 1a /6                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1a) 206 : FL,UNDOC,P6 */
        {I_HINT_NOP22, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70430, 653},
    /*   1 : HINT_NOP22 rm32 [m:        o32 0f 1a /6                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1a) 206 : FL,UNDOC,P6 */
        {I_HINT_NOP22, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70436, 653},
    /*   2 : HINT_NOP22 rm64 [m:        o64 0f 1a /6                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1a) 206 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP22, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70442, 654},
};

static const struct itemplate instrux_HINT_NOP23[3] = {
    /*   0 : HINT_NOP23 rm16 [m:        o16 0f 1a /7                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1a) 207 : FL,UNDOC,P6 */
        {I_HINT_NOP23, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70448, 653},
    /*   1 : HINT_NOP23 rm32 [m:        o32 0f 1a /7                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1a) 207 : FL,UNDOC,P6 */
        {I_HINT_NOP23, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70454, 653},
    /*   2 : HINT_NOP23 rm64 [m:        o64 0f 1a /7                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1a) 207 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP23, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70460, 654},
};

static const struct itemplate instrux_HINT_NOP24[3] = {
    /*   0 : HINT_NOP24 rm16 [m:        o16 0f 1b /0                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1b) 200 : FL,UNDOC,P6 */
        {I_HINT_NOP24, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70466, 653},
    /*   1 : HINT_NOP24 rm32 [m:        o32 0f 1b /0                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1b) 200 : FL,UNDOC,P6 */
        {I_HINT_NOP24, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70472, 653},
    /*   2 : HINT_NOP24 rm64 [m:        o64 0f 1b /0                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1b) 200 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP24, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70478, 654},
};

static const struct itemplate instrux_HINT_NOP25[3] = {
    /*   0 : HINT_NOP25 rm16 [m:        o16 0f 1b /1                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1b) 201 : FL,UNDOC,P6 */
        {I_HINT_NOP25, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70484, 653},
    /*   1 : HINT_NOP25 rm32 [m:        o32 0f 1b /1                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1b) 201 : FL,UNDOC,P6 */
        {I_HINT_NOP25, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70490, 653},
    /*   2 : HINT_NOP25 rm64 [m:        o64 0f 1b /1                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1b) 201 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP25, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70496, 654},
};

static const struct itemplate instrux_HINT_NOP26[3] = {
    /*   0 : HINT_NOP26 rm16 [m:        o16 0f 1b /2                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1b) 202 : FL,UNDOC,P6 */
        {I_HINT_NOP26, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70502, 653},
    /*   1 : HINT_NOP26 rm32 [m:        o32 0f 1b /2                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1b) 202 : FL,UNDOC,P6 */
        {I_HINT_NOP26, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70508, 653},
    /*   2 : HINT_NOP26 rm64 [m:        o64 0f 1b /2                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1b) 202 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP26, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70514, 654},
};

static const struct itemplate instrux_HINT_NOP27[3] = {
    /*   0 : HINT_NOP27 rm16 [m:        o16 0f 1b /3                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1b) 203 : FL,UNDOC,P6 */
        {I_HINT_NOP27, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70520, 653},
    /*   1 : HINT_NOP27 rm32 [m:        o32 0f 1b /3                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1b) 203 : FL,UNDOC,P6 */
        {I_HINT_NOP27, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70526, 653},
    /*   2 : HINT_NOP27 rm64 [m:        o64 0f 1b /3                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1b) 203 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP27, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70532, 654},
};

static const struct itemplate instrux_HINT_NOP28[3] = {
    /*   0 : HINT_NOP28 rm16 [m:        o16 0f 1b /4                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1b) 204 : FL,UNDOC,P6 */
        {I_HINT_NOP28, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70538, 653},
    /*   1 : HINT_NOP28 rm32 [m:        o32 0f 1b /4                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1b) 204 : FL,UNDOC,P6 */
        {I_HINT_NOP28, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70544, 653},
    /*   2 : HINT_NOP28 rm64 [m:        o64 0f 1b /4                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1b) 204 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP28, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70550, 654},
};

static const struct itemplate instrux_HINT_NOP29[3] = {
    /*   0 : HINT_NOP29 rm16 [m:        o16 0f 1b /5                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1b) 205 : FL,UNDOC,P6 */
        {I_HINT_NOP29, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70556, 653},
    /*   1 : HINT_NOP29 rm32 [m:        o32 0f 1b /5                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1b) 205 : FL,UNDOC,P6 */
        {I_HINT_NOP29, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70562, 653},
    /*   2 : HINT_NOP29 rm64 [m:        o64 0f 1b /5                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1b) 205 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP29, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70568, 654},
};

static const struct itemplate instrux_HINT_NOP30[3] = {
    /*   0 : HINT_NOP30 rm16 [m:        o16 0f 1b /6                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1b) 206 : FL,UNDOC,P6 */
        {I_HINT_NOP30, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70574, 653},
    /*   1 : HINT_NOP30 rm32 [m:        o32 0f 1b /6                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1b) 206 : FL,UNDOC,P6 */
        {I_HINT_NOP30, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70580, 653},
    /*   2 : HINT_NOP30 rm64 [m:        o64 0f 1b /6                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1b) 206 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP30, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70586, 654},
};

static const struct itemplate instrux_HINT_NOP31[3] = {
    /*   0 : HINT_NOP31 rm16 [m:        o16 0f 1b /7                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1b) 207 : FL,UNDOC,P6 */
        {I_HINT_NOP31, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70592, 653},
    /*   1 : HINT_NOP31 rm32 [m:        o32 0f 1b /7                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1b) 207 : FL,UNDOC,P6 */
        {I_HINT_NOP31, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70598, 653},
    /*   2 : HINT_NOP31 rm64 [m:        o64 0f 1b /7                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1b) 207 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP31, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70604, 654},
};

static const struct itemplate instrux_HINT_NOP32[3] = {
    /*   0 : HINT_NOP32 rm16 [m:        o16 0f 1c /0                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1c) 200 : FL,UNDOC,P6 */
        {I_HINT_NOP32, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70610, 653},
    /*   1 : HINT_NOP32 rm32 [m:        o32 0f 1c /0                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1c) 200 : FL,UNDOC,P6 */
        {I_HINT_NOP32, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70616, 653},
    /*   2 : HINT_NOP32 rm64 [m:        o64 0f 1c /0                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1c) 200 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP32, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70622, 654},
};

static const struct itemplate instrux_HINT_NOP33[3] = {
    /*   0 : HINT_NOP33 rm16 [m:        o16 0f 1c /1                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1c) 201 : FL,UNDOC,P6 */
        {I_HINT_NOP33, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70628, 653},
    /*   1 : HINT_NOP33 rm32 [m:        o32 0f 1c /1                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1c) 201 : FL,UNDOC,P6 */
        {I_HINT_NOP33, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70634, 653},
    /*   2 : HINT_NOP33 rm64 [m:        o64 0f 1c /1                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1c) 201 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP33, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70640, 654},
};

static const struct itemplate instrux_HINT_NOP34[3] = {
    /*   0 : HINT_NOP34 rm16 [m:        o16 0f 1c /2                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1c) 202 : FL,UNDOC,P6 */
        {I_HINT_NOP34, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70646, 653},
    /*   1 : HINT_NOP34 rm32 [m:        o32 0f 1c /2                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1c) 202 : FL,UNDOC,P6 */
        {I_HINT_NOP34, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70652, 653},
    /*   2 : HINT_NOP34 rm64 [m:        o64 0f 1c /2                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1c) 202 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP34, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70658, 654},
};

static const struct itemplate instrux_HINT_NOP35[3] = {
    /*   0 : HINT_NOP35 rm16 [m:        o16 0f 1c /3                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1c) 203 : FL,UNDOC,P6 */
        {I_HINT_NOP35, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70664, 653},
    /*   1 : HINT_NOP35 rm32 [m:        o32 0f 1c /3                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1c) 203 : FL,UNDOC,P6 */
        {I_HINT_NOP35, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70670, 653},
    /*   2 : HINT_NOP35 rm64 [m:        o64 0f 1c /3                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1c) 203 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP35, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70676, 654},
};

static const struct itemplate instrux_HINT_NOP36[3] = {
    /*   0 : HINT_NOP36 rm16 [m:        o16 0f 1c /4                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1c) 204 : FL,UNDOC,P6 */
        {I_HINT_NOP36, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70682, 653},
    /*   1 : HINT_NOP36 rm32 [m:        o32 0f 1c /4                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1c) 204 : FL,UNDOC,P6 */
        {I_HINT_NOP36, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70688, 653},
    /*   2 : HINT_NOP36 rm64 [m:        o64 0f 1c /4                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1c) 204 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP36, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70694, 654},
};

static const struct itemplate instrux_HINT_NOP37[3] = {
    /*   0 : HINT_NOP37 rm16 [m:        o16 0f 1c /5                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1c) 205 : FL,UNDOC,P6 */
        {I_HINT_NOP37, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70700, 653},
    /*   1 : HINT_NOP37 rm32 [m:        o32 0f 1c /5                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1c) 205 : FL,UNDOC,P6 */
        {I_HINT_NOP37, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70706, 653},
    /*   2 : HINT_NOP37 rm64 [m:        o64 0f 1c /5                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1c) 205 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP37, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70712, 654},
};

static const struct itemplate instrux_HINT_NOP38[3] = {
    /*   0 : HINT_NOP38 rm16 [m:        o16 0f 1c /6                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1c) 206 : FL,UNDOC,P6 */
        {I_HINT_NOP38, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70718, 653},
    /*   1 : HINT_NOP38 rm32 [m:        o32 0f 1c /6                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1c) 206 : FL,UNDOC,P6 */
        {I_HINT_NOP38, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70724, 653},
    /*   2 : HINT_NOP38 rm64 [m:        o64 0f 1c /6                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1c) 206 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP38, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70730, 654},
};

static const struct itemplate instrux_HINT_NOP39[3] = {
    /*   0 : HINT_NOP39 rm16 [m:        o16 0f 1c /7                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1c) 207 : FL,UNDOC,P6 */
        {I_HINT_NOP39, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70736, 653},
    /*   1 : HINT_NOP39 rm32 [m:        o32 0f 1c /7                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1c) 207 : FL,UNDOC,P6 */
        {I_HINT_NOP39, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70742, 653},
    /*   2 : HINT_NOP39 rm64 [m:        o64 0f 1c /7                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1c) 207 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP39, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70748, 654},
};

static const struct itemplate instrux_HINT_NOP40[3] = {
    /*   0 : HINT_NOP40 rm16 [m:        o16 0f 1d /0                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1d) 200 : FL,UNDOC,P6 */
        {I_HINT_NOP40, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70754, 653},
    /*   1 : HINT_NOP40 rm32 [m:        o32 0f 1d /0                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1d) 200 : FL,UNDOC,P6 */
        {I_HINT_NOP40, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70760, 653},
    /*   2 : HINT_NOP40 rm64 [m:        o64 0f 1d /0                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1d) 200 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP40, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70766, 654},
};

static const struct itemplate instrux_HINT_NOP41[3] = {
    /*   0 : HINT_NOP41 rm16 [m:        o16 0f 1d /1                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1d) 201 : FL,UNDOC,P6 */
        {I_HINT_NOP41, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70772, 653},
    /*   1 : HINT_NOP41 rm32 [m:        o32 0f 1d /1                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1d) 201 : FL,UNDOC,P6 */
        {I_HINT_NOP41, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70778, 653},
    /*   2 : HINT_NOP41 rm64 [m:        o64 0f 1d /1                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1d) 201 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP41, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70784, 654},
};

static const struct itemplate instrux_HINT_NOP42[3] = {
    /*   0 : HINT_NOP42 rm16 [m:        o16 0f 1d /2                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1d) 202 : FL,UNDOC,P6 */
        {I_HINT_NOP42, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70790, 653},
    /*   1 : HINT_NOP42 rm32 [m:        o32 0f 1d /2                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1d) 202 : FL,UNDOC,P6 */
        {I_HINT_NOP42, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70796, 653},
    /*   2 : HINT_NOP42 rm64 [m:        o64 0f 1d /2                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1d) 202 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP42, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70802, 654},
};

static const struct itemplate instrux_HINT_NOP43[3] = {
    /*   0 : HINT_NOP43 rm16 [m:        o16 0f 1d /3                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1d) 203 : FL,UNDOC,P6 */
        {I_HINT_NOP43, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70808, 653},
    /*   1 : HINT_NOP43 rm32 [m:        o32 0f 1d /3                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1d) 203 : FL,UNDOC,P6 */
        {I_HINT_NOP43, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70814, 653},
    /*   2 : HINT_NOP43 rm64 [m:        o64 0f 1d /3                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1d) 203 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP43, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70820, 654},
};

static const struct itemplate instrux_HINT_NOP44[3] = {
    /*   0 : HINT_NOP44 rm16 [m:        o16 0f 1d /4                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1d) 204 : FL,UNDOC,P6 */
        {I_HINT_NOP44, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70826, 653},
    /*   1 : HINT_NOP44 rm32 [m:        o32 0f 1d /4                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1d) 204 : FL,UNDOC,P6 */
        {I_HINT_NOP44, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70832, 653},
    /*   2 : HINT_NOP44 rm64 [m:        o64 0f 1d /4                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1d) 204 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP44, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70838, 654},
};

static const struct itemplate instrux_HINT_NOP45[3] = {
    /*   0 : HINT_NOP45 rm16 [m:        o16 0f 1d /5                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1d) 205 : FL,UNDOC,P6 */
        {I_HINT_NOP45, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70844, 653},
    /*   1 : HINT_NOP45 rm32 [m:        o32 0f 1d /5                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1d) 205 : FL,UNDOC,P6 */
        {I_HINT_NOP45, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70850, 653},
    /*   2 : HINT_NOP45 rm64 [m:        o64 0f 1d /5                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1d) 205 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP45, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70856, 654},
};

static const struct itemplate instrux_HINT_NOP46[3] = {
    /*   0 : HINT_NOP46 rm16 [m:        o16 0f 1d /6                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1d) 206 : FL,UNDOC,P6 */
        {I_HINT_NOP46, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70862, 653},
    /*   1 : HINT_NOP46 rm32 [m:        o32 0f 1d /6                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1d) 206 : FL,UNDOC,P6 */
        {I_HINT_NOP46, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70868, 653},
    /*   2 : HINT_NOP46 rm64 [m:        o64 0f 1d /6                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1d) 206 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP46, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70874, 654},
};

static const struct itemplate instrux_HINT_NOP47[3] = {
    /*   0 : HINT_NOP47 rm16 [m:        o16 0f 1d /7                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1d) 207 : FL,UNDOC,P6 */
        {I_HINT_NOP47, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70880, 653},
    /*   1 : HINT_NOP47 rm32 [m:        o32 0f 1d /7                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1d) 207 : FL,UNDOC,P6 */
        {I_HINT_NOP47, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70886, 653},
    /*   2 : HINT_NOP47 rm64 [m:        o64 0f 1d /7                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1d) 207 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP47, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70892, 654},
};

static const struct itemplate instrux_HINT_NOP48[3] = {
    /*   0 : HINT_NOP48 rm16 [m:        o16 0f 1e /0                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1e) 200 : FL,UNDOC,P6 */
        {I_HINT_NOP48, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70898, 653},
    /*   1 : HINT_NOP48 rm32 [m:        o32 0f 1e /0                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1e) 200 : FL,UNDOC,P6 */
        {I_HINT_NOP48, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70904, 653},
    /*   2 : HINT_NOP48 rm64 [m:        o64 0f 1e /0                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1e) 200 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP48, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70910, 654},
};

static const struct itemplate instrux_HINT_NOP49[3] = {
    /*   0 : HINT_NOP49 rm16 [m:        o16 0f 1e /1                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1e) 201 : FL,UNDOC,P6 */
        {I_HINT_NOP49, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70916, 653},
    /*   1 : HINT_NOP49 rm32 [m:        o32 0f 1e /1                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1e) 201 : FL,UNDOC,P6 */
        {I_HINT_NOP49, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70922, 653},
    /*   2 : HINT_NOP49 rm64 [m:        o64 0f 1e /1                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1e) 201 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP49, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70928, 654},
};

static const struct itemplate instrux_HINT_NOP50[3] = {
    /*   0 : HINT_NOP50 rm16 [m:        o16 0f 1e /2                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1e) 202 : FL,UNDOC,P6 */
        {I_HINT_NOP50, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70934, 653},
    /*   1 : HINT_NOP50 rm32 [m:        o32 0f 1e /2                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1e) 202 : FL,UNDOC,P6 */
        {I_HINT_NOP50, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70940, 653},
    /*   2 : HINT_NOP50 rm64 [m:        o64 0f 1e /2                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1e) 202 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP50, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70946, 654},
};

static const struct itemplate instrux_HINT_NOP51[3] = {
    /*   0 : HINT_NOP51 rm16 [m:        o16 0f 1e /3                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1e) 203 : FL,UNDOC,P6 */
        {I_HINT_NOP51, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70952, 653},
    /*   1 : HINT_NOP51 rm32 [m:        o32 0f 1e /3                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1e) 203 : FL,UNDOC,P6 */
        {I_HINT_NOP51, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70958, 653},
    /*   2 : HINT_NOP51 rm64 [m:        o64 0f 1e /3                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1e) 203 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP51, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70964, 654},
};

static const struct itemplate instrux_HINT_NOP52[3] = {
    /*   0 : HINT_NOP52 rm16 [m:        o16 0f 1e /4                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1e) 204 : FL,UNDOC,P6 */
        {I_HINT_NOP52, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70970, 653},
    /*   1 : HINT_NOP52 rm32 [m:        o32 0f 1e /4                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1e) 204 : FL,UNDOC,P6 */
        {I_HINT_NOP52, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70976, 653},
    /*   2 : HINT_NOP52 rm64 [m:        o64 0f 1e /4                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1e) 204 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP52, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70982, 654},
};

static const struct itemplate instrux_HINT_NOP53[3] = {
    /*   0 : HINT_NOP53 rm16 [m:        o16 0f 1e /5                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1e) 205 : FL,UNDOC,P6 */
        {I_HINT_NOP53, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70988, 653},
    /*   1 : HINT_NOP53 rm32 [m:        o32 0f 1e /5                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1e) 205 : FL,UNDOC,P6 */
        {I_HINT_NOP53, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+70994, 653},
    /*   2 : HINT_NOP53 rm64 [m:        o64 0f 1e /5                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1e) 205 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP53, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71000, 654},
};

static const struct itemplate instrux_HINT_NOP54[3] = {
    /*   0 : HINT_NOP54 rm16 [m:        o16 0f 1e /6                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1e) 206 : FL,UNDOC,P6 */
        {I_HINT_NOP54, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71006, 653},
    /*   1 : HINT_NOP54 rm32 [m:        o32 0f 1e /6                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1e) 206 : FL,UNDOC,P6 */
        {I_HINT_NOP54, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71012, 653},
    /*   2 : HINT_NOP54 rm64 [m:        o64 0f 1e /6                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1e) 206 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP54, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71018, 654},
};

static const struct itemplate instrux_HINT_NOP55[3] = {
    /*   0 : HINT_NOP55 rm16 [m:        o16 0f 1e /7                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1e) 207 : FL,UNDOC,P6 */
        {I_HINT_NOP55, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71024, 653},
    /*   1 : HINT_NOP55 rm32 [m:        o32 0f 1e /7                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1e) 207 : FL,UNDOC,P6 */
        {I_HINT_NOP55, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71030, 653},
    /*   2 : HINT_NOP55 rm64 [m:        o64 0f 1e /7                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1e) 207 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP55, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71036, 654},
};

static const struct itemplate instrux_HINT_NOP56[3] = {
    /*   0 : HINT_NOP56 rm16 [m:        o16 0f 1f /0                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1f) 200 : FL,UNDOC,P6 */
        {I_HINT_NOP56, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66236, 653},
    /*   1 : HINT_NOP56 rm32 [m:        o32 0f 1f /0                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1f) 200 : FL,UNDOC,P6 */
        {I_HINT_NOP56, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66242, 653},
    /*   2 : HINT_NOP56 rm64 [m:        o64 0f 1f /0                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1f) 200 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP56, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+66248, 654},
};

static const struct itemplate instrux_HINT_NOP57[3] = {
    /*   0 : HINT_NOP57 rm16 [m:        o16 0f 1f /1                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1f) 201 : FL,UNDOC,P6 */
        {I_HINT_NOP57, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71042, 653},
    /*   1 : HINT_NOP57 rm32 [m:        o32 0f 1f /1                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1f) 201 : FL,UNDOC,P6 */
        {I_HINT_NOP57, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71048, 653},
    /*   2 : HINT_NOP57 rm64 [m:        o64 0f 1f /1                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1f) 201 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP57, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71054, 654},
};

static const struct itemplate instrux_HINT_NOP58[3] = {
    /*   0 : HINT_NOP58 rm16 [m:        o16 0f 1f /2                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1f) 202 : FL,UNDOC,P6 */
        {I_HINT_NOP58, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71060, 653},
    /*   1 : HINT_NOP58 rm32 [m:        o32 0f 1f /2                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1f) 202 : FL,UNDOC,P6 */
        {I_HINT_NOP58, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71066, 653},
    /*   2 : HINT_NOP58 rm64 [m:        o64 0f 1f /2                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1f) 202 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP58, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71072, 654},
};

static const struct itemplate instrux_HINT_NOP59[3] = {
    /*   0 : HINT_NOP59 rm16 [m:        o16 0f 1f /3                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1f) 203 : FL,UNDOC,P6 */
        {I_HINT_NOP59, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71078, 653},
    /*   1 : HINT_NOP59 rm32 [m:        o32 0f 1f /3                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1f) 203 : FL,UNDOC,P6 */
        {I_HINT_NOP59, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71084, 653},
    /*   2 : HINT_NOP59 rm64 [m:        o64 0f 1f /3                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1f) 203 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP59, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71090, 654},
};

static const struct itemplate instrux_HINT_NOP60[3] = {
    /*   0 : HINT_NOP60 rm16 [m:        o16 0f 1f /4                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1f) 204 : FL,UNDOC,P6 */
        {I_HINT_NOP60, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71096, 653},
    /*   1 : HINT_NOP60 rm32 [m:        o32 0f 1f /4                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1f) 204 : FL,UNDOC,P6 */
        {I_HINT_NOP60, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71102, 653},
    /*   2 : HINT_NOP60 rm64 [m:        o64 0f 1f /4                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1f) 204 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP60, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71108, 654},
};

static const struct itemplate instrux_HINT_NOP61[3] = {
    /*   0 : HINT_NOP61 rm16 [m:        o16 0f 1f /5                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1f) 205 : FL,UNDOC,P6 */
        {I_HINT_NOP61, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71114, 653},
    /*   1 : HINT_NOP61 rm32 [m:        o32 0f 1f /5                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1f) 205 : FL,UNDOC,P6 */
        {I_HINT_NOP61, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71120, 653},
    /*   2 : HINT_NOP61 rm64 [m:        o64 0f 1f /5                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1f) 205 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP61, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71126, 654},
};

static const struct itemplate instrux_HINT_NOP62[3] = {
    /*   0 : HINT_NOP62 rm16 [m:        o16 0f 1f /6                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1f) 206 : FL,UNDOC,P6 */
        {I_HINT_NOP62, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71132, 653},
    /*   1 : HINT_NOP62 rm32 [m:        o32 0f 1f /6                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1f) 206 : FL,UNDOC,P6 */
        {I_HINT_NOP62, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71138, 653},
    /*   2 : HINT_NOP62 rm64 [m:        o64 0f 1f /6                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1f) 206 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP62, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71144, 654},
};

static const struct itemplate instrux_HINT_NOP63[3] = {
    /*   0 : HINT_NOP63 rm16 [m:        o16 0f 1f /7                      ] ND,FL,UNDOC,P6 */
        /* 320 355 001(1f) 207 : FL,UNDOC,P6 */
        {I_HINT_NOP63, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71150, 653},
    /*   1 : HINT_NOP63 rm32 [m:        o32 0f 1f /7                      ] ND,FL,UNDOC,P6 */
        /* 321 355 001(1f) 207 : FL,UNDOC,P6 */
        {I_HINT_NOP63, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71156, 653},
    /*   2 : HINT_NOP63 rm64 [m:        o64 0f 1f /7                      ] ND,LONG,FL,PROT,UNDOC,X86_64 */
        /* 324 355 001(1f) 207 : LONG,FL,PROT,UNDOC,X86_64 */
        {I_HINT_NOP63, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+71162, 654},
};

const struct itemplate_list nasm_instructions[2636] = {
    {   0, NULL /* DB */ },
    {   0, NULL /* DW */ },
    {   0, NULL /* DD */ },
    {   0, NULL /* DQ */ },
    {   0, NULL /* DT */ },
    {   0, NULL /* DO */ },
    {   0, NULL /* DY */ },
    {   0, NULL /* DZ */ },
    {   1, instrux_RESB },
    {   1, instrux_RESW },
    {   1, instrux_RESD },
    {   1, instrux_RESQ },
    {   1, instrux_REST },
    {   1, instrux_RESO },
    {   1, instrux_RESY },
    {   1, instrux_RESZ },
    {   0, NULL /* INCBIN */ },
    {   3, instrux_EQU },
    {   7, instrux_NOP },
    {   1, instrux_NOP2 },
    {  84, instrux_MOV },
    {  12, instrux_MOVABS },
    {   8, instrux_MOVRS },
    {   6, instrux_LEA },
    {  80, instrux_ADD },
    {  80, instrux_OR },
    {  64, instrux_ADC },
    {  64, instrux_SBB },
    {  80, instrux_AND },
    {  64, instrux_SUB },
    {  80, instrux_XOR },
    {  19, instrux_CMP },
    {  24, instrux_TEST },
    { 100, instrux_ROL },
    { 100, instrux_ROR },
    {  96, instrux_RCL },
    {  96, instrux_RCR },
    { 136, instrux_SHL },
    { 128, instrux_SAL },
    { 136, instrux_SHR },
    { 128, instrux_SAR },
    {   4, instrux_RORX },
    {   4, instrux_ROLX },
    {  32, instrux_SHLX },
    {  32, instrux_SALX },
    {  32, instrux_SARX },
    {  32, instrux_SHRX },
    {  18, instrux_INC },
    {  18, instrux_DEC },
    {  38, instrux_IMUL },
    {  42, instrux_MUL },
    {   8, instrux_MULX },
    {   8, instrux_IDIV },
    {   8, instrux_DIV },
    {  16, instrux_NEG },
    {  32, instrux_NOT },
    {   6, instrux_ADCX },
    {   6, instrux_ADOX },
    {  26, instrux_SHLD },
    {  26, instrux_SHRD },
    {   6, instrux_BT },
    {   6, instrux_BTC },
    {   6, instrux_BTR },
    {   6, instrux_BTS },
    {   3, instrux_BSF },
    {   3, instrux_BSR },
    {   2, instrux_IBTS },
    {   2, instrux_XBTS },
    {   6, instrux_LZCNT },
    {   6, instrux_TZCNT },
    {  24, instrux_ANDN },
    {  12, instrux_BEXTR },
    {   4, instrux_BLSMSK },
    {   4, instrux_BLSR },
    {   4, instrux_BLSI },
    {   8, instrux_BZHI },
    {   8, instrux_PDEP },
    {   8, instrux_PEXT },
    {   2, instrux_BLCI },
    {   2, instrux_BLCIC },
    {   2, instrux_BLSIC },
    {   2, instrux_BLCFILL },
    {   2, instrux_BLSFILL },
    {   2, instrux_BLCMSK },
    {   2, instrux_BLCS },
    {   2, instrux_TZMSK },
    {   2, instrux_T1MSKC },
    {   1, instrux_AAA },
    {   2, instrux_AAD },
    {   2, instrux_AAM },
    {   1, instrux_AAS },
    {   1, instrux_DAA },
    {   1, instrux_DAS },
    {   6, instrux_BSWAP },
    {  12, instrux_MOVBE },
    {   1, instrux_CBW },
    {   1, instrux_CDQ },
    {   1, instrux_CDQE },
    {   1, instrux_CQO },
    {   1, instrux_CWD },
    {   1, instrux_CWDE },
    {  12, instrux_MOVSX },
    {   4, instrux_MOVSXB },
    {   4, instrux_MOVSXW },
    {   4, instrux_MOVSXD },
    {   9, instrux_MOVZX },
    {   3, instrux_MOVZXB },
    {   3, instrux_MOVZXW },
    {   3, instrux_MOVZXD },
    {   4, instrux_CMPXCHG },
    {   1, instrux_CMPXCHG8B },
    {   1, instrux_CMPXCHG16B },
    {   4, instrux_XADD },
    {  15, instrux_XCHG },
    {   3, instrux_CMPXCHG486 },
    {   2, instrux_JMPABS },
    {  28, instrux_JMP },
    {  12, instrux_JA },
    {  12, instrux_JAE },
    {  12, instrux_JB },
    {  12, instrux_JBE },
    {  12, instrux_JC },
    {  12, instrux_JE },
    {  12, instrux_JG },
    {  12, instrux_JGE },
    {  12, instrux_JL },
    {  12, instrux_JLE },
    {  12, instrux_JNA },
    {  12, instrux_JNAE },
    {  12, instrux_JNB },
    {  12, instrux_JNBE },
    {  12, instrux_JNC },
    {  12, instrux_JNE },
    {  12, instrux_JNG },
    {  12, instrux_JNGE },
    {  12, instrux_JNL },
    {  12, instrux_JNLE },
    {  12, instrux_JNO },
    {  12, instrux_JNP },
    {  12, instrux_JNS },
    {  12, instrux_JNZ },
    {  12, instrux_JO },
    {  12, instrux_JP },
    {  12, instrux_JPE },
    {  12, instrux_JPO },
    {  12, instrux_JS },
    {  12, instrux_JZ },
    {   8, instrux_JCXZ },
    {   3, instrux_JECXZ },
    {   1, instrux_JRCXZ },
    {   9, instrux_LOOP },
    {   2, instrux_LOOPW },
    {   3, instrux_LOOPD },
    {   1, instrux_LOOPQ },
    {   9, instrux_LOOPE },
    {   2, instrux_LOOPEW },
    {   3, instrux_LOOPED },
    {   1, instrux_LOOPEQ },
    {   9, instrux_LOOPNE },
    {   2, instrux_LOOPNEW },
    {   3, instrux_LOOPNED },
    {   1, instrux_LOOPNEQ },
    {   9, instrux_LOOPZ },
    {   2, instrux_LOOPZW },
    {   3, instrux_LOOPZD },
    {   1, instrux_LOOPZQ },
    {   9, instrux_LOOPNZ },
    {   2, instrux_LOOPNZW },
    {   3, instrux_LOOPNZD },
    {   1, instrux_LOOPNZQ },
    {   9, instrux_JMPE },
    {  20, instrux_CALL },
    {   2, instrux_RET },
    {   2, instrux_RETW },
    {   2, instrux_RETD },
    {   2, instrux_RETQ },
    {   2, instrux_RETF },
    {   2, instrux_RETFW },
    {   2, instrux_RETFD },
    {   2, instrux_RETFQ },
    {   2, instrux_RETN },
    {   2, instrux_RETNW },
    {   2, instrux_RETND },
    {   2, instrux_RETNQ },
    {   1, instrux_INT },
    {   1, instrux_INT1 },
    {   1, instrux_INT01 },
    {   1, instrux_ICEBP },
    {   1, instrux_INT3 },
    {   1, instrux_INT03 },
    {   1, instrux_BRKPT },
    {   1, instrux_INTO },
    {   1, instrux_SYSCALL },
    {   1, instrux_SYSENTER },
    {   1, instrux_SYSEXIT },
    {   1, instrux_SYSRET },
    {   1, instrux_IRET },
    {   1, instrux_IRETW },
    {   1, instrux_IRETD },
    {   1, instrux_IRETQ },
    {   1, instrux_ERETS },
    {   1, instrux_ERETU },
    {   1, instrux_CLC },
    {   1, instrux_CLD },
    {   1, instrux_CLI },
    {   1, instrux_CLAC },
    {   1, instrux_STC },
    {   1, instrux_STD },
    {   1, instrux_STI },
    {   1, instrux_STAC },
    {   1, instrux_CMC },
    {   1, instrux_LAHF },
    {   1, instrux_SAHF },
    {   1, instrux_SALC },
    {   1, instrux_PUSHF },
    {   1, instrux_PUSHFW },
    {   1, instrux_PUSHFD },
    {   1, instrux_PUSHFQ },
    {   1, instrux_POPF },
    {   1, instrux_POPFW },
    {   1, instrux_POPFD },
    {   1, instrux_POPFQ },
    {   1, instrux_CMPSB },
    {   1, instrux_CMPSW },
    {   2, instrux_CMPSD },
    {   1, instrux_CMPSQ },
    {   1, instrux_LODSB },
    {   1, instrux_LODSW },
    {   1, instrux_LODSD },
    {   1, instrux_LODSQ },
    {   1, instrux_MOVSB },
    {   1, instrux_MOVSW },
    {   3, instrux_MOVSD },
    {   1, instrux_MOVSQ },
    {   1, instrux_STOSB },
    {   1, instrux_STOSW },
    {   1, instrux_STOSD },
    {   1, instrux_STOSQ },
    {   1, instrux_SCASB },
    {   1, instrux_SCASW },
    {   1, instrux_SCASD },
    {   1, instrux_SCASQ },
    {   1, instrux_INSB },
    {   1, instrux_INSW },
    {   1, instrux_INSD },
    {   1, instrux_OUTSB },
    {   1, instrux_OUTSW },
    {   1, instrux_OUTSD },
    {   2, instrux_LFENCE },
    {   2, instrux_MFENCE },
    {   2, instrux_SFENCE },
    {   1, instrux_SERIALIZE },
    {   1, instrux_CLFLUSH },
    {   1, instrux_CLFLUSHOPT },
    {   1, instrux_CLWB },
    {   1, instrux_PCOMMIT },
    {   4, instrux_CLZERO },
    {   1, instrux_INVD },
    {   1, instrux_WBINVD },
    {   1, instrux_WBNOINVD },
    {   3, instrux_INVPCID },
    {   1, instrux_INVLPG },
    {   4, instrux_INVLPGA },
    {   1, instrux_RDPMC },
    {   1, instrux_RDTSC },
    {   1, instrux_RDTSCP },
    {   3, instrux_RDRAND },
    {   3, instrux_RDSEED },
    {   3, instrux_RDPID },
    {   1, instrux_CLTS },
    {   1, instrux_CPUID },
    {   1, instrux_LMSW },
    {   5, instrux_SMSW },
    {   1, instrux_WRMSR },
    {   3, instrux_RDMSR },
    {   3, instrux_WRMSRNS },
    {   1, instrux_RDMSRLIST },
    {   1, instrux_WRMSRLIST },
    {   4, instrux_URDMSR },
    {   4, instrux_UWRMSR },
    {   6, instrux_UMOV },
    {   1, instrux_BB0_RESET },
    {   1, instrux_BB1_RESET },
    {   1, instrux_CPU_READ },
    {   1, instrux_CPU_WRITE },
    {   1, instrux_DMINT },
    {   1, instrux_RDM },
    {   1, instrux_SMINT },
    {   1, instrux_SMINTOLD },
    {   1, instrux_RSM },
    {   1, instrux_WRSHR },
    {   1, instrux_RDSHR },
    {   1, instrux_RSDC },
    {   1, instrux_RSLDT },
    {   1, instrux_RSTS },
    {   1, instrux_SVDC },
    {   1, instrux_SVLDT },
    {   1, instrux_SVTS },
    {   1, instrux_HLT },
    {   1, instrux_PAUSE },
    {   4, instrux_MONITOR },
    {   1, instrux_MONITORW },
    {   1, instrux_MONITORD },
    {   1, instrux_MONITORQ },
    {   2, instrux_MWAIT },
    {   7, instrux_MONITORX },
    {   2, instrux_MWAITX },
    {   2, instrux_TPAUSE },
    {   3, instrux_UMONITOR },
    {   2, instrux_UMWAIT },
    {   6, instrux_IN },
    {   6, instrux_OUT },
    {   2, instrux_LDS },
    {   2, instrux_LES },
    {   3, instrux_LFS },
    {   3, instrux_LGS },
    {   3, instrux_LSS },
    {  21, instrux_PUSH },
    {  14, instrux_POP },
    {   2, instrux_RDFSBASE },
    {   2, instrux_RDGSBASE },
    {   2, instrux_WRFSBASE },
    {   2, instrux_WRGSBASE },
    {   2, instrux_ARPL },
    {   3, instrux_LAR },
    {   3, instrux_LSL },
    {   1, instrux_VERR },
    {   1, instrux_VERW },
    {   1, instrux_SWAPGS },
    {   1, instrux_LKGS },
    {   3, instrux_LGDT },
    {   3, instrux_LIDT },
    {   4, instrux_LLDT },
    {   4, instrux_LTR },
    {   3, instrux_SGDT },
    {   3, instrux_SIDT },
    {   4, instrux_SLDT },
    {   4, instrux_STR },
    {   1, instrux_LOADALL },
    {   1, instrux_LOADALL286 },
    {   1, instrux_F2XM1 },
    {   1, instrux_FABS },
    {   7, instrux_FADD },
    {   3, instrux_FADDP },
    {   2, instrux_FBLD },
    {   2, instrux_FBSTP },
    {   1, instrux_FCHS },
    {   1, instrux_FCLEX },
    {   3, instrux_FCMOVB },
    {   3, instrux_FCMOVBE },
    {   3, instrux_FCMOVE },
    {   3, instrux_FCMOVNB },
    {   3, instrux_FCMOVNBE },
    {   3, instrux_FCMOVNE },
    {   3, instrux_FCMOVNU },
    {   3, instrux_FCMOVU },
    {   5, instrux_FCOM },
    {   3, instrux_FCOMI },
    {   3, instrux_FCOMIP },
    {   5, instrux_FCOMP },
    {   1, instrux_FCOMPP },
    {   1, instrux_FCOS },
    {   1, instrux_FDECSTP },
    {   1, instrux_FDISI },
    {   7, instrux_FDIV },
    {   3, instrux_FDIVP },
    {   7, instrux_FDIVR },
    {   3, instrux_FDIVRP },
    {   1, instrux_FEMMS },
    {   1, instrux_FENI },
    {   2, instrux_FFREE },
    {   2, instrux_FFREEP },
    {   2, instrux_FIADD },
    {   2, instrux_FICOM },
    {   2, instrux_FICOMP },
    {   2, instrux_FIDIV },
    {   2, instrux_FIDIVR },
    {   3, instrux_FILD },
    {   2, instrux_FIMUL },
    {   1, instrux_FINCSTP },
    {   1, instrux_FINIT },
    {   2, instrux_FIST },
    {   3, instrux_FISTP },
    {   3, instrux_FISTTP },
    {   2, instrux_FISUB },
    {   2, instrux_FISUBR },
    {   5, instrux_FLD },
    {   1, instrux_FLD1 },
    {   1, instrux_FLDCW },
    {   1, instrux_FLDENV },
    {   1, instrux_FLDL2E },
    {   1, instrux_FLDL2T },
    {   1, instrux_FLDLG2 },
    {   1, instrux_FLDLN2 },
    {   1, instrux_FLDPI },
    {   1, instrux_FLDZ },
    {   7, instrux_FMUL },
    {   3, instrux_FMULP },
    {   1, instrux_FNCLEX },
    {   1, instrux_FNDISI },
    {   1, instrux_FNENI },
    {   1, instrux_FNINIT },
    {   1, instrux_FNOP },
    {   1, instrux_FNSAVE },
    {   1, instrux_FNSTCW },
    {   1, instrux_FNSTENV },
    {   2, instrux_FNSTSW },
    {   1, instrux_FPATAN },
    {   1, instrux_FPREM },
    {   1, instrux_FPREM1 },
    {   1, instrux_FPTAN },
    {   1, instrux_FRNDINT },
    {   1, instrux_FRSTOR },
    {   1, instrux_FSAVE },
    {   1, instrux_FSCALE },
    {   1, instrux_FSETPM },
    {   1, instrux_FSIN },
    {   1, instrux_FSINCOS },
    {   1, instrux_FSQRT },
    {   4, instrux_FST },
    {   1, instrux_FSTCW },
    {   1, instrux_FSTENV },
    {   5, instrux_FSTP },
    {   2, instrux_FSTSW },
    {   7, instrux_FSUB },
    {   3, instrux_FSUBP },
    {   7, instrux_FSUBR },
    {   3, instrux_FSUBRP },
    {   1, instrux_FTST },
    {   3, instrux_FUCOM },
    {   3, instrux_FUCOMI },
    {   3, instrux_FUCOMIP },
    {   3, instrux_FUCOMP },
    {   1, instrux_FUCOMPP },
    {   1, instrux_FXAM },
    {   4, instrux_FXCH },
    {   1, instrux_FXTRACT },
    {   1, instrux_FYL2X },
    {   1, instrux_FYL2XP1 },
    {   1, instrux_EMMS },
    {  16, instrux_MOVD },
    {  18, instrux_MOVQ },
    {   2, instrux_PACKSSDW },
    {   2, instrux_PACKSSWB },
    {   2, instrux_PACKUSWB },
    {   2, instrux_PADDB },
    {   2, instrux_PADDD },
    {   2, instrux_PADDSB },
    {   1, instrux_PADDSIW },
    {   2, instrux_PADDSW },
    {   2, instrux_PADDUSB },
    {   2, instrux_PADDUSW },
    {   2, instrux_PADDW },
    {   2, instrux_PAND },
    {   2, instrux_PANDN },
    {   1, instrux_PAVEB },
    {   1, instrux_PAVGUSB },
    {   2, instrux_PCMPEQB },
    {   2, instrux_PCMPEQD },
    {   2, instrux_PCMPEQW },
    {   2, instrux_PCMPGTB },
    {   2, instrux_PCMPGTD },
    {   2, instrux_PCMPGTW },
    {   1, instrux_PDISTIB },
    {   1, instrux_PF2ID },
    {   1, instrux_PFACC },
    {   1, instrux_PFADD },
    {   1, instrux_PFCMPEQ },
    {   1, instrux_PFCMPGE },
    {   1, instrux_PFCMPGT },
    {   1, instrux_PFMAX },
    {   1, instrux_PFMIN },
    {   1, instrux_PFMUL },
    {   1, instrux_PFRCP },
    {   1, instrux_PFRCPIT1 },
    {   1, instrux_PFRCPIT2 },
    {   1, instrux_PFRSQIT1 },
    {   1, instrux_PFRSQRT },
    {   1, instrux_PFSUB },
    {   1, instrux_PFSUBR },
    {   1, instrux_PI2FD },
    {   1, instrux_PMACHRIW },
    {   2, instrux_PMADDWD },
    {   1, instrux_PMAGW },
    {   1, instrux_PMULHRIW },
    {   1, instrux_PMULHRWA },
    {   1, instrux_PMULHRWC },
    {   2, instrux_PMULHW },
    {   2, instrux_PMULLW },
    {   1, instrux_PMVGEZB },
    {   1, instrux_PMVLZB },
    {   1, instrux_PMVNZB },
    {   1, instrux_PMVZB },
    {   2, instrux_POR },
    {   1, instrux_PREFETCH },
    {   1, instrux_PREFETCHW },
    {   4, instrux_PSLLD },
    {   4, instrux_PSLLQ },
    {   4, instrux_PSLLW },
    {   4, instrux_PSRAD },
    {   4, instrux_PSRAW },
    {   4, instrux_PSRLD },
    {   4, instrux_PSRLQ },
    {   4, instrux_PSRLW },
    {   2, instrux_PSUBB },
    {   2, instrux_PSUBD },
    {   2, instrux_PSUBSB },
    {   1, instrux_PSUBSIW },
    {   2, instrux_PSUBSW },
    {   2, instrux_PSUBUSB },
    {   2, instrux_PSUBUSW },
    {   2, instrux_PSUBW },
    {   2, instrux_PUNPCKHBW },
    {   2, instrux_PUNPCKHDQ },
    {   2, instrux_PUNPCKHWD },
    {   2, instrux_PUNPCKLBW },
    {   2, instrux_PUNPCKLDQ },
    {   2, instrux_PUNPCKLWD },
    {   1, instrux_PUSHA },
    {   1, instrux_PUSHAW },
    {   1, instrux_PUSHAD },
    {   1, instrux_POPA },
    {   1, instrux_POPAW },
    {   1, instrux_POPAD },
    {   2, instrux_ENTER },
    {   2, instrux_ENTERW },
    {   2, instrux_ENTERD },
    {   2, instrux_ENTERQ },
    {   1, instrux_LEAVE },
    {   1, instrux_LEAVEW },
    {   1, instrux_LEAVED },
    {   1, instrux_LEAVEQ },
    {   2, instrux_BOUND },
    {   3, instrux_PUSHP },
    {   3, instrux_POPP },
    {   2, instrux_PUSH2 },
    {   2, instrux_PUSH2P },
    {   2, instrux_POP2 },
    {   2, instrux_POP2P },
    {   2, instrux_PXOR },
    {   1, instrux_SKINIT },
    {   4, instrux_UD0 },
    {   4, instrux_UD1 },
    {   4, instrux_UD2B },
    {   4, instrux_UD2 },
    {   4, instrux_UD2A },
    {   1, instrux_UDB },
    {   1, instrux_FWAIT },
    {   1, instrux_XLATB },
    {   1, instrux_XLAT },
    {  15, instrux_CCMP },
    {  15, instrux_CCMPA },
    {  15, instrux_CCMPAE },
    {  15, instrux_CCMPB },
    {  15, instrux_CCMPBE },
    {  15, instrux_CCMPC },
    {  15, instrux_CCMPE },
    {  15, instrux_CCMPF },
    {  15, instrux_CCMPG },
    {  15, instrux_CCMPGE },
    {  15, instrux_CCMPL },
    {  15, instrux_CCMPLE },
    {  15, instrux_CCMPNA },
    {  15, instrux_CCMPNAE },
    {  15, instrux_CCMPNB },
    {  15, instrux_CCMPNBE },
    {  15, instrux_CCMPNC },
    {  15, instrux_CCMPNE },
    {  15, instrux_CCMPNG },
    {  15, instrux_CCMPNGE },
    {  15, instrux_CCMPNL },
    {  15, instrux_CCMPNLE },
    {  15, instrux_CCMPNO },
    {  15, instrux_CCMPNS },
    {  15, instrux_CCMPNZ },
    {  15, instrux_CCMPO },
    {  15, instrux_CCMPS },
    {  15, instrux_CCMPT },
    {  15, instrux_CCMPZ },
    {  12, instrux_CTEST },
    {  12, instrux_CTESTA },
    {  12, instrux_CTESTAE },
    {  12, instrux_CTESTB },
    {  12, instrux_CTESTBE },
    {  12, instrux_CTESTC },
    {  12, instrux_CTESTE },
    {  12, instrux_CTESTF },
    {  12, instrux_CTESTG },
    {  12, instrux_CTESTGE },
    {  12, instrux_CTESTL },
    {  12, instrux_CTESTLE },
    {  12, instrux_CTESTNA },
    {  12, instrux_CTESTNAE },
    {  12, instrux_CTESTNB },
    {  12, instrux_CTESTNBE },
    {  12, instrux_CTESTNC },
    {  12, instrux_CTESTNE },
    {  12, instrux_CTESTNG },
    {  12, instrux_CTESTNGE },
    {  12, instrux_CTESTNL },
    {  12, instrux_CTESTNLE },
    {  12, instrux_CTESTNO },
    {  12, instrux_CTESTNS },
    {  12, instrux_CTESTNZ },
    {  12, instrux_CTESTO },
    {  12, instrux_CTESTS },
    {  12, instrux_CTESTT },
    {  12, instrux_CTESTZ },
    {   6, instrux_CMOVA },
    {   6, instrux_CMOVAE },
    {   6, instrux_CMOVB },
    {   6, instrux_CMOVBE },
    {   6, instrux_CMOVC },
    {   6, instrux_CMOVE },
    {   6, instrux_CMOVG },
    {   6, instrux_CMOVGE },
    {   6, instrux_CMOVL },
    {   6, instrux_CMOVLE },
    {   6, instrux_CMOVNA },
    {   6, instrux_CMOVNAE },
    {   6, instrux_CMOVNB },
    {   6, instrux_CMOVNBE },
    {   6, instrux_CMOVNC },
    {   6, instrux_CMOVNE },
    {   6, instrux_CMOVNG },
    {   6, instrux_CMOVNGE },
    {   6, instrux_CMOVNL },
    {   6, instrux_CMOVNLE },
    {   6, instrux_CMOVNO },
    {   6, instrux_CMOVNP },
    {   6, instrux_CMOVNS },
    {   6, instrux_CMOVNZ },
    {   6, instrux_CMOVO },
    {   6, instrux_CMOVP },
    {   6, instrux_CMOVPE },
    {   6, instrux_CMOVPO },
    {   6, instrux_CMOVS },
    {   6, instrux_CMOVZ },
    {  15, instrux_CFCMOVA },
    {  15, instrux_CFCMOVAE },
    {  15, instrux_CFCMOVB },
    {  15, instrux_CFCMOVBE },
    {  15, instrux_CFCMOVC },
    {  15, instrux_CFCMOVE },
    {  15, instrux_CFCMOVG },
    {  15, instrux_CFCMOVGE },
    {  15, instrux_CFCMOVL },
    {  15, instrux_CFCMOVLE },
    {  15, instrux_CFCMOVNA },
    {  15, instrux_CFCMOVNAE },
    {  15, instrux_CFCMOVNB },
    {  15, instrux_CFCMOVNBE },
    {  15, instrux_CFCMOVNC },
    {  15, instrux_CFCMOVNE },
    {  15, instrux_CFCMOVNG },
    {  15, instrux_CFCMOVNGE },
    {  15, instrux_CFCMOVNL },
    {  15, instrux_CFCMOVNLE },
    {  15, instrux_CFCMOVNO },
    {  15, instrux_CFCMOVNP },
    {  15, instrux_CFCMOVNS },
    {  15, instrux_CFCMOVNZ },
    {  15, instrux_CFCMOVO },
    {  15, instrux_CFCMOVP },
    {  15, instrux_CFCMOVPE },
    {  15, instrux_CFCMOVPO },
    {  15, instrux_CFCMOVS },
    {  15, instrux_CFCMOVZ },
    {   4, instrux_SETA },
    {   4, instrux_SETAE },
    {   4, instrux_SETB },
    {   4, instrux_SETBE },
    {   4, instrux_SETC },
    {   4, instrux_SETE },
    {   4, instrux_SETG },
    {   4, instrux_SETGE },
    {   4, instrux_SETL },
    {   4, instrux_SETLE },
    {   4, instrux_SETNA },
    {   4, instrux_SETNAE },
    {   4, instrux_SETNB },
    {   4, instrux_SETNBE },
    {   4, instrux_SETNC },
    {   4, instrux_SETNE },
    {   4, instrux_SETNG },
    {   4, instrux_SETNGE },
    {   4, instrux_SETNL },
    {   4, instrux_SETNLE },
    {   4, instrux_SETNO },
    {   4, instrux_SETNP },
    {   4, instrux_SETNS },
    {   4, instrux_SETNZ },
    {   4, instrux_SETO },
    {   4, instrux_SETP },
    {   4, instrux_SETPE },
    {   4, instrux_SETPO },
    {   4, instrux_SETS },
    {   4, instrux_SETZ },
    {   3, instrux_SETAZU },
    {   3, instrux_SETAEZU },
    {   3, instrux_SETBZU },
    {   3, instrux_SETBEZU },
    {   3, instrux_SETCZU },
    {   3, instrux_SETEZU },
    {   3, instrux_SETGZU },
    {   3, instrux_SETGEZU },
    {   3, instrux_SETLZU },
    {   3, instrux_SETLEZU },
    {   3, instrux_SETNAZU },
    {   3, instrux_SETNAEZU },
    {   3, instrux_SETNBZU },
    {   3, instrux_SETNBEZU },
    {   3, instrux_SETNCZU },
    {   3, instrux_SETNEZU },
    {   3, instrux_SETNGZU },
    {   3, instrux_SETNGEZU },
    {   3, instrux_SETNLZU },
    {   3, instrux_SETNLEZU },
    {   3, instrux_SETNOZU },
    {   3, instrux_SETNPZU },
    {   3, instrux_SETNSZU },
    {   3, instrux_SETNZZU },
    {   3, instrux_SETOZU },
    {   3, instrux_SETPZU },
    {   3, instrux_SETPEZU },
    {   3, instrux_SETPOZU },
    {   3, instrux_SETSZU },
    {   3, instrux_SETZZU },
    {   4, instrux_CMPAXADD },
    {   4, instrux_CMPAEXADD },
    {   4, instrux_CMPBXADD },
    {   4, instrux_CMPBEXADD },
    {   4, instrux_CMPCXADD },
    {   4, instrux_CMPEXADD },
    {   4, instrux_CMPGXADD },
    {   4, instrux_CMPGEXADD },
    {   4, instrux_CMPLXADD },
    {   4, instrux_CMPLEXADD },
    {   4, instrux_CMPNAXADD },
    {   4, instrux_CMPNAEXADD },
    {   4, instrux_CMPNBXADD },
    {   4, instrux_CMPNBEXADD },
    {   4, instrux_CMPNCXADD },
    {   4, instrux_CMPNEXADD },
    {   4, instrux_CMPNGXADD },
    {   4, instrux_CMPNGEXADD },
    {   4, instrux_CMPNLXADD },
    {   4, instrux_CMPNLEXADD },
    {   4, instrux_CMPNOXADD },
    {   4, instrux_CMPNPXADD },
    {   4, instrux_CMPNSXADD },
    {   4, instrux_CMPNZXADD },
    {   4, instrux_CMPOXADD },
    {   4, instrux_CMPPXADD },
    {   4, instrux_CMPPEXADD },
    {   4, instrux_CMPPOXADD },
    {   4, instrux_CMPSXADD },
    {   4, instrux_CMPZXADD },
    {   1, instrux_ADDPS },
    {   1, instrux_ADDSS },
    {   1, instrux_ANDNPS },
    {   1, instrux_ANDPS },
    {   1, instrux_CMPEQPS },
    {   1, instrux_CMPEQSS },
    {   1, instrux_CMPLEPS },
    {   1, instrux_CMPLESS },
    {   1, instrux_CMPLTPS },
    {   1, instrux_CMPLTSS },
    {   1, instrux_CMPNEQPS },
    {   1, instrux_CMPNEQSS },
    {   1, instrux_CMPNLEPS },
    {   1, instrux_CMPNLESS },
    {   1, instrux_CMPNLTPS },
    {   1, instrux_CMPNLTSS },
    {   1, instrux_CMPORDPS },
    {   1, instrux_CMPORDSS },
    {   1, instrux_CMPUNORDPS },
    {   1, instrux_CMPUNORDSS },
    {   1, instrux_CMPPS },
    {   1, instrux_CMPSS },
    {   1, instrux_COMISS },
    {   1, instrux_CVTPI2PS },
    {   1, instrux_CVTPS2PI },
    {   2, instrux_CVTSI2SS },
    {   2, instrux_CVTSS2SI },
    {   1, instrux_CVTTPS2PI },
    {   2, instrux_CVTTSS2SI },
    {   1, instrux_DIVPS },
    {   1, instrux_DIVSS },
    {   1, instrux_LDMXCSR },
    {   1, instrux_MAXPS },
    {   1, instrux_MAXSS },
    {   1, instrux_MINPS },
    {   1, instrux_MINSS },
    {   2, instrux_MOVAPS },
    {   2, instrux_MOVHPS },
    {   1, instrux_MOVLHPS },
    {   2, instrux_MOVLPS },
    {   1, instrux_MOVHLPS },
    {   2, instrux_MOVMSKPS },
    {   1, instrux_MOVNTPS },
    {   2, instrux_MOVSS },
    {   2, instrux_MOVUPS },
    {   1, instrux_MULPS },
    {   1, instrux_MULSS },
    {   1, instrux_ORPS },
    {   1, instrux_RCPPS },
    {   1, instrux_RCPSS },
    {   1, instrux_RSQRTPS },
    {   1, instrux_RSQRTSS },
    {   1, instrux_SHUFPS },
    {   1, instrux_SQRTPS },
    {   1, instrux_SQRTSS },
    {   1, instrux_STMXCSR },
    {   1, instrux_SUBPS },
    {   1, instrux_SUBSS },
    {   1, instrux_UCOMISS },
    {   1, instrux_UNPCKHPS },
    {   1, instrux_UNPCKLPS },
    {   1, instrux_XORPS },
    {   1, instrux_FXRSTOR },
    {   1, instrux_FXRSTOR64 },
    {   1, instrux_FXSAVE },
    {   1, instrux_FXSAVE64 },
    {   1, instrux_XGETBV },
    {   1, instrux_XSETBV },
    {   1, instrux_XSAVE },
    {   1, instrux_XSAVE64 },
    {   1, instrux_XSAVEC },
    {   1, instrux_XSAVEC64 },
    {   1, instrux_XSAVEOPT },
    {   1, instrux_XSAVEOPT64 },
    {   1, instrux_XSAVES },
    {   1, instrux_XSAVES64 },
    {   1, instrux_XRSTOR },
    {   1, instrux_XRSTOR64 },
    {   1, instrux_XRSTORS },
    {   1, instrux_XRSTORS64 },
    {   1, instrux_PREFETCHNTA },
    {   1, instrux_PREFETCHT0 },
    {   1, instrux_PREFETCHT1 },
    {   1, instrux_PREFETCHT2 },
    {   1, instrux_PREFETCHIT0 },
    {   1, instrux_PREFETCHIT1 },
    {   1, instrux_MASKMOVQ },
    {   1, instrux_MOVNTQ },
    {   2, instrux_PAVGB },
    {   2, instrux_PAVGW },
    {   6, instrux_PEXTRW },
    {   8, instrux_PINSRW },
    {   2, instrux_PMAXSW },
    {   2, instrux_PMAXUB },
    {   2, instrux_PMINSW },
    {   2, instrux_PMINUB },
    {   2, instrux_PMOVMSKB },
    {   2, instrux_PMULHUW },
    {   2, instrux_PSADBW },
    {   1, instrux_PSHUFW },
    {   1, instrux_PF2IW },
    {   1, instrux_PFNACC },
    {   1, instrux_PFPNACC },
    {   1, instrux_PI2FW },
    {   1, instrux_PSWAPD },
    {   1, instrux_MASKMOVDQU },
    {   1, instrux_MOVNTDQ },
    {   2, instrux_MOVNTI },
    {   1, instrux_MOVNTPD },
    {   2, instrux_MOVDQA },
    {   2, instrux_MOVDQU },
    {   1, instrux_MOVDQ2Q },
    {   1, instrux_MOVQ2DQ },
    {   2, instrux_PADDQ },
    {   2, instrux_PMULUDQ },
    {   2, instrux_PSHUFD },
    {   2, instrux_PSHUFHW },
    {   2, instrux_PSHUFLW },
    {   1, instrux_PSLLDQ },
    {   1, instrux_PSRLDQ },
    {   2, instrux_PSUBQ },
    {   1, instrux_PUNPCKHQDQ },
    {   1, instrux_PUNPCKLQDQ },
    {   1, instrux_ADDPD },
    {   1, instrux_ADDSD },
    {   1, instrux_ANDNPD },
    {   1, instrux_ANDPD },
    {   1, instrux_CMPEQPD },
    {   1, instrux_CMPEQSD },
    {   1, instrux_CMPLEPD },
    {   1, instrux_CMPLESD },
    {   1, instrux_CMPLTPD },
    {   1, instrux_CMPLTSD },
    {   1, instrux_CMPNEQPD },
    {   1, instrux_CMPNEQSD },
    {   1, instrux_CMPNLEPD },
    {   1, instrux_CMPNLESD },
    {   1, instrux_CMPNLTPD },
    {   1, instrux_CMPNLTSD },
    {   1, instrux_CMPORDPD },
    {   1, instrux_CMPORDSD },
    {   1, instrux_CMPUNORDPD },
    {   1, instrux_CMPUNORDSD },
    {   1, instrux_CMPPD },
    {   1, instrux_COMISD },
    {   1, instrux_CVTDQ2PD },
    {   1, instrux_CVTDQ2PS },
    {   1, instrux_CVTPD2DQ },
    {   1, instrux_CVTPD2PI },
    {   1, instrux_CVTPD2PS },
    {   1, instrux_CVTPI2PD },
    {   1, instrux_CVTPS2DQ },
    {   1, instrux_CVTPS2PD },
    {   2, instrux_CVTSD2SI },
    {   1, instrux_CVTSD2SS },
    {   2, instrux_CVTSI2SD },
    {   1, instrux_CVTSS2SD },
    {   1, instrux_CVTTPD2PI },
    {   1, instrux_CVTTPD2DQ },
    {   1, instrux_CVTTPS2DQ },
    {   2, instrux_CVTTSD2SI },
    {   1, instrux_DIVPD },
    {   1, instrux_DIVSD },
    {   1, instrux_MAXPD },
    {   1, instrux_MAXSD },
    {   1, instrux_MINPD },
    {   1, instrux_MINSD },
    {   2, instrux_MOVAPD },
    {   2, instrux_MOVHPD },
    {   2, instrux_MOVLPD },
    {   2, instrux_MOVMSKPD },
    {   2, instrux_MOVUPD },
    {   1, instrux_MULPD },
    {   1, instrux_MULSD },
    {   1, instrux_ORPD },
    {   1, instrux_SHUFPD },
    {   1, instrux_SQRTPD },
    {   1, instrux_SQRTSD },
    {   1, instrux_SUBPD },
    {   1, instrux_SUBSD },
    {   1, instrux_UCOMISD },
    {   1, instrux_UNPCKHPD },
    {   1, instrux_UNPCKLPD },
    {   1, instrux_XORPD },
    {   1, instrux_ADDSUBPD },
    {   1, instrux_ADDSUBPS },
    {   1, instrux_HADDPD },
    {   1, instrux_HADDPS },
    {   1, instrux_HSUBPD },
    {   1, instrux_HSUBPS },
    {   1, instrux_LDDQU },
    {   1, instrux_MOVDDUP },
    {   1, instrux_MOVSHDUP },
    {   1, instrux_MOVSLDUP },
    {   1, instrux_CLGI },
    {   1, instrux_STGI },
    {   1, instrux_VMCALL },
    {   1, instrux_VMCLEAR },
    {   1, instrux_VMFUNC },
    {   1, instrux_VMLAUNCH },
    {   1, instrux_VMLOAD },
    {   1, instrux_VMMCALL },
    {   1, instrux_VMPTRLD },
    {   1, instrux_VMPTRST },
    {   2, instrux_VMREAD },
    {   1, instrux_VMRESUME },
    {   1, instrux_VMRUN },
    {   1, instrux_VMSAVE },
    {   2, instrux_VMWRITE },
    {   1, instrux_VMXOFF },
    {   1, instrux_VMXON },
    {   3, instrux_INVEPT },
    {   3, instrux_INVVPID },
    {   1, instrux_PVALIDATE },
    {   1, instrux_RMPADJUST },
    {   2, instrux_VMGEXIT },
    {   2, instrux_PABSB },
    {   2, instrux_PABSW },
    {   2, instrux_PABSD },
    {   2, instrux_PALIGNR },
    {   2, instrux_PHADDW },
    {   2, instrux_PHADDD },
    {   2, instrux_PHADDSW },
    {   2, instrux_PHSUBW },
    {   2, instrux_PHSUBD },
    {   2, instrux_PHSUBSW },
    {   2, instrux_PMADDUBSW },
    {   2, instrux_PMULHRSW },
    {   2, instrux_PSHUFB },
    {   2, instrux_PSIGNB },
    {   2, instrux_PSIGNW },
    {   2, instrux_PSIGND },
    {   2, instrux_EXTRQ },
    {   2, instrux_INSERTQ },
    {   1, instrux_MOVNTSD },
    {   1, instrux_MOVNTSS },
    {   1, instrux_BLENDPD },
    {   1, instrux_BLENDPS },
    {   2, instrux_BLENDVPD },
    {   2, instrux_BLENDVPS },
    {   1, instrux_DPPD },
    {   1, instrux_DPPS },
    {   2, instrux_EXTRACTPS },
    {   1, instrux_INSERTPS },
    {   1, instrux_MOVNTDQA },
    {   1, instrux_MPSADBW },
    {   1, instrux_PACKUSDW },
    {   2, instrux_PBLENDVB },
    {   1, instrux_PBLENDW },
    {   1, instrux_PCMPEQQ },
    {   3, instrux_PEXTRB },
    {   1, instrux_PEXTRD },
    {   1, instrux_PEXTRQ },
    {   1, instrux_PHMINPOSUW },
    {   3, instrux_PINSRB },
    {   1, instrux_PINSRD },
    {   1, instrux_PINSRQ },
    {   1, instrux_PMAXSB },
    {   1, instrux_PMAXSD },
    {   1, instrux_PMAXUD },
    {   1, instrux_PMAXUW },
    {   1, instrux_PMINSB },
    {   1, instrux_PMINSD },
    {   1, instrux_PMINUD },
    {   1, instrux_PMINUW },
    {   1, instrux_PMOVSXBW },
    {   1, instrux_PMOVSXBD },
    {   1, instrux_PMOVSXBQ },
    {   1, instrux_PMOVSXWD },
    {   1, instrux_PMOVSXWQ },
    {   1, instrux_PMOVSXDQ },
    {   1, instrux_PMOVZXBW },
    {   1, instrux_PMOVZXBD },
    {   1, instrux_PMOVZXBQ },
    {   1, instrux_PMOVZXWD },
    {   1, instrux_PMOVZXWQ },
    {   1, instrux_PMOVZXDQ },
    {   1, instrux_PMULDQ },
    {   1, instrux_PMULLD },
    {   1, instrux_PTEST },
    {   1, instrux_ROUNDPD },
    {   1, instrux_ROUNDPS },
    {   1, instrux_ROUNDSD },
    {   1, instrux_ROUNDSS },
    {  18, instrux_CRC32 },
    {   1, instrux_PCMPESTRI },
    {   1, instrux_PCMPESTRM },
    {   1, instrux_PCMPISTRI },
    {   1, instrux_PCMPISTRM },
    {   1, instrux_PCMPGTQ },
    {   6, instrux_POPCNT },
    {   1, instrux_GETSEC },
    {   1, instrux_PFRCPV },
    {   1, instrux_PFRSQRTV },
    {   1, instrux_AESENC },
    {   1, instrux_AESENCLAST },
    {   1, instrux_AESDEC },
    {   1, instrux_AESDECLAST },
    {   1, instrux_AESIMC },
    {   1, instrux_AESKEYGENASSIST },
    {  10, instrux_VAESENC },
    {  10, instrux_VAESENCLAST },
    {  10, instrux_VAESDEC },
    {  10, instrux_VAESDECLAST },
    {   1, instrux_VAESIMC },
    {   1, instrux_VAESKEYGENASSIST },
    {   1, instrux_AESDEC128KL },
    {   1, instrux_AESDEC256KL },
    {   1, instrux_AESENC128KL },
    {   1, instrux_AESENC256KL },
    {   1, instrux_ENCODEKEY128 },
    {   1, instrux_ENCODEKEY256 },
    {   1, instrux_LOADIWKEY },
    {   1, instrux_AESDECWIDE128KL },
    {   1, instrux_AESDECWIDE256KL },
    {   1, instrux_AESENCWIDE128KL },
    {   1, instrux_AESENCWIDE256KL },
    {  10, instrux_VADDPD },
    {  10, instrux_VADDPS },
    {   4, instrux_VADDSD },
    {   4, instrux_VADDSS },
    {   4, instrux_VADDSUBPD },
    {   4, instrux_VADDSUBPS },
    {  10, instrux_VANDPD },
    {  10, instrux_VANDPS },
    {  10, instrux_VANDNPD },
    {  10, instrux_VANDNPS },
    {   4, instrux_VBLENDPD },
    {   4, instrux_VBLENDPS },
    {   4, instrux_VBLENDVPD },
    {   4, instrux_VBLENDVPS },
    {  10, instrux_VBROADCASTSS },
    {   6, instrux_VBROADCASTSD },
    {   1, instrux_VBROADCASTF128 },
    {  11, instrux_VCMPEQ_OSPD },
    {   7, instrux_VCMPEQPD },
    {   7, instrux_VCMPLT_OSPD },
    {   7, instrux_VCMPLTPD },
    {   7, instrux_VCMPLE_OSPD },
    {   7, instrux_VCMPLEPD },
    {   7, instrux_VCMPUNORD_QPD },
    {   7, instrux_VCMPUNORDPD },
    {   7, instrux_VCMPNEQ_UQPD },
    {   7, instrux_VCMPNEQPD },
    {   7, instrux_VCMPNLT_USPD },
    {   7, instrux_VCMPNLTPD },
    {   7, instrux_VCMPNLE_USPD },
    {   7, instrux_VCMPNLEPD },
    {   7, instrux_VCMPORD_QPD },
    {   7, instrux_VCMPORDPD },
    {   7, instrux_VCMPEQ_UQPD },
    {   7, instrux_VCMPNGE_USPD },
    {   7, instrux_VCMPNGEPD },
    {   7, instrux_VCMPNGT_USPD },
    {   7, instrux_VCMPNGTPD },
    {   7, instrux_VCMPFALSE_OQPD },
    {   7, instrux_VCMPFALSEPD },
    {   7, instrux_VCMPNEQ_OQPD },
    {   7, instrux_VCMPGE_OSPD },
    {   7, instrux_VCMPGEPD },
    {   7, instrux_VCMPGT_OSPD },
    {   7, instrux_VCMPGTPD },
    {   7, instrux_VCMPTRUE_UQPD },
    {   7, instrux_VCMPTRUEPD },
    {   7, instrux_VCMPLT_OQPD },
    {   7, instrux_VCMPLE_OQPD },
    {   7, instrux_VCMPUNORD_SPD },
    {   7, instrux_VCMPNEQ_USPD },
    {   7, instrux_VCMPNLT_UQPD },
    {   7, instrux_VCMPNLE_UQPD },
    {   7, instrux_VCMPORD_SPD },
    {   7, instrux_VCMPEQ_USPD },
    {   7, instrux_VCMPNGE_UQPD },
    {   7, instrux_VCMPNGT_UQPD },
    {   7, instrux_VCMPFALSE_OSPD },
    {   7, instrux_VCMPNEQ_OSPD },
    {   7, instrux_VCMPGE_OQPD },
    {   7, instrux_VCMPGT_OQPD },
    {   7, instrux_VCMPTRUE_USPD },
    {   7, instrux_VCMPPD },
    {  11, instrux_VCMPEQ_OSPS },
    {   7, instrux_VCMPEQPS },
    {   7, instrux_VCMPLT_OSPS },
    {   7, instrux_VCMPLTPS },
    {   7, instrux_VCMPLE_OSPS },
    {   7, instrux_VCMPLEPS },
    {   7, instrux_VCMPUNORD_QPS },
    {   7, instrux_VCMPUNORDPS },
    {   7, instrux_VCMPNEQ_UQPS },
    {   7, instrux_VCMPNEQPS },
    {   7, instrux_VCMPNLT_USPS },
    {   7, instrux_VCMPNLTPS },
    {   7, instrux_VCMPNLE_USPS },
    {   7, instrux_VCMPNLEPS },
    {   7, instrux_VCMPORD_QPS },
    {   7, instrux_VCMPORDPS },
    {   7, instrux_VCMPEQ_UQPS },
    {   7, instrux_VCMPNGE_USPS },
    {   7, instrux_VCMPNGEPS },
    {   7, instrux_VCMPNGT_USPS },
    {   7, instrux_VCMPNGTPS },
    {   7, instrux_VCMPFALSE_OQPS },
    {   7, instrux_VCMPFALSEPS },
    {   7, instrux_VCMPNEQ_OQPS },
    {   7, instrux_VCMPGE_OSPS },
    {   7, instrux_VCMPGEPS },
    {   7, instrux_VCMPGT_OSPS },
    {   7, instrux_VCMPGTPS },
    {   7, instrux_VCMPTRUE_UQPS },
    {   7, instrux_VCMPTRUEPS },
    {   7, instrux_VCMPLT_OQPS },
    {   7, instrux_VCMPLE_OQPS },
    {   7, instrux_VCMPUNORD_SPS },
    {   7, instrux_VCMPNEQ_USPS },
    {   7, instrux_VCMPNLT_UQPS },
    {   7, instrux_VCMPNLE_UQPS },
    {   7, instrux_VCMPORD_SPS },
    {   7, instrux_VCMPEQ_USPS },
    {   7, instrux_VCMPNGE_UQPS },
    {   7, instrux_VCMPNGT_UQPS },
    {   7, instrux_VCMPFALSE_OSPS },
    {   7, instrux_VCMPNEQ_OSPS },
    {   7, instrux_VCMPGE_OQPS },
    {   7, instrux_VCMPGT_OQPS },
    {   7, instrux_VCMPTRUE_USPS },
    {   7, instrux_VCMPPS },
    {   5, instrux_VCMPEQ_OSSD },
    {   3, instrux_VCMPEQSD },
    {   3, instrux_VCMPLT_OSSD },
    {   3, instrux_VCMPLTSD },
    {   3, instrux_VCMPLE_OSSD },
    {   3, instrux_VCMPLESD },
    {   3, instrux_VCMPUNORD_QSD },
    {   3, instrux_VCMPUNORDSD },
    {   3, instrux_VCMPNEQ_UQSD },
    {   3, instrux_VCMPNEQSD },
    {   3, instrux_VCMPNLT_USSD },
    {   3, instrux_VCMPNLTSD },
    {   3, instrux_VCMPNLE_USSD },
    {   3, instrux_VCMPNLESD },
    {   3, instrux_VCMPORD_QSD },
    {   3, instrux_VCMPORDSD },
    {   3, instrux_VCMPEQ_UQSD },
    {   3, instrux_VCMPNGE_USSD },
    {   3, instrux_VCMPNGESD },
    {   3, instrux_VCMPNGT_USSD },
    {   3, instrux_VCMPNGTSD },
    {   3, instrux_VCMPFALSE_OQSD },
    {   3, instrux_VCMPFALSESD },
    {   3, instrux_VCMPNEQ_OQSD },
    {   3, instrux_VCMPGE_OSSD },
    {   3, instrux_VCMPGESD },
    {   3, instrux_VCMPGT_OSSD },
    {   3, instrux_VCMPGTSD },
    {   3, instrux_VCMPTRUE_UQSD },
    {   3, instrux_VCMPTRUESD },
    {   3, instrux_VCMPLT_OQSD },
    {   3, instrux_VCMPLE_OQSD },
    {   3, instrux_VCMPUNORD_SSD },
    {   3, instrux_VCMPNEQ_USSD },
    {   3, instrux_VCMPNLT_UQSD },
    {   3, instrux_VCMPNLE_UQSD },
    {   3, instrux_VCMPORD_SSD },
    {   3, instrux_VCMPEQ_USSD },
    {   3, instrux_VCMPNGE_UQSD },
    {   3, instrux_VCMPNGT_UQSD },
    {   3, instrux_VCMPFALSE_OSSD },
    {   3, instrux_VCMPNEQ_OSSD },
    {   3, instrux_VCMPGE_OQSD },
    {   3, instrux_VCMPGT_OQSD },
    {   3, instrux_VCMPTRUE_USSD },
    {   3, instrux_VCMPSD },
    {   5, instrux_VCMPEQ_OSSS },
    {   3, instrux_VCMPEQSS },
    {   3, instrux_VCMPLT_OSSS },
    {   3, instrux_VCMPLTSS },
    {   3, instrux_VCMPLE_OSSS },
    {   3, instrux_VCMPLESS },
    {   3, instrux_VCMPUNORD_QSS },
    {   3, instrux_VCMPUNORDSS },
    {   3, instrux_VCMPNEQ_UQSS },
    {   3, instrux_VCMPNEQSS },
    {   3, instrux_VCMPNLT_USSS },
    {   3, instrux_VCMPNLTSS },
    {   3, instrux_VCMPNLE_USSS },
    {   3, instrux_VCMPNLESS },
    {   3, instrux_VCMPORD_QSS },
    {   3, instrux_VCMPORDSS },
    {   3, instrux_VCMPEQ_UQSS },
    {   3, instrux_VCMPNGE_USSS },
    {   3, instrux_VCMPNGESS },
    {   3, instrux_VCMPNGT_USSS },
    {   3, instrux_VCMPNGTSS },
    {   3, instrux_VCMPFALSE_OQSS },
    {   3, instrux_VCMPFALSESS },
    {   3, instrux_VCMPNEQ_OQSS },
    {   3, instrux_VCMPGE_OSSS },
    {   3, instrux_VCMPGESS },
    {   3, instrux_VCMPGT_OSSS },
    {   3, instrux_VCMPGTSS },
    {   3, instrux_VCMPTRUE_UQSS },
    {   3, instrux_VCMPTRUESS },
    {   3, instrux_VCMPLT_OQSS },
    {   3, instrux_VCMPLE_OQSS },
    {   3, instrux_VCMPUNORD_SSS },
    {   3, instrux_VCMPNEQ_USSS },
    {   3, instrux_VCMPNLT_UQSS },
    {   3, instrux_VCMPNLE_UQSS },
    {   3, instrux_VCMPORD_SSS },
    {   3, instrux_VCMPEQ_USSS },
    {   3, instrux_VCMPNGE_UQSS },
    {   3, instrux_VCMPNGT_UQSS },
    {   3, instrux_VCMPFALSE_OSSS },
    {   3, instrux_VCMPNEQ_OSSS },
    {   3, instrux_VCMPGE_OQSS },
    {   3, instrux_VCMPGT_OQSS },
    {   3, instrux_VCMPTRUE_USSS },
    {   3, instrux_VCMPSS },
    {   2, instrux_VCOMISD },
    {   2, instrux_VCOMISS },
    {   5, instrux_VCVTDQ2PD },
    {   5, instrux_VCVTDQ2PS },
    {   7, instrux_VCVTPD2DQ },
    {   7, instrux_VCVTPD2PS },
    {   5, instrux_VCVTPS2DQ },
    {   5, instrux_VCVTPS2PD },
    {   4, instrux_VCVTSD2SI },
    {   4, instrux_VCVTSD2SS },
    {  10, instrux_VCVTSI2SD },
    {  10, instrux_VCVTSI2SS },
    {   4, instrux_VCVTSS2SD },
    {   4, instrux_VCVTSS2SI },
    {   7, instrux_VCVTTPD2DQ },
    {   5, instrux_VCVTTPS2DQ },
    {   4, instrux_VCVTTSD2SI },
    {   4, instrux_VCVTTSS2SI },
    {  10, instrux_VDIVPD },
    {  10, instrux_VDIVPS },
    {   4, instrux_VDIVSD },
    {   4, instrux_VDIVSS },
    {   2, instrux_VDPPD },
    {   4, instrux_VDPPS },
    {   1, instrux_VEXTRACTF128 },
    {   4, instrux_VEXTRACTPS },
    {   4, instrux_VHADDPD },
    {   4, instrux_VHADDPS },
    {   4, instrux_VHSUBPD },
    {   4, instrux_VHSUBPS },
    {   2, instrux_VINSERTF128 },
    {   4, instrux_VINSERTPS },
    {   2, instrux_VLDDQU },
    {   1, instrux_VLDQQU },
    {   1, instrux_VLDMXCSR },
    {   1, instrux_VMASKMOVDQU },
    {   4, instrux_VMASKMOVPS },
    {   4, instrux_VMASKMOVPD },
    {  10, instrux_VMAXPD },
    {  10, instrux_VMAXPS },
    {   4, instrux_VMAXSD },
    {   4, instrux_VMAXSS },
    {  10, instrux_VMINPD },
    {  10, instrux_VMINPS },
    {   4, instrux_VMINSD },
    {   4, instrux_VMINSS },
    {  13, instrux_VMOVAPD },
    {  13, instrux_VMOVAPS },
    {   6, instrux_VMOVD },
    {   8, instrux_VMOVQ },
    {   5, instrux_VMOVDDUP },
    {   4, instrux_VMOVDQA },
    {   2, instrux_VMOVQQA },
    {   4, instrux_VMOVDQU },
    {   2, instrux_VMOVQQU },
    {   4, instrux_VMOVHLPS },
    {   6, instrux_VMOVHPD },
    {   6, instrux_VMOVHPS },
    {   4, instrux_VMOVLHPS },
    {   6, instrux_VMOVLPD },
    {   6, instrux_VMOVLPS },
    {   4, instrux_VMOVMSKPD },
    {   4, instrux_VMOVMSKPS },
    {   5, instrux_VMOVNTDQ },
    {   1, instrux_VMOVNTQQ },
    {   5, instrux_VMOVNTDQA },
    {   5, instrux_VMOVNTPD },
    {   5, instrux_VMOVNTPS },
    {  12, instrux_VMOVSD },
    {   5, instrux_VMOVSHDUP },
    {   5, instrux_VMOVSLDUP },
    {  12, instrux_VMOVSS },
    {  13, instrux_VMOVUPD },
    {  13, instrux_VMOVUPS },
    {   7, instrux_VMPSADBW },
    {  10, instrux_VMULPD },
    {  10, instrux_VMULPS },
    {   4, instrux_VMULSD },
    {   4, instrux_VMULSS },
    {  10, instrux_VORPD },
    {  10, instrux_VORPS },
    {   5, instrux_VPABSB },
    {   5, instrux_VPABSW },
    {   5, instrux_VPABSD },
    {  10, instrux_VPACKSSWB },
    {  10, instrux_VPACKSSDW },
    {  10, instrux_VPACKUSWB },
    {  10, instrux_VPACKUSDW },
    {  10, instrux_VPADDB },
    {  10, instrux_VPADDW },
    {  10, instrux_VPADDD },
    {  10, instrux_VPADDQ },
    {  10, instrux_VPADDSB },
    {  10, instrux_VPADDSW },
    {  10, instrux_VPADDUSB },
    {  10, instrux_VPADDUSW },
    {  10, instrux_VPALIGNR },
    {   4, instrux_VPAND },
    {   4, instrux_VPANDN },
    {  10, instrux_VPAVGB },
    {  10, instrux_VPAVGW },
    {   4, instrux_VPBLENDVB },
    {   4, instrux_VPBLENDW },
    {   1, instrux_VPCMPESTRI },
    {   1, instrux_VPCMPESTRM },
    {   1, instrux_VPCMPISTRI },
    {   1, instrux_VPCMPISTRM },
    {  10, instrux_VPCMPEQB },
    {  10, instrux_VPCMPEQW },
    {  10, instrux_VPCMPEQD },
    {  10, instrux_VPCMPEQQ },
    {  10, instrux_VPCMPGTB },
    {  10, instrux_VPCMPGTW },
    {  10, instrux_VPCMPGTD },
    {  10, instrux_VPCMPGTQ },
    {  15, instrux_VPERMILPD },
    {  15, instrux_VPERMILPS },
    {   2, instrux_VPERM2F128 },
    {   8, instrux_VPEXTRB },
    {  12, instrux_VPEXTRW },
    {   3, instrux_VPEXTRD },
    {   2, instrux_VPEXTRQ },
    {   4, instrux_VPHADDW },
    {   4, instrux_VPHADDD },
    {   4, instrux_VPHADDSW },
    {   1, instrux_VPHMINPOSUW },
    {   4, instrux_VPHSUBW },
    {   4, instrux_VPHSUBD },
    {   4, instrux_VPHSUBSW },
    {  10, instrux_VPINSRB },
    {  10, instrux_VPINSRW },
    {   6, instrux_VPINSRD },
    {   6, instrux_VPINSRQ },
    {  10, instrux_VPMADDWD },
    {  10, instrux_VPMADDUBSW },
    {  10, instrux_VPMAXSB },
    {  10, instrux_VPMAXSW },
    {  10, instrux_VPMAXSD },
    {  10, instrux_VPMAXUB },
    {  10, instrux_VPMAXUW },
    {  10, instrux_VPMAXUD },
    {  10, instrux_VPMINSB },
    {  10, instrux_VPMINSW },
    {  10, instrux_VPMINSD },
    {  10, instrux_VPMINUB },
    {  10, instrux_VPMINUW },
    {  10, instrux_VPMINUD },
    {   4, instrux_VPMOVMSKB },
    {   5, instrux_VPMOVSXBW },
    {   6, instrux_VPMOVSXBD },
    {   6, instrux_VPMOVSXBQ },
    {   5, instrux_VPMOVSXWD },
    {   6, instrux_VPMOVSXWQ },
    {   5, instrux_VPMOVSXDQ },
    {   5, instrux_VPMOVZXBW },
    {   6, instrux_VPMOVZXBD },
    {   6, instrux_VPMOVZXBQ },
    {   5, instrux_VPMOVZXWD },
    {   6, instrux_VPMOVZXWQ },
    {   5, instrux_VPMOVZXDQ },
    {  10, instrux_VPMULHUW },
    {  10, instrux_VPMULHRSW },
    {  10, instrux_VPMULHW },
    {  10, instrux_VPMULLW },
    {  10, instrux_VPMULLD },
    {  10, instrux_VPMULUDQ },
    {  10, instrux_VPMULDQ },
    {   4, instrux_VPOR },
    {  10, instrux_VPSADBW },
    {  10, instrux_VPSHUFB },
    {   5, instrux_VPSHUFD },
    {   5, instrux_VPSHUFHW },
    {   5, instrux_VPSHUFLW },
    {   4, instrux_VPSIGNB },
    {   4, instrux_VPSIGNW },
    {   4, instrux_VPSIGND },
    {  10, instrux_VPSLLDQ },
    {  10, instrux_VPSRLDQ },
    {  20, instrux_VPSLLW },
    {  20, instrux_VPSLLD },
    {  20, instrux_VPSLLQ },
    {  20, instrux_VPSRAW },
    {  20, instrux_VPSRAD },
    {  20, instrux_VPSRLW },
    {  20, instrux_VPSRLD },
    {  20, instrux_VPSRLQ },
    {   2, instrux_VPTEST },
    {  10, instrux_VPSUBB },
    {  10, instrux_VPSUBW },
    {  10, instrux_VPSUBD },
    {  10, instrux_VPSUBQ },
    {  10, instrux_VPSUBSB },
    {  10, instrux_VPSUBSW },
    {  10, instrux_VPSUBUSB },
    {  10, instrux_VPSUBUSW },
    {  10, instrux_VPUNPCKHBW },
    {  10, instrux_VPUNPCKHWD },
    {  10, instrux_VPUNPCKHDQ },
    {  10, instrux_VPUNPCKHQDQ },
    {  10, instrux_VPUNPCKLBW },
    {  10, instrux_VPUNPCKLWD },
    {  10, instrux_VPUNPCKLDQ },
    {  10, instrux_VPUNPCKLQDQ },
    {   4, instrux_VPXOR },
    {   2, instrux_VRCPPS },
    {   2, instrux_VRCPSS },
    {   2, instrux_VRSQRTPS },
    {   2, instrux_VRSQRTSS },
    {   2, instrux_VROUNDPD },
    {   2, instrux_VROUNDPS },
    {   2, instrux_VROUNDSD },
    {   2, instrux_VROUNDSS },
    {  10, instrux_VSHUFPD },
    {  10, instrux_VSHUFPS },
    {   5, instrux_VSQRTPD },
    {   5, instrux_VSQRTPS },
    {   4, instrux_VSQRTSD },
    {   4, instrux_VSQRTSS },
    {   1, instrux_VSTMXCSR },
    {  10, instrux_VSUBPD },
    {  10, instrux_VSUBPS },
    {   4, instrux_VSUBSD },
    {   4, instrux_VSUBSS },
    {   2, instrux_VTESTPS },
    {   2, instrux_VTESTPD },
    {   2, instrux_VUCOMISD },
    {   2, instrux_VUCOMISS },
    {  10, instrux_VUNPCKHPD },
    {  10, instrux_VUNPCKHPS },
    {  10, instrux_VUNPCKLPD },
    {  10, instrux_VUNPCKLPS },
    {  10, instrux_VXORPD },
    {  10, instrux_VXORPS },
    {   1, instrux_VZEROALL },
    {   1, instrux_VZEROUPPER },
    {   1, instrux_PCLMULLQLQDQ },
    {   1, instrux_PCLMULHQLQDQ },
    {   1, instrux_PCLMULLQHQDQ },
    {   1, instrux_PCLMULHQHQDQ },
    {   1, instrux_PCLMULQDQ },
    {  10, instrux_VPCLMULLQLQDQ },
    {  10, instrux_VPCLMULHQLQDQ },
    {  10, instrux_VPCLMULLQHQDQ },
    {  10, instrux_VPCLMULHQHQDQ },
    {  10, instrux_VPCLMULQDQ },
    {   5, instrux_VFMADD132PS },
    {   5, instrux_VFMADD132PD },
    {   2, instrux_VFMADD312PS },
    {   2, instrux_VFMADD312PD },
    {   5, instrux_VFMADD213PS },
    {   5, instrux_VFMADD213PD },
    {   2, instrux_VFMADD123PS },
    {   2, instrux_VFMADD123PD },
    {   5, instrux_VFMADD231PS },
    {   5, instrux_VFMADD231PD },
    {   2, instrux_VFMADD321PS },
    {   2, instrux_VFMADD321PD },
    {   5, instrux_VFMADDSUB132PS },
    {   5, instrux_VFMADDSUB132PD },
    {   2, instrux_VFMADDSUB312PS },
    {   2, instrux_VFMADDSUB312PD },
    {   5, instrux_VFMADDSUB213PS },
    {   5, instrux_VFMADDSUB213PD },
    {   2, instrux_VFMADDSUB123PS },
    {   2, instrux_VFMADDSUB123PD },
    {   5, instrux_VFMADDSUB231PS },
    {   5, instrux_VFMADDSUB231PD },
    {   2, instrux_VFMADDSUB321PS },
    {   2, instrux_VFMADDSUB321PD },
    {   5, instrux_VFMSUB132PS },
    {   5, instrux_VFMSUB132PD },
    {   2, instrux_VFMSUB312PS },
    {   2, instrux_VFMSUB312PD },
    {   5, instrux_VFMSUB213PS },
    {   5, instrux_VFMSUB213PD },
    {   2, instrux_VFMSUB123PS },
    {   2, instrux_VFMSUB123PD },
    {   5, instrux_VFMSUB231PS },
    {   5, instrux_VFMSUB231PD },
    {   2, instrux_VFMSUB321PS },
    {   2, instrux_VFMSUB321PD },
    {   5, instrux_VFMSUBADD132PS },
    {   5, instrux_VFMSUBADD132PD },
    {   2, instrux_VFMSUBADD312PS },
    {   2, instrux_VFMSUBADD312PD },
    {   5, instrux_VFMSUBADD213PS },
    {   5, instrux_VFMSUBADD213PD },
    {   2, instrux_VFMSUBADD123PS },
    {   2, instrux_VFMSUBADD123PD },
    {   5, instrux_VFMSUBADD231PS },
    {   5, instrux_VFMSUBADD231PD },
    {   2, instrux_VFMSUBADD321PS },
    {   2, instrux_VFMSUBADD321PD },
    {   5, instrux_VFNMADD132PS },
    {   5, instrux_VFNMADD132PD },
    {   2, instrux_VFNMADD312PS },
    {   2, instrux_VFNMADD312PD },
    {   5, instrux_VFNMADD213PS },
    {   5, instrux_VFNMADD213PD },
    {   2, instrux_VFNMADD123PS },
    {   2, instrux_VFNMADD123PD },
    {   5, instrux_VFNMADD231PS },
    {   5, instrux_VFNMADD231PD },
    {   2, instrux_VFNMADD321PS },
    {   2, instrux_VFNMADD321PD },
    {   5, instrux_VFNMSUB132PS },
    {   5, instrux_VFNMSUB132PD },
    {   2, instrux_VFNMSUB312PS },
    {   2, instrux_VFNMSUB312PD },
    {   5, instrux_VFNMSUB213PS },
    {   5, instrux_VFNMSUB213PD },
    {   2, instrux_VFNMSUB123PS },
    {   2, instrux_VFNMSUB123PD },
    {   5, instrux_VFNMSUB231PS },
    {   5, instrux_VFNMSUB231PD },
    {   2, instrux_VFNMSUB321PS },
    {   2, instrux_VFNMSUB321PD },
    {   2, instrux_VFMADD132SS },
    {   2, instrux_VFMADD132SD },
    {   1, instrux_VFMADD312SS },
    {   1, instrux_VFMADD312SD },
    {   2, instrux_VFMADD213SS },
    {   2, instrux_VFMADD213SD },
    {   1, instrux_VFMADD123SS },
    {   1, instrux_VFMADD123SD },
    {   2, instrux_VFMADD231SS },
    {   2, instrux_VFMADD231SD },
    {   1, instrux_VFMADD321SS },
    {   1, instrux_VFMADD321SD },
    {   2, instrux_VFMSUB132SS },
    {   2, instrux_VFMSUB132SD },
    {   1, instrux_VFMSUB312SS },
    {   1, instrux_VFMSUB312SD },
    {   2, instrux_VFMSUB213SS },
    {   2, instrux_VFMSUB213SD },
    {   1, instrux_VFMSUB123SS },
    {   1, instrux_VFMSUB123SD },
    {   2, instrux_VFMSUB231SS },
    {   2, instrux_VFMSUB231SD },
    {   1, instrux_VFMSUB321SS },
    {   1, instrux_VFMSUB321SD },
    {   2, instrux_VFNMADD132SS },
    {   2, instrux_VFNMADD132SD },
    {   1, instrux_VFNMADD312SS },
    {   1, instrux_VFNMADD312SD },
    {   2, instrux_VFNMADD213SS },
    {   2, instrux_VFNMADD213SD },
    {   1, instrux_VFNMADD123SS },
    {   1, instrux_VFNMADD123SD },
    {   2, instrux_VFNMADD231SS },
    {   2, instrux_VFNMADD231SD },
    {   1, instrux_VFNMADD321SS },
    {   1, instrux_VFNMADD321SD },
    {   2, instrux_VFNMSUB132SS },
    {   2, instrux_VFNMSUB132SD },
    {   1, instrux_VFNMSUB312SS },
    {   1, instrux_VFNMSUB312SD },
    {   2, instrux_VFNMSUB213SS },
    {   2, instrux_VFNMSUB213SD },
    {   1, instrux_VFNMSUB123SS },
    {   1, instrux_VFNMSUB123SD },
    {   2, instrux_VFNMSUB231SS },
    {   2, instrux_VFNMSUB231SD },
    {   1, instrux_VFNMSUB321SS },
    {   1, instrux_VFNMSUB321SD },
    {   8, instrux_VCVTPH2PS },
    {  14, instrux_VCVTPS2PH },
    {   1, instrux_XSTORE },
    {   1, instrux_XCRYPTECB },
    {   1, instrux_XCRYPTCBC },
    {   1, instrux_XCRYPTCTR },
    {   1, instrux_XCRYPTCFB },
    {   1, instrux_XCRYPTOFB },
    {   1, instrux_MONTMUL },
    {   1, instrux_XSHA1 },
    {   1, instrux_XSHA256 },
    {   2, instrux_LLWPCB },
    {   2, instrux_SLWPCB },
    {   2, instrux_LWPVAL },
    {   2, instrux_LWPINS },
    {   8, instrux_VFMADDPD },
    {   8, instrux_VFMADDPS },
    {   4, instrux_VFMADDSD },
    {   4, instrux_VFMADDSS },
    {   8, instrux_VFMADDSUBPD },
    {   8, instrux_VFMADDSUBPS },
    {   8, instrux_VFMSUBADDPD },
    {   8, instrux_VFMSUBADDPS },
    {   8, instrux_VFMSUBPD },
    {   8, instrux_VFMSUBPS },
    {   4, instrux_VFMSUBSD },
    {   4, instrux_VFMSUBSS },
    {   8, instrux_VFNMADDPD },
    {   8, instrux_VFNMADDPS },
    {   4, instrux_VFNMADDSD },
    {   4, instrux_VFNMADDSS },
    {   8, instrux_VFNMSUBPD },
    {   8, instrux_VFNMSUBPS },
    {   4, instrux_VFNMSUBSD },
    {   4, instrux_VFNMSUBSS },
    {   4, instrux_VFRCZPD },
    {   4, instrux_VFRCZPS },
    {   2, instrux_VFRCZSD },
    {   2, instrux_VFRCZSS },
    {   8, instrux_VPCMOV },
    {   2, instrux_VPCOMB },
    {   2, instrux_VPCOMD },
    {   2, instrux_VPCOMQ },
    {   2, instrux_VPCOMUB },
    {   2, instrux_VPCOMUD },
    {   2, instrux_VPCOMUQ },
    {   2, instrux_VPCOMUW },
    {   2, instrux_VPCOMW },
    {   2, instrux_VPHADDBD },
    {   2, instrux_VPHADDBQ },
    {   2, instrux_VPHADDBW },
    {   2, instrux_VPHADDDQ },
    {   2, instrux_VPHADDUBD },
    {   2, instrux_VPHADDUBQ },
    {   2, instrux_VPHADDUBW },
    {   2, instrux_VPHADDUDQ },
    {   2, instrux_VPHADDUWD },
    {   2, instrux_VPHADDUWQ },
    {   2, instrux_VPHADDWD },
    {   2, instrux_VPHADDWQ },
    {   2, instrux_VPHSUBBW },
    {   2, instrux_VPHSUBDQ },
    {   2, instrux_VPHSUBWD },
    {   2, instrux_VPMACSDD },
    {   2, instrux_VPMACSDQH },
    {   2, instrux_VPMACSDQL },
    {   2, instrux_VPMACSSDD },
    {   2, instrux_VPMACSSDQH },
    {   2, instrux_VPMACSSDQL },
    {   2, instrux_VPMACSSWD },
    {   2, instrux_VPMACSSWW },
    {   2, instrux_VPMACSWD },
    {   2, instrux_VPMACSWW },
    {   2, instrux_VPMADCSSWD },
    {   2, instrux_VPMADCSWD },
    {   4, instrux_VPPERM },
    {   6, instrux_VPROTB },
    {   6, instrux_VPROTD },
    {   6, instrux_VPROTQ },
    {   6, instrux_VPROTW },
    {   4, instrux_VPSHAB },
    {   4, instrux_VPSHAD },
    {   4, instrux_VPSHAQ },
    {   4, instrux_VPSHAW },
    {   4, instrux_VPSHLB },
    {   4, instrux_VPSHLD },
    {   4, instrux_VPSHLQ },
    {   4, instrux_VPSHLW },
    {   1, instrux_VBROADCASTI128 },
    {   4, instrux_VPBLENDD },
    {  19, instrux_VPBROADCASTB },
    {  16, instrux_VPBROADCASTW },
    {  13, instrux_VPBROADCASTD },
    {  13, instrux_VPBROADCASTQ },
    {   6, instrux_VPERMD },
    {   7, instrux_VPERMPD },
    {   6, instrux_VPERMPS },
    {   7, instrux_VPERMQ },
    {   2, instrux_VPERM2I128 },
    {   1, instrux_VEXTRACTI128 },
    {   2, instrux_VINSERTI128 },
    {   6, instrux_VPMASKMOVD },
    {   6, instrux_VPMASKMOVQ },
    {  10, instrux_VPSLLVD },
    {  10, instrux_VPSLLVQ },
    {  10, instrux_VPSRAVD },
    {  10, instrux_VPSRLVD },
    {  10, instrux_VPSRLVQ },
    {   5, instrux_VGATHERDPD },
    {   5, instrux_VGATHERQPD },
    {   5, instrux_VGATHERDPS },
    {   5, instrux_VGATHERQPS },
    {   5, instrux_VPGATHERDD },
    {   5, instrux_VPGATHERQD },
    {   5, instrux_VPGATHERDQ },
    {   5, instrux_VPGATHERQQ },
    {   1, instrux_XABORT },
    {   4, instrux_XBEGIN },
    {   1, instrux_XEND },
    {   1, instrux_XTEST },
    {   1, instrux_PREFETCHWT1 },
    {   1, instrux_BNDMK },
    {   3, instrux_BNDCL },
    {   3, instrux_BNDCU },
    {   3, instrux_BNDCN },
    {   4, instrux_BNDMOV },
    {   3, instrux_BNDLDX },
    {   5, instrux_BNDSTX },
    {   1, instrux_SHA1MSG1 },
    {   1, instrux_SHA1MSG2 },
    {   1, instrux_SHA1NEXTE },
    {   1, instrux_SHA1RNDS4 },
    {   1, instrux_SHA256MSG1 },
    {   1, instrux_SHA256MSG2 },
    {   2, instrux_SHA256RNDS2 },
    {   1, instrux_VSHA512MSG1 },
    {   1, instrux_VSHA512MSG2 },
    {   1, instrux_VSHA512RNDS2 },
    {   1, instrux_VSM3MSG1 },
    {   1, instrux_VSM3MSG2 },
    {   1, instrux_VSM3RNDS2 },
    {   5, instrux_VSM4KEY4 },
    {   5, instrux_VSM4RNDS4 },
    {   2, instrux_VBCSTNEBF16PS },
    {   2, instrux_VBCSTNEBF162PS },
    {   2, instrux_VBCSTNESH2PS },
    {   2, instrux_VCVTNEEBF162PS },
    {   2, instrux_VCVTNEEPH2PS },
    {   2, instrux_VCVTNEOBF162PS },
    {   2, instrux_VCVTNEOPH2PS },
    {   5, instrux_VCVTNEPS2BF16 },
    {   8, instrux_VPDPBUSD },
    {   8, instrux_VPDPBUSDS },
    {   8, instrux_VPDPWSSD },
    {   8, instrux_VPDPWSSDS },
    {   5, instrux_VPDPBSSD },
    {   5, instrux_VPDPBSSDS },
    {   5, instrux_VPDPBSUD },
    {   5, instrux_VPDPBSUDS },
    {   5, instrux_VPDPBUUD },
    {   5, instrux_VPDPBUUDS },
    {   5, instrux_VPDPWSUD },
    {   5, instrux_VPDPWSUDS },
    {   5, instrux_VPDPWUSD },
    {   5, instrux_VPDPWUSDS },
    {   5, instrux_VPDPWUUD },
    {   5, instrux_VPDPWUUDS },
    {   5, instrux_VPMADD52HUQ },
    {   5, instrux_VPMADD52LUQ },
    {  10, instrux_KMOVB },
    {  10, instrux_KMOVW },
    {   8, instrux_KMOVD },
    {   8, instrux_KMOVQ },
    {  36, instrux_KMOV },
    {  10, instrux_MOVB },
    {  10, instrux_MOVW },
    {   4, instrux_KADDB },
    {   4, instrux_KADDW },
    {   4, instrux_KADDD },
    {   4, instrux_KADDQ },
    {  16, instrux_KADD },
    {   4, instrux_ADDB },
    {   4, instrux_ADDW },
    {   4, instrux_ADDD },
    {   4, instrux_ADDQ },
    {   4, instrux_KANDB },
    {   4, instrux_KANDW },
    {   4, instrux_KANDD },
    {   4, instrux_KANDQ },
    {  16, instrux_KAND },
    {   4, instrux_ANDB },
    {   4, instrux_ANDW },
    {   4, instrux_ANDD },
    {   4, instrux_ANDQ },
    {   4, instrux_KANDNB },
    {   4, instrux_KANDNW },
    {   4, instrux_KANDND },
    {   4, instrux_KANDNQ },
    {  16, instrux_KANDN },
    {   4, instrux_ANDNB },
    {   4, instrux_ANDNW },
    {   4, instrux_ANDND },
    {   4, instrux_ANDNQ },
    {   4, instrux_KNOTB },
    {   4, instrux_KNOTW },
    {   4, instrux_KNOTD },
    {   4, instrux_KNOTQ },
    {  16, instrux_KNOT },
    {   4, instrux_NOTB },
    {   4, instrux_NOTW },
    {   4, instrux_NOTD },
    {   4, instrux_NOTQ },
    {   4, instrux_KORB },
    {   4, instrux_KORW },
    {   4, instrux_KORD },
    {   4, instrux_KORQ },
    {  16, instrux_KOR },
    {   4, instrux_ORB },
    {   4, instrux_ORW },
    {   4, instrux_ORD },
    {   4, instrux_ORQ },
    {   2, instrux_KORTESTB },
    {   2, instrux_KORTESTW },
    {   2, instrux_KORTESTD },
    {   2, instrux_KORTESTQ },
    {   8, instrux_KORTEST },
    {   2, instrux_ORTESTB },
    {   2, instrux_ORTESTW },
    {   2, instrux_ORTESTD },
    {   2, instrux_ORTESTQ },
    {   8, instrux_ORTEST },
    {   2, instrux_KSHIFTLB },
    {   2, instrux_KSHIFTLW },
    {   2, instrux_KSHIFTLD },
    {   2, instrux_KSHIFTLQ },
    {   8, instrux_KSHIFTL },
    {   2, instrux_SHIFTLB },
    {   2, instrux_SHIFTLW },
    {   2, instrux_SHIFTLD },
    {   2, instrux_SHIFTLQ },
    {   8, instrux_SHIFTL },
    {   2, instrux_KSHLB },
    {   2, instrux_KSHLW },
    {   2, instrux_KSHLD },
    {   2, instrux_KSHLQ },
    {   8, instrux_KSHL },
    {   2, instrux_SHLB },
    {   2, instrux_SHLW },
    {   2, instrux_SHLQ },
    {   2, instrux_KSHIFTRB },
    {   2, instrux_KSHIFTRW },
    {   2, instrux_KSHIFTRD },
    {   2, instrux_KSHIFTRQ },
    {   8, instrux_KSHIFTR },
    {   2, instrux_SHIFTRB },
    {   2, instrux_SHIFTRW },
    {   2, instrux_SHIFTRD },
    {   2, instrux_SHIFTRQ },
    {   8, instrux_SHIFTR },
    {   2, instrux_KSHRB },
    {   2, instrux_KSHRW },
    {   2, instrux_KSHRD },
    {   2, instrux_KSHRQ },
    {   8, instrux_KSHR },
    {   2, instrux_SHRB },
    {   2, instrux_SHRW },
    {   2, instrux_SHRQ },
    {   2, instrux_KTESTB },
    {   2, instrux_KTESTW },
    {   2, instrux_KTESTD },
    {   2, instrux_KTESTQ },
    {   8, instrux_KTEST },
    {   2, instrux_TESTB },
    {   2, instrux_TESTW },
    {   2, instrux_TESTD },
    {   2, instrux_TESTQ },
    {   4, instrux_KUNPCKBW },
    {   4, instrux_KUNPCKW },
    {  12, instrux_KUNPCK },
    {   4, instrux_UNPCKBW },
    {   4, instrux_UNPCKW },
    {  12, instrux_UNPCK },
    {   4, instrux_KUNPCKWD },
    {   4, instrux_KUNPCKD },
    {   4, instrux_UNPCKWD },
    {   4, instrux_UNPCKD },
    {   4, instrux_KUNPCKDQ },
    {   4, instrux_KUNPCKQ },
    {   4, instrux_UNPCKDQ },
    {   4, instrux_UNPCKQ },
    {   4, instrux_KXNORB },
    {   4, instrux_KXNORW },
    {   4, instrux_KXNORD },
    {   4, instrux_KXNORQ },
    {  16, instrux_KXNOR },
    {   4, instrux_XNORB },
    {   4, instrux_XNORW },
    {   4, instrux_XNORD },
    {   4, instrux_XNORQ },
    {  16, instrux_XNOR },
    {   4, instrux_KXORB },
    {   4, instrux_KXORW },
    {   4, instrux_KXORD },
    {   4, instrux_KXORQ },
    {  16, instrux_KXOR },
    {   4, instrux_XORB },
    {   4, instrux_XORW },
    {   4, instrux_XORD },
    {   4, instrux_XORQ },
    {   6, instrux_VALIGND },
    {   6, instrux_VALIGNQ },
    {   3, instrux_VBLENDMPD },
    {   3, instrux_VBLENDMPS },
    {   2, instrux_VBROADCASTF32X2 },
    {   2, instrux_VBROADCASTF32X4 },
    {   1, instrux_VBROADCASTF32X8 },
    {   2, instrux_VBROADCASTF64X2 },
    {   1, instrux_VBROADCASTF64X4 },
    {   3, instrux_VBROADCASTI32X2 },
    {   2, instrux_VBROADCASTI32X4 },
    {   1, instrux_VBROADCASTI32X8 },
    {   2, instrux_VBROADCASTI64X2 },
    {   1, instrux_VBROADCASTI64X4 },
    {   3, instrux_VCMPEQ_OQPD },
    {   3, instrux_VCMPEQ_OQPS },
    {   1, instrux_VCMPEQ_OQSD },
    {   1, instrux_VCMPEQ_OQSS },
    {   6, instrux_VCOMPRESSPD },
    {   6, instrux_VCOMPRESSPS },
    {   3, instrux_VCVTPD2QQ },
    {   3, instrux_VCVTPD2UDQ },
    {   3, instrux_VCVTPD2UQQ },
    {   3, instrux_VCVTPS2QQ },
    {   3, instrux_VCVTPS2UDQ },
    {   3, instrux_VCVTPS2UQQ },
    {   3, instrux_VCVTQQ2PD },
    {   3, instrux_VCVTQQ2PS },
    {   2, instrux_VCVTSD2USI },
    {   2, instrux_VCVTSS2USI },
    {   3, instrux_VCVTTPD2QQ },
    {   3, instrux_VCVTTPD2UDQ },
    {   3, instrux_VCVTTPD2UQQ },
    {   3, instrux_VCVTTPS2QQ },
    {   3, instrux_VCVTTPS2UDQ },
    {   3, instrux_VCVTTPS2UQQ },
    {   2, instrux_VCVTTSD2USI },
    {   2, instrux_VCVTTSS2USI },
    {   3, instrux_VCVTUDQ2PD },
    {   3, instrux_VCVTUDQ2PS },
    {   3, instrux_VCVTUQQ2PD },
    {   3, instrux_VCVTUQQ2PS },
    {   2, instrux_VCVTUSI2SD },
    {   3, instrux_VCVTUSI2SS },
    {   6, instrux_VDBPSADBW },
    {   1, instrux_VEXP2PD },
    {   1, instrux_VEXP2PS },
    {   6, instrux_VEXPANDPD },
    {   6, instrux_VEXPANDPS },
    {   4, instrux_VEXTRACTF32X4 },
    {   2, instrux_VEXTRACTF32X8 },
    {   4, instrux_VEXTRACTF64X2 },
    {   2, instrux_VEXTRACTF64X4 },
    {   4, instrux_VEXTRACTI32X4 },
    {   2, instrux_VEXTRACTI32X8 },
    {   4, instrux_VEXTRACTI64X2 },
    {   2, instrux_VEXTRACTI64X4 },
    {   6, instrux_VFIXUPIMMPD },
    {   6, instrux_VFIXUPIMMPS },
    {   2, instrux_VFIXUPIMMSD },
    {   2, instrux_VFIXUPIMMSS },
    {   3, instrux_VFPCLASSPD },
    {   3, instrux_VFPCLASSPS },
    {   1, instrux_VFPCLASSSD },
    {   1, instrux_VFPCLASSSS },
    {   1, instrux_VGATHERPF0DPD },
    {   1, instrux_VGATHERPF0DPS },
    {   1, instrux_VGATHERPF0QPD },
    {   1, instrux_VGATHERPF0QPS },
    {   1, instrux_VGATHERPF1DPD },
    {   1, instrux_VGATHERPF1DPS },
    {   1, instrux_VGATHERPF1QPD },
    {   1, instrux_VGATHERPF1QPS },
    {   3, instrux_VGETEXPPD },
    {   3, instrux_VGETEXPPS },
    {   1, instrux_VGETEXPSD },
    {   1, instrux_VGETEXPSS },
    {   3, instrux_VGETMANTPD },
    {   3, instrux_VGETMANTPS },
    {   1, instrux_VGETMANTSD },
    {   1, instrux_VGETMANTSS },
    {   4, instrux_VINSERTF32X4 },
    {   2, instrux_VINSERTF32X8 },
    {   4, instrux_VINSERTF64X2 },
    {   2, instrux_VINSERTF64X4 },
    {   4, instrux_VINSERTI32X4 },
    {   2, instrux_VINSERTI32X8 },
    {   4, instrux_VINSERTI64X2 },
    {   2, instrux_VINSERTI64X4 },
    {   6, instrux_VMOVDQA32 },
    {   6, instrux_VMOVDQA64 },
    {   6, instrux_VMOVDQU16 },
    {   6, instrux_VMOVDQU32 },
    {   6, instrux_VMOVDQU64 },
    {   6, instrux_VMOVDQU8 },
    {   3, instrux_VPABSQ },
    {   6, instrux_VPANDD },
    {   6, instrux_VPANDND },
    {   6, instrux_VPANDNQ },
    {   6, instrux_VPANDQ },
    {   3, instrux_VPBLENDMB },
    {   3, instrux_VPBLENDMD },
    {   3, instrux_VPBLENDMQ },
    {   3, instrux_VPBLENDMW },
    {   3, instrux_VPBROADCASTMB2Q },
    {   3, instrux_VPBROADCASTMW2D },
    {   3, instrux_VPCMPEQUB },
    {   3, instrux_VPCMPEQUD },
    {   3, instrux_VPCMPEQUQ },
    {   3, instrux_VPCMPEQUW },
    {   3, instrux_VPCMPGEB },
    {   3, instrux_VPCMPGED },
    {   3, instrux_VPCMPGEQ },
    {   3, instrux_VPCMPGEUB },
    {   3, instrux_VPCMPGEUD },
    {   3, instrux_VPCMPGEUQ },
    {   3, instrux_VPCMPGEUW },
    {   3, instrux_VPCMPGEW },
    {   3, instrux_VPCMPGTUB },
    {   3, instrux_VPCMPGTUD },
    {   3, instrux_VPCMPGTUQ },
    {   3, instrux_VPCMPGTUW },
    {   3, instrux_VPCMPLEB },
    {   3, instrux_VPCMPLED },
    {   3, instrux_VPCMPLEQ },
    {   3, instrux_VPCMPLEUB },
    {   3, instrux_VPCMPLEUD },
    {   3, instrux_VPCMPLEUQ },
    {   3, instrux_VPCMPLEUW },
    {   3, instrux_VPCMPLEW },
    {   3, instrux_VPCMPLTB },
    {   3, instrux_VPCMPLTD },
    {   3, instrux_VPCMPLTQ },
    {   3, instrux_VPCMPLTUB },
    {   3, instrux_VPCMPLTUD },
    {   3, instrux_VPCMPLTUQ },
    {   3, instrux_VPCMPLTUW },
    {   3, instrux_VPCMPLTW },
    {   3, instrux_VPCMPNEQB },
    {   3, instrux_VPCMPNEQD },
    {   3, instrux_VPCMPNEQQ },
    {   3, instrux_VPCMPNEQUB },
    {   3, instrux_VPCMPNEQUD },
    {   3, instrux_VPCMPNEQUQ },
    {   3, instrux_VPCMPNEQUW },
    {   3, instrux_VPCMPNEQW },
    {   3, instrux_VPCMPNGTB },
    {   3, instrux_VPCMPNGTD },
    {   3, instrux_VPCMPNGTQ },
    {   3, instrux_VPCMPNGTUB },
    {   3, instrux_VPCMPNGTUD },
    {   3, instrux_VPCMPNGTUQ },
    {   3, instrux_VPCMPNGTUW },
    {   3, instrux_VPCMPNGTW },
    {   3, instrux_VPCMPNLEB },
    {   3, instrux_VPCMPNLED },
    {   3, instrux_VPCMPNLEQ },
    {   3, instrux_VPCMPNLEUB },
    {   3, instrux_VPCMPNLEUD },
    {   3, instrux_VPCMPNLEUQ },
    {   3, instrux_VPCMPNLEUW },
    {   3, instrux_VPCMPNLEW },
    {   3, instrux_VPCMPNLTB },
    {   3, instrux_VPCMPNLTD },
    {   3, instrux_VPCMPNLTQ },
    {   3, instrux_VPCMPNLTUB },
    {   3, instrux_VPCMPNLTUD },
    {   3, instrux_VPCMPNLTUQ },
    {   3, instrux_VPCMPNLTUW },
    {   3, instrux_VPCMPNLTW },
    {   3, instrux_VPCMPB },
    {   3, instrux_VPCMPD },
    {   3, instrux_VPCMPQ },
    {   3, instrux_VPCMPUB },
    {   3, instrux_VPCMPUD },
    {   3, instrux_VPCMPUQ },
    {   3, instrux_VPCMPUW },
    {   3, instrux_VPCMPW },
    {   6, instrux_VPCOMPRESSD },
    {   6, instrux_VPCOMPRESSQ },
    {   3, instrux_VPCONFLICTD },
    {   3, instrux_VPCONFLICTQ },
    {   6, instrux_VPERMB },
    {   3, instrux_VPERMI2B },
    {   3, instrux_VPERMI2D },
    {   3, instrux_VPERMI2PD },
    {   3, instrux_VPERMI2PS },
    {   3, instrux_VPERMI2Q },
    {   3, instrux_VPERMI2W },
    {   3, instrux_VPERMT2B },
    {   3, instrux_VPERMT2D },
    {   3, instrux_VPERMT2PD },
    {   3, instrux_VPERMT2PS },
    {   3, instrux_VPERMT2Q },
    {   3, instrux_VPERMT2W },
    {   6, instrux_VPERMW },
    {   6, instrux_VPEXPANDD },
    {   6, instrux_VPEXPANDQ },
    {   3, instrux_VPLZCNTD },
    {   3, instrux_VPLZCNTQ },
    {   6, instrux_VPMAXSQ },
    {   6, instrux_VPMAXUQ },
    {   6, instrux_VPMINSQ },
    {   6, instrux_VPMINUQ },
    {   3, instrux_VPMOVB2M },
    {   3, instrux_VPMOVD2M },
    {   6, instrux_VPMOVDB },
    {   6, instrux_VPMOVDW },
    {   3, instrux_VPMOVM2B },
    {   3, instrux_VPMOVM2D },
    {   3, instrux_VPMOVM2Q },
    {   3, instrux_VPMOVM2W },
    {   3, instrux_VPMOVQ2M },
    {   6, instrux_VPMOVQB },
    {   6, instrux_VPMOVQD },
    {   6, instrux_VPMOVQW },
    {   6, instrux_VPMOVSDB },
    {   6, instrux_VPMOVSDW },
    {   6, instrux_VPMOVSQB },
    {   6, instrux_VPMOVSQD },
    {   6, instrux_VPMOVSQW },
    {   6, instrux_VPMOVSWB },
    {   6, instrux_VPMOVUSDB },
    {   6, instrux_VPMOVUSDW },
    {   6, instrux_VPMOVUSQB },
    {   6, instrux_VPMOVUSQD },
    {   6, instrux_VPMOVUSQW },
    {   6, instrux_VPMOVUSWB },
    {   3, instrux_VPMOVW2M },
    {   6, instrux_VPMOVWB },
    {   6, instrux_VPMULLQ },
    {   6, instrux_VPMULTISHIFTQB },
    {   6, instrux_VPORD },
    {   6, instrux_VPORQ },
    {   6, instrux_VPROLD },
    {   6, instrux_VPROLQ },
    {   6, instrux_VPROLVD },
    {   6, instrux_VPROLVQ },
    {   6, instrux_VPRORD },
    {   6, instrux_VPRORQ },
    {   6, instrux_VPRORVD },
    {   6, instrux_VPRORVQ },
    {   3, instrux_VPSCATTERDD },
    {   3, instrux_VPSCATTERDQ },
    {   3, instrux_VPSCATTERQD },
    {   3, instrux_VPSCATTERQQ },
    {   6, instrux_VPSLLVW },
    {  12, instrux_VPSRAQ },
    {   6, instrux_VPSRAVQ },
    {   6, instrux_VPSRAVW },
    {   6, instrux_VPSRLVW },
    {   3, instrux_VPTERNLOGD },
    {   3, instrux_VPTERNLOGQ },
    {   3, instrux_VPTESTMB },
    {   3, instrux_VPTESTMD },
    {   3, instrux_VPTESTMQ },
    {   3, instrux_VPTESTMW },
    {   3, instrux_VPTESTNMB },
    {   3, instrux_VPTESTNMD },
    {   3, instrux_VPTESTNMQ },
    {   3, instrux_VPTESTNMW },
    {   6, instrux_VPXORD },
    {   6, instrux_VPXORQ },
    {   6, instrux_VRANGEPD },
    {   6, instrux_VRANGEPS },
    {   2, instrux_VRANGESD },
    {   2, instrux_VRANGESS },
    {   3, instrux_VRCP14PD },
    {   3, instrux_VRCP14PS },
    {   2, instrux_VRCP14SD },
    {   2, instrux_VRCP14SS },
    {   1, instrux_VRCP28PD },
    {   1, instrux_VRCP28PS },
    {   2, instrux_VRCP28SD },
    {   2, instrux_VRCP28SS },
    {   3, instrux_VREDUCEPD },
    {   3, instrux_VREDUCEPS },
    {   2, instrux_VREDUCESD },
    {   2, instrux_VREDUCESS },
    {   3, instrux_VRNDSCALEPD },
    {   3, instrux_VRNDSCALEPH },
    {   3, instrux_VRNDSCALEPS },
    {   2, instrux_VRNDSCALESD },
    {   2, instrux_VRNDSCALESH },
    {   2, instrux_VRNDSCALESS },
    {   3, instrux_VRSQRT14PD },
    {   3, instrux_VRSQRT14PS },
    {   2, instrux_VRSQRT14SD },
    {   2, instrux_VRSQRT14SS },
    {   1, instrux_VRSQRT28PD },
    {   1, instrux_VRSQRT28PS },
    {   2, instrux_VRSQRT28SD },
    {   2, instrux_VRSQRT28SS },
    {   6, instrux_VSCALEFPD },
    {   6, instrux_VSCALEFPS },
    {   2, instrux_VSCALEFSD },
    {   2, instrux_VSCALEFSS },
    {   3, instrux_VSCATTERDPD },
    {   3, instrux_VSCATTERDPS },
    {   1, instrux_VSCATTERPF0DPD },
    {   1, instrux_VSCATTERPF0DPS },
    {   1, instrux_VSCATTERPF0QPD },
    {   1, instrux_VSCATTERPF0QPS },
    {   1, instrux_VSCATTERPF1DPD },
    {   1, instrux_VSCATTERPF1DPS },
    {   1, instrux_VSCATTERPF1QPD },
    {   1, instrux_VSCATTERPF1QPS },
    {   3, instrux_VSCATTERQPD },
    {   3, instrux_VSCATTERQPS },
    {   4, instrux_VSHUFF32X4 },
    {   4, instrux_VSHUFF64X2 },
    {   4, instrux_VSHUFI32X4 },
    {   4, instrux_VSHUFI64X2 },
    {   1, instrux_RDPKRU },
    {   1, instrux_WRPKRU },
    {   2, instrux_PTWRITE },
    {   1, instrux_CLDEMOTE },
    {   4, instrux_MOVDIRI },
    {   4, instrux_MOVDIR64B },
    {   2, instrux_PCONFIG },
    {   1, instrux_PBNDKB },
    {   1, instrux_PREFETCHRST2 },
    {   1, instrux_GF2P8AFFINEINVQB },
    {  10, instrux_VGF2P8AFFINEINVQB },
    {   1, instrux_GF2P8AFFINEQB },
    {  10, instrux_VGF2P8AFFINEQB },
    {   1, instrux_GF2P8MULB },
    {  10, instrux_VGF2P8MULB },
    {   6, instrux_VPCOMPRESSB },
    {   6, instrux_VPCOMPRESSW },
    {   3, instrux_VPEXPANDB },
    {   3, instrux_VPEXPANDW },
    {   6, instrux_VPSHLDW },
    {   6, instrux_VPSHLDD },
    {   6, instrux_VPSHLDQ },
    {   6, instrux_VPSHLDVW },
    {   6, instrux_VPSHLDVD },
    {   6, instrux_VPSHLDVQ },
    {   6, instrux_VPSHRDW },
    {   6, instrux_VPSHRDD },
    {   6, instrux_VPSHRDQ },
    {   6, instrux_VPSHRDVW },
    {   6, instrux_VPSHRDVD },
    {   6, instrux_VPSHRDVQ },
    {   3, instrux_VPOPCNTB },
    {   3, instrux_VPOPCNTW },
    {   3, instrux_VPOPCNTD },
    {   3, instrux_VPOPCNTQ },
    {   3, instrux_VPSHUFBITQMB },
    {   1, instrux_V4FMADDPS },
    {   1, instrux_V4FNMADDPS },
    {   1, instrux_V4FMADDSS },
    {   1, instrux_V4FNMADDSS },
    {   1, instrux_V4DPWSSDS },
    {   1, instrux_V4DPWSSD },
    {   1, instrux_ENCLS },
    {   1, instrux_ENCLU },
    {   1, instrux_ENCLV },
    {   1, instrux_CLRSSBSY },
    {   1, instrux_ENDBR32 },
    {   1, instrux_ENDBR64 },
    {   1, instrux_INCSSPD },
    {   1, instrux_INCSSPQ },
    {   1, instrux_RDSSPD },
    {   1, instrux_RDSSPQ },
    {   1, instrux_RSTORSSP },
    {   1, instrux_SAVEPREVSSP },
    {   1, instrux_SETSSBSY },
    {   2, instrux_WRUSSD },
    {   2, instrux_WRUSSQ },
    {   2, instrux_WRSSD },
    {   2, instrux_WRSSQ },
    {   5, instrux_ENQCMD },
    {   5, instrux_ENQCMDS },
    {   1, instrux_XRESLDTRK },
    {   1, instrux_XSUSLDTRK },
    {   6, instrux_VCVTNE2PS2BF16 },
    {   6, instrux_VDPBF16PS },
    {   3, instrux_VP2INTERSECTD },
    {   3, instrux_VP2INTERSECTQ },
    {   2, instrux_LDTILECFG },
    {   2, instrux_STTILECFG },
    {   1, instrux_TDPBF16PS },
    {   1, instrux_TDPFP16PS },
    {   1, instrux_TCMMIMFP16PS },
    {   1, instrux_TCMMRLFP16PS },
    {   1, instrux_TDPBSSD },
    {   1, instrux_TDPBSUD },
    {   1, instrux_TDPBUSD },
    {   1, instrux_TDPBUUD },
    {   2, instrux_TILELOADD },
    {   2, instrux_TILELOADDT1 },
    {   1, instrux_TILERELEASE },
    {   2, instrux_TILESTORED },
    {   1, instrux_TILEZERO },
    {   2, instrux_TILELOADDRS },
    {   2, instrux_TILELOADDRST1 },
    {   1, instrux_T2RPNTLVWZ0 },
    {   1, instrux_T2RPNTLVWZ0T1 },
    {   1, instrux_T2RPNTLVWZ1 },
    {   1, instrux_T2RPNTLVWZ1T1 },
    {   1, instrux_T2RPNTLVWZ0RS },
    {   1, instrux_T2RPNTLVWZ0RST1 },
    {   1, instrux_T2RPNTLVWZ1RS },
    {   1, instrux_T2RPNTLVWZ1RST1 },
    {   1, instrux_TCONJTCMMIMFP16PS },
    {   1, instrux_TCONJTFP16 },
    {   2, instrux_TCVTROWD2PS },
    {   2, instrux_TCVTROWPS2BF16H },
    {   2, instrux_TCVTROWPS2BF16L },
    {   2, instrux_TCVTROWPS2PHH },
    {   2, instrux_TCVTROWPS2PHL },
    {   1, instrux_TDPBF8PS },
    {   1, instrux_TDPBHF8PS },
    {   1, instrux_TDPHBF8PS },
    {   1, instrux_TDPHF8PS },
    {   2, instrux_TILEMOVROW },
    {   1, instrux_TMMULTF32PS },
    {   1, instrux_TTCMMIMFP16PS },
    {   1, instrux_TTCMMRLFP16PS },
    {   1, instrux_TTDPBF16PS },
    {   1, instrux_TTDPFP16PS },
    {   1, instrux_TTMMULTF32PS },
    {   1, instrux_TTRANSPOSED },
    {   6, instrux_VADDPH },
    {   2, instrux_VADDSH },
    {   6, instrux_VCMPPH },
    {   2, instrux_VCMPSH },
    {   1, instrux_VCOMISH },
    {   3, instrux_VCVTDQ2PH },
    {   3, instrux_VCVTPD2PH },
    {   3, instrux_VCVTPH2DQ },
    {   3, instrux_VCVTPH2PD },
    {   3, instrux_VCVTPH2PSX },
    {   3, instrux_VCVTPH2QQ },
    {   3, instrux_VCVTPH2UDQ },
    {   3, instrux_VCVTPH2UQQ },
    {   3, instrux_VCVTPH2UW },
    {   3, instrux_VCVTPH2W },
    {   3, instrux_VCVTPS2PHX },
    {   3, instrux_VCVTQQ2PH },
    {   2, instrux_VCVTSD2SH },
    {   2, instrux_VCVTSH2SD },
    {   2, instrux_VCVTSH2SI },
    {   2, instrux_VCVTSH2SS },
    {   2, instrux_VCVTSH2USI },
    {   4, instrux_VCVTSI2SH },
    {   2, instrux_VCVTSS2SH },
    {   3, instrux_VCVTTPH2DQ },
    {   3, instrux_VCVTTPH2QQ },
    {   3, instrux_VCVTTPH2UDQ },
    {   3, instrux_VCVTTPH2UQQ },
    {   3, instrux_VCVTTPH2UW },
    {   3, instrux_VCVTTPH2W },
    {   2, instrux_VCVTTSH2SI },
    {   2, instrux_VCVTTSH2USI },
    {   3, instrux_VCVTUDQ2PH },
    {   3, instrux_VCVTUQQ2PH },
    {   1, instrux_VCVTUSI2SH },
    {   3, instrux_VCVTUW2PH },
    {   3, instrux_VCVTW2PH },
    {   6, instrux_VDIVPH },
    {   2, instrux_VDIVSH },
    {   6, instrux_VFCMADDCPH },
    {   6, instrux_VFMADDCPH },
    {   2, instrux_VFCMADDCSH },
    {   2, instrux_VFMADDCSH },
    {   6, instrux_VFCMULCPH },
    {   6, instrux_VFMULCPH },
    {   2, instrux_VFCMULCSH },
    {   2, instrux_VFMULCSH },
    {   6, instrux_VFMADDSUB132PH },
    {   6, instrux_VFMADDSUB213PH },
    {   6, instrux_VFMADDSUB231PH },
    {   6, instrux_VFMSUBADD132PH },
    {   6, instrux_VFMSUBADD213PH },
    {   6, instrux_VFMSUBADD231PH },
    {   6, instrux_VFMADD132PH },
    {   6, instrux_VFMADD213PH },
    {   6, instrux_VFMADD231PH },
    {   6, instrux_VFNMADD132PH },
    {   6, instrux_VFNMADD213PH },
    {   6, instrux_VFNMADD231PH },
    {   2, instrux_VFMADD132SH },
    {   2, instrux_VFMADD213SH },
    {   2, instrux_VFMADD231SH },
    {   2, instrux_VFNMADD132SH },
    {   2, instrux_VFNMADD213SH },
    {   2, instrux_VFNMADD231SH },
    {   6, instrux_VFMSUB132PH },
    {   6, instrux_VFMSUB213PH },
    {   6, instrux_VFMSUB231PH },
    {   6, instrux_VFNMSUB132PH },
    {   6, instrux_VFNMSUB213PH },
    {   6, instrux_VFNMSUB231PH },
    {   2, instrux_VFMSUB132SH },
    {   2, instrux_VFMSUB213SH },
    {   2, instrux_VFMSUB231SH },
    {   2, instrux_VFNMSUB132SH },
    {   2, instrux_VFNMSUB213SH },
    {   2, instrux_VFNMSUB231SH },
    {   3, instrux_VFPCLASSPH },
    {   1, instrux_VFPCLASSSH },
    {   3, instrux_VGETEXPPH },
    {   1, instrux_VGETEXPSH },
    {   3, instrux_VGETMANTPH },
    {   1, instrux_VGETMANTSH },
    {   6, instrux_VMAXPH },
    {   1, instrux_VMAXSH },
    {   6, instrux_VMINPH },
    {   1, instrux_VMINSH },
    {   6, instrux_VMOVSH },
    {   4, instrux_VMOVW },
    {   6, instrux_VMULPH },
    {   2, instrux_VMULSH },
    {   6, instrux_VRCPPH },
    {   2, instrux_VRCPSH },
    {   3, instrux_VREDUCEPH },
    {   2, instrux_VREDUCESH },
    {   3, instrux_VENDSCALEPH },
    {   2, instrux_VENDSCALESH },
    {   3, instrux_VRSQRTPH },
    {   2, instrux_VRSQRTSH },
    {   6, instrux_VSCALEFPH },
    {   2, instrux_VSCALEFSH },
    {   3, instrux_VSQRTPH },
    {   2, instrux_VSQRTSH },
    {   6, instrux_VSUBPH },
    {   2, instrux_VSUBSH },
    {   1, instrux_VUCOMISH },
    {   4, instrux_AADD },
    {   4, instrux_AAND },
    {   4, instrux_AOR },
    {   4, instrux_AXOR },
    {   1, instrux_CLUI },
    {   1, instrux_SENDUIPI },
    {   1, instrux_STUI },
    {   1, instrux_TESTUI },
    {   1, instrux_UIRET },
    {   2, instrux_HRESET },
    {   3, instrux_VADDBF16 },
    {   3, instrux_VCMPBF16 },
    {   1, instrux_VCOMISBF16 },
    {   3, instrux_VDIVBF16 },
    {   3, instrux_VFMADD132BF16 },
    {   3, instrux_VFMADD213BF16 },
    {   3, instrux_VFMADD231BF16 },
    {   3, instrux_VFMSUB132BF16 },
    {   3, instrux_VFMSUB213BF16 },
    {   3, instrux_VFMSUB231BF16 },
    {   3, instrux_VFNMADD132BF16 },
    {   3, instrux_VFNMADD213BF16 },
    {   3, instrux_VFNMADD231BF16 },
    {   3, instrux_VFNMSUB132BF16 },
    {   3, instrux_VFNMSUB213BF16 },
    {   3, instrux_VFNMSUB231BF16 },
    {   3, instrux_VFPCLASSBF16 },
    {   3, instrux_VGETEXPBF16 },
    {   3, instrux_VGETMANTBF16 },
    {   3, instrux_VMAXBF16 },
    {   3, instrux_VMINBF16 },
    {   3, instrux_VMULBF16 },
    {   3, instrux_VRCPBF16 },
    {   3, instrux_VREDUCEBF16 },
    {   3, instrux_VRNDSCALEBF16 },
    {   3, instrux_VRSQRTBF16 },
    {   3, instrux_VSCALEFBF16 },
    {   3, instrux_VSQRTBF16 },
    {   3, instrux_VSUBBF16 },
    {   1, instrux_VCOMXSD },
    {   1, instrux_VCOMXSH },
    {   1, instrux_VCOMXSS },
    {   1, instrux_VUCOMXSD },
    {   1, instrux_VUCOMXSH },
    {   1, instrux_VUCOMXSS },
    {   3, instrux_VCVT2PH2BF8 },
    {   3, instrux_VCVT2PH2BF8S },
    {   3, instrux_VCVT2PH2HF8 },
    {   3, instrux_VCVT2PH2HF8S },
    {   3, instrux_VCVTPH2BF8 },
    {   3, instrux_VCVTPH2BF8S },
    {   3, instrux_VCVTPH2HF8 },
    {   3, instrux_VCVTPH2HF8S },
    {   3, instrux_VCVT2PS2PHX },
    {   3, instrux_VCVTBIASPH2BF8 },
    {   3, instrux_VCVTBIASPH2BF8S },
    {   3, instrux_VCVTBIASPH2HF8 },
    {   3, instrux_VCVTBIASPH2HF8S },
    {   3, instrux_VCVTHF82PH },
    {   3, instrux_VDPPHPS },
    {   3, instrux_VMINMAXBF16 },
    {   3, instrux_VMINMAXPD },
    {   3, instrux_VMINMAXPH },
    {   3, instrux_VMINMAXPS },
    {   1, instrux_VMINMAXSD },
    {   1, instrux_VMINMAXSH },
    {   1, instrux_VMINMAXSS },
    {   3, instrux_VCVTBF162IBS },
    {   3, instrux_VCVTBF162IUBS },
    {   3, instrux_VCVTTBF162IBS },
    {   3, instrux_VCVTTBF162IUBS },
    {   3, instrux_VCVTTPD2DQS },
    {   3, instrux_VCVTTPD2QQS },
    {   3, instrux_VCVTTPD2UDQS },
    {   3, instrux_VCVTTPD2UQQS },
    {   3, instrux_VCVTPH2IBS },
    {   3, instrux_VCVTPH2IUBS },
    {   3, instrux_VCVTTPH2IBS },
    {   3, instrux_VCVTTPH2IUBS },
    {   3, instrux_VCVTTPS2DQS },
    {   3, instrux_VCVTPS2IBS },
    {   3, instrux_VCVTPS2IUBS },
    {   3, instrux_VCVTTPS2IBS },
    {   3, instrux_VCVTTPS2IUBS },
    {   3, instrux_VCVTTPS2QQS },
    {   3, instrux_VCVTTPS2UDQS },
    {   3, instrux_VCVTTPS2UQQS },
    {   2, instrux_VCVTTSD2SIS },
    {   2, instrux_VCVTTSD2USIS },
    {   2, instrux_VCVTTSS2SIS },
    {   2, instrux_VCVTTSS2USIS },
    {   3, instrux_HINT_NOP },
    {   3, instrux_HINT_NOP0 },
    {   3, instrux_HINT_NOP1 },
    {   3, instrux_HINT_NOP2 },
    {   3, instrux_HINT_NOP3 },
    {   3, instrux_HINT_NOP4 },
    {   3, instrux_HINT_NOP5 },
    {   3, instrux_HINT_NOP6 },
    {   3, instrux_HINT_NOP7 },
    {   3, instrux_HINT_NOP8 },
    {   3, instrux_HINT_NOP9 },
    {   3, instrux_HINT_NOP10 },
    {   3, instrux_HINT_NOP11 },
    {   3, instrux_HINT_NOP12 },
    {   3, instrux_HINT_NOP13 },
    {   3, instrux_HINT_NOP14 },
    {   3, instrux_HINT_NOP15 },
    {   3, instrux_HINT_NOP16 },
    {   3, instrux_HINT_NOP17 },
    {   3, instrux_HINT_NOP18 },
    {   3, instrux_HINT_NOP19 },
    {   3, instrux_HINT_NOP20 },
    {   3, instrux_HINT_NOP21 },
    {   3, instrux_HINT_NOP22 },
    {   3, instrux_HINT_NOP23 },
    {   3, instrux_HINT_NOP24 },
    {   3, instrux_HINT_NOP25 },
    {   3, instrux_HINT_NOP26 },
    {   3, instrux_HINT_NOP27 },
    {   3, instrux_HINT_NOP28 },
    {   3, instrux_HINT_NOP29 },
    {   3, instrux_HINT_NOP30 },
    {   3, instrux_HINT_NOP31 },
    {   3, instrux_HINT_NOP32 },
    {   3, instrux_HINT_NOP33 },
    {   3, instrux_HINT_NOP34 },
    {   3, instrux_HINT_NOP35 },
    {   3, instrux_HINT_NOP36 },
    {   3, instrux_HINT_NOP37 },
    {   3, instrux_HINT_NOP38 },
    {   3, instrux_HINT_NOP39 },
    {   3, instrux_HINT_NOP40 },
    {   3, instrux_HINT_NOP41 },
    {   3, instrux_HINT_NOP42 },
    {   3, instrux_HINT_NOP43 },
    {   3, instrux_HINT_NOP44 },
    {   3, instrux_HINT_NOP45 },
    {   3, instrux_HINT_NOP46 },
    {   3, instrux_HINT_NOP47 },
    {   3, instrux_HINT_NOP48 },
    {   3, instrux_HINT_NOP49 },
    {   3, instrux_HINT_NOP50 },
    {   3, instrux_HINT_NOP51 },
    {   3, instrux_HINT_NOP52 },
    {   3, instrux_HINT_NOP53 },
    {   3, instrux_HINT_NOP54 },
    {   3, instrux_HINT_NOP55 },
    {   3, instrux_HINT_NOP56 },
    {   3, instrux_HINT_NOP57 },
    {   3, instrux_HINT_NOP58 },
    {   3, instrux_HINT_NOP59 },
    {   3, instrux_HINT_NOP60 },
    {   3, instrux_HINT_NOP61 },
    {   3, instrux_HINT_NOP62 },
    {   3, instrux_HINT_NOP63 },
};
